A phase-locked loop frequency modulation system, frequency division control method and device, equipment and medium

Abstract

The embodiment of the application discloses a phase-locked loop frequency modulation system, a frequency division control method and device, equipment and a medium. The phase-locked loop frequency modulation system comprises a Gray code frequency divider, and a frequency discriminator, a charge pump, a loop filter and a voltage-controlled oscillator connected in sequence. The Gray code frequency divider is connected between the frequency discriminator and the voltage-controlled oscillator to form a loop structure. The Gray code frequency divider is used to determine a target frequency division coefficient according to a running description parameter, and determine a frequency division adjustment plan according to the target frequency division coefficient. At least one Gray code control word is generated according to the frequency division adjustment plan. Each received signal to be frequency divided is adjusted according to each Gray code control word to output at least one second to-be-compared signal to control the output frequency of the phase-locked loop frequency modulation system. The technical scheme of the embodiment of the application can reduce the complexity of the phase-locked loop frequency modulation system, reduce the probability of losing lock during phase-locked loop frequency modulation, and improve the success rate of phase-locked loop frequency modulation.

Description

TECHNICAL FIELD

[0001] The embodiment of the present application relates to the frequency modulation technical field, in particular to a phase-locked loop frequency modulation system, a frequency division control method and device, equipment and medium. BACKGROUND

[0002] At present, in the digital circuit, the code is often required to change in a certain order. For example, the natural number is counted (for example, four bits of binary number are changed from 0111 to 1000, and four bits need to be changed), and in the actual circuit, the change of four bits cannot absolutely occur at the same time, so that the other codes (1100 and 0000) can appear in the counting. Since the traditional asynchronous timing sampling phase-locked loop also uses the natural number counting method, when the phase-locked loop frequency modulation and the frequency division coefficient corresponding binary number need to be changed, if the binary number to be changed is not all converted and is sampled by the circuit, the phase-locked loop will appear for a long time, so that the phase-locked loop is lost. In a specific case, the phase-locked loop lost can cause the circuit state error or input error, although the problem can be optimized by using the synchronization in the digital circuit, but from the probability point of view, the intermediate state can also cause the phase-locked loop lost. When the frequency is adjusted by using multiple phase-locked loops, the frequency-locked phase-locked loop needs to be switched by using the rear multiplexer, but the complexity of the phase-locked loop frequency modulation system used when the frequency is adjusted by using multiple phase-locked loops is high. SUMMARY

[0003] The embodiment of the present application provides a phase-locked loop frequency modulation system, a frequency division control method, a device, equipment and medium, which can reduce the complexity of the phase-locked loop frequency modulation system, reduce the lost probability of the phase-locked loop frequency modulation, and improve the success rate of the phase-locked loop frequency modulation.

[0004] In the first aspect, the embodiment of the present application provides a phase-locked loop frequency modulation system, which comprises a Gray code frequency divider, and a frequency discriminator, a charge pump, a loop filter and a voltage-controlled oscillator connected in sequence, and the Gray code frequency divider is connected between the frequency discriminator and the voltage-controlled oscillator to form a loop structure, and wherein:

[0005] The frequency discriminator is used for generating a first adjustment signal according to a first comparison signal sent by a reference clock and a second comparison signal fed back by the Gray code frequency divider;

[0006] The charge pump is used for performing signal processing on the received first adjustment signal to obtain a second adjustment signal;

[0007] The loop filter is used for performing filtering processing on the received second adjustment signal to obtain a third adjustment signal;

[0008] a voltage-controlled oscillator configured to generate a to-be-divided signal according to a third adjustment signal and send the to-be-divided signal to the gray code divider;

[0009] the gray code divider is configured to determine a target division coefficient according to the operation description parameter, determine a division adjustment plan according to the target division coefficient, generate at least one gray code control word according to the division adjustment plan, and adjust the received to-be-divided signal according to each gray code control word to gradually output at least one second to-be-comparison signal to control the output frequency of the phase-locked loop frequency modulation system.

[0010] In a second aspect, an embodiment of the present application further provides a division control method, which is executed by the gray code divider in the phase-locked loop frequency modulation system of the first aspect, and includes:

[0011] determining a target division coefficient according to the operation description parameter, and determining a division adjustment plan according to the target division coefficient;

[0012] generating at least one gray code control word according to the division adjustment plan;

[0013] adjusting the received to-be-divided signal according to each gray code control word to gradually obtain at least one second to-be-comparison signal to control the output frequency of the phase-locked loop frequency modulation system.

[0014] In a third aspect, an embodiment of the present application further provides a division control device, which is executed by the gray code divider in the phase-locked loop frequency modulation system of the first aspect, and includes:

[0015] a division adjustment plan determination module configured to determine a target division coefficient according to the operation description parameter, and determine a division adjustment plan according to the target division coefficient;

[0016] a gray code control word generation module configured to generate at least one gray code control word according to the division adjustment plan;

[0017] a second to-be-comparison signal update module configured to adjust the received to-be-divided signal according to each gray code control word to gradually obtain at least one second to-be-comparison signal to control the output frequency of the phase-locked loop frequency modulation system.

[0018] In a fourth aspect, an embodiment of the present application further provides an electronic device, which includes:

[0019] one or more processors;

[0020] a storage device configured to store one or more programs;

[0021] when the one or more programs are executed by the one or more processors, the one or more processors implement the division control method provided by any embodiment of the present application.

[0022] In a fifth aspect, an embodiment of the present application further provides a computer storage medium, which stores a computer program, and the computer program is executed by a processor to implement the frequency division control method provided by any of the embodiments of the present application.

[0023] The technical scheme of the embodiment comprises a Gray code frequency divider, and a phase-frequency detector, a charge pump, a loop filter and a voltage-controlled oscillator connected in sequence to form a phase-locked loop frequency modulation system. The phase-frequency detector generates a first adjustment signal sent to the charge pump, and the charge pump generates a second adjustment signal sent to the loop filter according to the first adjustment signal. The loop filter generates a third adjustment signal sent to the voltage-controlled oscillator according to the second adjustment signal, and the voltage-controlled oscillator generates a frequency-divided signal sent to the Gray code frequency divider according to the third adjustment signal. The Gray code frequency divider determines a target frequency division coefficient according to the operation description parameter, determines a frequency division adjustment plan according to the target frequency division coefficient, and further generates at least one Gray code control word according to the frequency division adjustment plan, so as to adjust the received frequency-divided signal according to each Gray code control word to output at least one second comparison signal for controlling the output frequency of the phase-locked loop frequency modulation system. Since the target frequency division coefficient determined by the Gray code frequency divider is determined according to the operation description parameter, the target frequency division coefficient can better meet the operation requirements of the equipment. The frequency division adjustment plan is determined according to the target frequency division coefficient, and the Gray code control word is generated according to the frequency division adjustment plan, so that the generated Gray code control word also better meets the operation requirements of the equipment. The Gray code control word is a Gray code control word, and the received frequency-divided signal is adjusted according to the Gray code control word, which can avoid the long intermediate state of the phase-locked loop caused by the change of the natural binary number corresponding to the frequency division coefficient during the frequency modulation of the phase-locked loop frequency modulation system, thereby reducing the probability of the phase-locked loop losing lock. The phase-locked loop frequency modulation system in the scheme does not need to deploy multiple phase-locked loops, nor does it need to deploy a post-stage multiplexer, and can realize frequency adjustment, thereby solving the problem of the phase-locked loop losing lock caused by the change of the binary number corresponding to the frequency division coefficient during the frequency modulation of the phase-locked loop in the prior art, reducing the complexity of the phase-locked loop frequency modulation system, reducing the probability of the phase-locked loop losing lock during the frequency modulation, and improving the success rate of the phase-locked loop frequency modulation. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a schematic diagram of a phase-locked loop frequency modulation system provided by an embodiment of the present application;

[0025] Figure 2 is a schematic diagram of a phase-locked loop frequency modulation system provided by an embodiment of the present application;

[0026] Figure 3 is a flowchart of a frequency division control method provided by an embodiment of the present application;

[0027] Figure 4 is a data processing flow diagram of a Gray code frequency divider provided by the second embodiment of the present application;

[0028] Figure 5 is a frequency division control device diagram provided by the third embodiment of the present application;

[0029] Figure 6 is a structure diagram of an electronic device provided by the fourth embodiment of the present application. DETAILED DESCRIPTION

[0030] The present application will be further described below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

[0031] It should also be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the contents. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted by flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of the operations can be implemented in parallel, concurrently or simultaneously. In addition, the order of the operations can be rearranged. The processes can be terminated when the operations are completed, but can also have additional steps not included in the drawings. The processes can correspond to methods, functions, procedures, subroutines, etc.

[0032] Embodiment One

[0033] Figure 1 is a schematic diagram of a phase-locked loop frequency modulation system provided by the first embodiment of the present application, as shown in Figure 1As shown, the phase-locked loop frequency modulation system comprises a Gray code frequency divider 150, and a frequency discriminator 110, a charge pump 120, a loop filter 130 and a voltage-controlled oscillator 140 connected in sequence, the Gray code frequency divider 150 is connected between the frequency discriminator 110 and the voltage-controlled oscillator 140 to form a loop structure, wherein: the frequency discriminator 110 is used for generating a first adjustment signal according to a first to-be-compared signal sent by a reference clock 100 and a second to-be-compared signal fed back by the Gray code frequency divider 150; the charge pump 120 is used for signal processing on the received first adjustment signal to obtain a second adjustment signal; the loop filter 130 is used for filtering processing on the received second adjustment signal to obtain a third adjustment signal; the voltage-controlled oscillator 140 is used for generating a to-be-frequency-divided signal according to the third adjustment signal and sending the to-be-frequency-divided signal to the Gray code frequency divider 150; the Gray code frequency divider 150 is used for determining a target frequency division coefficient according to a running description parameter, and determining a frequency division adjustment plan according to the target frequency division coefficient; generating at least one Gray code control word according to the frequency division adjustment plan; and adjusting the received to-be-frequency-divided signal according to each Gray code control word to output at least one second to-be-compared signal step by step to control the output frequency of the phase-locked loop frequency modulation system.

[0034] The Gray code frequency divider 150 can be a device capable of generating a control word in the form of a Gray code and capable of performing frequency division processing on an electrical signal according to the control word in the form of a Gray code. The first comparison signal can be a clock signal sent by the reference clock 100 to the phase-locked loop frequency modulation system. The second comparison signal can be a signal sent by the Gray code frequency divider 150 to the frequency discriminator 110 for comparison with the clock signal sent by the reference clock 100. The first adjustment signal can be a signal determined by the frequency discriminator 110 according to the first comparison signal and the second comparison signal and sent to the charge pump 120. The second adjustment signal can be a signal sent by the charge pump 120 to the loop filter 130 after signal processing of the first adjustment signal. For example, when the charge pump 120 is a current type charge pump, the charge pump 120 can perform current up, current down or negative current conversion processing on the first adjustment signal. When the charge pump 120 is a voltage type charge pump, the charge pump 120 can perform voltage up, voltage down or negative voltage conversion processing on the first adjustment signal. The third adjustment signal can be a signal sent by the loop filter 130 to the voltage controlled oscillator 140 after filtering processing of the second adjustment signal. The frequency division signal can be a pulse frequency signal determined by the voltage controlled oscillator 140 according to the third adjustment signal and sent to the Gray code frequency divider 150. The operation description parameter can be an operation parameter describing a peripheral device provided with a working signal by the voltage controlled oscillator 140. It should be noted that the peripheral device provided with a working signal by the voltage controlled oscillator 140 is not a device constituting the phase-locked loop adjustment system. The frequency division signal output by the voltage controlled oscillator 140 can be sent to the above-mentioned peripheral device as a desired output signal (equivalent to a working signal). The target frequency division coefficient can be a frequency division coefficient determined by the Gray code frequency divider 150 according to the operation description parameter. The frequency division adjustment plan can be a frequency division strategy of the Gray code frequency divider 150 for frequency division processing of the current frequency division signal. The Gray code control word can be a control word in the form of a Gray code, which is used to adjust the frequency division signal.

[0035] In the embodiment of the present application, the phase-frequency detector 110 is connected with the reference clock 100, the charge pump 120 and the Gray code frequency divider 150 respectively, the charge pump 120 is connected with the loop filter 130, the loop filter 130 is connected with the voltage-controlled oscillator 140, and the voltage-controlled oscillator 140 is connected with the Gray code frequency divider 150. The Gray code frequency divider 150 is located between the phase-frequency detector 110 and the voltage-controlled oscillator 140, so that the phase-frequency detector 110, the charge pump 120, the loop filter 130, the voltage-controlled oscillator 140 and the Gray code frequency divider 150 form a loop structure. After the reference clock 100 inputs the first to-be-compared signal to the phase-frequency detector 110 and the Gray code frequency divider 150 inputs the second to-be-compared signal to the phase-frequency detector 110, the phase-frequency detector 110 can compare and calculate the first to-be-compared signal and the second to-be-compared signal, generate the first adjustment signal, and input the first adjustment signal to the charge pump 120. The charge pump 120 processes the first adjustment signal to generate the second adjustment signal, and inputs the second adjustment signal to the loop filter 130. The loop filter 130 filters the received second adjustment signal to obtain the third adjustment signal, and inputs the third adjustment signal to the voltage-controlled oscillator 140. The voltage-controlled oscillator 140 can convert the received third adjustment signal into the to-be-divided signal based on the pulse conversion circuit, and input the to-be-divided signal to the Gray code frequency divider 150. Before receiving the to-be-divided signal, the Gray code frequency divider 150 can first acquire the operation description parameter, and then determine the target frequency division coefficient according to the operation description parameter and the equipment operation requirement, so as to generate the frequency division adjustment plan by taking the target frequency division coefficient as the adjustment target, further determine a plurality of Gray code control words matched with the frequency division adjustment plan, and then adjust the frequency of the to-be-divided signal step by step according to each Gray code control word matched with the frequency division adjustment plan, so as to output at least one second to-be-compared signal step by step, so as to control the output frequency of the voltage-controlled oscillator 140 of the phase-locked loop frequency modulation system.

[0036] Optionally, the operation description parameter can be acquired by the sensor, and then the operation description parameter is sent to the Gray code frequency divider 150 periodically or in real time by the sensor. The operation description parameter can also be sent to the Gray code frequency divider 150 in the form of an offline data packet according to the frequency adjustment strategy. The embodiment of the present application does not limit the acquisition form of the operation description parameter acquired by the Gray code frequency divider 150.

[0037] In the phase-locked loop frequency modulation system, the Gray code control word of the Gray code frequency divider adopts the encoding mode of the Gray code, so that only one binary number is different between any two adjacent Gray code control words, the output error caused by the change of the multi-bit control bit of the hardware circuit is effectively reduced, and it is a reliable encoding mode of error minimization. For example, when the control word is generated by using the natural number increment method, if the control word needs to be modified from 01111 to 10000, the intermediate state problem of the phase-locked loop occurs with a high probability, and the Gray code control word only needs to be modified from 01000 to 11000, so that the problem of the multi-bit data asynchronization of the actual circuit can be avoided from the source because only one bit is different between the adjacent codes.

[0038] Figure 2 is a schematic diagram of a phase-locked loop frequency modulation extension system provided by an embodiment of the present application, as Figure 2 The output of the voltage-controlled oscillator 140 can also be connected with the post-stage frequency divider 160, and the post-stage frequency divider 160 is used for performing frequency division processing on the to-be-divided signal output by the voltage-controlled oscillator 140. The frequency division coefficient of the post-stage frequency divider 160 can be the same as or different from the frequency division coefficient of the Gray code frequency divider 150. The signal output by the post-stage frequency divider 160 can be used as a clock output signal of an external device.

[0039] The technical scheme of the embodiment comprises a Gray code frequency divider, and a phase frequency detector, a charge pump, a loop filter and a voltage controlled oscillator connected in sequence to form a phase-locked loop frequency modulation system. The phase frequency detector generates a first adjustment signal sent to the charge pump, and the charge pump generates a second adjustment signal sent to the loop filter according to the first adjustment signal. The loop filter generates a third adjustment signal sent to the voltage controlled oscillator according to the second adjustment signal, and the voltage controlled oscillator generates a frequency-divided signal sent to the Gray code frequency divider according to the third adjustment signal. The Gray code frequency divider determines a target frequency division coefficient according to the operation description parameter, and determines a frequency division adjustment plan according to the target frequency division coefficient, and further generates at least one Gray code control word according to the frequency division adjustment plan, so as to adjust the received frequency-divided signal according to each Gray code control word to output at least one second comparison signal for controlling the output frequency of the phase-locked loop frequency modulation system. Since the target frequency division coefficient determined by the Gray code frequency divider is determined according to the operation description parameter, the target frequency division coefficient can better meet the equipment operation requirement. The frequency division adjustment plan is determined according to the target frequency division coefficient, and the Gray code control word is generated according to the frequency division adjustment plan, so that the generated Gray code control word also better meets the equipment operation requirement. The Gray code control word is a Gray code form control word, and adjusting the received frequency-divided signal according to the Gray code control word can avoid the long intermediate state of the phase-locked loop caused by the change of the natural binary number corresponding to the frequency division coefficient during the frequency modulation of the phase-locked loop frequency modulation system, thereby reducing the probability of the phase-locked loop losing lock. The phase-locked loop frequency modulation system in the scheme does not need to deploy multiple phase-locked loops, and does not need to deploy a post-stage multiplexer, and can realize frequency adjustment, solve the problem of the phase-locked loop losing lock caused by the change of the binary number corresponding to the frequency division coefficient during the frequency modulation of the phase-locked loop in the prior art, and reduce the complexity of the phase-locked loop frequency modulation system and the probability of losing lock during the frequency modulation of the phase-locked loop, and improve the success rate of the frequency modulation of the phase-locked loop.

[0040] Embodiment two

[0041] Figure 3 It is a flowchart of a frequency division control method provided by the embodiment two of the application, and the embodiment can be applied to the case of reducing the probability of the phase-locked loop losing lock. The method can be executed by the Gray code frequency divider in the phase-locked loop frequency modulation system, and correspondingly, as shown in Figure 3 the method comprises the following operations:

[0042] S210, determining a target frequency division coefficient according to the operation description parameter, and determining a frequency division adjustment plan according to the target frequency division coefficient.

[0043] In an optional embodiment of the present application, determining the target frequency division coefficient according to the operation description parameter, and determining the frequency division adjustment plan according to the target frequency division coefficient can include: determining the target frequency data according to the operation description parameter, and determining the target frequency division coefficient according to the target frequency data; wherein the operation description parameter includes at least one of temperature data, power consumption data, and computing power data; obtaining the current frequency division coefficient, and determining the frequency division adjustment plan according to the current frequency division coefficient and the target frequency division coefficient.

[0044] The target frequency data can be a frequency to which a voltage-controlled oscillator of a phase-locked loop frequency modulation system needs to be adjusted. The temperature data can be data representing a temperature of a peripheral device that is provided with a working signal by the voltage-controlled oscillator. The power consumption data can be data representing a device power consumption of the peripheral device that is provided with the working signal by the voltage-controlled oscillator. The computing power data can be data representing a computing power requirement of the peripheral device that is provided with the working signal by the voltage-controlled oscillator. The current frequency division coefficient can be a frequency division coefficient when a to-be-frequency-divided signal in the Gray code frequency divider is currently frequency-divided.

[0045] In an embodiment of the present application, the Gray code frequency divider can first obtain one or more of temperature data, power consumption data, and computing power data of a peripheral device that is provided with a working signal by a voltage-controlled oscillator, to obtain operation description parameters, and then determine target frequency data that can enable the peripheral device to be in a required working state according to the operation description parameters and device operation requirements, so as to calculate a target frequency division coefficient according to the target frequency data and a reference clock, and further determine a frequency division adjustment plan that takes the current frequency division coefficient in the current working state as an adjustment initial value and takes the target frequency division coefficient as an adjustment target according to the current frequency division coefficient and the target frequency division coefficient. For example, temperature data, power consumption data, and computing power data of the peripheral device (such as a main processor) can be collected by a sensor system of a GPU (Graphics Processing Unit, graphics processing unit), and the collected temperature data, power consumption data, and computing power data can be periodically sent to the Gray code frequency divider. The present application does not limit the manner of obtaining the temperature data, power consumption data, and computing power data, and does not limit the device that collects the temperature data, power consumption data, and computing power data.

[0046] In an optional embodiment of the present application, determining the target frequency data according to the operation description parameter can include: determining first adjustment frequency data according to the temperature data; determining second adjustment frequency data according to the power consumption data, preset rated power data, and preset peak power data; determining third adjustment frequency data according to the computing power data; and determining the target frequency data according to the first adjustment frequency data, the second adjustment frequency data, and the third adjustment frequency data.

[0047] The first adjustment frequency data can be a working frequency to which the peripheral device provided with the working signal by the voltage-controlled oscillator needs to be adjusted, which is determined according to the temperature data. The preset rated power data can be a preset rated power of the peripheral device provided with the working signal by the voltage-controlled oscillator. The preset peak power data can be a maximum power that can be reached by the peripheral device provided with the working signal by the voltage-controlled oscillator. The second adjustment frequency data can be a working frequency to which the peripheral device provided with the working signal by the voltage-controlled oscillator needs to be adjusted, which is determined according to the power consumption data, the preset rated power data and the preset peak power data. The third adjustment frequency data can be a working frequency to which the peripheral device provided with the working signal by the voltage-controlled oscillator needs to be adjusted, which is determined according to the computing power data.

[0048] In the embodiment of the present application, the Gray code frequency divider can determine a temperature variation trend of the peripheral device provided with the working signal by the voltage-controlled oscillator according to temperature data in a period of time, determine the first adjustment frequency data according to the temperature variation trend of the peripheral device, determine a power consumption variation trend of the peripheral device provided with the working signal by the voltage-controlled oscillator according to power consumption data in a period of time, determine the second adjustment frequency data according to the power consumption variation trend of the peripheral device, the preset rated power data and the preset peak power data, further determine the demand for computing power of the current application according to the current computing power data, determine a power ratio matching the demand for computing power of the current application according to the scheduling strategy, generate the third adjustment frequency data, and further determine the target frequency data meeting the device operation demand according to the first adjustment frequency data, the second adjustment frequency data and the third adjustment frequency data according to a preset value strategy.

[0049] Optionally, the Gray code frequency divider can input the temperature data of the peripheral device into a prediction model to obtain predicted temperature data, and then determine the first adjustment frequency data according to the predicted temperature data, that is, the device temperature adjustment effect can be achieved by setting the first adjustment frequency data as the target frequency. The Gray code frequency divider can input the power consumption data of the peripheral device into a prediction model to obtain predicted power consumption data, and then determine the second adjustment frequency data that keeps the power consumption of the peripheral device within the preset rated power data and the preset peak power data according to the power consumption control strategy combined with the predicted power consumption data. The Gray code frequency divider can also determine the demand for computing power of the current application, and use the DVFS (Dynamic voltage and frequency scaling) to make the peripheral device always work at the optimal frequency ratio, so that the peripheral device releases more excellent performance under the rated power consumption.

[0050] According to the preset value strategy, the target frequency data meeting the device operation requirement is determined according to the first adjustment frequency data, the second adjustment frequency data and the third adjustment frequency data, including: selecting the minimum value of the first adjustment frequency data, the second adjustment frequency data and the third adjustment frequency data as the target frequency data, or selecting the preset decimal multiple of the maximum value of the above three data as the target frequency data. The embodiment of the application does not limit the specific content of the value strategy for determining the target frequency data, as long as the target frequency data meeting the device operation requirement can be determined. Wherein, DVFS is a very important function in the AI (Artificial Intelligence) GPU accelerator product system, which can decide the optimal frequency and voltage combination in different scenarios (for the same chip, the higher the frequency, the higher the required voltage) according to the demand of the upper application for computing power and the power consumption data, and dynamically adjust the voltage and frequency of the chip to improve the performance and power consumption of the product. The clock required for the AI GPU accelerator to run is generally provided by the phase-locked loop in the chip, so that the GPU can run at an extremely high operating frequency range of tens of megahertz to about 1,500 megahertz.

[0051] In an optional embodiment of the application, the current frequency division coefficient is obtained, and the frequency division adjustment plan is determined according to the current frequency division coefficient and the target frequency division coefficient, which can include: determining a single step increment and a step number according to the current frequency division coefficient and the target frequency division coefficient; constructing at least one adjustment subtask for adjusting the current frequency division coefficient to the target frequency division coefficient according to the single step increment; wherein each adjustment subtask includes: a starting frequency division coefficient and target adjustment frequency data, and the number of adjustment subtasks matches the step number; and combining the adjustment subtasks to obtain the frequency division adjustment plan.

[0052] Wherein, the single step increment can be the adjustment increment of the frequency division coefficient when the frequency division signal is adjusted once. Optionally, the single step increment can be a positive increment or a negative increment. For example, when the target frequency division coefficient is greater than the current frequency division coefficient, the single step increment is a positive increment, and when the target frequency division coefficient is less than the current frequency division coefficient, the single step increment is a negative increment. The absolute value of the single step increment can be 1 or 2, etc. When the absolute value of the single step increment is 1, the probability of phase-locked loop lock loss is the lowest when the frequency division signal is adjusted by the Gray code frequency divider. The step number can be the number of adjustments of the frequency division signal. The adjustment subtask can be a subtask constituting the frequency division adjustment plan, used for adjusting the frequency division signal. The starting frequency division coefficient can be the adjustment initial value of the frequency division coefficient of the adjustment subtask. The target adjustment frequency data can be the adjustment target of the frequency division coefficient of the adjustment subtask.

[0053] In the embodiment of the present application, the Gray code frequency divider can set the absolute value of the single-step increment according to the adjustment requirement of the signal to be divided, and then take the current frequency division coefficient as the initial value of the frequency division adjustment plan and the target frequency division coefficient as the target of the frequency division adjustment plan. The current frequency division coefficient and the target frequency division coefficient are further compared to determine the positive or negative of the single-step increment, so as to determine the single-step increment according to the set absolute value of the single-step increment and the positive or negative of the single-step increment, and then determine the step number according to the difference between the target frequency division coefficient and the current frequency division coefficient and the single-step increment. After obtaining the single-step increment and the step number, the difference between the target frequency division coefficient and the current frequency division coefficient can be divided by the single-step increment to obtain at least one adjustment subtask for adjusting the current frequency division coefficient to the target frequency division coefficient step by step. Specifically, each adjustment subtask including the starting frequency division coefficient and the target adjustment frequency data can be determined according to the difference between the target frequency division coefficient and the current frequency division coefficient and the single-step increment, and the number of the determined adjustment subtasks is equal to the step number, that is, the number of the adjustment subtasks has a corresponding relationship with the step number. For example, the number of the adjustment subtasks can be equal to the step number, or the number of the adjustment subtasks has a certain proportional relationship with the step number, and so on.

[0054] For example, assuming that the current frequency division coefficient is 100 and the target frequency division coefficient is 97, since the target frequency division coefficient is less than the current frequency division coefficient, -1 can be taken as the single-step increment to construct three adjustment subtasks for adjusting the current frequency division coefficient to the target frequency division coefficient step by step, and the three adjustment subtasks are 100-99, 99-98 and 98-97. When the adjustment subtask is 100-99, the starting frequency division coefficient of the adjustment subtask is 100 and the target adjustment frequency data is 99. Similarly, the starting frequency division coefficient and the target adjustment frequency data of other adjustment subtasks can be obtained.

[0055] When the single-step increment of the Gray code frequency divider is 1, the problem that the frequency divider coefficient can only take integer values such as 1, 2, 3 and 4, leading to the problem that the control granularity cannot be fine and there is a large frequency difference between each stage, can be avoided. A larger step makes the peripheral device unable to work at the optimal frequency and voltage combination, and also introduces oscillation due to the coarse control granularity, leading to system instability. When a clock edge erasing module is separately added to the later-stage frequency divider, part of the clock period can be erased according to the frequency requirement when the clock passes through the module, so that the equivalent clock frequency can be obtained. However, the effective output frequency of the later-stage clock edge erasing module can only be selected as 1 / N, 2 / N,..., (N-1) / N. The larger the value of N is, the more complex the hardware design requirement of the module is. Since the obtained frequency is equivalent, the real clock performance is poor, which introduces high-frequency noise in the system, leading to performance degradation. When the single-step increment of the Gray code frequency divider in the scheme is 1, the frequency control granularity can be the reference clock granularity, and the difference generated by frequency adjustment can be reduced.

[0056] S220, generating at least one Gray code control word according to the frequency division adjustment plan.

[0057] In an optional embodiment of the present application, generating at least one Gray code control word according to the frequency division adjustment plan can include: determining target adjustment frequency division data of each adjustment subtask; and performing Gray code conversion on the target adjustment frequency division data to obtain a Gray code control word matched with each adjustment subtask.

[0058] In the embodiment of the present application, the Gray code frequency divider can first determine each adjustment subtask included in the frequency division adjustment plan, then determine target adjustment frequency division data matched with each adjustment subtask, further perform Gray code conversion on the target adjustment frequency division data of each adjustment subtask to obtain Gray code data format target adjustment frequency division data, and then use the Gray code data format target adjustment frequency division data as the Gray code control word of the corresponding adjustment subtask, so as to adjust the frequency division signal according to the Gray code control word.

[0059] Optionally, the Gray code control word and the frequency division coefficient have a mapping relationship. After the Gray code frequency divider determines the Gray code control word matched with the adjustment subtask, the frequency division coefficient corresponding to the Gray code control word can be determined according to the mapping relationship between the Gray code control word and the frequency division coefficient, and then the frequency division signal can be adjusted according to the frequency division coefficient corresponding to the Gray code control word. The mapping relationship between the Gray code control word and the frequency division coefficient can be pre-configured data of the Gray code frequency divider, that is, the Gray code frequency divider can determine the frequency division coefficient according to the mapping relationship between the Gray code control word and the frequency division coefficient after determining the Gray code control word.

[0060] Taking the current frequency division coefficient as 100 and the target frequency division coefficient as 97 as an example, the Gray code frequency divider can first determine the Gray code 01010010 corresponding to 99, and take 01010010 as the Gray code control word of the 100-99 adjustment subtask, then determine the Gray code 01010011 corresponding to 98, and take 01010011 as the Gray code control word of the 99-98 adjustment subtask, and then determine the Gray code 01010001 corresponding to 97, and take 01010001 as the Gray code control word of the 98-97 adjustment subtask. After obtaining the Gray code control word matched with each adjustment subtask, the Gray code frequency divider can adjust the to-be-frequency-divided signal according to the Gray code 01010010 corresponding to 99 in the order of 100-97 step by step, then adjust the to-be-frequency-divided signal according to the Gray code 01010011 corresponding to 98, and finally adjust the to-be-frequency-divided signal according to the Gray code 01010001 corresponding to 97.

[0061] S230, adjust the received to-be-frequency-divided signal according to each Gray code control word respectively to obtain at least one second to-be-comparison signal to control the output frequency of the phase-locked loop frequency modulation system.

[0062] In an optional embodiment of the present application, adjusting the received to-be-frequency-divided signal according to each Gray code control word can include: in the case of determining that the back read signal of the frequency discriminator is a lock signal, determining the next adjustment subtask according to the target adjustment frequency division data of the current adjustment subtask; determining the Gray code control word matched with the next adjustment subtask of the current adjustment subtask; and adjusting the received to-be-frequency-divided signal according to the Gray code control word matched with the next adjustment subtask of the current adjustment subtask.

[0063] Wherein, the back read signal can be a signal read when the frequency discriminator is back read. The lock signal can be a signal representing that the phase-locked loop completes frequency locking.

[0064] In the embodiment of the present application, the Gray code frequency divider can perform read-back check on the phase-frequency detector, if it is determined through the read-back check that the read-back signal of the phase-frequency detector is a locking signal, it indicates that the frequency locking of the phase-locked loop frequency modulation system is completed, the current adjustment subtask can be further determined, and the target adjustment frequency division data matched with the current adjustment subtask can be obtained, so as to further determine the adjustment subtask taking the target adjustment frequency division data as the starting frequency division coefficient, and then the adjustment subtask taking the target adjustment frequency division data as the starting frequency division coefficient is taken as the next adjustment subtask of the current adjustment subtask. After obtaining the next adjustment subtask of the current adjustment subtask, the target adjustment frequency division data of the next adjustment subtask of the current adjustment subtask is determined, and then the Gray code control word matched with the target adjustment frequency division data of the next adjustment subtask of the current adjustment subtask is obtained, and the received frequency division signal is adjusted according to the Gray code control word matched with the next adjustment subtask of the current adjustment subtask. If it is determined through the read-back check that the read-back signal of the phase-frequency detector is not a locking signal, it indicates that the frequency locking of the phase-locked loop frequency modulation system is not completed, and the received frequency division signal is not adjusted according to the Gray code control word matched with the next adjustment subtask.

[0065] In an optional embodiment of the present application, after the received frequency division signal is adjusted according to each Gray code control word respectively to obtain at least one second comparison signal step by step, it can further include: when it is determined that the current frequency division coefficient matches the target frequency division coefficient, returning to perform the operation of determining the target frequency division coefficient according to the running description parameter, so as to perform real-time dynamic adjustment on the output frequency of the phase-locked loop frequency modulation system.

[0066] In the embodiment of the present application, the Gray code frequency divider can compare the current frequency division coefficient in the current working state with the target frequency division coefficient, if the current frequency division coefficient matches the target frequency division coefficient, returning to perform the operation of determining the target frequency division coefficient according to the running description parameter, realizing the periodic update of the target frequency division coefficient, and then obtaining the current frequency division coefficient, and updating the frequency division adjustment plan according to the current frequency division coefficient and the updated target frequency division coefficient, further generating at least one Gray code control word according to the updated frequency division adjustment plan, and then adjusting the received frequency division signal according to each Gray code control word respectively to output at least one second comparison signal step by step, so as to dynamically adjust and control the output frequency of the phase-locked loop frequency modulation system. Wherein, the matching of the current frequency division coefficient and the target frequency division coefficient can be understood as that the current frequency division coefficient is equal to the target frequency division coefficient, or the current frequency division coefficient is in a certain proportion to the target frequency division coefficient, etc., and the matching rule of the current frequency division coefficient and the target frequency division coefficient can be set according to actual needs, and the embodiment of the present application does not set the matching rule of the current frequency division coefficient and the target frequency division coefficient.

[0067] Figure 4is a data processing flow schematic diagram of a Gray code frequency divider provided by Embodiment Two of the present application, as shown in Figure 4 As shown, the GPU temperature sensor of the GPU sensor system collects temperature data of the peripheral device, the GPU power consumption sensor collects power consumption data of the peripheral device, and the GPU performance sensor collects computing power data of the peripheral device, and the GPU sensor system sends the collected running description parameters to the Gray code frequency divider. The Gray code frequency divider obtains the running description parameters, arbitrates the target frequency data according to the preset value strategy and the running description parameters, and then determines the frequency adjustment plan according to the target frequency data, so as to generate at least one Gray code control word according to the frequency adjustment plan, and adjust the received frequency division signal according to each Gray code control word. When the current frequency division coefficient of the Gray code frequency divider matches the target frequency division coefficient, the Gray code frequency divider can send a data acquisition request to the GPU sensor system, and the GPU sensor system sends the running description parameters to the Gray code frequency divider according to the data acquisition request of the Gray code frequency divider, so that the Gray code frequency divider returns to execute the operation of arbitrating the target frequency data according to the preset value strategy and the running description parameters.

[0068] The technical scheme of the present embodiment determines the target frequency division coefficient according to the running description parameters, determines the frequency adjustment plan according to the target frequency division coefficient, and further generates at least one Gray code control word according to the frequency adjustment plan, so as to adjust the received frequency division signal according to each Gray code control word, and output at least one second comparison signal to control the output frequency of the phase-locked loop frequency modulation system. Since the target frequency division coefficient determined by the Gray code frequency divider is determined according to the running description parameters, the target frequency division coefficient can better meet the device running requirements. The frequency adjustment plan is determined according to the target frequency division coefficient, and the Gray code control word is generated according to the frequency adjustment plan, so the generated Gray code control word also better meets the device running requirements. The Gray code control word is a Gray code form control word, and the received frequency division signal is adjusted according to the Gray code control word, which can avoid the long intermediate state of the phase-locked loop caused by the change of multiple bits of the natural binary number corresponding to the frequency division coefficient when the phase-locked loop frequency modulation system modulates the frequency, thereby reducing the probability of phase-locked loop loss of lock, solving the problem of phase-locked loop loss of lock caused by the change of multiple bits of the binary number corresponding to the frequency division coefficient when the phase-locked loop frequency modulation system modulates the frequency, and reducing the probability of phase-locked loop loss of lock when the phase-locked loop modulates the frequency, and improving the success rate of phase-locked loop frequency modulation.

[0069] It should be noted that any arrangement and combination of the technical features in the above embodiments also belong to the protection scope of the present application.

[0070] Embodiment Three

[0071] Figure 5is a schematic diagram of a frequency division control device provided by Embodiment Three of the present application, as shown in the figure, the device is executed by a Gray code frequency divider in a phase-locked loop frequency modulation system, comprising: a frequency division adjustment plan determination module 310, a Gray code control word generation module 320, and a second to-be-compared signal updating module 330, wherein: Figure 5

[0072] The frequency division adjustment plan determination module 310 is configured to determine a target frequency division coefficient according to the operation description parameter, and determine a frequency division adjustment plan according to the target frequency division coefficient.

[0073] The Gray code control word generation module 320 is configured to generate at least one Gray code control word according to the frequency division adjustment plan.

[0074] The second to-be-compared signal updating module 330 is configured to adjust the received to-be-frequency-divided signal according to each Gray code control word to obtain at least one second to-be-compared signal step by step, and control the output frequency of the phase-locked loop frequency modulation system.

[0075] The technical scheme of the present embodiment determines the target frequency division coefficient according to the operation description parameter through the Gray code frequency divider, determines the frequency division adjustment plan according to the target frequency division coefficient, further generates at least one Gray code control word according to the frequency division adjustment plan, and adjusts the received to-be-frequency-divided signal according to each Gray code control word to obtain at least one second to-be-compared signal step by step, and controls the output frequency of the phase-locked loop frequency modulation system. Since the target frequency division coefficient determined by the Gray code frequency divider is determined according to the operation description parameter, the target frequency division coefficient can better meet the equipment operation requirements. The frequency division adjustment plan is determined according to the target frequency division coefficient, and the Gray code control word is generated according to the frequency division adjustment plan, so the generated Gray code control word also better meets the equipment operation requirements. The Gray code control word is a Gray code form control word, and the received to-be-frequency-divided signal is adjusted according to the Gray code control word, which can avoid the long intermediate state of the phase-locked loop caused by the change of multiple bits of the natural binary number corresponding to the frequency division coefficient during the frequency modulation of the phase-locked loop frequency modulation system, thereby reducing the probability of phase-locked loop loss, solving the problem of phase-locked loop loss caused by the change of multiple bits of the binary number corresponding to the frequency division coefficient during the frequency modulation of the phase-locked loop frequency modulation system, and reducing the probability of phase-locked loop loss during the frequency modulation of the phase-locked loop frequency modulation system.

[0076] Optionally, the frequency division adjustment plan determination module 310 is specifically configured to determine target frequency data according to the operation description parameter, and determine the target frequency division coefficient according to the target frequency data; wherein the operation description parameter comprises at least one of temperature data, power consumption data, and computing power data; obtain a current frequency division coefficient, and determine the frequency division adjustment plan according to the current frequency division coefficient and the target frequency division coefficient.

[0077] ​Optionally, the frequency division adjustment plan determination module 310 is specifically configured to determine first adjustment frequency data according to the temperature data; determine second adjustment frequency data according to the power consumption data, preset rated power data and preset peak power data; determine third adjustment frequency data according to the computing power data; and determine the target frequency data according to the first adjustment frequency data, the second adjustment frequency data and the third adjustment frequency data.

[0078] Optionally, the frequency division adjustment plan determination module 310 is specifically configured to determine a single step increment and a step number according to the current frequency division coefficient and the target frequency division coefficient; construct at least one adjustment subtask for adjusting the current frequency division coefficient to the target frequency division coefficient in stages according to the single step increment; wherein each adjustment subtask includes a starting frequency division coefficient and target adjustment frequency data, and the number of the adjustment subtasks matches the step number; and combine the adjustment subtasks to obtain the frequency division adjustment plan.

[0079] Optionally, the Gray code control word generation module 320 is specifically configured to determine the target adjustment frequency data of each adjustment subtask; and perform Gray code conversion on the target adjustment frequency data to obtain a Gray code control word matched with each adjustment subtask.

[0080] Optionally, the second to-be-compared signal updating module 330 is specifically configured to, in a case where it is determined that the back-reading signal of the phase-frequency detector is a locked signal, determine a next adjustment subtask according to the target adjustment frequency data of a current adjustment subtask; determine a Gray code control word matched with the next adjustment subtask of the current adjustment subtask; and adjust a received to-be-frequency-division signal according to the Gray code control word matched with the next adjustment subtask of the current adjustment subtask.

[0081] Optionally, the second to-be-compared signal updating module 330 is specifically configured to, in a case where it is determined that the current frequency division coefficient matches the target frequency division coefficient, return to perform the operation of determining the target frequency division coefficient according to the running description parameter, to perform real-time dynamic adjustment on the output frequency of the phase-locked loop frequency modulation system.

[0082] The frequency division control device described above can perform the frequency division control method provided by any embodiment of the application, has the function modules and beneficial effects corresponding to the execution method. Technical details not described in detail in the present embodiment can be referred to the frequency division control method provided by any embodiment of the application.

[0083] Since the frequency division control device described above is a device that can implement the frequency division control method in the embodiments of the present application, based on the frequency division control method described in the embodiments of the present application, those skilled in the art can understand the specific implementation of the frequency division control device of the embodiments and various variations thereof, and therefore how the frequency division control device implements the frequency division control method in the embodiments of the present application will not be described in detail here. As long as the device used to implement the frequency division control method in the embodiments of the present application is implemented by those skilled in the art, it belongs to the scope of protection of the present application.

[0084] Embodiment Four

[0085] Figure 6 A structural schematic diagram of an electronic device provided in Embodiment Four of the present application. Figure 6 A block diagram of an electronic device 412 suitable for implementing embodiments of the present application is shown. Figure 6 The electronic device 412 shown is merely an example and should not limit the function and scope of use of the embodiments of the present application. The electronic device 412 may, for example, be a computer device or a server device, etc.

[0086] As shown in Figure 6 The electronic device 412 is shown in the form of a general-purpose computing device. The components of the electronic device 412 can include, but are not limited to, one or more processors 416, storage devices 428, and a bus 418 connecting different system components, including the storage devices 428 and the processors 416.

[0087] The bus 418 represents one or more of several types of bus structures, including a memory bus or bus controller, a peripheral bus, a graphics acceleration port, a processor or local bus using any of a variety of bus architectures. For example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0088] The electronic device 412 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device 412, including volatile and non-volatile media, removable and non-removable media.

[0089] Storage device 428 may include computer system readable media in the form of volatile memory, such as RAM (Random Access Memory) 430 and / or cache 432. Electronic device 412 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 434 may be used to read and write non-removable, non-volatile magnetic media (… Figure 6 Not shown; usually referred to as a "hard drive"). Although Figure 6 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disc drive for reading and writing to a removable non-volatile optical disc (e.g., a compact disc-read-only memory (CD-ROM), a digital video disc-read-only memory (DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to bus 418 via one or more data media interfaces. Storage device 428 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0090] A program 436 having at least one set of program modules 426 may be stored in, for example, a storage device 428. Such program modules 426 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 426 typically perform the functions and / or methods described in the embodiments of the present invention.

[0091] The electronic device 412 can also communicate with one or more external devices 414 such as a keyboard or pointing device, a camera, a display 424, etc.; one or more devices that enable a user to interact with the electronic device 412; and / or one or more devices (e.g., a network card, a modem, etc.) that enable the electronic device 412 to communicate with one or more other computing devices. Such communication can be facilitated by an I / O interface 422. Still yet, the electronic device 412 can communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or the Internet) through a network adapter 420. As depicted, the network adapter 420 communicates with the other components of the electronic device 412 through the bus 418. It should be appreciated that although not shown, other hardware and / or software modules could be used in connection with the electronic device 412. Such modules can include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0092] The processor 416 performs various function applications and data processing by running programs stored in the storage 428, such as implementing the frequency division control method provided by the above-mentioned embodiments of the present application: determining a target frequency division coefficient according to a running description parameter, and determining a frequency division adjustment plan according to the target frequency division coefficient; generating at least one Golay code control word according to the frequency division adjustment plan; and adjusting the received signal to be frequency divided according to each Golay code control word to obtain at least one second comparison signal pair by step to control the output frequency of a phase-locked loop frequency modulation system.

[0093] The technical scheme of the embodiment determines the target frequency division coefficient according to the operation description parameter, determines the frequency division adjustment plan according to the target frequency division coefficient, and further generates at least one gray code control word according to the frequency division adjustment plan, so as to adjust the received frequency division signal according to each gray code control word, and output at least one second comparison signal to control the output frequency of the phase-locked loop frequency modulation system. Since the target frequency division coefficient determined by the gray code frequency divider is determined according to the operation description parameter, the target frequency division coefficient can meet the equipment operation requirement. The frequency division adjustment plan is determined according to the target frequency division coefficient, and the gray code control word is generated according to the frequency division adjustment plan, so that the generated gray code control word also meets the equipment operation requirement. The gray code control word is a control word in the form of gray code, and the received frequency division signal is adjusted according to the gray code control word, which can avoid the long intermediate state of the phase-locked loop caused by the change of the natural binary number corresponding to the frequency division coefficient when the phase-locked loop frequency modulation system modulates the frequency, thereby reducing the probability of phase-locked loop loss of lock, solving the problem of phase-locked loop loss of lock caused by the change of the binary number corresponding to the frequency division coefficient when the phase-locked loop frequency modulation system modulates the frequency, and reducing the probability of phase-locked loop loss of lock when the phase-locked loop modulates the frequency, and improving the success rate of phase-locked loop frequency modulation.

[0094] Embodiment five

[0095] The embodiment five also provides a computer storage medium storing a computer program, which is used to execute the frequency division control method of any one of the above-mentioned embodiments of the application when executed by a computer processor: determining a target frequency division coefficient according to an operation description parameter, and determining a frequency division adjustment plan according to the target frequency division coefficient; generating at least one gray code control word according to the frequency division adjustment plan; and adjusting the received frequency division signal according to each gray code control word to obtain at least one second comparison signal to control the output frequency of the phase-locked loop frequency modulation system.

[0096] The computer storage medium of the embodiments of the present application can adopt any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination thereof. More specific examples (non-exhaustive list) of the computer readable storage medium include: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus or device.

[0097] The computer readable signal medium can include a data signal propagating in baseband or propagated as a carrier wave in a propagated data signal, in which computer readable program code is embodied. Such propagated data signal can take a variety of forms, including but not limited to electro-magnetic, optical or any suitable combination thereof. The computer readable signal medium can also be any computer readable medium that is not a storage medium and that can communicate, propagate or transport program for use by or in connection with an instruction execution system, apparatus or device.

[0098] The program code contained on the computer readable medium can be transmitted using any suitable medium, including but not limited to wireless, wire line, optical fiber cable, radio frequency (RF), or any suitable combination thereof.

[0099] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0100] It is to be understood that the above description is directed to the preferred embodiments and that those skilled in the art will be able to devise various modifications which, although not specifically described herein, embody the principles of the application and are included within the spirit and scope of the application. Accordingly, while the preferred embodiments have been described above, those skilled in the art will understand that they are not to be limited to the preferred embodiments, but are to include all such embodiments falling within the scope of the application as defined by the appended claims.

Claims

1. A phase-locked loop frequency modulation system, characterized in that, include: A Gray code frequency divider, and sequentially connected frequency and phase detectors, a charge pump, a loop filter, and a voltage-controlled oscillator, wherein the Gray code frequency divider is connected between the frequency and phase detectors and the voltage-controlled oscillator to form a loop structure, wherein: The frequency and phase detector is used to generate a first adjustment signal based on the first comparison signal sent by the reference clock and the second comparison signal fed back by the Gray code divider. The charge pump is used to process the received first adjustment signal to obtain a second adjustment signal; The loop filter is used to filter the received second adjustment signal to obtain the third adjustment signal; The voltage-controlled oscillator is used to generate a frequency-divided signal according to the third adjustment signal, and send the frequency-divided signal to the Gray code frequency divider; The Gray code frequency divider is used to determine target frequency data based on operating description parameters, and to determine target frequency division coefficients based on the target frequency data; to obtain the current frequency division coefficients, and to determine a frequency division adjustment plan based on the current frequency division coefficients and the target frequency division coefficients; to generate at least one Gray code control word according to the frequency division adjustment plan; and to adjust the received frequency-to-division signal according to each Gray code control word, so as to output at least one second comparison signal step by step to control the output frequency of the phase-locked loop frequency modulation system. The operation description parameters include at least one of temperature data, power consumption data, and computing power data; the Gray code control word adopts the Gray code encoding method.

2. A frequency division control method, characterized in that, Performed by a Gray code divider in the phase-locked loop frequency modulation system as described in claim 1, the method includes: Based on the operating description parameters, determine the target frequency division coefficient, and based on the target frequency division coefficient, determine the frequency division adjustment plan; Generate at least one Gray code control word according to the frequency division adjustment plan; According to each Gray code control word, the received frequency-division signal is adjusted to obtain at least one second comparison signal step by step to control the output frequency of the phase-locked loop frequency modulation system; wherein, the Gray code control word adopts the Gray code encoding method; The step of determining the target frequency division coefficient based on the operating description parameters, and determining the frequency division adjustment plan based on the target frequency division coefficient, includes: The target frequency data is determined based on the operation description parameters, and the target frequency division coefficient is determined based on the target frequency data; wherein, the operation description parameters include at least one of temperature data, power consumption data, and computing power data; Obtain the current frequency division coefficient, and determine the frequency division adjustment plan based on the current frequency division coefficient and the target frequency division coefficient.

3. The method according to claim 2, characterized in that, The step of determining the target frequency data based on the operational description parameters includes: The first adjustment frequency data is determined based on the temperature data; The second adjustment frequency data is determined based on the power consumption data, the preset rated power data, and the preset peak power data. The third adjustment frequency data is determined based on the computing power data; The target frequency data is determined based on the first adjusted frequency data, the second adjusted frequency data, and the third adjusted frequency data.

4. The method according to claim 2, characterized in that, The step of obtaining the current frequency division coefficient and determining the frequency division adjustment plan based on the current frequency division coefficient and the target frequency division coefficient includes: Based on the current frequency division coefficient and the target frequency division coefficient, determine the single step increment and the number of steps; Based on the single step increment, construct at least one adjustment subtask to gradually adjust the current frequency division coefficient to the target frequency division coefficient; Each adjustment subtask includes: an initial frequency division coefficient and target adjustment frequency division data, and the number of adjustment subtasks matches the number of steps. The frequency division adjustment plan is obtained by combining the various adjustment sub-tasks.

5. The method according to claim 4, characterized in that, The step of generating at least one Gray code control word according to the frequency division adjustment plan includes: Determine the target adjustment frequency division data for each of the aforementioned adjustment sub-tasks; The target adjustment frequency division data is converted to Gray code to obtain Gray code control words that match each adjustment subtask.

6. The method according to claim 4, characterized in that, The step of adjusting the received frequency-divided signal according to each of the Gray code control words includes: If the readback signal of the frequency and phase detector is determined to be a lock signal, the next adjustment subtask is determined based on the target adjustment frequency division data of the current adjustment subtask. Determine the Gray code control word that matches the next adjustment subtask of the current adjustment subtask; The received frequency-division signal is adjusted according to the Gray code control word that matches the next adjustment subtask of the current adjustment subtask.

7. The method according to claim 2, characterized in that, After adjusting the received frequency-division signal according to each of the Gray code control words to obtain at least one second comparison signal step by step, the method further includes: When it is determined that the current frequency division coefficient matches the target frequency division coefficient, the operation of determining the target frequency division coefficient based on the running description parameters is returned to perform real-time dynamic adjustment of the output frequency of the phase-locked loop frequency modulation system.

8. A frequency division control device, characterized in that, Performed by the Gray code divider in the phase-locked loop frequency modulation system as described in claim 1, comprising: The frequency division adjustment plan determination module is used to determine the target frequency division coefficient based on the operating description parameters, and to determine the frequency division adjustment plan based on the target frequency division coefficient. The Gray code control word generation module is used to generate at least one Gray code control word according to the frequency division adjustment plan; wherein the Gray code control word adopts the Gray code encoding method; The second comparison signal update module is used to adjust the received frequency division signal according to each of the Gray code control words, so as to obtain at least one second comparison signal step by step to control the output frequency of the phase-locked loop frequency modulation system. The frequency division adjustment plan determination module is specifically used to determine target frequency data based on the operation description parameters, and to determine target frequency division coefficient based on the target frequency data; wherein, the operation description parameters include at least one of temperature data, power consumption data, and computing power data; to obtain the current frequency division coefficient, and to determine the frequency division adjustment plan based on the current frequency division coefficient and the target frequency division coefficient.

9. An electronic device, characterized in that, The electronic device includes: One or more processors; Storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the frequency division control method as described in any one of claims 2-7.

10. A computer storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the frequency division control method as described in any one of claims 2-7.

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