All-digital fractional frequency division phase-locked loop based on high-level synthesis and implementation method thereof
By combining high-level synthesis and register-transfer stage design in an all-digital phase-locked loop, a hybrid architecture of time-to-digital converter, digital loop filter and numerically controlled oscillator is realized, which solves the problems of low development efficiency and insufficient timing performance in the prior art, and realizes a high-efficiency and stable phase-locked loop that is suitable for modern communication and signal processing systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGZHOU SINE SCI INSTR CO LTD
- Filing Date
- 2025-12-12
- Publication Date
- 2026-05-05
AI Technical Summary
Existing all-digital phase-locked loop (PLL) design methods suffer from low development efficiency and insufficient timing performance. Pure register-transfer level implementation methods have long development cycles, while pure high-level synthesis implementation methods experience functional failures in key timing modules, resulting in the PLL being unable to lock stably.
A fully digital fractional-frequency-locked loop based on high-level synthesis is adopted. The time-to-digital converter is implemented based on register transfer stage, the digital loop filter is implemented based on high-level synthesis, the numerically controlled oscillator is implemented based on IP core, and the feedback frequency divider is also based on high-level synthesis. By combining high-level synthesis and register transfer stage design, the best balance between development efficiency and timing performance is achieved.
It realizes a high-performance, high-efficiency, and stable lockable all-digital phase-locked loop, solving the problems of long development cycle and insufficient timing performance, and is suitable for modern communication, computing and signal processing systems.
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Figure CN121984499A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of digital circuit design technology, and in particular to an all-digital fractional frequency-locked loop based on high-level synthesis and its implementation method. Background Technology
[0002] Phase-locked loops (PLLs) are indispensable core modules in modern communication, computing, and signal processing systems, primarily functioning to achieve frequency synthesis and clock synchronization. Traditional analog PLLs are mainly implemented using analog circuits. However, analog circuits face significant challenges in modern deep submicron CMOS processes: First, analog circuits are highly sensitive to process, voltage, and temperature (PVT) variations, exhibiting poor stability and insufficient robustness. Second, analog designs (such as high-voltage VCOs) are inherently complex, have long design cycles, and are difficult to port across different process nodes. Furthermore, passive components such as large capacitors required for analog filters occupy a significant amount of chip area, making them incompatible with highly integrated digital systems-on-chips (SoCs). With the rapid increase in the integration density of digital circuits, traditional analog PLLs have become a bottleneck in digital SoC integration.
[0003] To overcome the aforementioned shortcomings of traditional analog phase-locked loops (APLLs), all-digital PLLs have emerged. All-digital PLLs replace all analog modules with digital modules, offering significant advantages such as insensitivity to process, voltage, and temperature (PVT) variations, ease of integration, high portability, and easy scaling with process technology. However, existing all-digital PLL design methods have a clear technological gap: while pure register-transfer-level (RTL) implementations are functionally feasible, their algorithm iteration and maintenance costs are too high, resulting in low development efficiency; while pure high-level synthesis (HLS) implementations, although highly efficient, fail to function on critical timing modules (such as time-delayed conversion stages) required for all-digital PLLs. Furthermore, most PLLs in the industry are fabricated using small integrated circuits, whose accuracy and flexibility are far inferior to FPGA development systems based on high-level synthesis (HLS); and high-precision PLL technologies are extremely scarce. Summary of the Invention
[0004] To address the aforementioned technical problems, the purpose of this application is to provide a high-performance, high-efficiency, and stably lockable all-digital fractional frequency-locked loop based on high-level synthesis and its implementation method.
[0005] To achieve the above objectives, one aspect of this application proposes an all-digital fractional frequency-locked loop based on high-level synthesis, comprising: A time-to-digital converter, implemented based on a register transfer stage, is used to output a phase error signal based on an externally input reference clock signal and a feedback clock signal input from a feedback divider. A digital loop filter, the input of which is connected to the output of the time-to-digital converter, is implemented based on high-level synthesis and is used to output a frequency control word according to the phase error signal; A numerically controlled oscillator, the input of which is connected to the output of the digital loop filter, is implemented based on an IP core and is used to output a digital sine wave signal according to the frequency control word; The feedback frequency divider, whose input is connected to the output of the numerically controlled oscillator and whose output is connected to the input of the time-to-digital converter, is implemented based on high-level synthesis and is used to output the feedback clock signal according to the digital sine wave signal.
[0006] In some embodiments, the all-digital fractional frequency-locked loop further includes: A modulator, the input of which is connected to the output of the digital loop filter, and the modulator is also connected to the feedback divider, for outputting a digital sequence according to the frequency control word, the digital sequence being used to control the division ratio of the feedback divider.
[0007] To achieve the above objectives, another aspect of this application proposes a method for implementing a fully digital fractional-frequency-locked loop based on high-level synthesis. This method, implemented using the aforementioned fully digital fractional-frequency-locked loop based on high-level synthesis, includes the following steps: The phase error signal is output by the time-to-digital converter based on the externally input reference clock signal and the feedback clock signal input by the feedback divider. Based on the phase error signal, a frequency control word is output through a digital loop filter; A digital sine wave signal is output through a numerically controlled oscillator according to the frequency control word; The feedback frequency divider outputs the feedback clock signal based on the digital sine wave signal. The time-to-digital converter is implemented based on a register transfer stage, the digital loop filter and the feedback frequency divider are implemented based on high-level synthesis, and the numerically controlled oscillator is implemented based on an IP core.
[0008] In some embodiments, the step of outputting a phase error signal via a time-to-digital converter based on an externally input reference clock signal and a feedback clock signal input from a feedback divider specifically includes: The reference clock signal, the feedback clock signal, and the first system clock signal are received through the time-to-digital converter. Based on the first system clock signal, the phase difference between the reference clock signal and the feedback clock signal is calculated, and the phase error signal is output.
[0009] In some embodiments, the step of outputting a frequency control word based on the phase error signal through a digital loop filter specifically includes: The phase error signal is received through the digital loop filter; The phase error signal is subjected to proportional and integral operations to output the frequency control word.
[0010] In some embodiments, performing proportional and integral operations on the phase error signal and outputting the frequency control word specifically includes: Calculate the proportional term and integral term based on the phase error signal; The integral term is subjected to an integral saturation judgment, and then the integral term is clamped or updated based on the integral saturation judgment result; Calculate the control increment based on the proportional term and the clamped or updated integral term; Calculate the output value of the frequency control word based on the control increment; Determine the maximum and minimum values of the frequency control word; Based on the maximum value and the minimum value of the frequency control word, an output saturation judgment is performed on the output value, and then the output value, the maximum value of the frequency control word, or the minimum value of the frequency control word is output according to the output saturation judgment result.
[0011] In some embodiments, the step of performing an output saturation judgment on the output value based on the maximum value and the minimum value of the frequency control word, and then outputting the output value, the maximum value of the frequency control word, or the minimum value of the frequency control word according to the output saturation judgment structure, specifically includes: When the output value is greater than the minimum value of the frequency control word and less than the maximum value of the frequency control word, the output value is output. When the output value is less than the minimum value of the frequency control word, output the minimum value of the frequency control word; When the output value is greater than the maximum value of the frequency control word, the maximum value of the frequency control word is output.
[0012] In some embodiments, the step of outputting a digital sine wave signal via a numerically controlled oscillator according to the frequency control word specifically includes: The frequency control word and the second system clock signal are received through the numerically controlled oscillator. Convert the frequency control word into phase gain; The phase gain is accumulated according to the second system clock signal through the phase accumulator in the numerically controlled oscillator to obtain the accumulation result; Based on the sine and cosine lookup table and the accumulated result, the digital sine wave signal is output.
[0013] In some embodiments, the step of outputting the feedback clock signal based on the digital sine wave signal through the feedback divider specifically includes: The digital sine wave signal and the target frequency division coefficient are received through the feedback frequency divider; Invert the sign bit of the digital sine wave signal to obtain a square wave signal; The square wave signal is divided according to the target frequency division coefficient to obtain the feedback clock signal; The feedback clock signal is output to the time-to-digital converter.
[0014] In some embodiments, the method further includes: The modulator outputs a digital sequence based on the frequency control word, and the digital sequence is used to control the division ratio of the feedback divider.
[0015] The beneficial effects of this application are as follows: This application discloses a fully digital fractional-frequency-division phase-locked loop (PLL) based on high-level synthesis and its implementation method. The PLL includes a time-to-digital converter, implemented using a register-transfer stage, used to output a phase error signal based on an externally input reference clock signal and a feedback clock signal input from a feedback divider; a digital loop filter, implemented using high-level synthesis, used to output a frequency control word based on the phase error signal; a numerically controlled oscillator, implemented using an IP core, used to output a digital sine wave signal based on the frequency control word; and a feedback divider, implemented using high-level synthesis, used to output a feedback clock signal based on the digital sine wave signal. This application strategically divides the modules in the fully digital PLL and strategically combines high-level synthesis with register-transfer stage design, achieving an optimal balance between development efficiency and timing performance. It solves the problem that pure high-level synthesis implementation methods cannot successfully lock the frequency, and addresses the long development cycle of pure register-transfer stage implementation methods, thus realizing a high-performance, high-efficiency, and stably lockable fully digital PLL. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments of this application are described below. It should be understood that the drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions in this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 A structural block diagram of a fully digital fractional frequency-locked loop based on high-level synthesis provided in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of an integer frequency multiplication all-digital phase-locked loop provided in one embodiment of this application; Figure 3 This is a schematic diagram of the structure of a fractional frequency division all-digital phase-locked loop provided in one embodiment of this application; Figure 4 A schematic diagram illustrating the steps of an implementation method for a high-level synthesis-based all-digital fractional frequency-locked loop (PLL) according to an embodiment of this application; Figure 5 This is a schematic diagram of the RTL logic of a time-to-digital converter provided in one embodiment of this application; Figure 6 This is an HLS code logic flowchart of a digital loop filter provided in one embodiment of this application; Figure 7 This is a schematic diagram of the internal logic of a numerically controlled oscillator provided in one embodiment of this application; Figure 8 This is a schematic diagram of the RTL logic of a feedback divider provided in one embodiment of this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.
[0019] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”
[0020] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.
[0021] Phase-locked loops (PLLs) are an indispensable core module in modern communication, computing, and signal processing systems. Their main function is to achieve frequency synthesis and clock synchronization.
[0022] Traditional analog phase-locked loops (APLLs) are primarily implemented using analog circuits. Their classic architecture typically includes a phase detector (PD), a charge pump (CP), a loop filter (LF), and a voltage-controlled oscillator (VCO). However, analog circuits face significant challenges in modern deep submicron CMOS processes: First, analog circuits are highly sensitive to process, voltage, and temperature (PVT) variations, exhibiting poor stability and insufficient robustness. Second, analog designs (such as high-voltage VCOs) are inherently complex, have long design cycles, and are difficult to port across different process nodes. Furthermore, the large capacitors and other passive components required for analog filters occupy a significant amount of chip area, making them incompatible with highly integrated digital systems-on-chips (SoCs). With the rapid increase in digital circuit integration, traditional analog phase-locked loops (APLLs) have become a bottleneck in digital SoC integration.
[0023] To overcome the aforementioned shortcomings of traditional analog phase-locked loops (APLLs), all-digital PLLs have emerged. All-digital PLLs replace all analog modules with digital modules, offering significant advantages such as insensitivity to process, voltage, and temperature (PVT) variations, ease of integration, high portability, and easy scaling with process technology.
[0024] However, in terms of specific digital implementation methods, all-digital phase-locked loops have formed two mainstream technical routes, but each of these routes has insurmountable defects, constituting a "dilemma" in the existing technology: Defect A: Implementation method of pure register-transfer level (RTL): This is a traditional digital method for implementing a fully digital fractional-frequency-division phase-locked loop (PLL), which involves building all modules from the ground up using hardware description languages (HDLs) such as Verilog or VHDL. The main drawbacks of this method are low development efficiency and difficulty in algorithm iteration. One of the core components of a PLL is the loop filter (DLF), which is essentially a complex digital signal processing algorithm (such as a PI controller or IIR filter).
[0025] Low development efficiency: Implementing complex mathematical operations and state machines (such as loop filters) using register transfer level (RTL) requires designers to make a large number of low-level design decisions, resulting in a huge amount of code (usually 5-10 times the size of HLSC++ code) and an extremely long development and verification cycle.
[0026] Algorithm iteration is difficult: In the design of an all-digital fractional frequency division phase-locked loop, loop parameters (such as K of the PI controller) are challenging. P and K I Optimization of the coefficients and exploration of the filter architecture are crucial. When using register-transfer level (RTL), any adjustment to the filter algorithm (such as changing the gain or increasing the order) may mean "rewriting" the complex RTL state machine multiple times.
[0027] Defect B: Implementation method of pure high-level synthesis (HLS): High-level synthesis (HLS) implementation methods allow designers to describe algorithms using high-level languages such as C / C++ and automatically synthesize them into RTL hardware, aiming to significantly reduce development time. Therefore, a seemingly ideal solution is to use high-level synthesis (HLS) to implement all modules in a fully digital phase-locked loop.
[0028] However, this method has fundamental functional limitations in high-performance, time-critical systems like all-digital phase-locked loops (PLLs). A PLL is a high-performance closed-loop feedback system, and its Time-Controlled Logic (TDC) module must be able to accurately measure phase differences at the nanosecond (ns) or even picosecond (ps) level. HLS tools are not adept at inferring hardware with precise timing and structure (e.g., dedicated carry chains or trigger arrays for fine-grained delay measurements) from untimed C / C++ program logic. Ultimately, this prevents HLS tools from correctly synthesizing the TDC module's algorithmic description into hardware that meets nanosecond-level timing requirements, leading to inaccurate phase error measurements or excessive delays, and consequently, preventing the entire feedback loop from converging.
[0029] In summary, existing all-digital phase-locked loop (PLL) design methods exhibit a clear technological gap: while pure register-transfer-level (RTL) implementations are functionally feasible, their algorithm iteration and maintenance costs are too high, resulting in low development efficiency; and while pure high-level synthesis (HLS) implementations offer high development efficiency, they fail to function on the critical timing modules required for all-digital PLLs. Furthermore, the vast majority of PLLs in the industry are fabricated using small integrated circuits, whose accuracy and flexibility are far inferior to FPGA development systems based on HLS; and high-precision PLL technologies are extremely scarce.
[0030] In view of this, this application proposes a fully digital fractional-frequency-division phase-locked loop (PLL) based on high-level synthesis, including a time-to-digital converter (TD-SCDMA) implemented based on a register-transfer stage, used to output a phase error signal based on an externally input reference clock signal and a feedback clock signal input from a feedback divider; a digital loop filter, also implemented based on high-level synthesis, used to output a frequency control word based on the phase error signal; a numerically controlled oscillator (NCO), implemented based on an IP core, used to output a digital sine wave signal based on the frequency control word; and a feedback divider, also implemented based on high-level synthesis, used to output a feedback clock signal based on the digital sine wave signal. This application achieves an optimal balance between development efficiency and timing performance by strategically dividing the modules in the fully digital PLL and strategically combining high-level synthesis with register-transfer stage design. It solves the problem that pure high-level synthesis methods cannot successfully lock frequencies, and addresses the long development cycle of pure register-transfer stage methods, thus realizing a high-performance, high-efficiency, and stably lockable fully digital PLL.
[0031] Reference Figure 1 , Figure 1 This is a block diagram of a high-level synthesis-based all-digital fractional frequency-locked loop (FLL) according to one embodiment of this application. This embodiment proposes a high-level synthesis-based all-digital FLL, comprising: A time-to-digital converter, implemented based on a register transfer stage, is used to output a phase error signal based on an externally input reference clock signal and a feedback clock signal input from a feedback divider. A digital loop filter, whose input is connected to the output of a time-to-digital converter, is implemented using high-level synthesis and is used to output a frequency control word based on the phase error signal. A numerically controlled oscillator, whose input is connected to the output of a digital loop filter, is implemented based on an IP core and is used to output a digital sine wave signal according to a frequency control word. The feedback frequency divider connects its input to the output of the numerically controlled oscillator and its output to the input of the time-to-digital converter. It is implemented using high-level synthesis and is used to output a feedback clock signal based on a digital sine wave signal.
[0032] It should be noted that, to overcome the dilemma of pure Register Transfer Level (RTL) implementation (low development efficiency and difficult iteration) and pure High-Level Synthesis (HLS) implementation (failure of time-critical modules), this application provides an innovative hybrid all-digital fractional frequency divider phase-locked loop (ADPLL) architecture and implementation method based on high-level synthesis. This method strategically divides the modules in the all-digital fractional frequency divider PLL and strategically combines pure high-level synthesis (HLS) with register transfer level (RTL) design, achieving the best balance between development efficiency and timing performance. It solves the problem that the pure high-level synthesis (HLS) implementation method cannot successfully lock the frequency, as well as the long development cycle of the pure register transfer level (RTL) implementation method.
[0033] Specifically, the all-digital fractional-frequency phase-locked loop (PLL) of this application includes a time-to-digital converter (TDC), a digital loop filter (DLF), a numerically controlled oscillator (NCO), and a feedback divider. These modules are implemented using a hybrid approach. Specifically, the TDC and the feedback divider are implemented using RTL (Verilog), the DLF is implemented using HLS (C / C++), and the NCO is implemented using an IP core.
[0034] For example, such as Figure 2 The diagram shown is a schematic of an integer frequency multiplication all-digital phase-locked loop according to an embodiment of this application. The hybrid architecture all-digital fractional frequency division phase-locked loop of this application embodiment is implemented through an FPGA platform, thereby achieving a stable integer frequency multiplication (32 times) clock synthesis.
[0035] The hardware configuration includes: a chip, a time-to-digital converter (TDC), a feedback divider, a digital loop filter (DLF), and a numerically controlled oscillator (NCO). The chip, serving as the core processing unit of the phase-locked loop, utilizes a Zynq7020 FPGA, which deploys the hybrid architecture of this embodiment. The time-critical TDC and feedback divider are implemented using Verilog RTL; the algorithm-intensive DLF is implemented using HLSC++; and the NCO uses a Xilinx DDS Compiler IP core. The system clock is configured to 100MHz, and the target division factor (div_factor) is set to 32.
[0036] The working process is as follows: First, the time-to-digital converter (TDC) receives a 50kHz external reference clock signal rfclk and a feedback clock signal fbclk from the feedback divider. The TDC uses a 100MHz system clock signal as a reference to accurately measure the time difference between the rising edges of the reference clock signal rfclk and the feedback clock signal fbclk, and outputs a 12-bit digital phase error signal tdc_out. Next, the HLS-implemented digital loop filter (DLF) receives this digital phase error signal tdc_out, and its internal PI controller algorithm (in this embodiment, K is set to K...)... P =5, K I =1) The phase error is proportionally and integrally calculated to generate a 16-bit frequency control word fcw, which is used to dynamically correct the frequency of the numerically controlled oscillator (NCO). Then, the NCO receives the frequency control word fcw as its streaming phase increment input. Driven by a 100MHz system clock signal, the NCO generates a 32-bit floating-point digital sine wave signal sin_out, the frequency of which is precisely controlled by the frequency control word fcw (target 1.6MHz). Finally, the RTL-implemented feedback divider directly extracts the sign bit of the digital sine wave signal sin_out output by the NCO and uses it as a 1.6MHz square wave input clock clk_in. This square wave is divided by 32 to generate a 50kHz feedback clock signal fbclk, which is fed back to the time-to-digital converter (TDC) to form a closed loop.
[0037] Implementation Results: During loop convergence, the phase error signal tdc_out gradually converged from an initial large negative value (e.g., -1994) towards 0, eventually stabilizing near 0 (e.g., -1, 0, 1). This indicates that the feedback clock signal fbclk has been precisely synchronized with the reference clock signal rfclk, and the system has successfully achieved stable 32-fold frequency locking, overcoming the limitation of pure high-level synthesis (HLS) methods in frequency locking.
[0038] As an optional implementation, the all-digital fractional-frequency-locked loop further includes: The modulator's input is connected to the output of the digital loop filter. The modulator is also connected to the feedback divider, which outputs a digital sequence based on the frequency control word. The digital sequence is used to control the division ratio of the feedback divider.
[0039] For example, the hybrid architecture of this application embodiment achieves high-precision fractional-division frequency synthesis by introducing a Delta-Sigma modulator (DSM). Figure 3The diagram shown is a schematic representation of a fractional-frequency division all-digital phase-locked loop according to an embodiment of this application. The core processing unit of the chip (FPGA) is based on... Figure 2 The hybrid architecture shown is characterized by the insertion of a Delta-Sigma modulator (DSM) between the digital loop filter (DLF) and the numerically controlled oscillator (NCO). Simultaneously, the original feedback divider is replaced with a multi-modulus divider capable of N / N+1 switching, the division ratio of which is dynamically controlled by the output sequence of the modulator (DSM).
[0040] The process is as follows: The user sets a decimal division target (e.g., N+K / F, such as 32.125). The time-to-digital converter (TDC) and digital loop filter (DLF) operate as usual to track phase errors, and the DLF outputs a control word representing the average target frequency. The modulator (DSM) then receives this control word and converts it into a high-speed, pseudo-random digital sequence (e.g., a series of 0s and 1s). This digital sequence serves as an instruction to dynamically control the division ratio of the multimode feedback divider (Divider). For example, to achieve an average division ratio of 32.125 (i.e., K / F = 1 / 8), the output sequence of the modulator (DSM) will control the Divider to perform a division of 32 seven times and a division of 33 once every eight cycles. Through this high-speed time averaging, the average frequency of the feedback clock signal fbclk is precisely locked to the reference clock signal rfclk. Ultimately, the output frequency fout of the numerically controlled oscillator (NCO) stabilizes at (N+K / F)×f ref That is, 32.125 × f ref .
[0041] Implementation Results: This scheme utilizes the "noise shaping" characteristic of the modulator (DSM) to "push" the quantization noise introduced by fractional-division switching (which would otherwise generate strong spurious noise) to a high-frequency region far from the carrier. The digital loop filter (DLF) in the ADPLL loop is itself a low-pass filter, which can effectively filter out the noise pushed to higher frequencies by the modulator (DSM). Ultimately, the hybrid architecture of this application embodiment can achieve extremely high frequency resolution (e.g., target accuracy 10). 6) Frequency synthesis, while maintaining extremely low in-band phase noise and high signal purity.
[0042] The foregoing has described the structure and working principle of a fully digital fractional frequency-locked loop based on high-level synthesis according to an embodiment of this application. It can be recognized that, compared with existing pure register-transfer-level (RTL) implementation methods and pure high-level synthesis (HLS) implementation methods, this application has the following advantages: I. By adopting the register transfer level (RTL) implementation method, a time-critical time-to-digital converter (TDC) and feedback divider are implemented, ensuring precise nanosecond-level timing control. This enables the all-digital fractional frequency division phase-locked loop to be successfully locked, overcoming the fundamental defect of the pure high-level synthesis (HLS) implementation method that "cannot successfully lock the frequency".
[0043] II. A high-level synthesis (HLS) approach is adopted to implement an algorithm-intensive digital loop filter (DLF), which greatly improves development efficiency and algorithm flexibility, and allows for modification of loop parameters (K). P and K I The filter structure only requires modification of the C++ code and resynthesis, without rewriting the complex RTL state machine.
[0044] Third, based on the characteristics of the modules (time-critical, algorithm-intensive, and standard IP), a strategic division is made, which achieves a perfect combination of the high performance of register-transfer level (RTL) and the high efficiency of high-level synthesis (HLS), while retaining the portability of high-level synthesis (HLS) design and the reusability of standard IP cores.
[0045] Reference Figure 4 , Figure 4 This is a schematic diagram illustrating the steps of an implementation method for a high-level synthesis-based all-digital fractional frequency-locked loop (PLL) according to an embodiment of this application. The embodiment provides a method for implementing a high-level synthesis-based all-digital fractional frequency-locked loop, which is used to achieve the above-mentioned high-level synthesis-based all-digital fractional frequency-locked loop, including the following steps S101 to S104: Step S101: Using a time-to-digital converter, a phase error signal is output based on the externally input reference clock signal and the feedback clock signal input from the feedback divider. Step S102: Output a frequency control word based on the phase error signal through a digital loop filter; Step S103: Output a digital sine wave signal according to the frequency control word through a numerically controlled oscillator; Step S104: Output a feedback clock signal based on the digital sine wave signal using a feedback frequency divider; Among them, the time-to-digital converter is implemented based on the register transfer stage, the digital loop filter and feedback frequency divider are implemented based on high-level synthesis, and the numerically controlled oscillator is implemented based on IP cores.
[0046] As an optional implementation, step S101 can be further divided into the following steps S1011 to S1014: Step S1011: Receive the reference clock signal, the feedback clock signal, and the first system clock signal through a time-to-digital converter; Step S1012: Calculate the phase difference between the reference clock signal and the feedback clock signal based on the first system clock signal, and output the phase error signal.
[0047] Specifically, the time-to-digital converter (TDC) in this embodiment is implemented using the VerilogRTL hardware description language. For example... Figure 5 The diagram shows an RTL logic schematic of a time-to-digital converter (TDC) according to an embodiment of this application. First, the TDC receives an externally input reference clock signal rfclk (e.g., 50kHz-300kHz), a feedback clock signal fbclk from a feedback divider, and a first system clock signal clk (e.g., 100MHz). Internally, it includes a free-running counter cnt driven by the first system clock signal clk. Using edge detection logic (rfclk_rise, fbclk_rise) described in RTL, the current value of the free-running counter cnt is precisely latched into the cnt_rf and cnt_fb registers on the rising edges of the reference clock signal rfclk and the feedback clock signal fbclk. Next, phase difference calculation and judgment are performed. A combinational logic block calculates the difference between the two latched values and outputs a signed 12-bit phase error signal tdc_out and a tdc_valid signal.
[0048] If tdc_out <= {1'b0, (cnt_rf - cnt_fb)}, it indicates that the feedback clock is lagging behind, and the phase error signal tdc_out is a positive number; if tdc_out <= {1'b1, (cnt_fb - cnt_rf)}, it indicates that the feedback clock is leading, and the phase error signal tdc_out is a negative number.
[0049] It should be noted that the embodiments of this application implement the time-to-digital converter (TDC) based on register transfer level (RTL), which directly operates the clock edge and register at the hardware level, ensuring the measurement accuracy at the nanosecond level (10ns for a 100MHz clock period). This is the first key to the successful frequency locking of the embodiments of this application.
[0050] As an optional implementation, step S102 can be further divided into the following steps S1021 to S1022: Step S1021: Receive the phase error signal through a digital loop filter; Step S1022: Perform proportional and integral operations on the phase error signal and output the frequency control word.
[0051] Specifically, the digital loop filter (DLF) in this embodiment is implemented using HLS (C / C++ code). This module is implemented as a PI (proportional-integral) controller. It receives a 12-bit phase error signal tdc_out from the time-to-digital converter (TDC), performs proportional and integral operations on the phase error signal tdc_out, and generates a 16-bit frequency control word fcw.
[0052] As an optional implementation, step S1022 can be further divided into the following steps S10221 to S10226: Step S10221: Calculate the proportional term and integral term based on the phase error signal; Step S10222: Perform an integral saturation judgment on the integral term, and then clamp or update the integral term based on the integral saturation judgment result; Step S10223: Calculate the control increment based on the proportional term and the clamped or updated integral term; Step S10224: Calculate the output value of the frequency control word based on the control increment; Step S10225: Determine the maximum value and minimum value of the frequency control word; Step S10226: Based on the maximum and minimum values of the frequency control word, perform an output saturation judgment on the output value, and then output the output value, the maximum or minimum value of the frequency control word based on the output saturation judgment result.
[0053] As an optional implementation, step S10226 can be further divided into step A10226, step B10226, or step C10226: Step A10226: When the output value is greater than the minimum value of the frequency control word and less than the maximum value of the frequency control word, output the output value; Step B10226: When the output value is less than the minimum value of the frequency control word, output the minimum value of the frequency control word; Step C10226: When the output value is greater than the maximum value of the frequency control word, output the maximum value of the frequency control word.
[0054] Specifically, such as Figure 6The diagram shows the HLS code logic flowchart of a digital loop filter provided in one embodiment of this application. First, the integral term I and the proportional term P are calculated: In the C++ code, the integral term is defined using "static int i_part = 0". The `static` keyword is the core of the HLS state machine implementation. It instructs the HLS tool to synthesize i_part into a register that retains its value between function calls. This hardware implementation perfectly matches the characteristics of an integrator, where the integral value accumulates continuously over multiple operations. The formula for calculating the integral accumulation is: i_part = i_part + K I *(int)tdc_out; where K I tdc_out represents the integral gain coefficient, and tdc_out represents the input phase error signal. The formula for calculating the proportional term is: K P *(int)tdc_out; where K P This represents the proportional gain coefficient.
[0055] Next, an integral saturation check is performed on the integral term I. If it is saturated, the integral term I is clamped (its value is limited); if it is not saturated, the integral variable I_part is updated to the current integral value I. Then, the proportional term P and the integral term I are combined to calculate the control increment, the formula of which is: int fcw_delta=(K P * (int)tdc_out + i_part)>>4; where >>4 (right shift by 4 bits) is the standard practice in HLS for implementing hardware-friendly gain control (gain=1 / 16), which is synthesized into a simple wire-shift, avoiding the use of expensive dividers.
[0056] Furthermore, based on the control increment, the final output value of the frequency control word fcw is calculated using the formula: fcw = FCW_CENTER + fcw_delta; where FCW_CENTER represents the center value of the frequency control word, and fcw_delta represents the control increment. Next, output saturation is checked on the output value fcw. If the output value fcw is less than the minimum value MIN_FCW or greater than the maximum value MAX_FCW of the frequency control word, it indicates that the output value fcw is saturated, and the output fcw is clamped to the minimum or maximum value to prevent integral saturation and ensure loop stability. If the output value fcw is greater than the minimum value MIN_FCW and less than the maximum value MAX_FCW of the frequency control word, it indicates that the output value fcw is not saturated, and the frequency control word fcw is directly output.
[0057] It should be noted that the HLS tool can efficiently synthesize this C++ code into pipelined logic with extremely low latency (e.g., 0.0ns) and intervals of 1, enabling seamless integration with register-transfer-level (RTL) modules. Furthermore, this implementation is algorithmically flexible, allowing those skilled in the art to easily modify the gain coefficient K in the C++ code. P and K I This eliminates the need to rewrite complex RTL, which is the second key to the ease of maintenance and iteration of the embodiments of this application.
[0058] As an optional implementation, step S103 can be further divided into the following steps S1031 to S1034: Step S1031: Receive the frequency control word and the second system clock signal through the numerically controlled oscillator; Step S1032: Convert the frequency control word into phase gain; Step S1033: The phase gain is accumulated according to the second system clock signal through the phase accumulator in the numerically controlled oscillator to obtain the accumulation result; Step S1034: Output a digital sine wave signal based on the sine and cosine lookup table and the accumulation result.
[0059] Specifically, the numerically controlled oscillator (NCO) in this embodiment uses the DDSCompilerv6.0 IP core provided by the FPGA. This IP core is configured as a "Phase Generator and SINCOSLUT". The configured parameters include: a 100MHz second system clock signal, a 16-bit phase width, a 32-bit (floating-point) output width, and streaming phase increment programmability.
[0060] like Figure 7 The diagram shown is an internal logic schematic of a numerically controlled oscillator (NCO) according to an embodiment of this application. The 16-bit streaming phase input (S_AXIS_PHASE) of the NCO is perfectly matched with the 16-bit frequency control word fcw of the digital loop filter (DLF). The frequency control word fcw is used as the phase increment ( θ) is input to the numerically controlled oscillator (NCO). The phase accumulator of the NCO accumulates the frequency control word fcw every 100MHz clock cycle and generates a frequency of θ using a sine / cosine lookup table. The 32-bit floating-point digital sine wave signal sin_out.
[0061] As an optional implementation, step S104 can be further divided into the following steps S1041 to S1044: Step S1041: Receive the digital sine wave signal and the target frequency division coefficient through the feedback frequency divider; Step S1042: Invert the sign bit of the digital sine wave signal to obtain a square wave signal; Step S1043: Divide the square wave signal according to the target frequency division coefficient to obtain the feedback clock signal; Step S1044: Output the feedback clock signal to the time-to-digital converter.
[0062] Specifically, the feedback divider in this embodiment is implemented using the Verilog RTL hardware description language. For example... Figure 8 The diagram shows the RTL logic of a feedback divider according to one embodiment of this application. First, the feedback divider receives a target multiplication factor (div_factor, e.g., a target multiplication factor of 32) and a clock input (clk_in). It is implemented as an RTL counter, which counts under the drive of clk_in. When the RTL counter reaches div_factor-1, it toggles clk_out and resets the RTL counter, ultimately generating a feedback clock signal and feeding it back to the time-to-digital converter (TDC), forming a closed loop.
[0063] It should be noted that this embodiment provides an extremely efficient signal source for the clk_in of the feedback divider. Instead of using a complex zero-crossing comparator, this embodiment directly inverts the sign bit of the 32-bit single-precision floating-point digital sine wave signal sin_out output from the numerically controlled oscillator (NCO) to generate a square wave of the same frequency. That is, the clk_in of the feedback divider is directly connected to the sign bit of the digital sine wave signal sin_out, achieving zero-latency, zero-resource-overhead conversion from a digital sine wave to a square wave. This is the third key aspect of this embodiment's avoidance of the HLS trap and its optimization using RTL principles.
[0064] As an optional implementation method, the method for implementing a high-level synthesis-based all-digital fractional-frequency-locked loop further includes the following step S105: Step S105: The modulator outputs a digital sequence according to the frequency control word. The digital sequence is used to control the division ratio of the feedback divider.
[0065] Furthermore, the hybrid architecture of this application embodiment can achieve high-precision fractional-division frequency synthesis by introducing a Delta-Sigma modulator (DSM). The frequency control word is converted into a digital sequence by the modulator (DSM), and then the division ratio of the feedback divider is controlled by the digital sequence.
[0066] The contents of the above-described all-digital fractional frequency-locked loop embodiments are all applicable to this method embodiment. The specific functions implemented in this method embodiment are the same as those in the above-described all-digital fractional frequency-locked loop embodiments, and the beneficial effects achieved are also the same as those achieved in the above-described all-digital fractional frequency-locked loop embodiments.
[0067] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0068] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.
[0069] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.
Claims
1. A fully digital fractional-frequency-locked phase-locked loop based on high-level synthesis, characterized in that, include: A time-to-digital converter, implemented based on a register transfer stage, is used to output a phase error signal based on an externally input reference clock signal and a feedback clock signal input from a feedback divider. A digital loop filter, the input of which is connected to the output of the time-to-digital converter, is implemented based on high-level synthesis and is used to output a frequency control word according to the phase error signal; A numerically controlled oscillator, the input of which is connected to the output of the digital loop filter, is implemented based on an IP core and is used to output a digital sine wave signal according to the frequency control word; The feedback frequency divider, whose input is connected to the output of the numerically controlled oscillator and whose output is connected to the input of the time-to-digital converter, is implemented based on high-level synthesis and is used to output the feedback clock signal according to the digital sine wave signal.
2. The all-digital fractional frequency division phase-locked loop according to claim 1, characterized in that, The all-digital fractional frequency division phase-locked loop also includes: A modulator, the input of which is connected to the output of the digital loop filter, and the modulator is also connected to the feedback divider, for outputting a digital sequence according to the frequency control word, the digital sequence being used to control the division ratio of the feedback divider.
3. A method for implementing a fully digital fractional-frequency-locked loop based on high-level synthesis, wherein the loop is implemented using a fully digital fractional-frequency-locked loop based on high-level synthesis as described in any one of claims 1 to 2, characterized in that... Includes the following steps: The phase error signal is output by the time-to-digital converter based on the externally input reference clock signal and the feedback clock signal input by the feedback divider. Based on the phase error signal, a frequency control word is output through a digital loop filter; A digital sine wave signal is output through a numerically controlled oscillator according to the frequency control word; The feedback frequency divider outputs the feedback clock signal based on the digital sine wave signal. The time-to-digital converter is implemented based on a register transfer stage, the digital loop filter and the feedback frequency divider are implemented based on high-level synthesis, and the numerically controlled oscillator is implemented based on an IP core.
4. The method according to claim 3, characterized in that, The step of using a time-to-digital converter to output a phase error signal based on an externally input reference clock signal and a feedback clock signal input from a feedback divider specifically includes: The reference clock signal, the feedback clock signal, and the first system clock signal are received through the time-to-digital converter. Based on the first system clock signal, the phase difference between the reference clock signal and the feedback clock signal is calculated, and the phase error signal is output.
5. The method according to claim 3, characterized in that, The step of outputting a frequency control word based on the phase error signal through a digital loop filter specifically includes: The phase error signal is received through the digital loop filter; The phase error signal is subjected to proportional and integral operations to output the frequency control word.
6. The method according to claim 5, characterized in that, The step of performing proportional and integral operations on the phase error signal and outputting the frequency control word specifically includes: Calculate the proportional term and integral term based on the phase error signal; The integral term is subjected to an integral saturation judgment, and then the integral term is clamped or updated based on the integral saturation judgment result; Calculate the control increment based on the proportional term and the clamped or updated integral term; Calculate the output value of the frequency control word based on the control increment; Determine the maximum and minimum values of the frequency control word; Based on the maximum value and the minimum value of the frequency control word, an output saturation judgment is performed on the output value, and then the output value, the maximum value of the frequency control word, or the minimum value of the frequency control word is output according to the output saturation judgment result.
7. The method according to claim 6, characterized in that, The step of performing an output saturation judgment on the output value based on the maximum value and the minimum value of the frequency control word, and then outputting the output value, the maximum value of the frequency control word, or the minimum value of the frequency control word according to the output saturation judgment structure, specifically includes: When the output value is greater than the minimum value of the frequency control word and less than the maximum value of the frequency control word, the output value is output. When the output value is less than the minimum value of the frequency control word, output the minimum value of the frequency control word; When the output value is greater than the maximum value of the frequency control word, the maximum value of the frequency control word is output.
8. The method according to claim 3, characterized in that, The step of outputting a digital sine wave signal via a numerically controlled oscillator according to the frequency control word specifically includes: The frequency control word and the second system clock signal are received through the numerically controlled oscillator. Convert the frequency control word into phase gain; The phase gain is accumulated according to the second system clock signal through the phase accumulator in the numerically controlled oscillator to obtain the accumulation result; Based on the sine and cosine lookup table and the accumulated result, the digital sine wave signal is output.
9. The method according to claim 3, characterized in that, The step of outputting the feedback clock signal based on the digital sine wave signal through the feedback frequency divider specifically includes: The digital sine wave signal and the target frequency division coefficient are received through the feedback frequency divider; Invert the sign bit of the digital sine wave signal to obtain a square wave signal; The square wave signal is divided according to the target frequency division coefficient to obtain the feedback clock signal; The feedback clock signal is output to the time-to-digital converter.
10. The method according to claim 3, characterized in that, The method further includes: The modulator outputs a digital sequence based on the frequency control word, and the digital sequence is used to control the division ratio of the feedback divider.