Implementing Early Execution of an Immediate Move Instruction with a Variable Immediate Value Size in a Processor-Based Device

Abstract

Disclosed is the early execution of an immediate move instruction with a variable immediate value size in a processor-based device. In one exemplary embodiment, the processor-based device provides an immediate move logic circuit for detecting an immediate move instruction, the immediate move instruction including an immediate value and a destination register. For frequently encountered immediate values, the immediate move logic circuit allocates a physical register from an immediate physical register file (IPRF), and writes an IPRF tag corresponding to the allocated IPRF register into the most recent mapping table (MRT) entry of the destination register. Subsequent immediate move instructions and other dependent instructions embedding the same immediate value can then obtain the immediate value from the IPRF register by accessing the MRT entry. Additionally, the PE provides a frequent immediate table (FIT) for tracking the occurrences of immediate values, and allocates an IPRF register for a given immediate value only when the occurrence count of that immediate value exceeds the FIT threshold.

Description

Technical Field

[0001] The techniques of the present disclosure relate to the execution of immediate move instructions in processor-based devices, and more particularly to enabling early execution of immediate move instructions with variable immediate value sizes. Background Art

[0002] An immediate move instruction (e.g., MOVI) is an instruction provided by modern instruction set architectures (ISAs) for storing a constant value that is encoded as part of the immediate move instruction itself rather than retrieved from a specified register or memory address. As a non-limiting example, immediate move instructions are often used for purposes such as loading a constant value from an instruction stream, assigning an offset value to a load or store instruction, or assigning a branch offset. Because immediate move instructions do not require the use of complex arithmetic units, these immediate move instructions can be executed earlier within the execution pipeline of an out-of-order processor (e.g., at the rename stage of the execution pipeline). Such early execution of immediate move instructions can enable the acceleration of the execution of subsequent instructions that depend on the immediate move instruction, since the dependent instructions do not have to wait for their input operands that originate from the immediate move instruction.

[0003] However, in order to realize the benefits of early execution, the relevant instructions must know the immediate value encoded in the immediate move instruction and carry it along, or alternatively, must be able to access information about the physical location of the immediate value. For example, consider the following dependency chain of instructions I0 and I1:

[0004] I0: MOVI R1, #FA4D / / Move the immediate value #FA4D into register R1

[0005] I1: ADDI R2, R1, #1 / / Add the immediate value #1 to the content of register R1 and store the sum in register R2

[0006] In the above example, instruction I0 can be executed at the rename stage of the execution pipeline. In order to make instruction I1 independent of instruction I0 (i.e., break the dependency between instruction I1 and I0, thus accelerating the execution of instruction I1), the immediate value #FA4D should first be known, and then the immediate value #FA4D should be carried along, or the immediate value #FA4D should be accessible when instruction I1 is executed.

[0007] Based on the underlying ISA, the immediate value that is encoded as part of an immediate move instruction can have a variable size. However, designing a processor-based device to carry the maximum possible immediate value size throughout the execution pipeline can result in a significant processor area and power overhead. One way to mitigate such overhead is called "physical register inlining" and involves executing immediate move instructions with small immediate values at the rename stage of the execution pipeline. The small immediate values can then be embedded in the most recent mapping table (MRT) entries, where dependent instructions can access the small immediate values instead of the physical register names. Another approach allows immediate move instructions to be executed at the rename stage by writing their immediate values to a regular physical register. Dependent instructions can then be renamed to use the physical register and carry the physical register tag (which can be accessed before execution). This second approach can allow the use of larger immediate values than physical register inlining, but at the cost of requiring additional expensive write ports to the physical register file (PRF).

[0008] Accordingly, there is a need for a more efficient mechanism for implementing early execution of immediate move instructions with variable immediate value sizes. SUMMARY OF THE INVENTION

[0009] Exemplary embodiments disclosed herein include: enabling early execution of immediate move instructions with variable immediate value sizes in a processor-based device. In this regard, in one exemplary embodiment, a processor-based device provides a processing element (PE) that implements a hybrid method allowing an immediate move instruction to be executed at the rename stage of the PE's execution pipeline. The execution pipeline includes immediate move logic circuitry for detecting an immediate move instruction that includes an immediate value and a destination register. The immediate move logic circuitry allocates a physical register from a dedicated register pool referred to as an immediate physical register file (IPRF) and writes an IPRF tag corresponding to the allocated IPRF register into the latest mapping table (MRT) entry corresponding to the destination register (in some embodiments, together with a content indicator indicating that the MRT entry refers to the contents of the IPRF register). Subsequent immediate move instructions and other related instructions embedding the same immediate value can then obtain the immediate value from the IPRF register by accessing the MRT entry. In some embodiments, only immediate values that are too large to be stored in an MRT entry in a conventional manner are allocated an IPRF register. In some embodiments, the IPRF can physically be part of a general-purpose physical register file (PRF) or can be a separate physical structure. Additionally, the PE provides a frequent immediate table (FIT) for tracking the occurrences of immediate values and allocates an IPRF register for a given immediate value only when the occurrence count of that immediate value exceeds a FIT threshold.

[0010] In another exemplary embodiment, a processor-based device is provided. The processor-based device includes a PE that includes an instruction pipeline that includes immediate move logic circuitry. The PE further includes: an MRT that includes a plurality of MRT entries; a FIT that includes a plurality of FIT entries; and an IPRF that includes a plurality of IPRF registers. The PE is configured to use the immediate move logic circuitry of the execution pipeline to detect an immediate move instruction that includes an immediate value and a destination register. The PE is further configured to determine whether a FIT entry in the plurality of FIT entries of the FIT corresponds to the immediate value. The PE is further configured to: in response to determining that the FIT entry in the FIT corresponds to the immediate value, determine whether the FIT entry contains a valid IPRF tag corresponding to an IPRF register in the plurality of IPRF registers of the IPRF. The PE is additionally configured to: in response to determining that the FIT entry contains a valid IPRF tag corresponding to an IPRF register of the IPRF, write the IPRF tag of the IPRF register into the MRT entry in the plurality of MRT entries of the MRT that corresponds to the destination register.

[0011] In another exemplary embodiment, a method for implementing early execution of an immediate move instruction with a variable immediate value size is provided. The method includes: detecting, by immediate move logic circuitry of an execution pipeline of a PE of a processor-based device, a first immediate move instruction that includes a first immediate value and a first destination register. The method further includes: determining that a FIT entry among a plurality of FIT entries of a FIT corresponds to the first immediate value. The method further includes: in response to determining that a first FIT entry of the FIT corresponds to the first immediate value, determining that the first FIT entry includes a valid IPRF tag corresponding to a first IPRF register among a plurality of IPRF registers of an IPRF. The method additionally includes: in response to determining that the first FIT entry includes the valid first IPRF tag corresponding to the first IPRF register of the IPRF, writing the first IPRF tag of the first IPRF register to a first MRT entry among a plurality of MRT entries of an MRT, the first MRT entry corresponding to the first destination register.

[0012] In another exemplary embodiment, a non-transitory computer-readable medium is provided. The computer-readable medium stores computer-executable instructions thereon that, when executed by a processor, cause the processor to detect an immediate move instruction that includes an immediate value and a destination register. The computer-executable instructions further cause the processor to determine whether a FIT entry among a plurality of FIT entries of a FIT corresponds to the immediate value. The computer-executable instructions further cause the processor to: in response to determining that a FIT entry of the FIT corresponds to the immediate value, determine whether the FIT entry includes a valid IPRF tag corresponding to an IPRF register among a plurality of IPRF registers of an IPRF. The computer-executable instructions additionally cause the processor to: in response to determining that the FIT entry includes the valid IPRF tag corresponding to the IPRF register of the IPRF, write the IPRF tag of the IPRF register to an MRT entry among a plurality of MRT entries of an MRT, the MRT entry corresponding to the destination register.

[0013] After reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will appreciate the scope of the present disclosure and implement its additional embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0015] Figure 1is a block diagram of an exemplary processor-based device that includes a processing element (PE), the processing element includes an execution pipeline, the execution pipeline includes immediate move logic circuitry configured to implement early execution of an immediate move instruction with a variable immediate value size;

[0016] Figure 2 is a block diagram illustrating an exemplary embodiment of a frequent immediate table (FIT), an immediate physical register file (IPRF), a most recent mapping table (MRT), and the entry contents therein;

[0017] Figure 3 is a flowchart illustrating an exemplary operation for implementing early execution of an immediate move instruction with a variable immediate value size according to some embodiments;

[0018] Figure 4A and Figure 4B is a flowchart illustrating some other exemplary operations for filling and accessing Figure 1 and Figure 2 the FIT and IPRF; and

[0019] Figure 5 is a block diagram of an exemplary processor-based device (such as Figure 1 a processor-based device) configured to implement early execution of an immediate move instruction with a variable immediate value size. DETAILED DESCRIPTION

[0020] Exemplary embodiments disclosed herein include: enabling early execution of an immediate move instruction having a variable immediate value size in a processor-based device. In this regard, in one exemplary embodiment, a processor-based device provides a processing element (PE) that implements a hybrid approach allowing an immediate move instruction to execute at the rename stage of the PE's execution pipeline. The execution pipeline includes immediate move logic circuitry that detects an immediate move instruction that includes an immediate value and a destination register. The immediate move logic circuitry allocates a physical register from a dedicated register pool referred to as an immediate physical register file (IPRF) and writes an IPRF tag corresponding to the allocated IPRF register to the most recent mapping table (MRT) entry corresponding to the destination register (in some embodiments, along with a content indicator indicating that the MRT entry refers to an IPRF register). Subsequent immediate move instructions and other related instructions that embed the same immediate value can then obtain the immediate value from the IPRF register by accessing the MRT entry. In some embodiments, only immediate values that are too large to be stored in an MRT entry in a conventional manner are allocated an IPRF register. In some embodiments, the IPRF can physically be part of a general-purpose physical register file (PRF) or can be a separate physical structure. Additionally, some embodiments can provide a frequent immediate table (FIT) for tracking the occurrence of immediate values and can allocate an IPRF register for a given immediate value only when the occurrence count of that immediate value exceeds a FIT threshold.

[0021] In this regard, Figure 1 FIG. illustrates an exemplary processor-based device 100 that provides a processing element (PE) 102 for processing executable instructions. The PE 102 can include a central processing unit (CPU) having one or more processor cores or can include a separate processor core that includes logical execution units and associated caches and functional units. Figure 1 The PE 102 includes an execution pipeline 104 that is configured to perform out-of-order execution of an instruction stream that includes computer-executable instructions. In Figure 1In the example of, execution pipeline 104 includes an instruction fetch stage 106 for retrieving instructions for execution and a decode stage 108 for converting the fetched instructions into control signals for instruction execution. Execution pipeline 104 also includes a rename stage 110 for allocating physical register file (PRF) registers 112(0)-112(R) from PRF 114 and a dispatch stage 116 for issuing instructions for execution. Finally, the execution pipeline also includes an execution stage 118 for sending instructions and operands to an execution unit (not shown), and a commit stage 120 for irreversibly updating the architectural state of PE 102 based on the results of instruction execution. It should be understood that some embodiments of processor-based device 100 may include multiple PEs 102 instead of Figure 1 the single PE 102 shown in the example of, and it should also be understood that some embodiments of PE 102 may include fewer or more stages within execution pipeline 104 than Figure 1 the number of stages illustrated in the example of.

[0022] As mentioned above, PE 102 includes PRF 114, which contains multiple PRF registers 112(0)-112(R). The PRF registers 112(0)-112(R) of PRF 114 can be individually addressed and used as an intermediate data storage device between the system memory (not shown) of PE 102 and functional units (not shown). To implement register renaming, PE 102 also includes a most recent mapping table (MRT) 122, which contains multiple MRT entries 124(0)-124(M). As discussed in more detail below with respect to Figure 2 each of the MRT entries 124(0)-124(M) represents a mapping of a logical register to one of the PRF registers 112(0)-112(R) of PRF 114, which enables PE 102 to establish data dependencies between instructions.

[0023] Figure 1 Processor-based device 100 and its constituent elements can encompass any of the known digital logic elements, semiconductor circuits, processing cores, and / or memory structures and other elements or combinations thereof. The embodiments described herein are not limited to any particular arrangement of elements, and the disclosed techniques can be readily extended to various structures and layouts on a semiconductor socket or package. It should be understood that some embodiments of processor-based device 100 include elements in addition to Figure 1 those illustrated in. For example, PE 102 may also include one or more functional units, instruction caches, unified caches, memory controllers, interconnect buses, and / or additional memory devices, caches, and / or controller circuits.

[0024] As discussed above, since immediate move instructions do not require the use of a complex arithmetic unit, these immediate move instructions can be executed earlier within the execution pipeline 104 of the PE 102 (e.g., at the rename stage 110 of the execution pipeline 104). This early execution of immediate move instructions can also accelerate the execution of subsequent instructions that depend on the immediate move instructions, since the dependent instructions do not have to wait for their input operands that originate from the immediate move instructions. However, the variable size of immediate values poses a challenge to efficient early execution. For example, designing the processor-based device 100 to carry the maximum possible immediate value size throughout the execution pipeline 104 may result in a significant processor area and power overhead. Also, other methods may only be effective for smaller intermediate values or may require additional expensive write ports to the PRF 114.

[0025] In this regard, the PE 102 is configured to enable early execution of immediate move instructions with variable immediate value sizes within the processor-based device 100. To achieve this, the execution pipeline 104 includes immediate move logic circuitry 126, which can be implemented as a separate element within the execution pipeline 104 as shown in Figure 1 or integrated, in whole or in part, within one or more stages of the execution pipeline 104. As a non-limiting example, the immediate move logic circuitry 126 can be integrated into the rename stage 110 and / or the commit stage 120 of the execution pipeline 104. The PE 102 also includes dedicated storage for immediate values in the form of an immediate physical register file (IPRF) 128, which includes a plurality of IPRF registers 130(0)-130(P). In some embodiments, the IPRF 128 can be implemented as a physical structure separate from the PRF 114 as shown in Figure 1 or can be a subset of registers within the PRF 114. Finally, the PE 102 includes a frequent immediate table (FIT) 132, which includes a plurality of FIT entries 134(0)-134(F). As discussed in more detail below with respect to Figure 2 the FIT 132 is used to track the occurrence of immediate values and enables the immediate move logic circuitry 126 to limit the allocation of the IPRF registers 130(0)-130(P) to only frequently encountered immediate values.

[0026] To enable early execution of immediate move instructions with variable immediate value sizes, the immediate move logic circuit 126 of the execution pipeline 104 detects an immediate move instruction 136 that includes an immediate value 138 and a destination register 140. The immediate move logic circuit 126 determines (e.g., at the rename stage 110 of the execution pipeline 104) whether one of the FIT entries 134(0)-134(F) in the FIT 132 corresponds to the immediate value 138. If it is determined that one of the FIT entries 134(0)-134(F) corresponds to the immediate value 138, the immediate move logic circuit 126 then determines whether the FIT entry 134(F) contains a valid IPRF tag corresponding to one of the IPRF registers 130(0)-130(P) of the IPRF 128. If it is determined that the FIT entry 134(F) contains a valid IPRF tag corresponding to one of the IPRF registers 130(0)-130(P) of the IPRF 128, the immediate move logic circuit 126 writes the IPRF tag of the corresponding IPRF register 130(0)-130(P) to one of the MRT entries 124(0)-124(M) of the MRT 122 that corresponds to the destination register 140 of the immediate move instruction 136. In this way, subsequent immediate move instructions and other related instructions that embed the same immediate value 138 can access the MRT entries 124(0)-124(M) and, based on the IPRF tag stored in the MRT entries 124(0)-124(M), access the corresponding IPRF registers 130(0)-130(P), thus enabling early execution.

[0027] Operations for allocating and accessing the FIT entries 134(0)-134(F) of the FIT 132 and the IPRF registers 130(0)-130(P) of the IPRF 128 are discussed in more detail below with respect to Figure 2 which is discussed in more detail. Note that in some embodiments, the IPRF registers 130(0)-130(P) may be allocated only for immediate values that occur at a frequency higher than the FIT threshold 142. The FIT threshold 142 according to some embodiments may be dynamically updated based on the program phase of the executing program.

[0028] Figure 2 More specifically, it illustrates the content and interaction among the FIT 132, the IPRF 128, and the MRT 122 when the immediate move logic circuit 126 processes the immediate move instruction 136 according to an exemplary embodiment. As described above with respect to Figure 1 the immediate move logic circuit 126 processes the immediate move instruction 136 Figure 1 the content and interaction among the FIT 132, the IPRF 128, and the MRT 122. Figure 1As mentioned, in some embodiments, the FIT 132 is used to track the occurrences of immediate values (such as immediate value 138). Thus, the FIT 132 enables Figure 1 the immediate move logic circuit 126 of Figure 1 to allocate IPRF registers among the multiple IPRF registers 130(0)-130(P) only for frequently occurring immediate values. Each of the FIT entries 134(0)-134(F) in the FIT 132 includes a corresponding immediate value tag 200(0)-200(F) that associates the corresponding immediate value with that FIT entry 134(0)-134(F). As a non-limiting example, the immediate value tags 200(0)-200(F) may include a subset of bits of the corresponding immediate value or a hash value generated based on the corresponding immediate value. Each of the FIT entries 134(0)-134(F) also includes a corresponding IPRF tag 202(0)-202(F) that can be used to indicate which of the multiple IPRF registers 130(0)-130(P) (if any) stores the immediate value associated with that FIT entry 134(0)-134(F). The IPRF tags 202(0)-202(F) may include, for example, the register numbers of the corresponding IRPF registers 130(0)-130(P). The FIT entries 134(0)-134(F) also include corresponding count values 204(0)-204(F) that can be used to track how many times the immediate value associated with the FIT entry 134(0)-134(F) has been encountered. According to some embodiments, the count values 204(0)-204(F) may include N-bit saturated counters, where N specifies the implementation-specific number of bits of the count values 204(0)-204(F). Some embodiments may also provide that the FIT entries 134(0)-134(F) additionally include replacement metadata 206(0)-206(F) that can be used to implement a FIT replacement policy, as discussed in more detail below.

[0029] The IPRF 128 provides a pool of IPRF registers 130(0)-130(P) for storing immediate values, such as immediate value 138. As a non-limiting example, each of the IPRF registers 130(0)-130(P) is associated with a corresponding IPRF tag 208(0)-208(P), which may include the register number of the IPRF register 130(0)-130(P). In some embodiments, the IPRF tags 208(0)-208(P) may be associated with the corresponding IPRF registers 130(0)-130(P) and used to identify the corresponding IPRF registers 130(0)-130(P), but may not be explicitly stored as part of the IPRF registers 130(0)-130(P) as shown in Figure 2 In the figure. The IPRF registers 130(0)-130(P) also each store a corresponding immediate value 210(0)-210(P) for later retrieval by an early-executed immediate move instruction and / or other related instructions.

[0030] Finally, each of the MRT entries 124(0)-124(M) of the MRT 122 stores data that is conventionally used to map logical registers to physical registers for register renaming purposes. Thus, the MRT entries 124(0)-124(M) include logical register tags 212(0)-212(M) (e.g., the register numbers of the logical registers) and corresponding physical register tags 214(0)-214(M) (e.g., the register numbers of the PRF registers 112(0)-112(R) or the IPRF registers 130(0)-130(P) of the PRF 114). To facilitate the use of the IPRF registers 130(0)-130(P) to store immediate values, the MRT entries 124(0)-124(M) also provide content indicators 216(0)-216(M) to indicate to the immediate move logic circuit 126 the type of content stored in the MRT entries 124(0)-124(M). For example, in some embodiments, the content indicators 216(0)-216(M) include a two (2)-bit indicator with four potential values. A value of "00" indicates that the corresponding MRT entry 124(0)-124(M) is being used for conventional register renaming, and thus the MRT entry 124(0)-124(M) points to one of the PRF registers 112(0)-112(R) of the PRF 114. A value of "01" indicates that the corresponding MRT entry 124(0)-124(M) stores a small immediate value directly within the MRT entry 124(0)-124(M). A value of "10" indicates that the corresponding MRT entry 124(0)-124(M) points to one of the IPRF registers 130(0)-130(P) of the IPRF 128. Finally, a value of "11" may be reserved or may indicate undefined behavior or an invalid state.

[0031] In an exemplary operation, the immediate move logic circuit 126 of the execution pipeline 104 detects an immediate move instruction 136 that includes an immediate value 138 and a destination register 140. The immediate move logic circuit 126 determines (e.g., at the rename stage 110 of the execution pipeline 104) whether one of the immediate value tags 200(0)-200(F) of the FIT entries 134(0)-134(F) corresponds to the immediate value 138. In Figure 2 the example, it is assumed that the FIT entry 134(F) corresponds to the immediate value 138, as indicated by the arrow 218. The immediate move logic circuit 126 next determines whether the FIT entry 134(F) contains a valid IPRF tag 202(F) corresponding to one of the IPRF registers 130(0)-130(P) of the IPRF 128. In Figure 2In this case, the IPRF tag 202(F) of the FIT entry 134(F) corresponds to the IPRF register 130(0), as indicated by arrow 220. This means that the immediate value 138 has previously been encountered by the immediate move logic circuit 126, and the IPRF register 130(0) has been allocated to store the immediate value 138 as the immediate value 210(0).

[0032] The immediate move logic circuit 126 then writes the IPRF tag 208(0) of the IPRF register 130(0) into one of the MRT entries 124(0)-124(M) of the MRT 122, where the MRT entry has a logical register tag 212(0)-212(M) corresponding to the destination register 140 of the immediate move instruction 136, as indicated by arrow 222. As Figure 2 seen, the MRT entry 124(M) is assumed to correspond to the destination register 140, so the IPRF tag 208(0) of the IPRF register 130(0) is written into the MRT entry 124(M). In some embodiments, the content indicator 216(M) is also updated to indicate that the MRT entry 124(M) points to the IPRF register 130(0). In this way, subsequent immediate move instructions embedding the same immediate value 138 and other dependent instructions can access the MRT entry 124(M) and access the immediate value 210(0) from the IPRF register 130(0) based on the content indicator 216(M) and the IPRF tag 208(0) stored in the MRT entry 124(M).

[0033] In some embodiments, the immediate move logic circuit 126 can first determine whether the size of the immediate value 138 exceeds the size of the MRT entries 124(0)-124(M) (i.e., whether the immediate value 138 is too large to be stored in one of the MRT entries 124(0)-123(M)). If the immediate value 138 does not exceed the size of the MRT entries 124(0)-124(M), the immediate move logic circuit 126 can directly store the immediate value 138 in one of the MRT entries 124(0)-124(M) corresponding to the destination register 140.

[0034] According to some embodiments, if the immediate move logic circuit 126 determines that none of the FIT entries 134(0)-134(F) of the FIT 132 corresponds to the immediate value 138, the immediate move logic circuit 126 may reclaim one of the existing FIT entries 134(0)-134(F) according to a FIT replacement policy, and then use the reclaimed FIT entry 134(0)-134(F) to store the immediate value 138. As a non-limiting example, the FIT replacement policy may include reclaiming one of the FIT entries 134(0)-134(F) having the lowest count value 204(0)-204(F), and / or may include reclaiming the least recently used existing FIT entry 134(0)-134(F). In the latter scenario, the least recently used existing FIT entry 134(0)-134(F) may be determined based on the replacement metadata 206(0)-206(F) stored within the FIT entry 134(0)-134(F). Such a FIT replacement policy can be particularly useful in cases where a particular immediate value occurs frequently during a particular phase of an executing program but not during other phases, even if the corresponding count values 204(0)-204(F) have reached high values.

[0035] Some embodiments provide that if the immediate move logic circuit 126 determines that a FIT entry (such as FIT entry 134(F)) exists for an immediate value 138 but does not contain a valid IPRF tag 202(F), then the immediate move logic circuit 126 determines whether the count value 204(F) of the FIT entry 134(F) exceeds the FIT threshold 142. If it is determined that the count value 204(F) of the FIT entry 134(F) exceeds the FIT threshold 142, then the immediate move logic circuit 126 may conclude that the immediate value 138 has occurred at a sufficient frequency to justify allocating one of the IPRF registers 130(0)-130(P) to the immediate value 138. Accordingly, the immediate move logic circuit 126 allocates an IPRF register (such as IPRF register 130(0)), writes the IPRF tag 208(0) of the IPRF register 130(0) into the IPRF tag 202(F) of the FIT entry 134(F), and writes the immediate value 138 into the immediate value 210(0) of the IPRF register 130(0). In some embodiments, the immediate value 138 may be written into the allocated IPRF register 130(0) at the rename stage 110 of the execution pipeline 104, which may require the IPRF 128 to have an additional write port from the rename stage 110. If the count value 204(F) of the FIT entry 134(F) does not exceed the FIT threshold 142, then the immediate move logic circuit 126 may increment the count value 204(F) of the FIT entry 134(F) (e.g., during the commit stage 120 of the execution pipeline 104).

[0036] To illustrate exemplary operations for implementing early execution of an immediate move instruction with variable immediate value sizes in accordance with some embodiments, Figure 3 is provided. For clarity, Figure 1 and Figure 2 the elements of Figure 3 are referenced in the description Figure 3 The operation in begins with the immediate move logic circuit 126 of the execution pipeline 104 of the PE 102 of the processor-based device 100 detecting an immediate move instruction 136, which includes an immediate value 138 and a destination register 140 (block 302). The immediate move logic circuit 126 determines that a FIT entry (such as FIT entry 134(F)) among the plurality of FIT entries 134(0)-134(F) of the FIT 132 corresponds to the immediate value 138 (block 304).

[0037] In response to determining that the FIT entry 134(F) in the FIT 132 corresponds to the immediate value 138, the immediate move logic circuit 126 next determines that the FIT entry 134(F) includes a valid IPRF tag 202(F) corresponding to an IPRF register (such as the IPRF register 130(0)) among the multiple IPRF registers 130(0)-130(P) of the IPRF 128 (block 306). In response to determining that the FIT entry 134(F) includes the valid IPRF tag 202(F) corresponding to the IPRF register 130(0) of the IPRF 128, the immediate move logic circuit 126 writes the IPRF tag 208(0) of the IPRF register 130(0) into an MRT entry (such as the MRT entry 124(M)) among the multiple MRT entries 124(0)-124(M) of the MRT 122, and this MRT entry corresponds to the destination register 140 (block 308).

[0038] Figure 4A and Figure 4B illustrates in more detail other exemplary operations of the FIT 132 and the IPRF 128 for filling and accessing Figure 1 and Figure 2 . For clarity, Figure 1 and Figure 2 the components of Figure 4A and Figure 4B are referenced when describing Figure 4AIn this process, the operation begins when the immediate move logic circuit 126 detects an immediate move instruction 136, which includes an immediate value 138 and a destination register 140 (block 402). In some embodiments, the immediate move logic circuit 126 may determine whether the size of the immediate value 138 exceeds the size of each MRT entry among the multiple MRT entries 124(0)-124(M) of the MRT 122 (block 404). If it is determined that the size of the immediate value 138 does not exceed the size of each MRT entry among the multiple MRT entries 124(0)-124(M) of the MRT 122, the immediate value 138 is stored in an MRT entry (such as MRT entry 124(0)) among the multiple MRT entries 124(0)-124(M) of the MRT 122 that corresponds to the destination register 140 (block 406). However, if the immediate move logic circuit 126 determines in decision block 404 that the size of the immediate value 138 does not exceed the size of each MRT entry among the multiple MRT entries 124(0)-124(M) of the MRT 122, then in some embodiments, the immediate move logic circuit 126 may next determine whether a FIT entry among the multiple FIT entries 134(0)-134(F) of the FIT 132 corresponds to the immediate value 138 (block 408). If it is determined that a FIT entry among the multiple FIT entries 134(0)-134(F) of the FIT 132 corresponds to the immediate value 138, the process continues in Figure 4B block 410.

[0039] If the immediate move logic circuit 126 determines in decision block 408 that none of the FIT entries 134(0)-134(F) within the FIT 132 corresponds to the immediate value 138, then in accordance with some embodiments, the immediate move logic circuit 126 may reclaim an existing FIT entry among the multiple FIT entries 134(0)-134(F) of the FIT 132, such as FIT entry 134(0), according to a FIT replacement policy (block 412). Some embodiments may stipulate that the operation of block 412 for reclaiming the existing FIT entry 134(0) may include reclaiming the existing FIT entry 134(0) having the lowest count value 204(0)-204(F) among the multiple FIT entries 134(0)-134(F) of the FIT 132 (block 414). In accordance with some embodiments, the operation of block 412 for reclaiming the existing FIT entry 134(0) may include reclaiming the least recently used existing FIT entry 134(0) among the multiple FIT entries 134(0)-134(F) of the FIT 132 (block 416). The immediate move logic circuit 126 may then store the immediate value 138 in the existing FIT entry 134(0) of the FIT 132 (block 418).

[0040] Now refer to Figure 4B , if the immediate move logic circuit 126 determines in decision block 408 of Figure 4A that a FIT entry (such as FIT entry 134(F)) among the multiple FIT entries 134(0)-134(F) of the FIT 132 corresponds to the immediate value 138, the immediate move logic circuit 126 can then determine whether the FIT entry 134(F) contains a valid IPRF tag 202(F) corresponding to an IPRF register among the multiple IPRF registers 130(0)-130(P) of the IPRF 128 (block 410). If it is determined that the FIT entry 134(F) contains a valid IPRF tag 202(F) corresponding to an IPRF register among the multiple IPRF registers 130(0)-130(P) of the IPRF 128, the immediate move logic circuit 126 writes the IPRF tag 208(0) of the IPRF register 130(0) into an MRT entry (such as MRT entry 124(M)) among the multiple MRT entries 124(0)-124(M) of the MRT 122, and this MRT entry corresponds to the destination register 140 (block 420). The immediate move logic circuit 126 can also set the content indicator 216(M) of the MRT entry 124(M) to indicate that the MRT entry 124(M) is associated with the first IPRF register 130(0) (block 422).

[0041] If the immediate move logic circuit 126 determines in decision block 410 that the FIT entry 134(F) does not contain a valid IPRF tag 202(F), then in some embodiments, the immediate move logic circuit 126 determines whether the count value 204(F) of the FIT entry 134(F) exceeds the FIT threshold 142 (block 424). If it is determined that the count value 204(F) of the FIT entry 134(F) exceeds the FIT threshold 142, the immediate move logic circuit 126 allocates an IPRF register among the multiple IPRF registers 130(0)-130(P) of the IPRF 128, such as the IPRF register 130(0) (block 426). The immediate move logic circuit 126 then writes the IPRF tag 208(0) for the IPRF register 130(0) into the FIT entry 134(F) (block 428). Finally, the immediate move logic circuit 126 writes the immediate value 138 into the IPRF register 130(0) (block 430). If the immediate move logic circuit 126 determines in decision block 424 that the count value 204(F) does not exceed the FIT threshold 142, the immediate move logic circuit 126 increments the count value 204(0) of the FIT entry 134(0) (block 432).

[0042] Figure 5 is an exemplary processor-based device 500 (such asFigure 1 Block diagram of a processor - based device 500) that implements early execution of immediate move instructions with variable immediate value sizes. The processor - based device 500 can be one or more circuits included in an electronic board, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing board, a mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, the processor - based device 500 includes a processor 502. The processor 502 represents one or more general - purpose processing circuits, such as a microprocessor, a central processing unit, etc., and can correspond to Figure 1 the PE 102. The processor 502 is configured to execute the processing logic in the instructions for performing the operations and steps discussed herein. In this example, the processor 502 includes an instruction cache 504 for temporary fast - access memory storage of instructions and an instruction processing circuit 510. Instructions fetched or prefetched from memory (such as from system memory 508) via the system bus 506 are stored in the instruction cache 504. The instruction processing circuit 510 is configured to process the instructions fetched into the instruction cache 504 and process the instructions for execution.

[0043] The processor 502 and the system memory 508 are coupled to the system bus 506 and are capable of coupling the peripheral devices included in the processor - based device 500 to each other. As is well known, the processor 502 communicates with these other devices by exchanging address, control, and data information via the system bus 506. For example, the processor 502 can transmit a bus transaction request to a memory controller 512, which is an example of a peripheral device, in the system memory 508. Although Figure 5 not shown in the figure, multiple system buses 506 can be provided, where each system bus constitutes a different architecture. In this example, the memory controller 512 is configured to provide memory access requests to a memory array 514 in the system memory 508. The memory array 514 consists of an array of storage bit cells for storing data. As a non - limiting example, the system memory 508 can be a read - only memory (ROM), flash memory, dynamic random - access memory (DRAM) (such as synchronous DRAM (SDRAM), etc.), and static memory (e.g., flash memory, static random - access memory (SRAM), etc.).

[0044] Other devices can be connected to the system bus 506. As Figure 5As illustrated, by way of example, these devices can include a system memory 508, one or more input devices 516, one or more output devices 518, a modem 524, and one or more display controllers 520. The (s) input device(s) 516 can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The (s) output device(s) 518 can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem 524 can be any device configured to permit data exchange to and from a network 526. The network 526 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH TM networks, and the Internet. The modem 524 can be configured to support any type of communication protocol desired. The processor 502 can also be configured to access the (s) display controller(s) 520 via a system bus 506 to control information sent to one or more displays 522. The (s) display(s) 522 can include any type of display, including but not limited to cathode ray tubes (CRTs), liquid crystal displays (LCDs), plasma displays, etc.

[0045] Figure 5 The processor-based device 500 in can include a set of instructions 528 that can be encoded with an explicit consumer naming model based on arrival for execution by the processor 502 according to the instructions for any desired application. The instructions 528 can be stored in the system memory 508, the processor 502, and / or the instruction cache 504, which are examples of non-transitory computer-readable media 530. The instructions 528 can also reside entirely or at least partially within the system memory 508 and / or within the processor 502 during their execution. The instructions 528 can also be transmitted or received via the modem 524 over the network 526 such that the network 526 includes computer-readable media 530.

[0046] Although the computer-readable media 530 is shown as a single medium in the exemplary embodiments, the term "computer-readable media" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store a set or multiple sets of instructions 528. The term "computer-readable media" should also be considered to include any medium that can store, encode, or carry a set of instructions executed by a processing device and cause the processing device to perform any one or more of the methods of the embodiments disclosed herein. Thus, the term "computer-readable media" should be understood to include, but not be limited to, solid state memories, optical media, and magnetic media.

[0047] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein can be formed by hardware components or can be embodied in machine-executable instructions that can be used to cause a general or special-purpose processor programmed with the instructions to perform these steps. Alternatively, these steps can be performed by a combination of hardware and software processes.

[0048] The embodiments disclosed herein can be provided as a computer program product or software process that can include a machine-readable medium (or computer-readable medium) having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform a process in accordance with the embodiments disclosed herein. Machine-readable media include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include: machine-readable storage media (e.g., ROM, random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.) and the like.

[0049] Unless otherwise specifically stated and apparent from the foregoing discussion, it should be understood that throughout the description, discussions using terms such as “processing,” “computing,” “determining,” “displaying,” etc., refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system registers into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage, transmission, or display devices.

[0050] The algorithms and displays presented herein are inherently associated with any particular computer or other apparatus. Various systems can be used in conjunction with the programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The structure required for various such systems will become apparent from the foregoing description. In addition, the embodiments described herein are not described with reference to any particular programming language. It should be understood that a variety of programming languages can be used to implement the teachings of the embodiments described herein.

[0051] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, instructions stored in memory or other computer-readable media, and executed by a processor or other processing device, or a combination of both. By way of example, the components of the distributed antenna system described herein can be implemented in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of desired information. To clearly illustrate this interchangeability, the various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. The skilled person may implement the described functionality in different ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the embodiments.

[0052] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a controller can be a processor. The processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0053] The embodiments disclosed herein can be embodied in hardware and instructions stored in hardware, and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. The exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integrated with the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. In the alternative, the processor and the storage medium can reside as discrete components in a remote station, a base station, or a server.

[0054] It should also be noted that the operation steps described in any exemplary embodiments herein are described to provide examples and discussions. The described operations can be performed in many different orders different from the order illustrated. In addition, the operations described in a single operation step can actually be performed in multiple different steps. In addition, one or more operation steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that any of a variety of technologies and techniques can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0055] Unless otherwise expressly stated, no method set forth herein is intended to be construed as requiring that its steps be performed in a particular order. Accordingly, if a method claim does not actually recite an order of its steps or if the steps are not otherwise specifically limited to a particular order in the claims or specification, no particular order is intended to be inferred.

[0056] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub - combinations and variations of the disclosed embodiments incorporating the spirit and substance of the invention may occur to those skilled in the art, the invention should be construed to include all such within the scope of the appended claims and their equivalents.

Claims

1. A processor-based device, comprising: A processing element PE, comprising: An execution pipeline, including immediate move logic circuitry; A most recent mapping table MRT, including a plurality of MRT entries, wherein the MRT entries among the plurality of MRT entries of the MRT correspond to registers; A frequently immediate table FIT, including a plurality of FIT entries, wherein the FIT is configured to track the occurrences of immediate values; and An immediate physical register file IPRF, including a plurality of IPRF registers, wherein the IPRF is configured to store immediate values; The PE is configured to: Use the immediate move logic circuitry of the execution pipeline to detect an immediate move instruction, the immediate move instruction including an immediate value and a destination register; Determine whether a FIT entry among the plurality of FIT entries of the FIT corresponds to the immediate value; In response to determining that the FIT entry in the FIT corresponds to the immediate value, determine whether the FIT entry includes a valid IPRF tag corresponding to an IPRF register among the plurality of IPRF registers of the IPRF; and In response to determining that the FIT entry includes a valid IPRF tag corresponding to the IPRF register of the IPRF, write the IPRF tag of the IPRF register into an MRT entry among the plurality of MRT entries of the MRT, the MRT entry corresponding to the destination register.

2. The processor-based device according to claim 1, wherein the PE is further configured to: Determine whether the size of the storage space for the immediate value exceeds the size of each of the multiple MRT entries of the MRT; And In response to determining that the size of the storage space of the immediate value does not exceed the size of the MRT entry of the MRT, store the immediate value in an MRT entry among the plurality of MRT entries of the MRT, the MRT entry corresponding to the destination register; Wherein the PE is configured to determine whether a FIT entry among the plurality of FIT entries of the FIT corresponds to the immediate value in response to determining that the size of the immediate value exceeds the size of each MRT entry of the plurality of MRT entries of the MRT.

3. The processor-based device according to claim 1, wherein the PE is further configured to: further in response to determining that the FIT entry includes the valid IPRF tag corresponding to the IPRF register of the IPRF, set a content indicator of the MRT entry to indicate that the MRT entry is associated with the IPRF register.

4. The processor-based device according to claim 1, wherein the PE is further configured to, in response to determining that no FIT entry in the FIT corresponds to the immediate value: Recycle an existing FIT entry among the plurality of FIT entries of the FIT according to a FIT replacement policy; and Store the immediate value in the existing FIT entry among the plurality of FIT entries of the FIT.

5. The processor-based device according to claim 4, wherein the FIT entry among the plurality of FIT entries includes a count value indicating the number of occurrences of the immediate value associated with the FIT entry, and the FIT replacement policy includes reclaiming the existing FIT entry with the lowest count value among the plurality of FIT entries of the FIT.

6. The processor-based device according to claim 4, wherein the FIT replacement policy includes reclaiming the least recently used existing FIT entry among the plurality of FIT entries of the FIT.

7. The processor-based device according to claim 1, wherein the PE is further configured to, in response to determining that the FIT entry does not contain a valid IPRF tag corresponding to the IPRF register of the IPRF: allocate an IPRF register among the plurality of IPRF registers of the IPRF; write the IPRF tag for the IPRF register into the FIT entry; and write the immediate value into the IPRF register.

8. The processor-based device according to claim 7, wherein the FIT entry among the plurality of FIT entries includes a count value indicating the number of occurrences of the immediate value associated with the FIT entry, and the PE is further configured to determine whether the count value of the FIT entry exceeds a FIT threshold; wherein the PE is further configured to, in response to determining that the count value of the FIT entry exceeds the FIT threshold, allocate the IPRF register, write the IPRF tag for the IPRF register into the FIT entry, and write the immediate value into the IPRF register.

9. The processor-based device according to claim 8, wherein the PE is further configured to increment the count value of the FIT entry in response to determining that the count value of the FIT entry does not exceed the FIT threshold.

10. A method for implementing early execution of an immediate move instruction with a variable immediate value size, comprising: detecting a first immediate move instruction using the immediate move logic circuit of the execution pipeline of a processing element PE of a processor-based device, the first immediate move instruction including a first immediate value and a first destination register; determining that a first FIT entry among the plurality of FIT entries of a frequent immediate table FIT corresponds to the first immediate value, wherein the FIT is configured to track the occurrences of immediate values; in response to determining that the first FIT entry in the FIT corresponds to the first immediate value, determining that the first FIT entry contains a valid first IPRF tag corresponding to a first IPRF register among the plurality of IPRF registers of an immediate physical register file IPRF, wherein the IPRF is configured to store immediate values; and In response to determining that the first FIT entry contains the valid first IPRF tag corresponding to the first IPRF register of the IPRF, write the first IPRF tag of the first IPRF register into a first MRT entry among a plurality of MRT entries of the latest mapping table MRT, where the first MRT entry corresponds to the first destination register, and where the MRT entries among the plurality of MRT entries of the MRT correspond to registers.

11. The method according to claim 10, further comprising determining that a size of a storage space of the first immediate value exceeds a size of each of the MRT entries among the plurality of MRT entries of the MRT; where determining that the first FIT entry among the plurality of FIT entries of the FIT corresponds to the first immediate value is in response to determining that the size of the storage space of the first immediate value exceeds the size of each of the MRT entries among the plurality of MRT entries of the MRT.

12. The method according to claim 10, further comprising: using the immediate move logic circuit to detect a second immediate move instruction, the second immediate move instruction including a second immediate value and a second destination register; determining that a size of a storage space of the second immediate value does not exceed a size of each of the MRT entries among the plurality of MRT entries of the MRT; and and in response to determining that the size of the storage space of the second immediate value does not exceed the size of each of the MRT entries among the plurality of MRT entries of the MRT, storing the second immediate value in a second MRT entry among the plurality of MRT entries of the MRT, where the second MRT entry corresponds to the second destination register.

13. The method according to claim 10 further comprises: Further in response to determining that the first FIT entry contains the valid first IPRF tag corresponding to the first IPRF register of the IPRF, set a content indicator of the first MRT entry to indicate that the first MRT entry is associated with the first IPRF register.

14. The method according to claim 10, further comprising: detecting, by the immediate move logic circuit, a third immediate move instruction, the third immediate move instruction including a third immediate value and a third destination register; determining that no FIT entry in the FIT corresponds to the third immediate value; and in response to determining that no FIT entry in the FIT corresponds to the third immediate value: reclaiming an existing FIT entry among the plurality of FIT entries of the FIT according to a FIT replacement policy; and storing the third immediate value in the existing FIT entry among the plurality of FIT entries of the FIT.

15. The method according to claim 14, wherein the FIT entries among the plurality of FIT entries include count values, the count values indicating the number of occurrences of the immediate value associated with the FIT entry, and wherein the FIT replacement policy includes reclaiming the existing FIT entry among the plurality of FIT entries of the FIT having the lowest count value.

16. The method according to claim 14, wherein the FIT replacement policy includes reclaiming the least recently used existing FIT entry among the plurality of FIT entries of the FIT.

17. The method according to claim 10, further comprising: using the immediate move logic circuit to detect a fourth immediate move instruction, the fourth immediate move instruction including a fourth immediate value and a fourth destination register; determining that a fourth FIT entry among the plurality of FIT entries of the FIT corresponds to the fourth immediate value; in response to determining that the fourth FIT entry in the FIT corresponds to the fourth immediate value, determining that the fourth FIT entry does not contain a valid IPRF tag corresponding to the IPRF register of the IPRF; and in response to determining that the fourth FIT entry does not contain a valid IPRF tag corresponding to the IPRF register of the IPRF: allocating a fourth IPRF register among the plurality of IPRF registers of the IPRF; writing a fourth IPRF tag for the fourth IPRF register into the fourth FIT entry; and writing the fourth immediate value into the fourth IPRF register.

18. The method according to claim 17, further comprising determining that a count value of the fourth FIT entry exceeds a FIT threshold, the count value indicating the number of occurrences of the immediate value associated with the fourth FIT entry; wherein allocating the fourth IPRF register, writing the fourth IPRF tag for the fourth IPRF register into the fourth FIT entry, and writing the fourth immediate value into the fourth IPRF register are in response to determining that the count value of the fourth FIT entry exceeds the FIT threshold.

19. The method according to claim 10, further comprising: using the immediate move logic circuit to detect a fifth immediate move instruction, the fifth immediate move instruction including a fifth immediate value and a fifth destination register; determining that a fifth FIT entry among the plurality of FIT entries of the FIT corresponds to the fifth immediate value; in response to determining that the fifth FIT entry in the FIT corresponds to the fifth immediate value, determining that the fifth FIT entry does not contain a valid IPRF tag corresponding to the IPRF register of the IPRF; in response to determining that the fifth FIT entry does not contain a valid IPRF tag corresponding to the IPRF register of the IPRF, determining that a count value of the fifth FIT entry does not exceed the FIT threshold, the count value indicating the number of occurrences of the immediate value associated with the fifth FIT entry; and in response to determining that the count value of the fifth FIT entry does not exceed the FIT threshold, incrementing the count value of the fifth FIT entry.

20. A non-transitory computer-readable medium having computer-executable instructions stored thereon, the computer-executable instructions, when executed by a processor, cause the processor to: detect an immediate move instruction, the immediate move instruction including an immediate value and a destination register; Determine whether a FIT entry among multiple FIT entries of a frequent immediate table (FIT) corresponds to the immediate value, where the FIT is configured to track the occurrences of immediate values; In response to determining that the FIT entry in the FIT corresponds to the immediate value, determine whether the FIT entry contains a valid IPRF tag corresponding to an IPRF register among multiple IPRF registers of an immediate physical register file (IPRF), where the IPRF is configured to store immediate values; and In response to determining that the FIT entry contains a valid IPRF tag corresponding to the IPRF register of the IPRF, write the IPRF tag of the IPRF register to an MRT entry among multiple MRT entries of a latest mapping table (MRT), where the MRT entry corresponds to the destination register, and where the MRT entries among the multiple MRT entries of the MRT correspond to registers.

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