Data reading and writing circuit, chip, electronic device and method

Abstract

Embodiments of the present invention relate to the technical field of data reading and writing, and in particular, to a data reading and writing circuit, chip, electronic device and method. The data reading and writing circuit includes: a functional circuit, a first detection circuit and a random access memory RAM; the functional circuit is used to perform reading and writing operations on the RAM through the first detection circuit; the first detection circuit is used to determine, based on the address signal output by the functional circuit, when the functional circuit performs repeated reading and writing operations on the RAM at the same address, generate a second clock signal based on the periodically flipped first clock signal output by the functional circuit and output the second clock signal to the RAM; the second clock signal does not flip during repeated reading and writing operations; the RAM is used to perform reading and writing operations based on the second clock signal. Since the second clock signal does not flip during repeated reading and writing operations, the RAM will not perform repeated reading and writing operations. In this way, the power consumption waste of the RAM is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of data reading and writing, and in particular, to a data reading and writing circuit, a chip, an electronic device, and a data reading and writing method. Background Art

[0002] In hardware circuits, a large amount of random-access memory (RAM) is usually used to store data. Some functional circuits such as image processing circuits and look-up-table (LUT) circuits will write data into RAM or read data from RAM. For example, when the image processing circuit is working, it will read a line of image data stored in RAM in real time.

[0003] When RAM is powered on, it generates power consumption, which is divided into static power consumption and dynamic power consumption. Static power consumption refers to the power consumption generated by leakage current when the circuit is in a waiting or inactive state; dynamic power consumption refers to the power consumption generated when the chip is in operation and the transistor is in a jumping state, including switching power consumption and short-circuit power consumption.

[0004] In the prior art, the frequent calling of RAM by the functional circuit easily results in some unnecessary power consumption. The embodiment of the present invention provides a data reading and writing circuit to achieve the purpose of reducing the power consumption of RAM. Summary of the invention

[0005] The embodiment of the present invention provides a data reading and writing circuit to achieve the purpose of reducing RAM power consumption.

[0006] In a first aspect, an embodiment of the present invention provides a data reading and writing circuit, including a functional circuit, a first detection circuit and a random access memory RAM;

[0007] The functional circuit is used to perform read and write operations on the RAM through the first detection circuit;

[0008] The first detection circuit is used to determine, based on the address signal output by the functional circuit, that when the functional circuit performs repeated read and write operations on the same address of the RAM, generate a second clock signal based on the periodically flipped first clock signal output by the functional circuit and output the second clock signal to the RAM; the second clock signal does not flip during the repeated read and write operations;

[0009] The RAM is used to perform read and write operations based on the second clock signal.

[0010] The first detection circuit determines based on the address signal that when the functional circuit performs repeated read and write operations on the same address, it will generate a second clock signal that does not flip during repeated read and write operations from the first clock signal that originally flips periodically, and output it to the RAM. Then the RAM will read and write according to the second clock signal. Since the second clock signal does not flip during repeated read and write operations, the RAM will not perform repeated read and write operations. In this way, the power consumption waste of the RAM is reduced.

[0011] Optionally, the first detection circuit includes a storage area;

[0012] The first detection circuit is used to read the i-th address of the address signal in the i-th cycle of the first clock signal; if the i-th address is the same as the i-1-th address stored in the storage area, the chip select signal output by the functional circuit is valid and the read / write signal is a read signal, generate a second clock signal that is not flipped in the i-th cycle;

[0013] The first detection circuit is also used to output the read data of the i-th address read from the RAM in the m-th cycle stored in the storage area to the functional circuit; the m-th cycle is the first cycle in which the functional circuit continuously reads data from the i-th address.

[0014] When data is read through the RAM, if it is determined that the i-th address is the same as the i-1th address stored in the storage area and the chip select signal output by the functional circuit is valid, a second clock signal that has not flipped in the i-th cycle is generated. If the second clock signal does not flip, the RAM does not work and data will not be read from the RAM. In this way, the purpose of reducing power consumption is achieved. However, the read data of the i-th address read from the RAM in the m-th cycle is stored in the storage area, so the data can be returned to the functional circuit. That is, if the functional circuit repeatedly reads data from the same address through the first clock signal and the chip select signal for multiple times in a row, the first detection circuit will return the last read data stored in the storage area for multiple times in a row, but will not obtain data through the RAM for multiple times in a row, thus reducing power consumption.

[0015] Optionally, the first detection circuit includes a storage area;

[0016] The first detection circuit is used to read the i-th address of the address signal in the i-th cycle of the first clock signal; if the chip select signal output by the functional circuit is valid and the read / write signal output by the functional circuit is a write signal, the i-th address is the same as the i-1th address stored in the storage area, and the i-th write data output by the functional circuit is the same as the i-1th write data stored in the storage area, a second clock signal that is not flipped in the i-th cycle is generated.

[0017] When data is written through the RAM, if it is determined that the chip select signal is valid and the read / write signal output by the functional circuit is a write signal, the i-th address is the same as the i-1-th address stored in the storage area, and the i-th write data output by the functional circuit is the same as the i-1-th write data stored in the storage area, then a second clock signal that is not flipped in the i-th cycle is generated. If the second clock signal does not flip, the RAM does not work and data will not be written in the RAM. In this way, the purpose of reducing power consumption is achieved.

[0018] Optionally, the first detection circuit is further used to generate a second clock signal that is not flipped in the i-th cycle when it is determined that the chip select signal output by the functional circuit is invalid in the i-th cycle of the first clock signal.

[0019] When the chip select signal is an invalid signal, it means that the functional circuit does not select the RAM for reading, and then a second clock signal that is not flipped in the i-th cycle is generated. In this way, the flipping of the second clock signal is reduced, the frequency of reading data through the RAM is reduced, and power consumption is reduced.

[0020] Optionally, the first detection circuit is further used to output the address signal, chip select signal, read / write signal, and write data signal output by the functional circuit to the RAM.

[0021] In this way, the RAM can read and write data based on the address signal, chip select signal, read / write signal, and write data signal.

[0022] Optionally, it further includes: a second detection circuit;

[0023] The second detection circuit is used to generate a power consumption indication of the RAM according to a function signal output by the function circuit; the function signal is used to indicate whether the function circuit is in a working state;

[0024] The RAM is further used to determine whether to reduce leakage current according to the power consumption indication.

[0025] In this way, the working state of the functional circuit is linked to the power consumption indication of the RAM, and the design of the power consumption indication of the RAM can be realized directly through hardware, with accurate and automatic control, which saves manpower and static power consumption.

[0026] Optionally, the functional circuit is an image processing circuit;

[0027] The functional signal includes any one or more of the following: a valid display data selection signal DE, a line synchronization signal HS, a field synchronization signal VS and a sub-functional signal.

[0028] The above functional signal can indicate whether the functional circuit is in working state, and the design of power consumption indication of RAM can be realized directly through hardware, and the control is accurate and automatic, which saves manpower and static power consumption.

[0029] Optionally, the second detection circuit is specifically used to generate a power consumption indication of the RAM according to a function signal and a register signal output by the function circuit; the register signal is set by a user.

[0030] The register signal is set by the user, so the second detection circuit can be controlled not only by the function signal but also by the user, which improves the flexibility of generating the power consumption indication and the flexibility of controlling the working state of the RAM, and saves the power consumption of the RAM.

[0031] In a second aspect, an embodiment of the present invention further provides a chip, comprising a PCB (Printed Circuit Board) and the data reading and writing circuit as described above; the data reading and writing circuit is arranged on the PCB.

[0032] In a third aspect, an embodiment of the present invention further provides an electronic device, including a PCB, on which a data reading and writing circuit as described in any one of the above items is arranged.

[0033] In a fourth aspect, an embodiment of the present invention further provides a data reading and writing method, comprising:

[0034] Based on the address signal output by the functional circuit, determining whether the functional circuit performs repeated read and write operations on the same address on the RAM;

[0035] If it is determined that repeated read and write operations are performed on the RAM at the same address, a second clock signal is generated based on the periodically flipped first clock signal output by the functional circuit and the second clock signal is output to the RAM; the second clock signal does not flip during the repeated read and write operations.

[0036] Optionally, determining to perform repeated read and write operations on the same address on the RAM includes:

[0037] In the i-th cycle of the first clock signal, reading the i-th address of the address signal;

[0038] When the i-th address is the same as the i-1-th address, the chip select signal output by the functional circuit is valid, and the read / write signal output by the functional circuit is a read signal, determining to perform a repeated read operation on the same address of the RAM;

[0039] When the chip select signal output by the functional circuit is valid and the read / write signal output by the functional circuit is a write signal, the i-th address is the same as the i-1-th address, and the i-th write data output by the functional circuit is the same as the i-1-th write data, it is determined that a repeated write operation is performed on the same address of the RAM.

[0040] Optionally, the method further comprises:

[0041] The read data of the i-th address read from the RAM in the m-th cycle stored in the storage area is output to the functional circuit; the m-th cycle is the first cycle in which the functional circuit continuously reads data from the i-th address.

[0042] Optionally, the method further comprises:

[0043] In the i-th cycle of the first clock signal, when it is determined that the chip selection signal output by the functional circuit is invalid, a second clock signal that is not flipped in the i-th cycle is generated.

[0044] Optionally, the method further comprises:

[0045] The address signal, chip selection signal, read / write signal, and write data signal output by the functional circuit are output to the RAM.

[0046] Optionally, the method further comprises:

[0047] According to the function signal output by the function circuit, the power consumption indication of the RAM is generated, so that the RAM determines whether to reduce the leakage current according to the power consumption indication; the function signal is used to indicate whether the function circuit is in working state.

[0048] Optionally, the functional circuit is an image processing circuit;

[0049] The functional signal includes any one or more of the following: a valid display data selection signal DE, a line synchronization signal HS, a field synchronization signal VS and a sub-functional signal.

[0050] Optionally, generating a power consumption indication of the RAM according to a function signal output by the function circuit includes:

[0051] The power consumption indication of the RAM is generated according to the function signal and the register signal output by the function circuit; the register signal is set by the user. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0053] Figure 1 A schematic diagram of interaction between a functional circuit and RAM provided in an embodiment of the present invention;

[0054] Figure 2 A possible waveform diagram of a signal provided by an embodiment of the present invention;

[0055] Figure 3 A schematic diagram of a possible data reading and writing circuit provided by an embodiment of the present invention;

[0056] Figure 4 A schematic diagram of another possible interaction between a functional circuit and a RAM provided in an embodiment of the present invention;

[0057] Figure 5 A possible waveform diagram of a signal provided by an embodiment of the present invention;

[0058] Figure 6 A schematic diagram of another possible data reading and writing circuit provided by an embodiment of the present invention;

[0059] Figure 7 A schematic diagram of another possible data reading and writing circuit provided by an embodiment of the present invention;

[0060] Figure 8 A schematic diagram of another possible control method of the second detection circuit provided by an embodiment of the present invention;

[0061] Fig. 9 A schematic diagram of another possible control method of the second detection circuit provided by an embodiment of the present invention;

[0062] Fig.10 A schematic diagram of a data reading and writing method provided by an embodiment of the present invention;

[0063] Fig.11 A schematic diagram of the structure of a chip provided by an embodiment of the present invention;

[0064] Fig.12 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0065] In order to make the purpose, implementation mode and advantages of the present application clearer, the exemplary implementation mode of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0066] Based on the exemplary embodiments described in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the claims attached to this application. In addition, although the disclosure in this application is introduced according to one or several exemplary examples, it should be understood that each aspect of the disclosure can also constitute a complete implementation method separately.

[0067] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0068] The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise indicated. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, for example, they can be implemented according to orders other than those given in the diagrams or descriptions of the embodiments of this application.

[0069] In addition, the terms "include" and "have" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such products or devices.

[0070] In hardware circuits, a large amount of RAM is usually used to store data. Some functional circuits will write data into the RAM or read data from the RAM.

[0071] Functional circuits may be various circuits that need to call RAM, such as image processing circuits, lookup table circuits, etc. For example, the image processing circuit writes image data into RAM, or reads a line of image data from RAM for display.

[0072] RAM is an internal memory that directly exchanges data with functional circuits. It can be read and written at any time (except when refreshed) and is very fast. It is usually used as a temporary data storage medium for operating systems or other running programs. When RAM is working, information can be written (stored) or read (retrieved) from any specified address at any time. The biggest difference between it and ROM is the volatility of data, that is, once the power is off, the stored data will be lost. RAM is used in computers and digital systems to temporarily store programs, data and intermediate results. According to the working principles of the storage unit, RAM is divided into static random access memory (Static Random-Access Memory, SRAM) and dynamic random access memory (Dynamic Random Access Memory, DRAM).

[0073] RAM consists of several parts such as storage matrix, address decoder, read / write controller, input / output, chip select control, etc.

[0074] The memory matrix is ​​the core part of RAM, which is a register matrix used to store information.

[0075] The function of the address decoder is to translate the binary number corresponding to the register address into a valid row select signal and column select signal, thereby selecting the storage unit.

[0076] Read / write controller: When accessing RAM, whether to read or write the selected register is controlled by the read / write signal. During the read operation, the data of the selected unit is transmitted to the functional circuit via the data line and the input / output line; during the write operation, the functional circuit stores the data into the selected unit via the input / output line and the data line.

[0077] Input / output: RAM exchanges data with the functional circuit through the input / output terminal. It is an output terminal when reading and an input terminal when writing. It is controlled by the read / write control line. The number of input / output data lines is the same as the number of register bits corresponding to an address. Some RAM chips have separate input / output terminals. Usually the output terminal of RAM has an open collector or three-state output structure.

[0078] Chip select control: Due to the limitation of RAM integration, the memory system of a computer is often composed of many RAMs. When a functional circuit accesses the memory, it can only access one (or several) RAMs at a time, that is, only one address in one (or several) RAMs in the memory is accessed by the functional circuit and exchanges information with it, while other RAMs are not connected to the functional circuit. Chip select is used to achieve this control. Usually a RAM has one or several chip select lines. When the chip select line of a RAM is connected to a valid level, the RAM is selected, and the output signal of the address decoder controls the register of a certain address of the RAM to connect to the functional circuit; when the chip select line is connected to an invalid level, the RAM is disconnected from the functional circuit.

[0079] Figure 1 The schematic diagram of the interaction between a functional circuit and a RAM provided by an embodiment of the present invention is shown. As shown in the figure, the functional circuit inputs a clock signal clock, a chip select signal cs_n, a read / write signal wr_n, an address signal address and a write data signal Wdata to the RAM; the RAM outputs a read data signal Rdata to the functional circuit.

[0080] Figure 2 The possible waveform diagram of the above signal is shown below. Figure 1 and Figure 2 , introduce the functions of the above signals.

[0081] Clock signals are often used in synchronous circuits to play the role of timers, ensuring that related electronic components can operate according to the clock signal. Clock signals are the basis of sequential logic, used to determine when the state in the logic unit is updated. They are semaphores with a fixed period and are independent of operation. Clock signals have a fixed clock frequency, which is the reciprocal of the clock period. In electronics, especially synchronous digital circuits, clock signals are a special type of signal that oscillates between high and low states. The use of signals is like a metronome to coordinate the actions of digital circuits. Digital clock signals are basically square wave voltages, such as Figure 2 shown.

[0082] The clock edge trigger signal means that all state changes occur at the arrival of the clock edge. Only when the synchronization signal arrives will the related trigger change the output state according to the input signal, so that the related electronic components can operate synchronously. Whether the rising edge or the falling edge of the clock signal controls the change of the state quantity of the logic unit depends on the specific logic design.

[0083] In the embodiment of the present invention, Figure 2As shown, each number represents a cycle of the clock signal. The embodiment of the present invention adopts rising edge triggering, that is, at the rising edge of the clock signal, the RAM will read or write the address in the address signal.

[0084] As mentioned above, there are usually multiple RAMs. Whether the functional circuit selects the RAM to exchange information is determined by the chip select signal. For example, if the chip select signal is low and effective, when the chip select signal cs_n = 0, the RAM works, and when the chip select signal cs_n = 1, the RAM does not work. Figure 2 In the figure, the RAM works when cs_n=0. When combined with the clock signal, it can be seen that the RAM works at the rising edge of the clock signal and when cs_n=0.

[0085] The read / write signal wr_n is used to instruct the RAM to read or write. For example, when wr_n=0, the RAM performs writing; when wr_n=1, the RAM performs reading. The above is only an example and is not limited to this embodiment of the present invention. Figure 2 In the example, wr_n is always 1, which means that the RAM is always reading. Combined with the clock signal and the chip select signal, it can be seen that the RAM is reading at the rising edge of the clock signal, when cs_n=0, and wr_n=1.

[0086] The address signal address is used to indicate the address of the register in the RAM storage matrix. Since the data is stored in the register in the storage matrix, if it is to read data, the address of the register to read the data is determined according to the address signal; if it is to write data, the address of the register to write data is determined according to the address signal. Figure 2 In the figure, combining the clock signal, chip select signal, read and write signal, it can be seen that the RAM reads the address in the address signal at the rising edge of the clock signal, when cs_n=0, and wr_n=1. For example, the addresses read are 000, 001, 001, 001, 002, and 003, and then reads the data from the corresponding register according to the address. Data_0 is read at address 000, data_1 is read at address 001, data_1 is read at address 001, data_1 is read at address 001, and data_2 is read at address 002. Since the data reading process is delayed, the data reading lags behind the address reading for a period of time, such as Figure 2 shown.

[0087] The write data signal Wdata writes the data obtained from the write data signal into the address indicated by the address signal when writing data.

[0088] The read data signal Rdata, when data is read, reads the data at the address indicated by the address signal to form a read data signal and returns it to the functional circuit.

[0089] It can be found that the clock signal is always flipping. Every time the clock signal is rising, cs_n=0, and wr_n=1, there will be a read operation. Since one address stores one data, repeated reading of the same address will definitely read out the same data repeatedly. This repeated reading of the same address causes a waste of power consumption. Similarly, if the same data is repeatedly written to the same address, it will also cause a waste of power consumption.

[0090] The embodiment of the present invention provides a possible data reading and writing circuit, such as Figure 3 As shown, it includes a functional circuit, a first detection circuit and a RAM.

[0091] A functional circuit is used to perform read and write operations on the RAM through the first detection circuit.

[0092] The first detection circuit is used to determine, based on the address signal output by the functional circuit, that when the functional circuit performs repeated read and write operations on the same address of the RAM, a second clock signal is generated based on a first clock signal that periodically flips output by the functional circuit and the second clock signal is output to the RAM; the second clock signal does not flip during the repeated read and write operations.

[0093] RAM, used for performing read and write operations based on the second clock signal.

[0094] The process of repeatedly reading data at the same address is a repeated read operation, and the process of repeatedly writing the same data at the same address is a repeated write operation.

[0095] Based on the address signal, the first detection circuit determines that when the functional circuit performs repeated read and write operations on the same address, it will generate a second clock signal that does not flip during the repeated read and write operations from the first clock signal that originally flips periodically, and output it to the RAM. Then the RAM will read and write according to the second clock signal. Since the second clock signal does not flip during the repeated read and write operations, the RAM will not perform read and write operations. In this way, the power consumption waste of the RAM is reduced.

[0096] The first detection circuit is described in detail below.

[0097] The first detection circuit includes one or more storage areas, and the information stored in the storage area will be continuously updated. When new information is stored, the old information will be overwritten. When reading data, the storage area can be used to store the address information in the last address signal output by the functional circuit and the last read data read from the RAM; when writing data, the storage area can be used to store the address information in the last address signal input by the functional circuit and the write data in the last data signal output by the functional circuit. The above information can be stored in one storage area or in multiple storage areas. The embodiments of the present invention are not limited to this.

[0098] The storage area may be a latch, a register, etc. The embodiment of the present invention does not limit the type and quantity of the storage area.

[0099] Figure 4 Another possible interaction diagram of a functional circuit and a RAM provided by an embodiment of the present invention is shown. As shown in the figure, the first clock signal, chip selection signal, address signal, read / write signal and write data signal output by the functional circuit are input to the first detection circuit. After processing, the first detection circuit outputs the second clock signal to the RAM, so that the RAM reads and writes data under the control of the second clock signal. If data is read, the RAM will return the second read data signal to the first detection circuit according to the control of the second clock signal, and the first detection will return the first read data signal to the functional circuit according to the control of the first clock signal.

[0100] The following describes the process of performing data reading and data writing using the data reading and writing circuit provided by the embodiment of the present invention.

[0101] Embodiment 1: Data reading

[0102] In the i-th cycle of the first clock signal, the i-th address of the address signal is read; if the i-th address is the same as the i-1-th address stored in the storage area, the chip select signal output by the functional circuit is valid, and the read / write signal is a read signal, it can be determined that a repeated read operation is performed on the same address of the RAM, and a second clock signal that is not flipped in the i-th cycle is generated;

[0103] The first detection circuit also outputs the read data of the i-th address read from the RAM in the m-th cycle stored in the storage area to the functional circuit; the m-th cycle is the first cycle in which the functional circuit continuously reads data from the i-th address.

[0104] Optionally, when the chip select signal output by the functional circuit is invalid in the i-th cycle of the first clock signal, a second clock signal that is not flipped in the i-th cycle is also generated. If the clock signal is still flipped when the chip select signal is invalid, the entire device will still operate, and power consumption will still be wasted. Therefore, it is designed that when the chip select signal is invalid, the second clock signal will not flip either.

[0105] Optionally, the first detection circuit also outputs the address signal, chip selection signal, and read / write signal output by the functional circuit to the RAM. Figure 4 As shown. So that the RAM reads data according to these signals. Of course, whether these signals work is determined by the second clock signal. If the second clock signal flips in a certain cycle, the RAM will continue to determine whether to read data according to the chip select signal and the read-write signal; if the second clock signal does not flip in a certain cycle, the RAM will not read data.

[0106] For example, Figure 5 The first detection circuit works according to the control of the first clock signal, the chip selection signal, the read / write signal and the address signal.

[0107] At the rising edge of the first cycle of the first clock signal, the read / write signal is a read signal, the chip select signal is invalid, no data is read, and the generated second clock signal does not flip in the first cycle. Since the second clock signal received by the RAM does not flip, no data is read in the RAM. The RAM does not return the second read data to the first detection circuit.

[0108] At the rising edge of the second cycle, the read / write signal is a read signal, the chip select signal is valid, and the second address read through the address signal is 000. At this time, there is no storage address in the storage area, so it is determined that address 000 is different from the storage address in the storage area, and the generated second clock signal flips normally in the second cycle, and the address 000 is stored in the storage area; because the second clock signal received by the RAM flips, the RAM returns the second read data data_0 read at address 000 to the first detection circuit, and the first detection circuit returns the first read data data_0 to the functional circuit. At the same time, the first detection circuit also stores data_0 in the storage area. Address 000 and data_0 can be stored in the same storage area or in different storage areas, and the embodiment of the present invention does not limit this.

[0109] At the rising edge of the third cycle, the read / write signal is a read signal, the chip select signal is valid, and the third address read through the address signal is 001. At this time, the storage area stores address 000, so it is determined that address 000 is different from the storage address in the storage area. The generated second clock signal flips normally in the third cycle, and address 001 is stored in the storage area, and address 000 is deleted from the storage area; because the second clock signal received by the RAM flips, the RAM returns the second read data data_1 read at address 001 to the first detection circuit, and the first detection circuit returns the first read data data_1 to the functional circuit. At the same time, the first detection circuit also stores data_1 in the storage area and deletes data_0 from the storage area.

[0110] At the rising edge of the fourth cycle, the read / write signal is a read signal, the chip select signal is invalid, and no data is read. The generated second clock signal does not flip in the fourth cycle; since the second clock signal received by the RAM does not flip, no data is read in the RAM. The RAM does not return the second read data to the first detection circuit. However, since the storage area stores the read data data_1 of the third cycle, the first detection circuit returns the first read data data_1 to the functional circuit.

[0111] At the rising edge of the fifth cycle, the read / write signal is a read signal, the chip select signal is invalid, no data is read, and the generated second clock signal does not flip in the fifth cycle; since the second clock signal received by the RAM does not flip, no data is read in the RAM. The RAM does not return the second read data to the first detection circuit. However, since the storage area stores the read data data_1 of the third cycle, the first detection circuit continues to return the first read data data_1 to the functional circuit.

[0112] At the rising edge of the sixth cycle, the read / write signal is a read signal, the chip select signal is valid, and the sixth address read through the address signal is 001. At this time, the storage area stores address 001, so it is determined that address 001 is the same as the storage address in the storage area. The generated second clock signal does not flip in the sixth cycle, and address 001 is still stored in the storage area. Since the second clock signal received by the RAM does not flip, no data is read in the RAM. The RAM does not return the second read data to the first detection circuit. However, since the storage area stores the read data data_1 of the third cycle, the first detection circuit continues to return the first read data data_1 to the functional circuit.

[0113] The seventh cycle, the eighth cycle, the ninth cycle, ... are analyzed according to the above analysis method to determine the first reading data and the second reading data.

[0114] It can be found that in the above method, due to the change of the second clock signal, even if there are repeated address read instructions, no reading is performed in the RAM, thereby reducing the power consumption of the RAM. Instead, the data read from the RAM previously stored in the first detection circuit is returned to the functional circuit as the first read data.

[0115] Embodiment 2: Data writing

[0116] The data writing process requires the functional circuit to output a clock signal, a chip selection signal, a read / write signal to the first detection circuit, as well as an address signal and a write data signal to indicate that a certain data is written to a certain address of the RAM.

[0117] Specifically, in the i-th cycle of the first clock signal, the i-th address of the address signal is read; if the chip select signal output by the functional circuit is valid and the read / write signal output by the functional circuit is a write signal, the i-th address is the same as the i-1th address stored in the storage area, and the i-th write data output by the functional circuit is the same as the i-1th write data stored in the storage area, it can be determined that a repeated write operation is performed on the same address of the RAM. Then, a second clock signal that is not flipped in the i-th cycle is generated.

[0118] Optionally, when the chip select signal output by the functional circuit is invalid in the i-th cycle of the first clock signal, a second clock signal that is not flipped in the i-th cycle is also generated. If the clock signal is still flipped when the chip select signal is invalid, the entire device will still operate, and power consumption will still be wasted. Therefore, it is designed that when the chip select signal is invalid, the second clock signal will not flip either.

[0119] Optionally, the first detection circuit also outputs the address signal, chip select signal, read / write signal, and write data signal output by the functional circuit to the RAM, so that the RAM can write data according to these signals. Of course, whether these signals work is determined by the second clock signal. If the second clock signal flips in a certain cycle, the RAM will continue to determine whether to write data according to the chip select signal and the read / write signal; if the second clock signal does not flip in a certain cycle, the RAM will not write data.

[0120] The process of writing data is roughly similar to the process of reading data. The difference is that when writing data, it is necessary not only to determine that the i-th address is the same as the i-1-th address stored in the storage area, but also to determine that the i-th write data is the same as the i-1-th write data stored in the storage area. In this way, it can be determined that the operation is a repetitive operation that wastes power consumption.

[0121] Then, not only the i-1th address but also the i-1th data should be stored in the storage area. Since there is no data to be read, the RAM will not return any data to the first detection circuit, so the storage area does not need to store the data returned to the functional circuit.

[0122] Optionally, when writing data, just as when reading data, it may be determined that the i-th address is the same as the i-1-th address stored in the storage area, which may be regarded as a repeated operation that wastes power consumption.

[0123] The first detection circuit configured as above can avoid power consumption waste caused by the flipping of the clock signal by adjusting the second clock signal, thereby reducing dynamic power consumption.

[0124] Optionally, the data reading and writing circuit may also be provided with a second detection circuit to reduce static power consumption waste.

[0125] Figure 6 A schematic diagram of another possible data reading and writing circuit is shown. A second detection circuit is also included.

[0126] The functional circuit can output some functional signals to indicate whether the functional circuit is in working state. For example, the image processing circuit can output the effective display data selection signal DE, the line synchronization signal HS, the field synchronization signal VS and the sub-function signal. The sub-function signal can be used to calculate the backlight data of the previous image, pre-process the image display, etc. The above functional signal is also a pulse signal, and the level at each moment may be the same or different. At any moment, the level signal is output to the second detection circuit, and the second detection circuit can generate the power consumption indication of the RAM accordingly. For example, when the function signal is set to 1, it means that the functional circuit is in working state and the power consumption indication is in normal mode; when the function signal is set to 0, it means that the functional circuit is in non-working state, and the power consumption indication is in power saving mode, so that the bit line is suspended to reduce leakage. The above is only an example.

[0127] Take ARM RAM as an example. Figure 7 As shown, the function signal of the function circuit is output to the second detection circuit, and the second detection circuit generates a level switch LS signal to RET1N of the SRAM accordingly, and RET1N can control whether the RAM is in normal mode or power saving mode. The power saving mode can be selected as precharge mode and retention mode.

[0128] In this way, the working state of the functional circuit is linked to the power consumption indication of the RAM, and the design of the power consumption indication of the RAM can be realized directly through hardware, with accurate and automatic control, which saves manpower and static power consumption.

[0129] Optionally, Figure 8Another possible control method of the second detection circuit is shown. While the second detection circuit receives the function signal of the function circuit, it also receives the register signal, which is a level signal set by the user. The function signal and the register signal are input into the selector of the second detection circuit, and the selector can select the function signal or the register signal to generate the power consumption indication. In this way, the second detection circuit can not only choose to be controlled by the function signal, but also choose to be manually controlled by the user, which improves the flexibility of generating the power consumption indication and the flexibility of controlling the working state of the RAM. And it saves the power consumption of the RAM.

[0130] Fig. 9 A specific control method of the second detection circuit is shown. The DE signal and the vsync signal output by the image processing circuit determine the non-working interval porch area of ​​the image processing circuit through the DE signal and the vsync signal. For example, the level signal obtained according to the porch area is 1, and the level signal obtained according to the sub-function signal is 1. When both are 1, 1 is output to the selector. As long as one of the two is 0, it means that the image processing circuit is in a working state, and 0 is output to the selector. In this example, 1 is output to the selector, and the register signal is set by the user, for example, it is set to 0, then the selector can choose between 1 and 0. For example, the user sets the selector to select the register signal, then the selector selects the register signal, and the LS signal generated thereby is 0. The LS signal is input to the RAM through the RAM WRAP, and the RAM determines that the power consumption indication is a power saving mode. The above-mentioned design of the level signal, the design of the selector, the corresponding relationship between the level signal and the power consumption indication, etc. are all examples, and those skilled in the art can make various other designs. They are not listed one by one here.

[0131] If the RAM determines the power saving mode, then when receiving the second clock signal from the first detection circuit and other signals for reading and writing data, the RAM reads and writes data in the power saving mode. If the RAM determines the normal mode, then when receiving the second clock signal from the first detection circuit and other signals for reading and writing data, the RAM reads and writes data in the normal mode.

[0132] The above is only an example and is not intended to limit the embodiments of the present invention.

[0133] Based on the same technical concept, Fig.10 A data reading and writing method provided by an embodiment of the present invention is exemplarily shown.

[0134] like Fig.10 As shown, the method specifically includes:

[0135] Step 1001: Based on the address signal output by the functional circuit, determine whether the functional circuit performs repeated read and write operations on the same address on the RAM.

[0136] Step 1002, if it is determined that repeated read and write operations are performed on the RAM at the same address, a second clock signal is generated based on the periodically flipped first clock signal output by the functional circuit and the second clock signal is output to the RAM; the second clock signal does not flip during the repeated read and write operations.

[0137] Optionally, determining to perform repeated read and write operations on the same address on the RAM includes:

[0138] In the i-th cycle of the first clock signal, reading the i-th address of the address signal;

[0139] When the i-th address is the same as the i-1-th address, the chip select signal output by the functional circuit is valid, and the read / write signal output by the functional circuit is a read signal, determining to perform a repeated read operation on the same address of the RAM;

[0140] When the chip select signal output by the functional circuit is valid and the read / write signal output by the functional circuit is a write signal, the i-th address is the same as the i-1-th address, and the i-th write data output by the functional circuit is the same as the i-1-th write data, it is determined that a repeated write operation is performed on the same address of the RAM.

[0141] Optionally, the method further comprises:

[0142] The read data of the i-th address read from the RAM in the m-th cycle stored in the storage area is output to the functional circuit; the m-th cycle is the first cycle in which the functional circuit continuously reads data from the i-th address.

[0143] Optionally, the method further comprises:

[0144] In the i-th cycle of the first clock signal, when it is determined that the chip selection signal output by the functional circuit is invalid, a second clock signal that is not flipped in the i-th cycle is generated.

[0145] Optionally, the method further comprises:

[0146] The address signal, chip selection signal, read / write signal, and write data signal output by the functional circuit are output to the RAM.

[0147] Optionally, the method further comprises:

[0148] According to the function signal output by the function circuit, the power consumption indication of the RAM is generated, so that the RAM determines whether to reduce the leakage current according to the power consumption indication; the function signal is used to indicate whether the function circuit is in working state.

[0149] Optionally, the functional circuit is an image processing circuit;

[0150] The functional signal includes any one or more of the following: a valid display data selection signal DE, a line synchronization signal HS, a field synchronization signal VS and a sub-functional signal.

[0151] Optionally, generating a power consumption indication of the RAM according to a function signal output by the function circuit includes:

[0152] The power consumption indication of the RAM is generated according to the function signal and the register signal output by the function circuit; the register signal is set by the user.

[0153] Based on the same technical concept, the embodiment of the present invention also provides a chip, such as Fig.11 As shown, it includes a printed circuit board PCB and a data reading and writing circuit as described in any one of the above items; the data reading and writing circuit is arranged on the PCB.

[0154] Based on the same technical concept, an embodiment of the present invention further provides an electronic device, such as Fig.12 As shown, it includes a printed circuit board PCB, and the data reading and writing circuit as described in any one of the above items is arranged on the PCB.

[0155] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0156] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0157] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0158] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0159] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data reading and writing circuit, characterized in that: It includes a functional circuit, a first detection circuit and a random access memory RAM; The functional circuit is used to perform read and write operations on the RAM through the first detection circuit; The first detection circuit includes a storage area, and the storage area is used to: store address information in a previous address signal output by the functional circuit when performing a read and write operation on the RAM, and also store write data in a previous data signal output by the functional module when performing a write operation on the RAM; The first detection circuit is used to determine, based on the read / write signal output by the functional circuit, the address information in the address signal currently output by the functional circuit, and the address information in the previous address signal stored in the storage area, that when the functional circuit performs a repeated read operation on the RAM at the same address, generate a second clock signal that does not flip during the repeated read operation based on the first clock signal that flips periodically output by the functional circuit, and output the second clock signal to the RAM, or According to the read / write signal output by the functional circuit, the address information in the address signal currently output by the functional circuit, the address information in the last address signal stored in the storage area, the write data in the data signal output by the functional circuit, and the write data in the last data signal stored in the storage area, when determining that the functional circuit performs a repeated write operation on the RAM at the same address, a second clock signal that does not flip during the repeated write operation is generated based on the first clock signal, and the second clock signal is output to the RAM; The RAM is used to perform read and write operations based on the second clock signal.

2. The circuit according to claim 1, characterized in that The first detection circuit is used to generate a second clock signal that is not flipped in the i-th cycle when it is determined that the chip selection signal output by the functional circuit is valid and the read-write signal is a read signal, and the i-th address of the address signal read in the i-th cycle of the first clock signal is the same as the i-1-th address stored in the storage area; The first detection circuit is also used to output the read data of the i-th address read from the RAM in the m-th cycle stored in the storage area to the functional circuit; the m-th cycle is the first cycle in which the functional circuit continuously reads data from the i-th address.

3. The circuit according to claim 1, characterized in that The first detection circuit is used to generate a second clock signal that is not flipped in the i-cycle when it is determined that the chip select signal output by the functional circuit is valid and the read-write signal is a write signal, the i-th address of the address signal read in the i-th cycle of the first clock signal is the same as the i-1-th address stored in the storage area, and the i-th write data output by the functional circuit is the same as the i-1-th write data stored in the storage area.

4. The circuit according to claim 1, characterized in that The first detection circuit is further configured to generate a second clock signal that is not flipped in the i-th cycle when it is determined in the i-th cycle of the first clock signal that the chip select signal output by the functional circuit is invalid.

5. The circuit according to any one of claims 1 to 4, characterized in that: Also includes: a second detection circuit; The second detection circuit is used to generate a power consumption indication of the RAM according to the function signal output by the function circuit; The functional signal is used to indicate whether the functional circuit is in a working state; The RAM is further used to determine whether to reduce leakage current according to the power consumption indication.

6. The circuit according to claim 5, characterized in that The functional circuit is an image processing circuit; The functional signal includes any one or more of the following: a valid display data selection signal DE, a line synchronization signal HS, a field synchronization signal VS and a sub-functional signal.

7. The circuit according to claim 5, characterized in that The second detection circuit is specifically used to generate a power consumption indication of the RAM according to a function signal and a register signal output by the function circuit; the register signal is set by a user.

8. A chip, characterized in that: It comprises a printed circuit board PCB and a data reading and writing circuit as described in any one of claims 1 to 7; the data reading and writing circuit is arranged on the PCB.

9. A data reading and writing method, characterized in that: include: When it is determined that the functional circuit performs a repeated read operation on the RAM at the same address according to the read / write signal output by the functional circuit, the address information in the address signal currently output by the functional circuit, and the address information in the previous address signal stored in the storage area of ​​the first detection circuit, a second clock signal that does not flip during the repeated read operation is generated by the first detection circuit based on the first clock signal that flips periodically output by the functional circuit, and the second clock signal is output to the RAM; When it is determined that the functional circuit performs a repeated write operation on the RAM to the same address based on the read / write signal output by the functional circuit, the address information in the address signal currently output by the functional circuit, the address information in the last address signal stored in the storage area, the write data in the data signal output by the functional circuit, and the write data in the last data signal stored in the storage area, a second clock signal that does not flip during the repeated write operation is generated based on the first clock signal by the first detection circuit, and the second clock signal is output to the RAM; Performing read and write operations on the RAM based on the second clock signal; When the functional circuit performs read and write operations on the RAM through the first detection circuit, the storage area stores the address information in the last address signal output by the functional circuit, and when the RAM is written, the storage area also stores the write data in the last data signal output by the functional module.

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