Power management for memory devices

Abstract

This application is directed to power management for memory devices. For example, a memory device can include one or more memory dies and can be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage can be associated with a first defined voltage range, and the second supply voltage can be associated with a second defined voltage range. The memory device can include a power management integrated circuit (PMIC) coupled with the one or more memory dies and providing the supply voltages to the one or more memory dies. The PMIC can be configured to provide a first voltage within the first defined voltage range as the first supply voltage and a second voltage outside the second defined voltage range as the second supply voltage to the one or more memory dies.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 094,579, filed November 10, 2020, entitled “Power Management for a Memory Device,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to power management for memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of those states. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM, synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time, even without external power. Volatile memory devices, such as DRAM, may lose their stored state when disconnected from external power. Summary of the Invention

[0006] Describe a system. The system may include: a memory die configured to operate using a first supply voltage and a second supply voltage, wherein the first supply voltage is associated with a first defined voltage range and the second supply voltage is associated with a second defined voltage range; and a power management integrated circuit (PMIC) coupled to the memory die and configured to: provide a first voltage within the first defined voltage range as the first supply voltage to the memory die; and provide a second voltage outside the second defined voltage range as the second supply voltage to the memory die.

[0007] A method is described. The method may include: using a PMIC coupled to a memory die to generate a first voltage within a first defined voltage range corresponding to a first supply voltage of the memory die; using the PMIC to generate a second voltage outside a second defined voltage range corresponding to a second supply voltage of the memory die; and operating the memory die using the first voltage as the first supply voltage and using the second voltage as the second supply voltage.

[0008] Another method is described. The method may include: testing one or more performance characteristics of each memory die in a set of memory dies when a second voltage is supplied to each memory die, wherein the second voltage is different from a first voltage corresponding to a default supply voltage for each memory die in the set of memory dies; identifying, at least in part based on the test, a subset of memory dies within the set of memory dies that each satisfies a performance threshold when supplied with the second voltage; assembling a memory device including a PMIC and the subset of memory dies, at least in part based on the identification of the subset of memory dies; and setting the output voltage of the PMIC to be equal to the second voltage, wherein the PMIC is configured to supply the second voltage to the subset of memory dies during operation of the memory device, at least in part based on the output voltage of the PMIC being set to the second voltage. Attached Figure Description

[0009] Figure 1-3 This document describes examples of systems that support power management for memory devices, based on the examples disclosed herein.

[0010] Figure 4 This document describes an example of a process flow that supports power management for memory devices, based on the examples disclosed herein.

[0011] Figure 5 A block diagram of a system for power management of a memory device is shown, according to aspects of this disclosure.

[0012] Figure 6 and 7 A flowchart illustrating one or more methods for power management of memory devices, based on examples disclosed herein, is shown. Detailed Implementation

[0013] A memory device may receive one or more supply voltages to enable it to supply voltage to its various components. In some cases, a default value or range for the supply voltage may be defined (e.g., a range may correspond to a value plus or minus a tolerance). For example, a default value or range for the supply voltage may be defined in a standard applicable to memory devices (e.g., a JEDEC standard, or another standard). Here, a memory device operating with a supply voltage within a defined voltage range may be expected to meet one or more performance thresholds (e.g., a speed threshold, a reliability threshold, or another threshold for performing access operations).

[0014] However, in some cases, supplying a memory device with a supply voltage outside the defined voltage range (e.g., below or above the defined voltage range) can improve one or more metrics of the memory device (e.g., power consumption, speed, reliability). For example, a memory device may meet one or more performance thresholds based on receiving a supply voltage below the defined voltage range. Here, supplying a memory device with a supply voltage below the defined voltage range can reduce the power consumption of the memory device without preventing the memory device from meeting one or more performance thresholds. In another example, supplying a memory device with a supply voltage above the defined voltage range can improve the performance of the memory device (e.g., increase the speed, improve the reliability) compared to supplying a memory device with a supply voltage within the defined voltage range, or can increase production yield associated with producing the memory device by allowing one or more components (e.g., memory dies) that would otherwise not meet the performance thresholds to instead meet them. These benefits are exemplary, and those skilled in the art will appreciate other benefits of supplying a memory device with a supply voltage outside the default (e.g., standardized or otherwise defined) voltage range.

[0015] This document describes techniques for supplying a memory device with a supply voltage outside a defined voltage range associated with the memory device or one or more of its components (e.g., memory dies). For example, the memory device may be coupled to a power management integrated circuit (PMIC) configured to supply one or more supply voltages to the memory device (e.g., to one or more memory dies on the memory device). The PMIC may supply the memory device with supply voltages (e.g., drain supply voltage (VDD), programming supply voltage (VPP)) outside a defined voltage range (e.g., as defined by standards). For example, if the memory device meets a performance threshold when supplied with a voltage below the defined voltage range, the PMIC may provide a supply voltage below the defined voltage range, thereby reducing power consumption while maintaining the performance of the memory device (e.g., compared to the PMIC providing a supply voltage within the defined voltage range). Alternatively or concurrently, the PMIC may provide a supply voltage above the defined voltage range to improve the performance of the memory device (e.g., increase the operating speed of the memory device, improve the reliability of the memory device).

[0016] Initially, in reference Figure 1-3 Features of this disclosure are described in the context of the systems and apparatus described herein. (See references...) Figure 4 The features of this disclosure are described in the context of the described process flow. (This is achieved through references to...) Figure 5-7 The device diagrams and flowcharts for power management of memory devices further illustrate and describe these and other features of this disclosure with reference to the device diagrams and flowcharts.

[0017] Figure 1 This document describes an example of a system 100 supporting power management for memory devices, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0018] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptops, tablets, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of system 100 that can be used to store data for one or more other components of system 100.

[0019] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other instances. In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0020] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various physical package dimensions for host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0021] Memory device 110 may be operable to store data for components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0022] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0023] Processor 125 may be operable to provide control or other functionality for at least a portion of system 100 or host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0024] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0025] Memory device 110 may include device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Additionally, memory device 110 may include one or more PMICs 175 coupled to the memory dies 160. In some instances, memory device 110 may be a dual in-line memory module (DIMM). In some instances, one or more memory dies 160 may each contain a dynamic random access memory (DRAM) cell. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more groups, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. The memory device 110 comprising two or more memory dies 160 may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0026] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0027] A local memory controller 165 (e.g., locally for memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, the local memory controller 165 may be used to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, the memory device 110 may not include a device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

[0028] External memory controller 120 can be used to enable one or more of the following to be communicated between system 100 or a component of host device 105 (e.g., processor 125) and memory device 110: information, data, or commands. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0029] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to serve as part of channel 115.

[0030] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be transmitted on channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol of a signal (e.g., signal level) may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols of a signal (e.g., signal levels) may be registered for each clock cycle (e.g., on the rising and falling edges of the clock signal).

[0031] PMIC 175 can provide various supply voltages to components of memory device 110 (e.g., to one or more memory dies 160, device memory controller 155, or another component of memory device 110), and memory dies 160 can be configured to operate using the provided supply voltages. In some cases, the supply voltages may be defined by a standard (e.g., a JEDEC standard) or otherwise defined according to a standard (e.g., a JEDEC standard). For example, the standard may define a voltage range for the supply voltages. Here, memory die 160 operating using a supply voltage within the defined voltage range may be expected to meet one or more performance thresholds (e.g., a speed threshold for performing access operations, a reliability threshold). For example, the standard may indicate that memory die 160 receiving a supply voltage within the defined voltage range is expected to operate at a specific speed or higher. In another example, the standard may indicate that memory die 160 receiving a supply voltage within the defined voltage range is expected to meet a reliability threshold.

[0032] Memory die 160 may satisfy one or more performance thresholds when supplied with voltages outside a defined voltage range (e.g., as defined by a standard). Here, PMIC 175 may be configured to supply a voltage outside the defined voltage range to memory die 160. For example, PMIC 175 may supply a voltage below the defined voltage range to memory die 160, thereby saving power. In some other instances, PMIC 175 may supply a voltage above the defined voltage range to memory die 160, thereby improving the performance of memory die 160. In any instance, memory device 110 may be assembled to include memory die 160 having similar performance characteristics, and PMIC 175 may be configured to supply a supply voltage based on the performance characteristics of memory die 160. For example, memory device 110 may be assembled to include memory dies 160 that each satisfy one or more performance thresholds when receiving a supply voltage below the defined voltage range. Here, PMIC 175 may be additionally configured to provide a supply voltage below the defined voltage range to each of the memory dies 160. In another embodiment, memory device 110 may be assembled to include memory dies 160 that each have improved performance metrics when receiving a supply voltage above the defined voltage range. Here, PMIC 175 may be additionally configured to provide a supply voltage above the defined voltage range to each of the memory dies 160.

[0033] Figure 2 This document describes an example of a system 200 for power management of a memory device, based on the examples disclosed herein. System 200 may be implemented with reference to... Figure 1The described aspects of system 100. For example, system 200 may include memory device 210, which may be referenced. Figure 1 An example of the described memory device 110. The memory device 210 may include one or more memory dies 260 and PMICs 275. For example, the memory device 210 may include memory dies 260-a, memory dies 260-b, memory dies 260-c, and PMICs 275, which may be referenced respectively. Figure 1 Examples of the described memory die 160 and PMIC 175.

[0034] In some cases, memory device 210 may be an instance of a DIMM or a small-size DIMM (SO-DIMM). Here, memory device 210 may be packaged into a component or module so that memory device 210 can be integrated into a larger device (e.g., using one or more ports or connectors). Memory device 210 may include a set of memory dies 260, each of which may be configured to operate using one or more supply voltages. For example, memory die 260 may be configured to receive a first supply voltage (e.g., VDD 220), a second supply voltage (e.g., output stage drain supply voltage (VDDQ) 230), a third supply voltage (e.g., VPP 240), and a fourth supply voltage (e.g., ground supply voltage (VSS) 250). In some cases, the values ​​of one or more of the supply voltages VDD 220, VDDQ 230, VPP 240, and VSS 250 may be specified (e.g., defined) by a standard (e.g., a JEDEC standard). In some cases, the supply voltage may be specified by a defined voltage range. For example, the standard may indicate the nominal voltage value of the supply voltage (e.g., 1.1V for VDD 220 and VDDQ 230, 1.8V for VPP 240, and system ground for VSS 250) and the tolerance of the supply voltage (e.g., a percentage greater or less than the nominal voltage value). Therefore, each of the supply voltages VDD 220, VDDQ 230, VPP 240, and VSS 250 may be associated with a defined voltage range.

[0035] Memory device 210 may include a PMIC 275 configured to supply voltages VDD 220, VDDQ 230, and VPP 240 to each of the memory dies 260 of memory device 210. That is, PMIC 275 may be configured to manage the power constraints of the various components of memory device 210, including memory dies 260-a, 260-b, and 260-c. Here, PMIC 275 may perform current conversion, power selection, voltage scaling, power sequence, or deactivation state power control, or any combination thereof, to provide appropriate voltages to the various components of memory device 210 (e.g., memory dies 260). In some cases, memory dies 260 and PMIC 275 may each share (e.g., coupled to) a common VSS 250. In some cases, VSS 250 may be supplied by PMIC 275 along with VDD 220, VDDQ 230 and VPP 240, or alternatively, VSS 250 may be supplied by another component (not shown) of memory device 210 or may be a common ground reference.

[0036] The voltage level of each of the supply voltages (e.g., VDD 220, VDDQ 230, and VPP 240) output by the PMIC 275 can be adjusted before the operation of the system 200 (e.g., before the system 200 is connected to a reference voltage). Figure 1 The system 200 is configured during initialization prior to the described host device communication. In one example, the voltage level of each of the supply voltages output by the PMIC 275 may be configured before assembling the memory device 210 (e.g., before coupling the memory die 260 to the memory device 210). In another example, the voltage level of each of the supply voltages output by the PMIC 275 may be configured after assembling the memory device 210 (e.g., after each of the memory dies 260 is coupled to the memory device 210 and the PMIC 275).

[0037] PMIC 275 can identify (e.g., during system 200 initialization) which voltages are supplied to memory die 260 as VDD 220, VDDQ 230, and VPP 240. Subsequently, during subsequent operation of system 200, PMIC 275 can supply the identified voltages to memory die 260 as VDD 220, VDDQ 230, and VPP 240. In some cases, PMIC 275 can identify the voltage levels of VDD 220, VDDQ 230, and VPP 240 based on one or more values ​​stored in registers (e.g., coupled to or contained in PMIC 275). Here, PMIC 275 can read the values ​​stored in the registers (e.g., during system 200 initialization) and identify the voltage levels of VDD 220, VDDQ 230, and VPP 240 based on the values ​​stored in the registers. In some instances, configuring the voltage level of each of the supply voltages (e.g., VDD 220, VDDQ230, and VPP 240) of the PMIC 275 output may involve programming (e.g., writing) the value to a register.

[0038] The value of the supply voltage provided by PMIC 275 can be configured to be fixed (e.g., locked, static) for each of the supply voltages output by PMIC 275 (e.g., VDD 220, VDDQ 230, and VPP 240). That is, the supply voltage provided by PMIC 275 can be immutable after system 200 is assembled, during system 200 operation, or both. In some cases, memory device 210 can be integrated with components that are part of system 200 (e.g., ...). Figure 1 Referring to the description, the host device communicates, and the host device may not be able to change the voltage levels of VDD 220, VDDQ 230, and VPP 240 (e.g., during system 200 operation or at other times). Therefore, the values ​​of VDD 220, VDDQ 230, and VPP 240 may be fixed (e.g., locked). In an instance where the voltage levels of VDD 220, VDDQ 230, and VPP 240 are configured based on one or more values ​​in a register, the register may be a one-time programmable register (e.g., a fuse, a fuse array). Therefore, after the register is initially programmed, the host device may not be able to program the register to different values.

[0039] In some cases, PMIC 275 may be configured to provide one or more supply voltages, each within a defined voltage range associated with each of the supply voltages. In other cases, PMIC 275 may be configured to provide one or more supply voltages outside the defined voltage range associated with the supply voltage. That is, PMIC 275 may provide at least one supply voltage (e.g., VDD 220, VDDQ 230, VPP 240) outside the defined voltage range to memory die 260. For example, PMIC 275 may be configured to provide one or more supply voltages (e.g., VDD 220, VPP 240, or both) having a voltage level below the defined voltage range to memory die 260. That is, memory die 260 may meet performance thresholds when supplied with supply voltages below the defined voltage range (e.g., VDD 220, VPP 240, or both). Here, PMIC 275 may provide a lower supply voltage to save power.

[0040] Alternatively, PMIC 275 may be configured to supply one or more supply voltages (e.g., VDD 220, VPP 240, or both) having voltage levels greater than a defined voltage range to memory die 260. That is, the performance metrics of memory die 260 can be improved by supplying one or more supply voltages greater than a defined voltage range to memory die 260. In some cases, memory die 260 may fail to meet performance thresholds when supplied with supply voltages within a defined voltage range. Here, PMIC 275 may be configured to ensure that supplying supply voltages greater than a defined voltage range ensures that memory die 260 meets performance thresholds. In some other cases, memory die 260 meets performance thresholds when supplied with supply voltages within a defined voltage range, and PMIC 275 may be configured to supply one or more supply voltages greater than a defined voltage range to further improve the performance of memory die 260 (e.g., increase the speed of memory die 260, improve the reliability of memory die 260).

[0041] Figure 3 This document describes an example of a system 300 supporting power management for memory devices, based on the examples disclosed herein. System 300 can be implemented separately as described below. Figure 1 and 2 The described aspects of systems 100 and 200. For example, system 300 may include memory device 310-a and memory device 310-b, which may be referenced. Figure 1 and 2Examples of the described memory devices. Memory devices 310-a and 310-b may include one or more memory dies 360 and PMIC 375, which may be referenced. Figure 1 and 2 Examples of memory dies and PMICs described herein. Memory device 310-a may include memory dies 360-a, 360-b and 360-c and PMIC 375-a, and memory device 310-b may include memory dies 360-d, 360-e and 360-f and PMIC 375-b.

[0042] System 300 may include more than one memory device 310, wherein each memory device 310 includes a separate PMIC 375 and distinct memory dies 360. In some cases, the memory devices 310 may be configured separately. In some cases, system 300 may include memory devices 310 with different configurations. Alternatively, system 300 may include memory devices 310 with the same configuration. In some cases, memory devices 310 may be grouped into the same corresponding memory device 310 based on the performance characteristics of the memory dies 360 of memory devices 310. For example, each of the memory dies 360 of memory devices 310 may have similar performance characteristics. That is, memory device 310-a may be configured based on each of memory dies 360-a, 360-b, and 360-c with similar performance characteristics to each other, and memory device 310-b may be configured based on each of memory dies 360-d, 360-e, and 360-f with similar performance characteristics to each other. However, in another instance, the memory device 310 may include a memory die 360 ​​with different performance characteristics.

[0043] The performance characteristics of memory die 360 ​​may be related to whether memory die 360 ​​meets a performance threshold when supplied with supply voltages of different voltage levels. That is, if two memory dies 360 meet the performance threshold when supplied with a supply voltage within a defined voltage range (e.g., VDD 320, VDDQ 330, VPP 340, VSS 350), then the two memory dies 360 may have similar performance characteristics.

[0044] In one scenario, memory dies 360-a, 360-b, and 360-c may have similar performance characteristics to each other, and memory dies 360-d, 360-e, and 360-f may have similar performance characteristics to each other, but memory die 360 ​​of memory device 310-a may or may not have performance characteristics similar to those of memory die 360 ​​of memory device 310-b. For example, memory dies 360-a, 360-b, and 360-c of memory device 310-a may meet a performance threshold when supplied with a supply voltage below a defined voltage range associated with a supply voltage (e.g., VDD 320-a, VPP 340-a, or both). Therefore, PMIC 375-a may be configured to supply a supply voltage below the defined voltage range to memory dies 360-a, 360-b, and 360-c. Alternatively, PMIC 375-a may be configured to supply one or more supply voltages within a defined voltage range associated with one or more supply voltages (e.g., one or more of VDD 320-a, VDDQ 330-a, VPP 340-a, and VSS 350-a) to memory dies 360-a, 360-b, and 360-c.

[0045] In another example, one or more of the memory dies 360-d, 360-e, and 360-f of memory device 310-b may fail to meet performance thresholds when supplied with one or more supply voltages below a defined voltage range (e.g., VDD 320-b or VPP 340-b, or both). Here, PMIC 375-b may be configured to provide one or more supply voltages, respectively, within the defined voltage range, to memory dies 360-d, 360-e, and 360-f. In some other cases, one or more of the memory dies 360-d, 360-e, and 360-f may fail to meet performance thresholds when supplied with one or more supply voltages within a defined voltage range. Here, PMIC 375-b may be configured to provide one or more supply voltages greater than the defined voltage range to memory dies 360-d, 360-e, and 360-f. In some other cases, one or more of memory dies 360-d, 360-e, and 360-f can meet performance thresholds when supplied with one or more supply voltages within a defined voltage range, and PMIC 375-b can be configured to provide one or more supply voltages greater than the defined voltage range to further improve the performance of memory dies 360-d, 360-e, and 360-f.

[0046] Therefore, the memory device 310 (and the corresponding PMIC 375) can be configured based on the performance characteristics of the memory die 360 ​​associated with each memory device 310.

[0047] Figure 4 This document describes an example of a process flow 400 supporting power management for a memory device, based on the examples disclosed herein. Aspects of process flow 400 may be implemented by test equipment, manufacturing equipment, or any combination thereof. For example, aspects of process flow 400 may be implemented to test and assemble a memory device, which may be a reference device. Figures 1 to 3 An example of a memory device is described. Process flow 400 can be implemented to save power and improve the performance of the memory device during operation. In the following description of process flow 400, the operations may be performed in different orders or at different times. Some operations may also be omitted from process flow 400, and other operations may be added to process flow 400.

[0048] At position 405, one or more performance characteristics of each memory die in the memory die set can be tested. For example, one or more timing parameters of the memory die can be tested, such as array access time (T). AA Row address to column address delay (T) RCD ), write recovery time (T) WR ), or clock cycle (T) CK For example, one or more supply voltages can be used to test each memory die to verify whether each memory die meets one or more performance thresholds (e.g., corresponding performance thresholds for each tested performance characteristic) when supplied with a given voltage. In some cases, the given voltage may be VDD or VPP. At 410, it can be determined whether the memory die meets one or more performance thresholds when supplied with a reduced voltage (e.g., a voltage lower than the memory die's default (e.g., normalized or otherwise defined) supply voltage). If the memory die meets one or more performance thresholds when supplied with a reduced voltage, then the process may proceed to 415. Alternatively, if the memory die fails to meet the performance thresholds when supplied with a reduced voltage, then the process may proceed to 435.

[0049] At 415, a memory die can be classified as a low-voltage memory die based on determining that it meets one or more performance thresholds when supplied with a reduced voltage. At 420, a memory device can be assembled to include one or more low-voltage memory dies and a PMIC. At 425, the output voltage of the PMIC (e.g., VDD, or VPP, or both) can be set to a reduced voltage. At 430, the memory device can be operated using the reduced voltage. For example, the memory device can be incorporated into a system where it communicates with a host device and can perform one or more access operations when receiving one or more supply voltages less than a default voltage range associated with the supply voltage.

[0050] At 435, it can be determined whether the memory die meets one or more performance thresholds when received with a supply voltage of the nominal voltage (e.g., within the memory die's default voltage range, such as a default value plus or minus a tolerance). If it is determined that the memory die meets one or more performance thresholds when received with a supply voltage of the nominal voltage, then the process can proceed to 440. Alternatively, if it is determined that the memory die fails to meet the performance thresholds when supplied with the nominal voltage, then the process can proceed to 460. At 460, it can be determined whether the memory die meets one or more performance thresholds when received with an increased supply voltage (e.g., above the memory die's default voltage range). If it is determined that the memory die meets one or more performance thresholds when received with an increased supply voltage, then the process can proceed to 465. In some cases, if it is determined that the memory die fails to meet the performance thresholds when supplied with an increased voltage, then the process can proceed to 485, and the memory die can be discarded. Although Figure 4 The example illustrates that the determination at 435 occurs after the determination at 410, but it should be understood that the determination at 435 may alternatively occur before the determination at 410, and in general, aspects of process flow 400 may otherwise be time-dependent. Figure 4 The instances were rearranged.

[0051] At 440, a memory die can be classified as a nominal voltage memory die based on determining that it meets one or more performance thresholds at the nominal voltage. Alternatively, a memory die can be classified as a nominal voltage die based on determining that it fails to meet one or more performance thresholds at a reduced voltage (e.g., at 410), and the separate determination at 435 may not be performed.

[0052] At 445, the memory device can be assembled to include one or more nominal voltage memory dies and a PMIC. At 450, the output voltage of the PMIC (e.g., contained on the nominal voltage memory die) can be set to the nominal voltage. For example, one or more supply voltages (e.g., VDD, VPP) provided by the PMIC can be set to the nominal voltage. At 455, the memory device can be operated using the nominal voltage. For example, the memory device can be incorporated into a system where it communicates with a host device and can perform one or more access operations upon receiving a supply voltage within a defined voltage range.

[0053] In some cases, at 465, a memory die may be classified as a boost-voltage memory die. For example, a memory die may be classified as a boost-voltage memory die based on failing an evaluation at 435. Alternatively, a memory die may be classified as a boost-voltage memory die based on meeting one or more performance thresholds using a boost voltage (e.g., a voltage above a defined voltage range for the memory die). At 470, a memory device may be assembled to include one or more boost-voltage memory dies and a PMIC. At 475, the output voltage of the PMIC (e.g., contained on the boost-voltage memory die) may be set to a boost voltage. For example, the VDD or VPP provided by the PMIC, or both, may be set to a boost voltage. At 480, the memory device may be operated using the boost voltage. For example, the memory device may be incorporated into a system where the memory device communicates with a host device and can perform one or more access operations when receiving one or more supply voltages above a defined voltage range associated with the supply voltage.

[0054] In an example of process flow 400, one or more performance characteristics of the memory die can be tested before the memory device is assembled. However, alternatively, one or more performance characteristics of the memory die can be tested after the memory device is assembled. Here, the voltage level of each of the supply voltages output by the PMIC can be configured based on the testing of the memory die contained in the same memory device as the PMIC after the memory device is assembled.

[0055] For example, a memory device can be assembled to include a set of memory dies and a PMIC, wherein the memory dies may or may not have been previously tested separately. Testing can then be performed to determine whether each of the memory dies included in the memory device meets one or more performance thresholds when receiving one or more supply voltages less than a defined voltage range (e.g., when receiving one or more reduced voltages). If each memory die meets one or more performance thresholds, the PMIC can be configured to provide one or more reduced voltages to the memory device. Alternatively, if one or more of the memory dies fail to meet the performance thresholds when receiving one or more reduced voltages, the PMIC can be configured to provide the nominal supply voltage to the memory device. In some cases, a test apparatus can test each of the memory dies in the memory device at a nominal voltage (e.g., after assembly). If one or more memory dies fail to meet one or more performance thresholds at the nominal voltage, or fail to improve the performance of the memory dies, the PMIC can be configured to provide one or more increased (e.g., greater than a defined voltage range) supply voltages.

[0056] Figure 5A block diagram 500 illustrates a system 505 supporting power management for a memory device, according to an example disclosed herein. System 505 may be referenced. Figures 1 to 3 Examples of aspects of the described system. System 505 may include a supply voltage manager 510 and an operation manager 515. Each of these modules may communicate directly or indirectly (e.g., via one or more buses). In some cases, the supply voltage manager 510 may be or be included in a PMIC as described herein, and the operation manager 515 may be included in a memory die as described herein. In some cases, the system may include multiple memory dies, each of which may contain a corresponding operation manager 515.

[0057] The supply voltage manager 510 may use a PMIC coupled to the memory die to generate a first voltage within a first defined voltage range corresponding to a first supply voltage of the memory die. In some instances, the supply voltage manager 510 may use a PMIC to generate a second voltage outside a second defined voltage range corresponding to a second supply voltage of the memory die. In some cases, the supply voltage manager 510 is configured to provide a second voltage based on the memory die meeting a performance threshold when the second voltage is used as the second supply voltage.

[0058] In some cases, the supply voltage manager 510 can identify a second voltage during the initialization process executed before operating the memory die. In some cases, the second voltage is lower than a second defined voltage range. In some cases, the second voltage is higher than a second defined voltage range.

[0059] Operation manager 515 can operate memory dies using a first voltage as a first supply voltage and a second voltage as a second supply voltage. In some cases, the memory die is configured to exchange signaling with a host device according to a memory standard. In some cases, defining the first and second defined voltage ranges includes specifying the first and second defined voltage ranges by means of a memory standard. In some instances, operation manager 515 can use the first and second voltages as one or more corresponding first supply voltages and one or more second supply voltages for one or more additional memory dies coupled to a PMIC.

[0060] Figure 6 A flowchart illustrating one or more methods 600 for power management of a memory device according to aspects of this disclosure is shown. Operation of method 600 may be implemented by a system or its components as described herein. For example, operation of method 600 may be performed by, as referenced... Figure 5The system described is executed. In some instances, the system can execute a set of instructions to control the functional elements of the system to perform the described functions. Alternatively, the system may use dedicated hardware to perform aspects of the described functions.

[0061] At 605, the system can use a PMIC coupled to the memory die to generate a first voltage within a first defined voltage range corresponding to a first supply voltage of the memory die. Operation of 605 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 5 The described aspect of the supply voltage manager performs the operation of 605.

[0062] At 610, the system can use the PMIC to generate a second voltage outside the second defined voltage range corresponding to the second supply voltage of the memory die. Operation of 610 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 5 The described aspect of the supply voltage manager performing the operation of 610.

[0063] At point 615, the system can operate the memory die using a first voltage as a first supply voltage and a second voltage as a second supply voltage. The operation at point 615 can be performed according to the method described herein. In some instances, it can be achieved by referring to... Figure 5 The described operation manager performs the operations of 615.

[0064] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: generating a first voltage within a first defined voltage range corresponding to a first supply voltage of the memory die using a PMIC coupled to the memory die; generating a second voltage outside a second defined voltage range corresponding to a second supply voltage of the memory die using the PMIC; and operating the memory die using the first voltage as the first supply voltage and using the second voltage as the second supply voltage.

[0065] Some examples of the method 600 and apparatus described herein may additionally include operations, features, means, or instructions for operating one or more additional memory dies coupled to the PMIC using the first voltage and the second voltage as one or more corresponding first supply voltages and one or more second supply voltages of the one or more additional memory dies.

[0066] In some cases of the method 600 and apparatus described herein, generating the second voltage may additionally include operations, features, means, or instructions for identifying the second voltage during an initialization procedure executed prior to operating the memory die.

[0067] In some cases of the method 600 and apparatus described herein, the second voltage may be lower than the second defined voltage range.

[0068] In some instances of the method 600 and apparatus described herein, the second voltage may be higher than a second defined voltage range.

[0069] Figure 7 A flowchart illustrating one or more methods 700 for power management of a memory device according to aspects of this disclosure is shown. Operation of method 700 may be carried out by test equipment, manufacturing equipment, or any combination thereof as described herein.

[0070] At 705, a test apparatus, manufacturing apparatus, or any combination thereof can test one or more performance characteristics of each memory die in the memory die set when each memory die in the set is supplied with a second voltage, wherein the second voltage is different from a first voltage corresponding to a default supply voltage for each memory die in the memory die set. Operation 705 can be performed according to the method described herein.

[0071] At 710, a test apparatus, manufacturing apparatus, or any combination thereof may, based on the test, identify a subset of memory dies within the set that each meets a performance threshold when supplied with the second voltage. Operation 710 may be performed according to the method described herein.

[0072] At point 715, testing equipment, manufacturing equipment, or any combination thereof may assemble the memory device into a configuration including the PMIC and the subset of memory dies based on the identification of the subset of memory dies. Operation at point 715 may be performed according to the methods described herein.

[0073] At 720, a test apparatus, manufacturing apparatus, or any combination thereof may set the output voltage of the PMIC to be equal to the second voltage, wherein the PMIC is configured to supply the second voltage to a subset of the memory dies during operation of the memory device, based on the output voltage of the PMIC being set to the second voltage. Operation 720 may be performed according to the method described herein.

[0074] At point 725, the test equipment, manufacturing equipment, or any combination thereof can verify the performance of the memory device when the memory device is supplied with a second voltage. In one example, the test equipment or manufacturing equipment can determine, based on verifying the performance of the memory device, that the memory device meets one or more performance thresholds when supplied with the second voltage. Here, the memory device can then operate while the second voltage is supplied. In another example, the test equipment or manufacturing equipment can determine that the memory device fails to meet one or more performance thresholds when supplied with the second voltage. Here, the test equipment or manufacturing equipment can reconfigure the output voltage of the PMIC (e.g., reconfigure it to a first voltage, which enables the memory device to meet one or more performance thresholds).

[0075] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: testing one or more performance characteristics of each memory die in the memory die set when a second voltage is supplied to each memory die in the memory die set, wherein the second voltage is different from a first voltage corresponding to a default supply voltage for each memory die in the memory die set; based on the test, identifying a subset of memory dies in the memory die set that each meets a performance threshold when supplied with the second voltage; based on the identification of the subset of memory dies, assembling a memory device comprising a PMIC and the subset of memory dies; and setting the output voltage of the PMIC to be equal to the second voltage, wherein the PMIC is configured to supply the second voltage to the subset of memory dies during operation of the memory device based on the output voltage of the PMIC being set to the second voltage.

[0076] In some instances of the method 700 and apparatus described herein, the output voltage of the PMIC may be configured before the output voltage of the PMIC is set to be equal to the second voltage, and the output voltage of the PMIC may be fixed at the second voltage after the memory device is assembled.

[0077] Some aspects of the method 700 and apparatus described herein may additionally include operations, features, means, or instructions for: identifying, based on the test, a second subset of memory dies within the set of memory dies that, when supplied with the second voltage, each fails the performance threshold; assembling a memory device comprising a second PMIC and the second subset of memory dies based on the identification of the second subset of memory dies; and setting the output voltage of the second PMIC to be equal to the first voltage, wherein the second PMIC may be configured to supply the first voltage to the second subset of memory dies during operation of the second memory device, based on the output voltage of the second PMIC being set to the first voltage.

[0078] In some instances of the method 700 and apparatus described herein, the second voltage may be lower than the first voltage.

[0079] In some instances of the method 700 and apparatus described herein, the memory die set may be a DRAM die set, and the memory device may be a DIMM.

[0080] Some aspects of the method 700 and apparatus described herein may additionally include operations, features, means, or instructions for testing the subset of memory dies after assembly, wherein setting the output voltage of the PMIC to be equal to the second voltage occurs after assembly and may be based on the testing of the subset of memory dies. Testing the subset of memory dies after assembly, as described herein, may occur after assembly or, alternatively, individual memory dies may be tested before assembly.

[0081] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0082] Describe an apparatus. The apparatus may include a memory die configured to operate using a first supply voltage and a second supply voltage, wherein the first supply voltage is associated with a first defined voltage range and the second supply voltage is associated with a second defined voltage range, and may include a PMIC coupled to the memory die and configured to provide the memory die with a first voltage within the first defined voltage range as the first supply voltage; and to provide the memory die with a second voltage outside the second defined voltage range as the second supply voltage.

[0083] In some instances, the PMIC is configured to identify the second voltage outside the second defined voltage range during system initialization, wherein the second voltage can be provided based on the identification.

[0084] In some cases, the device may include a register coupled to or contained in the PMIC and configured to store a value indicating that the second voltage may be outside the second defined voltage range, wherein the identification may be based on the value indicating the second voltage stored in the register.

[0085] In some cases, the memory die may be configured to be coupled to a host device, and the values ​​may not be changeable by the host device.

[0086] In some instances, the PMIC may be configured to provide the second voltage based on the memory die meeting a performance threshold when using the second voltage as the second supply voltage.

[0087] In some cases, a DIMM includes a PMIC, a memory die, and one or more additional memory dies, each configured to operate using a first supply voltage and a second supply voltage. Each memory die and each of the additional memory dies contains a DRAM memory cell. The PMIC may be further configured to provide each of the one or more additional memory dies with a first voltage within the first defined voltage range as the first supply voltage, and to provide each of the one or more additional memory dies with a second voltage outside the second defined voltage range as the second supply voltage.

[0088] In some cases, the second voltage may be lower than the second defined voltage range. In other cases, the second voltage may be higher than the second defined voltage range.

[0089] In some instances, the memory die may be configured to exchange signaling with a host device according to a memory standard, and defining a first defined voltage range and a second defined voltage range may include specifying the first defined voltage range and the second defined voltage range by the memory standard.

[0090] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0091] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0092] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0093] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0094] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., most carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0095] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0096] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0097] The techniques described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For instance, due to the nature of software, the functionality described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributed portions of the functionality implemented in different physical locations.

[0098] For example, the various illustrative blocks and modules described herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0099] As used herein, the word "or," as used in the claims, such as in a list of items (e.g., a list followed by phrases such as "at least one of..." or "one or more of..."), indicates a list containing endpoints such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0100] Computer-readable media includes both non-transitory computer storage media and communication media that include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0101] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: A memory die configured to exchange signaling with a host device according to a memory standard and to operate using a first supply voltage and a second supply voltage, wherein the first supply voltage is associated with a first defined voltage range specified by the memory standard and the second supply voltage is associated with a second defined voltage range specified by the memory standard; and The power management integrated circuit (PMIC) is coupled to the memory die and configured to: Read a first value stored in a register and a second value stored in the register, wherein the first value indicates a first voltage of the first supply voltage and the second value indicates a second voltage of the second supply voltage; After reading the first value and the second value, at least in part based on reading the first value stored in the register, the first voltage within the first defined voltage range specified by the memory standard is provided as the first supply voltage to the memory die; and At least in part, based on reading the second value stored in the register, the second voltage, which is outside the second defined voltage range specified by the memory standard, is provided as the second supply voltage to the memory die simultaneously with providing the first voltage.

2. The system of claim 1, wherein the PMIC is further configured to: During the initialization of the system, the second voltage is identified as being outside the second defined voltage range, wherein the second voltage is provided based at least in part on the identification.

3. The system according to claim 2, further comprising: The register, which is coupled to or contained in the PMIC and configured to store a first value indicating a first voltage within a first defined voltage range and a second value indicating a second voltage outside a second defined voltage range, wherein the identification is at least in part based on the register storing the first value indicating the first voltage and the second value indicating the second voltage.

4. The system according to claim 3, wherein: The memory die is configured to be coupled to the host device; and The first value and the second value cannot be changed by the host device.

5. The system of claim 1, wherein the PMIC is configured to provide the second voltage based at least in part on the memory die meeting a performance threshold when the second voltage is used as the second supply voltage.

6. The system according to claim 1, wherein: A dual in-line memory module (DIMM) includes the PMIC, the memory die, and one or more additional memory dies, each configured to operate using the first supply voltage and the second supply voltage. Each of the memory die and the one or more additional memory dies includes a dynamic random access memory (DRAM) cell; and The PMIC is further configured to: The first voltage within the first defined voltage range is provided as the first supply voltage to each of the one or more additional memory dies; and The second voltage, which is outside the second defined voltage range, is provided as the second supply voltage to each of the one or more additional memory dies.

7. The system of claim 1, wherein the second voltage is lower than the second defined voltage range.

8. The system of claim 1, wherein the second voltage is higher than the second defined voltage range.

9. A method comprising: The memory die is configured to exchange signaling with a host device according to memory standards by reading a first value stored in a register and a second value stored in the register through a power management integrated circuit (PMIC) coupled to the memory die, wherein the first value indicates a first voltage of a first supply voltage and the second value indicates a second voltage of a second supply voltage; After reading the first value and the second value, the PMIC is used to generate, at least in part, a first voltage within a first defined voltage range specified by the memory standard, corresponding to the first supply voltage of the memory die, based on reading the first value stored in the register. Based at least in part on reading the second value stored in the register, the PMIC generates a second voltage outside the second defined voltage range specified by the memory standard, corresponding to the second supply voltage of the memory die; and The memory die is operated simultaneously using the first voltage as the first supply voltage and the second voltage as the second supply voltage.

10. The method of claim 9, further comprising: The first voltage and the second voltage are used as one or more corresponding first supply voltages and one or more second supply voltages for operating the one or more additional memory dies coupled to the PMIC.

11. The method of claim 9, wherein generating the second voltage further comprises: The second voltage is identified during the initialization process performed before the memory die is operated.

12. The method of claim 9, wherein the second voltage is lower than the second defined voltage range.

13. The method of claim 9, wherein the second voltage is higher than the second defined voltage range.

14. The method of claim 11, further comprising: The first value indicating the first voltage within the first defined voltage range and the second value indicating the second voltage outside the second defined voltage range are stored in the register coupled to or contained in the PMIC, wherein the identification is based at least in part on storing the first value indicating the first voltage and the second value indicating the second voltage in the register.

15. The method of claim 14, wherein: The memory die is configured to be coupled to the host device; and The first value and the second value cannot be changed by the host device.

16. The method of claim 9, wherein the generation of the second voltage using the PMIC is at least partially based on the memory die satisfying a performance threshold when the second voltage is used as the second supply voltage.

17. A memory device comprising: A memory die, configured to exchange signaling with a host device according to memory standards; and One or more controllers coupled to the memory die, wherein the one or more controllers are configured to cause the memory device to perform the following operations: A first value and a second value stored in a register are read by a power management integrated circuit (PMIC) coupled to the memory die, wherein the first value indicates a first voltage of a first supply voltage and the second value indicates a second voltage of a second supply voltage; After reading the first value and the second value, the PMIC is used to generate, at least in part, a first voltage within a first defined voltage range specified by the memory standard, corresponding to the first supply voltage of the memory die, based on reading the first value stored in the register. Based at least in part on reading the second value stored in the register, the PMIC generates a second voltage that is outside the second defined voltage range specified by the memory standard for the second supply voltage corresponding to the memory die; and The memory die is operated simultaneously using the first voltage as the first supply voltage and the second voltage as the second supply voltage.

18. The memory device of claim 17, wherein the one or more controllers are further configured to cause the memory device to perform the following operations: The first voltage and the second voltage are used as one or more corresponding first supply voltages and one or more second supply voltages for operating the one or more additional memory dies coupled to the PMIC.

19. The memory device according to claim 17, wherein, In order to generate the second voltage, the one or more controllers are further configured to cause the memory device to perform the following operations: The second voltage is identified during the initialization process performed before the memory die is operated.

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