Enhanced capacitor for integration with metal oxide semiconductor field effect transistor

Abstract

The invention relates to a capacitor for integration with a MOSFET device formed on the same substrate. The capacitor includes a first electrode plate and a second electrode plate; the first electrode plate includes a doped semiconductor layer of a first conductivity type; an insulating layer formed on the upper surface of the doped semiconductor layer; the second electrode plate includes a polysilicon layer formed on the upper surface of the insulating layer; an inversion layer is formed in the doped semiconductor layer, below the insulating layer and close to the upper surface of the doped semiconductor layer, and the inversion layer is formed according to the voltage applied between the first electrode plate and the second electrode plate. It further includes at least one doped region of a second conductivity type (opposite to the first conductivity type), and the doped region is formed in the doped semiconductor layer adjacent to the drain and / or source regions of the first conductivity type formed in the MOSFET device. The doped region is electrically connected to the inversion layer.

Description

Technical Field

[0001] The present invention generally relates to electrical, electronic, and computer technologies, and more particularly to capacitors for integration with metal oxide semiconductor field effect transistor devices. Background Art

[0002] Modern wireless communication circuits and systems impose extremely stringent requirements on power and linear performance. For example, requirements for power amplifiers and switching circuits operating at microwave frequencies. These increasing power and linear requirements pose challenges to the design of high-frequency, high-power circuit elements. In the past few years, silicon laterally diffused metal oxide semiconductor (LDMOS) power transistors have dominated in such applications. However, as the operability of such devices approaches its limit, other semiconductor materials and / or device structures are needed to meet the high-power and high-linearity requirements of next-generation wireless technologies.

[0003] It is well known that a field plate structure can be employed in LDMOS devices. The field plate is essentially an extension of the gate over the drift region in an LDMOS device. The field plate, typically formed of polysilicon, has been shown to not only increase the breakdown voltage in LDMOS devices but also suppress surface states, which significantly affect the power performance of the device. The large gate polysilicon area also helps accumulate electrons in the drift region under the field plate during the on-state of the LDMOS device, thereby reducing the on-resistance (R DSon ).

[0004] Unfortunately, although the field plate structure in conventional MOSFET devices helps increase the breakdown voltage of the device by locally adjusting the electric field, it generates an additional parasitic feedback capacitance from the drain to the gate, also known as the Miller capacitance (C gd ). More specifically, from a circuit perspective, the field plate acts as a gate-drain feedback capacitance, providing additional signal modulation at the input and output terminals of the device. This parasitic feedback capacitance adversely affects the overall high-frequency performance of the device, especially in high-speed switching applications, at least in part due to the additional phase change provided by the feedback path. Summary of the Invention

[0005] As shown in one or more embodiments, the present invention advantageously provides an enhanced capacitor suitable for integration with LDMOS transistor devices, as well as a method for manufacturing such a capacitor. This integrated capacitor is advantageously compatible with existing complementary metal oxide semiconductor (CMOS) manufacturing technologies and does not rely on the use of expensive processes and materials (such as dual silicide structures) to achieve a substantial improvement in the high-frequency performance of the device. In addition, embodiments of the present invention advantageously achieve enhanced high-frequency performance, such as by reducing the gate charge (Q g ) and / or reducing the gate-drain capacitance (Cgd ) without significantly reducing the breakdown voltage and / or on-resistance (R DSon ) in the device.

[0006] According to an embodiment of the present invention, a capacitor is provided for integration with a MOSFET device formed on the same substrate. The capacitor includes: a first plate including a doped semiconductor layer of a first conductivity type and an insulating layer formed on the upper surface of the doped semiconductor layer; and a second plate including a polysilicon layer formed on the upper surface of the insulating layer. An inversion layer is formed in the doped semiconductor layer, the inversion layer is located below at least a part of the insulating layer and near the upper surface of the doped semiconductor layer, and the inversion layer is formed according to a voltage applied between the first plate and the second plate of the capacitor; at least one doped region having a second conductivity type opposite in polarity to the first conductivity type, the doped region is formed in the doped semiconductor layer adjacent to the drain and / or source region of the first conductivity type in the MOSFET device. The doped region is electrically connected to the inversion layer.

[0007] According to another embodiment of the present invention, a method of manufacturing a capacitor configured to be integrated with at least one metal oxide semiconductor field effect transistor (MOSFET) device includes: forming a first plate including a doped semiconductor layer of a first conductivity type; forming an insulating layer formed on at least a part of the upper surface of the doped semiconductor layer; forming a second plate including a polysilicon layer on at least a part of the upper surface of the insulating layer, wherein an inversion layer is formed in the doped semiconductor layer, the inversion layer is located below at least a part of the insulating layer and near the upper surface of the doped semiconductor layer, and the inversion layer is formed according to a voltage applied between the first plate and the second plate of the capacitor; and forming at least one doped region of a second conductivity type in the doped semiconductor layer, the doped region is near the upper surface of the doped semiconductor layer and adjacent to one of the drain region and the source region of the first conductivity type formed in the MOSFET device, the doped region is electrically connected to the inversion layer, and the second conductivity type is opposite in polarity to the first conductivity type.

[0008] According to another embodiment of the present invention, a DC-DC voltage converter circuit includes a first MOSFET device having a drain coupled to an input node of the converter circuit, a source and a gate coupled to a switching node of the converter circuit, and the input node is adapted to receive an input voltage applied to the converter circuit. The voltage converter circuit further includes a second MOSFET device having a drain coupled to the switching node of the converter circuit, a source coupled to a return voltage of the converter circuit, and a gate. The DC-DC voltage converter circuit includes a controller circuit coupled to the first and second MOSFET devices, and the controller circuit is configured to generate first and second control signals, and the first and second control signals are provided to the gates of the first and second MOSFET devices to control the activation of the MOSFET devices; at least one energy storage element is coupled between the switching node and an output terminal of the converter circuit.

[0009] The DC-DC voltage converter circuit further includes an input capacitor coupled between the input node of the converter circuit and the return voltage, and the input capacitor is integrated with at least one of the first and second MOSFET devices. The input capacitor includes a first electrode plate including a doped semiconductor layer of a first conduction type, and the doped semiconductor layer forms at least one drift drain region and at least one body region in the first and second MOSFET devices. The input capacitor further includes an insulating layer and a second electrode plate, the insulating layer is formed on an upper surface of at least a part of the doped semiconductor layer, and the second electrode plate includes a polysilicon layer plate formed on an upper surface of at least a part of the insulating layer. An inversion layer is formed in the doped semiconductor layer, the inversion layer is located under at least a part of the insulating layer and close to the upper surface of the doped semiconductor layer, and the inversion layer is formed according to a voltage applied between the first electrode plate and the second electrode plate of the capacitor. The input capacitor further includes at least one doped region of a second conduction type (opposite in polarity to the first conduction type), the doped region is formed in the doped semiconductor layer, the doped region is close to the upper surface of the doped semiconductor layer, and is adjacent to at least one of the drains and / or sources of the first and second MOSFET devices. The doped region is electrically connected to the inversion layer.

[0010] The technology of the present invention can provide substantial beneficial technical effects. The listed embodiments are only examples and should not be construed restrictively. The integrated capacitor according to one or more embodiments of the present invention has one or more of the following advantages:

[0011] · High-value capacitor with a very small area;

[0012] · Compatible with standard CMOS manufacturing technology;

[0013] · Lower switching losses;

[0014] · Enhanced high-frequency performance;

[0015] · Excellent integration with DC-DC voltage converter applications.

[0016] These and other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the invention and should be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following drawings are provided by way of example only and should not be construed as limiting, wherein reference numerals (as shown in the figures) indicate corresponding elements in the various views, where:

[0018] Figure 1A is a perspective view depicting at least a portion of a laterally diffused metal oxide semiconductor (LDMOS) device having a field plate;

[0019] Figure 1B is described as Figure 1A shown, a cross-sectional view of at least a portion of the LDMOS device along line A-A' in Figure 1A ;

[0020] Figure 2 is a perspective view depicting at least a portion of an exemplary LDMOS device according to an embodiment of the present invention, the exemplary LDMOS device including a field plate structure having reduced parasitic capacitance;

[0021] Figure 3 is described as Figure 2 shown, a cross-sectional view of at least a portion of the exemplary LDMOS device of an embodiment of the present invention along line B-B';

[0022] Figure 4 is described as Figure 2 shown, a cross-sectional view of at least a portion of the exemplary LDMOS device of an embodiment of the present invention along line C-C';

[0023] Figure 5 is a perspective view depicting at least a portion of an exemplary LDMOS device of an embodiment of the present invention, the field plate structure of the LDMOS device having a plurality of openings formed therein;

[0024] Figures 6A to 6E is described as Figure 3 shown, a cross-sectional view of at least a portion of an exemplary processing step of the LDMOS device of an embodiment of the present invention.

[0025] Figure 7Ais a perspective view of at least a portion of an exemplary LDMOS device according to embodiments of the present invention, the LDMOS device including a field plate that forms a structure separated from the gate;

[0026] Figure 7B is a description of as Figure 7A shown perspective view of an exemplary LDMOS device, the LDMOS device includes a gate drive circuit connected to the outside;

[0027] Figure 8 is a description of as Figure 1A shown cross-sectional view of an exemplary LDMOS device, conceptually describes the associated parasitic capacitance elements;

[0028] Figure 9 is Figure 7A shown cross-sectional view of an exemplary LDMOS device, conceptually describes the associated parasitic capacitance elements;

[0029] Figure 10 is a cross-sectional view of at least a portion of an exemplary LDMOS device, the exemplary LDMOS device and Figures 2 to 7B shown exemplary LDMOS device consistent, in a preferred embodiment of the present invention, the thick insulating layer is replaced by a local oxidation of silicon (LOCOS) isolation structure;

[0030] Figure 11 is a cross-sectional view of at least a portion of an exemplary LDMOS device, the exemplary LDMOS device and Figure 2 to FIG. 7 shown exemplary LDMOS device consistent, in a preferred embodiment of the present invention, the thick insulating layer is replaced by a shallow trench isolation (STI) structure;

[0031] Figure 12 is an electrical schematic diagram of at least a portion of an exemplary switched DC-DC voltage regulator circuit, which can be applied to one or more embodiments of the present invention;

[0032] Figure 13 is at least a portion of an exemplary semiconductor structure described according to one or more embodiments of the present invention, the exemplary semiconductor structure includes an input capacitor of a high-side MOSFET device embedded with a DC-DC converter;

[0033] Figure 14 is an electrical schematic diagram described according to one or more embodiments of the present invention, which conceptually describes Figure 13 shown equivalent circuit of the embedded input capacitor;

[0034] Figure 15A cross-sectional view of at least a portion of an exemplary semiconductor structure described in one or more embodiments of the present invention, the semiconductor structure being consistent with the exemplary structure shown in Figure 13 and with a modification of adding an input capacitor embedded in a high-side MOSFET device;

[0035] Figure 16 An electrical schematic diagram described in one or more embodiments of the present invention, conceptually depicting the equivalent circuit of the embedded input capacitor shown in Figure 15 ;

[0036] Figure 17 A cross-sectional view described in one or more embodiments of the present invention, which conceptually depicts at least a portion of the exemplary semiconductor structure shown in Figure 15 when the high-side MOSFET device is turned off;

[0037] Figure 18 A cross-sectional view of at least a portion of the exemplary semiconductor structure described in one or more embodiments of the present invention, the exemplary semiconductor structure including an input capacitor embedded in a low-side MOSFET device of a DC-DC converter;

[0038] Figure 19 A cross-sectional view of at least a portion of the exemplary semiconductor structure described in one or more embodiments of the present invention, the exemplary semiconductor structure including an input capacitor embedded in a low-side MOSFET device of a DC-DC converter, the input capacitor including an n-type semiconductor layer as a second electrode plate;

[0039] Figure 20 A cross-sectional view described in one or more embodiments of the present invention, depicting at least a portion of an exemplary semiconductor structure, the exemplary semiconductor structure including: an input capacitor integrated on the same substrate as one or more power devices (either high-side or low-side MOSFET devices), and a p-type doped layer as one of the electrode plates of the capacitor structure, the capacitor being electrically isolated from the power device;

[0040] Figure 21 A cross-sectional view described in one or more other embodiments of the present invention, depicting at least a portion of an exemplary semiconductor structure, the exemplary semiconductor structure including: an input capacitor integrated on the same substrate as one or more power devices (either high-side or low-side MOSFET devices), and an n-type doped layer as one of the electrode plates of the capacitor structure, the capacitor being electrically isolated from the power device; and

[0041] Figure 22 As described in one or more embodiments of the present invention, as shown in Figure 21Cross-sectional view of at least a portion of an exemplary semiconductor structure, wherein the polysilicon layer of the capacitor is grounded through a silicide layer, and the semiconductor layer is connected to V through first and second doped regions IN .

[0042] It should be understood that the description of the elements in the drawings is for simplicity and clarity of presentation. In commercially viable embodiments, some elements that are useful or necessary but are well-known may not be shown in the drawings in order to reduce clutter in the views. Detailed Description

[0043] As shown in one or more embodiments, the principles of the present invention will be described in an exemplary laterally diffused metal oxide semiconductor (LDMOS) device, and a method of manufacturing the LDMOS device, which has a field plate structure for improving high-frequency performance without significantly degrading the power and linearity performance of the device. However, it should be noted that the present invention is not limited to the specific devices and / or methods shown and described in the present application. On the contrary, in light of the teachings of the present application, those skilled in the art will clearly recognize that many modifications can be made to the illustrated embodiments, and all of these embodiments are within the scope of the invention claimed. That is, no limitation of the present invention should be inferred from the embodiments described and recited in the present application.

[0044] For the purpose of describing and claiming embodiments of the invention, the term "MISFET" as used herein is intended to be construed broadly to include any type of metal-insulator-semiconductor field effect transistor. For example, the term "MISFET" is intended to include semiconductor field effect transistors that use an oxide material as the gate dielectric (i.e., MOSFETs), as well as semiconductor field effect transistors that do not use an oxide material as the gate dielectric. In addition, although the initials "MISFET" and "MOSFET" mention "metal", the terms "MISFET" and "MOSFET" are also intended to include semiconductor field effect transistors whose gates are made of non-metallic materials (such as polysilicon); the terms "MISFET" and "MOSFET" may be used interchangeably in the present application.

[0045] Although the overall manufacturing method and structure of the present application are completely new, according to one or more embodiments of the present invention, certain individual processing steps required to implement part or multiple parts of the method can utilize traditional semiconductor manufacturing technologies and traditional semiconductor manufacturing tools. These technologies and tools are already familiar to those with ordinary skills in the relevant field. In addition, many processing steps and tools for manufacturing semiconductor devices are also described in many readily available publications, such as "Compound Semiconductor Handbook: Formation, Processing, Characterization, and Devices" by P.H. Holloway et al., published by Cambridge University Press in 2008; and "Processing and Properties of Compound Semiconductors" by R.K. Willardson et al., published by Academic Press in 2001. The entire contents of the above two books are incorporated into the present application by reference. It should be emphasized that although some individual processing steps are listed here, these steps are merely illustrative, and those skilled in the art may be familiar with several equally suitable alternatives, which also fall within the scope of the present invention.

[0046] It should be understood that the layers and / or regions shown in the drawings are not necessarily drawn to scale. In addition, for ease of description, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure. However, this does not mean that the semiconductor layers not explicitly shown are omitted in the actual integrated circuit device.

[0047] Figure 1A and 1B are a perspective view and a cross-sectional view, respectively, in which at least a part of an exemplary LDMOS device 100 including a field plate structure is described in the perspective view; Figure 1B For Figure 1A is a cross-sectional view of the LDMOS device 100 along line A-A' in. Specifically, the LDMOS device 100 includes a substrate 102 that can be formed of single-crystalline silicon. Preferably, impurities or dopants (such as boron, phosphorus, arsenic, etc.) are added to the substrate 102 to change the conductivity type of the material (such as n-type or p-type polarity). In this example, since the LDMOS device 100 is an n-channel transistor and the substrate 102 has a p-type conductivity type, it can be referred to as a p-substrate (P-SUB).

[0048] In this embodiment, a body region 104 (P-BODY) having a p-type conductivity type is formed near the upper surface of the substrate 102, which extends laterally from the source side to the drain side of the device. A lightly doped drift (LDD) region 106 is formed near the upper surface of the substrate 102 and is adjacent to the body region 104 laterally. The LDD region 106 has a conductivity type opposite to that of the body region 104, which is an n-type conductivity type in this embodiment, and is therefore referred to as an n-type drain drift (NDD) region.

[0049] The LDMOS transistor 100 includes a source region 108, a drain region 110, and a gate 112. The source region 108 and the drain region 110 are respectively formed near the upper surface of the substrate 102 and are laterally spaced from each other. Preferably, the source region 108 and the drain region 110 are doped with impurities, for example, through conventional implantation steps, using known concentration levels of impurities, and selectively changing the conductivity type of the material as needed. In this example, the source region 108 and the drain region 110 have an n-type conductivity type.

[0050] The source region 108 is formed in at least a portion of the body region 104, and the drain region 110 is formed in at least a portion of the NDD region 106. A heavily doped region 114 having the same conductivity type as the body region 104 (p-type in this embodiment) is formed near the upper surface of the substrate 102, is laterally adjacent to the source region 108 and within the body region, and is in physical contact with the LDMOS device 100. The source region 108 is electrically connected to the body contact region 114.

[0051] The gate 112 is formed between the source region 108 and the drain region 110 and is formed on at least a portion of the body region. Although not explicitly stated, a thin oxide layer (e.g., silicon dioxide (S i O2)) is formed under the gate 112 to electrically isolate the gate, the source region 108, and the drain region 110 in the LDMOS device 100. As is understood by those skilled in the art, a bias voltage applied to the gate forms a channel in the body region 104 under the gate to control the current between the source region 108 and the drain region 110.

[0052] As Figure 1A and 1B shown, the gate 112 is configured to have a gate extension portion 116 that laterally extends through the NDD region 106 and extends in front of the drain region 110. The gate extension portion 116 is formed on a dielectric layer 118 having a thickness greater than the thickness of the gate oxide, and the gate extension portion 116 is generally referred to as a field plate. In this example, the field plate 116 is a continuous extension of the gate 112, and its function is to modulate the electric field in the LDMOS device 100, which increases the breakdown voltage of the device. The field plate 116 also causes electrons to accumulate near the upper surface of the NDD region 106 at the on-state position of the LDMOS device 100, which reduces the on-resistance (R DS-on ).

[0053] As described above, in the past few years, LDMOS power transistors have dominated in high-power applications, especially in power amplifier applications such as in wireless communication systems. As is well known, in MOSFET devices, a field plate structure is adopted to increase the breakdown voltage of the device by locally modulating the electric field. However, the additional parasitic feedback capacitance generated by the standard field plate structure has an adverse effect on the overall high-frequency performance of the device, making the device simply inapplicable to high-frequency applications without using complex and expensive materials and / or manufacturing processes.

[0054] To meet the frequency performance standards of modern high-frequency applications, a reduction in the parasitic gate-drain capacitance C gd can be adopted. Generally, the capacitance C of a parallel-plate capacitor is defined by the following formula:

[0055]

[0056] where ε0 is the absolute permittivity (i.e., the permittivity of vacuum ε0 = 8.854×10 -12 F / m), ε r is the relative permittivity of the dielectric or dielectric material between the parallel plates, A is the surface area of one end of each parallel plate, and d is the distance between the plates (i.e., the thickness of the dielectric material between the plates). Therefore, in order to reduce the capacitance, the thickness of the dielectric material between the plates can be increased and / or the surface area of one or both plates can be reduced.

[0057] To achieve enhanced high-frequency performance in an LDMOS device without significantly affecting the power and linear performance in the device, as shown in one or more embodiments of the present invention, the present invention provides an LDMOS device having a new field plate structure configured to reduce the overlapping area between the gate and the drain, thereby advantageously reducing the parasitic gate-drain capacitance (C gd ) in the device.

[0058] As an embodiment of the present invention, Figures 2 to 4 shown, at least a part of an exemplary LDMOS device 200 is conceptually described, including a field plate structure with reduced parasitic capacitance; Figure 2 is a perspective view describing at least a part of the exemplary LDMOS device 200, Figure 3 is a cross-sectional view along line B-B′ describing at least a part of the exemplary LDMOS device 200, Figure 4is a cross-sectional view of at least a portion of an exemplary LDMOS device 200 along the C-C′ line. The LDMOS device 200 includes a semiconductor substrate 202. In one or more embodiments, the substrate 202 is formed of single-crystalline silicon (e.g., having a <100> or <111> crystal orientation), and suitable alternative materials may also be used, such as but not limited to germanium, silicon germanium, silicon carbide, gallium arsenide, gallium nitride, or similar materials. Further, in one or more embodiments, the substrate 202 is preferably modified to change the conduction type (e.g., n-type or p-type) of the material by adding impurities or dopants (such as boron, phosphorus, arsenic, etc.). In one or more embodiments, the substrate 202 has a p-type conduction type and may thus be referred to as a p-type substrate (P-SUB). By adding a predetermined concentration level (e.g., about 10 14 to about 10 18 atoms per cubic centimeter) of a p-type impurity or dopant (e.g., a Group III element such as boron), a p-type substrate may be formed, for example, by using diffusion or implantation steps to change the conduction type of the material in the desired manner. In one or more alternative embodiments, an n-type substrate may be formed by adding a specified concentration level of an n-type impurity or dopant (e.g., a Group V element such as phosphorus) to the substrate material.

[0059] A lightly doped drain drift or drain extension region 206 is formed on at least a portion of the substrate 202 near its upper surface. The drain drift region 206 has a conduction type opposite to that of the substrate 202. In one or more embodiments, when a p-type substrate 202 is used, the drain drift region 206 has an n-type conduction type, which may be formed by implanting an n-type impurity (such as phosphorus) into a specific region of the substrate using standard CMOS manufacturing techniques, and is thus referred to herein as an n-type drain drift (NDD) region. The doping concentration of the NDD region 206 is closely related to the breakdown voltage of the LDMOS device 200, and thus, among other factors, by controlling the doping level of the NDD region 206, a desired breakdown voltage can be achieved in the device.

[0060] A local low-resistivity body region 204 is formed in at least a portion of the NDD region 206. The conductivity type of the body region 204 is opposite to that of the drain drift region 206. In one or more embodiments, the body region 204 includes a p-type well (or p-well) disposed near the upper surface of the NDD region 206. In this exemplary embodiment, the body region 204 is formed by implanting a p-type impurity (such as boron) into a specific region of the NDD region 206 using standard CMOS manufacturing techniques. Although the body region 204 has the same conductivity type as the substrate 202, preferably, it has a higher doping concentration relative to the substrate, so that the body region has a lower resistivity than the substrate, for example, about 0.01 to 0.3 Ω-cm. In one or more other embodiments employing an n-type substrate 202, the body region 204 may include an n-type well formed using similar CMOS manufacturing techniques.

[0061] First and second heavily doped regions having a conductivity type / polarity opposite to that of the substrate 202 (such as n-type) are formed near the upper surface of the LDMOS device 200, and the source region 208 and the drain region 210 of the LDMOS device are defined; the source region is formed in the body region 204, and the drain region is formed in the NDD region. In one or more embodiments, the source region 208 and the drain region 210 are composed of heavily doped n-type material formed using a standard CMOS implantation process. Specifically, standard CMOS manufacturing techniques can inject n-type material into the source region 208 and the drain region 210 to form a first n+ region corresponding to the source region 208 and a second n+ region corresponding to the drain region 210. The n-type material includes donor-type impurity atoms capable of providing electrons, such as but not limited to phosphorus, arsenic, antimony, or the like. Injecting n-type material into the source region 208 and / or the drain region 210 results in the carrier electron density in the source region 208 and / or the drain region 210 exceeding the carrier hole density.

[0062] A heavily doped region 211 is formed in the body region, having the same conductivity type as the body region 204 (i.e., p-type in this embodiment), only having a higher doping concentration than the body region. The heavily doped region 211 is formed within the body region 204, near the upper surface of the body region 204 and adjacent to the source region 208 laterally. The heavily doped region 211 forms the body contact region of the LDMOS device 200. For example, in a subsequent metallization step, the source region 208 is electrically connected to the body contact region 211.

[0063] Continue to refer to Figures 2 to 4, the gate 212 is formed over the body region 204, near the upper surface of the wafer, and between the source region 208 and the drain region 210. The gate 212 is electrically isolated from the body region 204 and the NDD region 206 by a thin insulating layer 214, which is disposed on the upper surface of the wafer where the gate is formed. In some embodiments, the thin insulating layer 214 may be formed of an oxide (e.g., silicon dioxide), and may thus be referred to herein as a gate oxide layer. Although other materials (such as metals) are similarly contemplated for forming the gate, preferably, the gate 212 is formed of heavily doped polysilicon. As is known to those skilled in the art, when a bias voltage is applied between the gate 212 and the source region 208, an inversion layer or channel is induced in the body region 204 under the gate oxide layer 214 by the field effect principle. The function of the channel is to facilitate current flow between the source region 208 and the drain region 210 of the LDMOS device 200, and to control the magnitude of the current according to the applied voltage.

[0064] In Figures 2 to 4 the illustrative embodiment, the gate 212 includes a shielding structure 216. Preferably, the shielding structure 216 is formed as a coextensive type of the gate 212, extending laterally over at least a portion of the NDD region 206. The shielding structure 216, also known as a Faraday shield or a field plate; in one or more embodiments the shielding structure 216 is configured as a stepped structure having a first end adjacent to the gate 212 and a second end extending laterally from the first end and disposed over the NDD region 206. The field plate (i.e., the shielding structure) 216 is electrically isolated from the NDD region 206 by an insulating layer 218. In one or more embodiments, the insulating layer 218 is formed as an extension of the gate oxide layer 214, located between the NDD region 206 and the field plate 216, and having a greater thickness relative to the gate oxide layer. In this example, the field plate 216, as an extension of the gate 212, is formed of the same material as the gate (e.g., doped polysilicon), and other embodiments of the present invention are similarly contemplated, where the gate and the field plate are formed as separate structures composed of the same or different materials. The main function of the field plate 216 is to mitigate the local high electric field at the gate edge on the drain side of the LDMOS device 200, which can cause electron injection (e.g., hot carrier injection) into the gate oxide layer 214, resulting in threshold drift and thus deteriorating linearity.

[0065] As described above, in accordance with aspects of the present invention, field plate 216 is configured to reduce the overlap region between the gate and the drain, thereby advantageously reducing the parasitic gate-drain capacitance in the device. Specifically, in one or more embodiments, field plate 216 is formed to have at least one opening 220 that exposes at least a portion of underlying NDD region 206. The opening 220 in field plate 216 is configured to reduce the number of overlapping regions (i.e., the gate portions overlapping the NDD region), which advantageously reduces the gate-drain capacitance in LDMOS device 200. The degree of reduction of the gate-drain capacitance affects the size of opening 220. The gate-drain capacitance is inversely proportional to the area of opening 220, i.e., the larger the area of opening 220, the smaller the gate-drain capacitance.

[0066] Although the shape of opening 220 is rectangular, embodiments of the present invention are not limited to any particular shape or size. For example, in one or more embodiments, the shape of opening 220 is substantially elliptical. Additionally, field plates having multiple openings are also considered similarly in embodiments of the present invention. Specifically, referring to the alternative embodiment as Figure 5 shown. The field plate 216 in LDMOS device 500 is configured to have multiple openings 502, 504, and 506, and the field plate 216 covers the NDD region 206. It should be understood that embodiments of the present invention do not limit any particular number of openings, nor any particular shape and / or size of each of openings 502, 504, and 506.

[0067] Although omitted in Figure 2 , as shown in Figure 3 and 4 , preferably an insulating spacer 222 is formed on the sidewalls of gate 212 and field plate 216. The insulating spacer 222 electrically isolates gate 212 and field plate 216 from other elements of LDMOS device 200. Optionally, referring to Figure 3 , an implant layer 224 is formed in NDD region 206, which is near the upper surface of the NDD region and below opening 220 between gate 212 and field plate 216. In this exemplary embodiment, implant layer 224 is doped with an n-type impurity having a specific concentration level (e.g., about 10 15 to about 10 18 atoms per cubic centimeter).

[0068] Implant layer 224 is at least partially used to increase the n-type concentration at the channel end closest to drain region 210, thereby reducing the on-resistance (R DS-on)。The implanted layer 224 is also used to define the channel region under the gate 212, effectively forming an extension of the self-aligned channel, enabling the use of a shorter gate length and enhancing stability. In high-frequency applications, it is desirable that a smaller gate length corresponds to a smaller gate charge (Q g )。When the gate length is reduced below a certain size (e.g., less than the lateral diffusion length of the p-type body region), the p-type body region 204 extends beyond the gate 212, and it becomes difficult for the LDMOS device to conduct. By adding the n-type implanted layer 224, the p-type body region 204 extending beyond the gate 212 will be counter-doped to the n-type conductivity type (as in this exemplary embodiment), making it easier for the LDMOS device 200 to conduct and being less affected by the unstable lateral diffusion of the body region 206.

[0069] In one or more embodiments, a silicide 226 (an alloy of a metal and silicon) layer is formed on at least a portion of the upper surface of the gate 212 and the field plate structure 216 to reduce the resistivity of the gate and the field plate structure. Although not explicitly shown, the silicide layer may also be formed on at least a portion of the upper surface of the source region 208 and the drain region 210 to form low-resistance interconnections between the source region and the corresponding source contact region, and between the drain region and the corresponding drain contact region. The source and drain contact regions (not explicitly shown in the drawings but implied) provide electrical connections to the source region 208 and the drain region 210 of the LDMOS device 200, respectively.

[0070] Using standard CMOS manufacturing steps, once the front-end processing for forming the LDMOS device 200 is completed, the LDMOS device can be interconnected with one or more components fabricated on the same wafer to form the desired circuit. This is applied in a series of wafer processing steps, which are collectively referred to as back-end-of-line (BEOL) processing. BEOL processing mainly involves creating metal interconnections isolated by insulating layers (i.e., dielectrics). The insulating material used to form the dielectric layer has traditionally been silicon dioxide (S i O2), and embodiments of the present invention also contemplate the use of other materials (such as silicate glass, etc.).

[0071] As shown in one embodiment of the present invention, this embodiment is only an example and not a restrictive illustration. For example, Figures 6A to 6E is a cross-sectional view of at least a portion of the intermediate process processing step 600 of the exemplary LDMOS device 200 as shown in an embodiment of the present invention. Referring to Figure 3 Figure 6A ​, the exemplary processing step 600 starts with a substrate 202 which, in one or more embodiments, comprises single-crystalline silicon or alternatively other semiconductor materials such as, but not limited to, germanium, silicon-germanium, silicon carbide, gallium arsenide, gallium nitride, or the like. In the present embodiment, the substrate 202 is doped with a p-type impurity or dopant (e.g., boron, phosphorus, arsenic, etc.) to form a p-type conductive substrate or p-type substrate (P-SUB). Embodiments of the present invention also contemplate the use of an n-type conductive substrate. An NDD region 206 is formed on the upper surface of at least a portion of the substrate 202. In one or more embodiments, the NDD region 206 is preferably formed using an implantation process, e.g., ion implantation.

[0072] As Figure 6B shown, a thick (high-voltage) insulating layer 218 is formed on at least a portion of the upper surface of the NDD region 206. In one or more embodiments, the insulating layer 218 comprises an oxide (e.g., silicon dioxide (S i O2)) formed using a standard oxidation process, and other suitable insulating materials may also be considered. A deposition process may also be used to form the high-voltage insulating layer 218. The high-voltage insulating layer 218 is then patterned using standard lithography and etching, and the resulting structure is as Figure 6B shown.

[0073] In Figure 6C it, a thin insulating (gate oxide) layer 214 is formed, such as by oxidizing the wafer. As mentioned before, the thickness of the gate oxide layer 214 is less than the thickness of the high-voltage insulating layer 218. The S i O2 used to form the high-voltage insulating layer 218 and the gate oxide layer 214 is typically formed by a chemical reaction driven by oxygen and silicon in a high-temperature environment (e.g., about 800 degrees Celsius to 1200 degrees Celsius); however, even at room temperature, a thin natural oxide layer (e.g., about 1 nanometer (nm) thick) can be formed in an air environment. To grow a thicker oxide in a controllable environment, several known methods can be used, e.g., plasma-enhanced chemical vapor deposition (PECVD).

[0074] Then a polysilicon layer is deposited on at least a portion of the upper surface of the wafer, particularly above the high-voltage insulating layer 218 and the gate oxide layer 214. After the polysilicon layer is patterned and etched, a gate 212 and a field plate 216 structure of the LDMOS device 200 are formed. As mentioned before, in the present exemplary embodiment, the field plate 216 is substantially an extension of the gate 212 and is configured to have at least one opening 220 therein, and this opening 220 is used to reduce the parasitic gate-drain overlap capacitance C gd .

[0075] Continuing to refer to Figure 6C, a doped body region 204 is formed in a part of the NDD region 206 and is close to the upper surface of the NDD region. In this example, the body region 204 is doped with impurities having a conductivity type opposite to that of the NDD region (i.e., p-type impurities), thereby forming the p-type body region of the LDMOS device 200. The body region 204 is preferably formed using an implantation process, for example, ion implantation, and is usually followed by annealing at a specified temperature to drive and distribute the impurities in the NDD region 206. By applying a specific bias voltage (e.g., at least equal to the threshold voltage V Figure 2 of the LDMOS device) between the gate and the source region (212 and 208 respectively in t ), an inversion layer or channel is established in the body region 204 under the gate oxide layer 214 of the LDMOS device 200. The role of this channel is to facilitate the current flow between the source region and the drain region in the LDMOS device 200 according to the applied bias voltage.

[0076] Optionally, an implanted layer 224 is formed in the NDD region 206, close to the upper surface of the NDD region, under the opening 220 between the gate 212 and the field plate 216. During implantation, the gate 212 and the field plate 216 are preferably used as masks. As described above, the implanted layer 224 in this exemplary embodiment is an n-type implanted layer, which is used to increase the n-type doping concentration level at the channel edge closest to the drain region 210, thereby reducing the on-resistance of the LDMOS device. The implanted layer 224 is also used to limit the channel region under the gate 212 to improve the high-frequency performance.

[0077] In Figure 6D , insulating spacers 222 are formed on the sidewalls of the gate 212 and the field plate 216. In addition, the source region 208 and the drain region 210 are formed, for example, by using an implantation process (such as ion implantation) to generate impurities with a specified concentration level and type, and then a diffusion step is used to promote the distribution of the dopants. Preferably, the source region 208 and the drain region 210 are formed respectively close to the upper surfaces of the body region 204 and the NDD region 206 and are laterally spaced from each other. Preferably, a heavily doped region 211 is formed near the source region 208 using an implantation process. In the preferred example, this region 211 has a p-type conductivity type and is used as a body contact region.

[0078] As Figure 6EAs shown, a silicide layer 226 is formed on the upper surfaces of the gate 212 and the field plate 216, thereby reducing the resistance of this structure. As is known to those skilled in the art, silicides are typically formed by depositing a metal on the upper surface of a silicon structure and then performing a high-temperature annealing (e.g., about 900 degrees Celsius) to convert the deposited metal into a silicide layer. The silicide layer 226 is formed only in regions where the deposited metal (the metal component that becomes a silicide after annealing) is in direct contact with silicon, so the process is self-aligned. As is known to those skilled in the art, after the silicide formation is completed, the BEOL process is preferably used to interconnect individual devices (such as transistors, capacitors, resistors, etc.) with the wiring and metallization layers on the wafer.

[0079] Figure 7A FIG. 4 is a perspective view showing at least a portion of an exemplary LDMOS device 700 including an enhanced field plate structure according to an alternative embodiment of the present invention. Specifically, the LDMOS device 700 is configured in a manner consistent with the exemplary LDMOS device 200 shown in Figure 2 FIG. 2. The difference is that the LDMOS device 700 does not have a field plate ( Figure 2 labeled 216 in FIG. 2) formed as an extension of the gate 212, but includes a shielding structure 702, which is a structure separated from the gate 212. Compared with the field plate structure shown in Figure 2 FIG. 2, the separation of the shielding structure 702 from the gate 212 further reduces the parasitic gate-drain capacitance in the LDMOS device 700. In addition, since the shielding structure 702 is configured as a structure separated from the gate 212, the shielding structure does not have to be formed of the same material as the gate.

[0080] In the present exemplary embodiment, the shielding structure 702 is electrically connected to the gate 212 through a gate electrode 704 and a corresponding conductive via 706. The conductive via 706 is configured to provide a direct electrical connection between the gate electrode 704 and the respective ends of the gate 212 and the shielding structure 702. In one or more embodiments, the ends of the gate 212 and the shielding structure 702 located at the distal end of the conductive via 706 remain electrically open (i.e., not connected). In addition, the conductive via 706 is adapted to vertically separate the gate electrode 704 from the NDD region 206, thereby further reducing the parasitic gate-drain capacitance. The gate electrode 704 and the conductive via 706 can be composed of a metal (such as an aluminum gate electrode and a tungsten via), and the embodiments of the present invention are not limited to any specific conductive material. In addition, the gate electrode 704 and the conductive via 706 do not have to be composed of the same material.

[0081] Preferably, in one or more embodiments, the gate electrode 704 and / or the conductive via 706 are formed of a high-impedance material. Forming the gate electrode 704 and / or the conductive via 706 with a high-impedance material can minimize the drain electrode voltage spikes coupled to the gate 212 at high switching frequencies, thereby helping to reduce the likelihood of breakdown due to false gate turn-on, which often occurs in high-frequency power switching applications.

[0082] In this embodiment, the gate and shield structures are configured as parallel, independent finger-like structures. Since the shield structure 702 is electrically connected to the gate 212 only through the gate electrode 704 and the conductive via 706 at the finger-like ends of the gate and shield structures, the number of electrical couplings of the gate over the NDD region 206 and the parasitic gate-drain capacitance are significantly reduced.

[0083] In an alternative embodiment, the gate 212 and the shield structure 702 are electrically connected together through an external circuit. Specifically, Figure 7B is a perspective view depicting an exemplary LDMOS device 700 as shown in Figure 7A and, according to an embodiment of the present invention, includes a connection to an external gate drive circuit 708. In this exemplary embodiment, the gate electrode ( Figure 7A labeled 704) is divided into a gate electrode 710 and a shield structure electrode 712 that are physically and electrically separated from each other. The gate electrode 708, similar to the gate electrode 704 shown in Figure 7A , is electrically connected to the gate 212 through a corresponding conductive via 706. Similarly, the shield structure electrode 712 is electrically connected to the shield structure 702 through its corresponding conductive via 714.

[0084] Continuing as shown in Figure 7B , the external gate drive circuit 708 is coupled between the gate electrode 710 and the shield structure electrode 712. In one or more embodiments, in addition to providing control signals for independently driving the gate 212 and the shield structure 702, the gate drive circuit 708 also provides a high-impedance (e.g., about 1000 ohms) electrical connection between the gate 212 and the shield structure 702. As previously mentioned, one benefit of this high-impedance connection arrangement is to minimize the drain voltage spikes that may be coupled to the gate 212 at high switching frequencies, which can lead to false gate turn-on; this helps to reduce the likelihood of breakdown; that is, when both devices are turned on, the high-voltage power supply shorts to ground through the high-side and low-side MOSFETs.

[0085] Figure 8 is Figure 1A a cross-sectional view of the LDMOS device 100 shown in Figure 9Yes Figure 7A Cross-sectional view of the LDMOS device 700 shown in. Conceptually describes parasitic capacitance elements associated with the gate 212 and the shielding structure 702.

[0086] More specifically, referring to Figure 8 , the LDMOS device 100 includes parasitic gate-drain capacitance elements C gd1 , C gd2 and C gd3 resulting from the extension of the gate 112 and the field plate 116 over the NDD region 106. The capacitance of C gd3 is less than that of C gd2 , at least in part due to the thicker dielectric layer 118 formed on the field plate 116. The distributed parallel capacitance elements C gd1 , C gd2 and C gd3 are added together as the total gate-drain capacitance 100 in the LDMOS device. By comparison, compared with the new configuration of the shielding structure 702 shown in Figure 9 , the parasitic gate-drain capacitance elements present in the LDMOS device 700 are C gd1 , C gd2 and C gd3 , where C gd1 is attributed to the slight electrical coupling at the edge of the gate 212 over the NDD region 206, C gd2 is attributed to the slight overlap at the edge of the shielding structure 702 over the NDD region, and C gd3 is attributed to the extension of the shielding structure over the NDD region. However, since a large portion of the gate extension over the NDD region in the LDMOS device 700 has been removed, these parasitic gate-drain capacitance elements in the LDMOS device 700 are much smaller compared to the corresponding parasitic capacitance elements in the LDMOS device 100 in FIG. 1A. In addition, since the gate-drain capacitance is the main source of switch-induced false gate turn-on in the LDMOS device, compared with the LDMOS device 100, the LDMOS device 700 will beneficially achieve enhanced device reliability at higher switching frequencies.

[0087] As mentioned above, to reduce the parasitic capacitance resulting from the extension of the field plate 216 (as shown in Figure 2 ) over the NDD region 206, the thickness of the insulating layer 218 between the field plate (i.e., the shielding structure 702 in Figure 7A and 7B ) and the NDD region is increased. The insulating layer 218 is shown in Figures 2 to 7B , and preferably, as shown in the embodiments of the present invention, is formed using an oxidation process or an oxide deposition process. To better be compatible with the current semiconductor processing platform, Figure 10 and Figure 11An alternative embodiment is shown in which a high-voltage insulating layer is formed under the field plate 216.

[0088] Specifically, Figure 10 at least a partial cross-sectional view of an exemplary LDMOS device 1000 is described, which is formed in a consistent manner with the exemplary LDMOS device 1000 shown in Figures 2 to 7B . According to an embodiment of the present invention, the high-voltage insulating layer (such as Figure 2 , 7A and the 218 labeled in FIG. 7B) is replaced by a local oxidation of silicon (LOCOS) structure 1002. As is known to those skilled in the art, during the LOCOS process, regions of the wafer that are not to be oxidized are coated with a material (such as silicon nitride) that prevents oxygen diffusion at high temperatures (such as about 800 to 1200 °C). In one or more embodiments, the LOCOS structure 1002 is formed by thermally oxidizing silicon in the NDD region 206. During this high-temperature process, the silicon wafer is "consumed" and "replaced" by silicon oxide. Then, a field plate 216 is formed on at least a portion of the LOCOS structure 1002 in a manner consistent with the formation of the field plate 216 on the high-voltage insulating layer 218 shown in Figure 2 .

[0089] Similarly, Figure 11 at least a partial cross-sectional view of an exemplary LDMOS device 1100 is described, which is formed in a manner consistent with the exemplary LDMOS device shown in Figures 2 to 7B . According to an embodiment of the present invention, the high-voltage insulating layer (such as Figure 2 , 7A and the 218 labeled in FIG. 7B) is replaced by a shallow trench isolation (STI) structure 1102. As is known to those skilled in the art, the STI structure 1102 is formed early in the semiconductor device manufacturing process, before transistors and other active elements are formed. In one or more embodiments, the STI structure 1102 is formed by etching trenches in a portion of the NDD region 206 (between the implant layer 224 and the drain region 210), depositing one or more dielectric materials (such as silicon dioxide) to fill the trenches, and using a planarization technique such as CMP to remove the excess dielectric material. Then, a field plate 216 is formed on at least a portion of the STI structure 1102 in a manner consistent with the formation of the field plate 216 on the high-voltage insulating layer 218 shown in Figure 2 . However, since the STI structure 1102 is substantially flush with the upper surface of the wafer, the field plate 216 is formed on the NDD region 206 so that it is substantially flush with the gate 212; that is, the field plate is not a stepped structure similar to the field plates shown in Figure 2 , 7A or FIG. 7B.

[0090] Embodiments of the present invention can be beneficially used to form high-value capacitors in a relatively small area. It is very suitable for practical applications, such as but not limited to switched DC-DC synchronous converters, which typically require a relatively high-value input capacitor to improve the switching voltage ringing problem that usually plagues switched DC-DC synchronous converters.

[0091] By way of example only, without limitation or loss of generality, Figure 12 is an electrical schematic diagram depicting at least a portion of an exemplary switched DC-DC voltage converter circuit 1200 implemented as a synchronous buck converter, in which aspects of one or more embodiments of the present invention can be utilized. The voltage converter circuit 1200 includes a first MOSFET device M1, which can be referred to herein as the high-side device, and a second MOSFET device M2, which can be referred to herein as the low-side device. The drain (D) of the high-side device M1 is connected to the input voltage V IN , the source (S) of M1 is connected to the output switch node SW, and the gate (G) of M1 is connected to the first drive circuit 1202. The drain of the low-side device M2 is connected to the output switch node SW, the source of M2 is connected to ground or to another return voltage of the circuit 1200, and the gate of M2 is connected to the second drive circuit 1204.

[0092] The first and second drive circuits 1202, 1204 form part of a controller circuit 1206 for generating first and second control signals respectively supplied to the gates of the MOSFET devices M1 and M2. The first drive circuit 1202 is coupled between the switch node SW and the bootstrap power supply voltage BOOT, and the second drive circuit 1204 is coupled between the drive power supply voltage V DR and ground. In one or more embodiments, each of the drive circuits 1202, 1204 can be implemented using an inverter. Preferably, the drive power supply voltage V DR is supplied to the second drive circuit 1204, and the bootstrap power supply voltage BOOT is supplied to the first drive circuit 1202. The connected diode D1 has an anode coupled to the drive power supply voltage V DR and a cathode connected to the bootstrap power supply voltage BOOT. Preferably, a capacitor C1 is connected between the bootstrap power supply voltage BOOT and the switch node SW. When an N-channel MOSFET is used for the high-side transistor of the converter circuit 1200, the diode D1 and the capacitor C1 are typically required to together form a bootstrap circuit for generating a high enough voltage V GS to fully turn on the N-channel MOSFET as the high-side switch.

[0093] The DC-DC converter circuit 1200 also includes an input capacitor CIN and an output capacitor C OUT , the input capacitor C IN is connected between the input voltage V IN and ground, and the output capacitor C OUT is connected between the regulated output voltage V OUT and ground. The output inductor L OUT , coupled between the switch node SW and the output of the conversion circuit 1200, is used to generate the regulated output voltage V OUT . The inductor L1 and the output capacitor C OUT together serve as the energy storage elements of the conversion circuit 1200.

[0094] Typically, in a DC-DC converter circuit, the input capacitor C IN is placed on a printed circuit board far from the switching devices M1 and M2, so parasitic effects tend to be severe. Therefore, a preferred method is to integrate the input capacitor C IN on a silicon wafer, thus keeping the distance between the input capacitor and the switching devices as short as possible. Conventionally, the integrated input capacitor C IN is typically formed as a metal-insulator-metal (MIM) capacitor. Although this method may help reduce parasitic capacitance, the MIM capacitor requires a large area on the wafer to achieve the capacitance value typically required by a DC-DC converter, and an additional masking step is needed, so it is not a preferred technical solution.

[0095] To overcome the disadvantages of the conventional method, one or more embodiments of the present invention advantageously integrate the input capacitor with one or two primary switching devices, for example, directly embedding the input capacitor into the drain of the high-side MOSFET device M1 or into the source of the low-side MOSFET device M2, or both. Figure 13 is a cross-sectional view of at least a part of an exemplary semiconductor structure 1300 according to one or more embodiments of the present invention. The exemplary semiconductor structure 1300 includes an input capacitor 1302 embedded in the high-side MOSFET device 1304 of a DC-DC converter. In this example, it is assumed that the high-side MOSFET device 1304 is turned on, as is known to those skilled in the art, for example, by applying a voltage potential between the gate and source of the MOSFET device, and this voltage potential is greater than the threshold voltage of the device (V T ). As Figure 13 shown, in this exemplary embodiment, the input capacitor 1302 is a polysilicon-oxide-silicon (POS) capacitor, which is formed in the NDD region 1306 of the high-side MOSFET device 1304.

[0096] The input capacitor 1302 includes an insulating layer 1308. In this embodiment, preferably, the insulating layer 1308 includes an oxide formed on at least a part of the upper surface of the NDD region 1306, and a polysilicon layer 1310 formed on at least a part of the upper surface of the oxide layer 1308. The polysilicon layer 1310 forms the first electrode plate of the input capacitor 1302, and the NDD region 1306 forms the second electrode plate of the input capacitor.

[0097] By using an optional silicide process, where a metal silicide is deposited on the upper surface of the wafer, a silicide layer 1312 can be formed on at least a part of the upper surface of the polysilicon layer 1310 to provide a low-resistance connection to the polysilicon layer. Other parts of the structure 1300, such as the gate of the MOSFET device, the control gate polysilicon, the source and drain regions, can also be silicided.

[0098] Continue as Figure 13 As shown, one or more drain regions 1314 of the high-side MOSFET device 1304 are formed in the NDD region 1306 near the upper surface of the NDD region. In this exemplary embodiment, the drain regions 1314 are doped with n-type impurities to form N+ drain regions. Similarly, embodiments of the present invention can also use p-type drain regions. The insulating layer 1308 is formed between the drain regions 1314. The drain regions 1314 can be electrically coupled together through a metal connection (such as an M1 connection layer), which is not explicitly shown but is included in the technical solution. According to the voltage potential difference between the polysilicon layer 1310 and the drain regions 1314, a depletion region 1316 is formed in the NDD region 1306 near the upper surface of the NDD region and between the drain regions 1314. An insulating spacer 1318 is preferably formed on the sidewalls of the polysilicon layer 1310, and its function is to electrically isolate the input capacitor 1302 from other circuit elements formed on a common substrate (P-SUB).

[0099] The drain regions 1314 of the high-side MOSFET device 1304 are adapted to receive an applied input voltage (V IN ), and the polysilicon layer 1310 of the input capacitor 1302 is preferably connected to ground (GND). When configured in this way, the input capacitor 1302 (C IN ) will include two primary capacitive elements connected in series, namely an oxide capacitor (C OX ) 1320 and a depletion capacitor (C DEP ) 1322. The equivalent circuit of the input capacitor 1302 is shown in the figure. After the two capacitive elements are connected in series, the total capacitance (C TOT ) of the input capacitor 1302 can be determined by the following formula:

[0100]

[0101] As can be seen from the above expression (1), the total capacitance of the input capacitor C IN 1302 is as follows Figure 13 shown, which is much smaller than the capacitance element C OX or C DEP respectively. Therefore, in order to increase the total capacitance of the input capacitor C IN 1302, the semiconductor structure 1300 can be modified according to aspects of the present invention, thereby effectively short - circuiting the depletion capacitance element, such that C IN ≈C OX . For this purpose, preferably, one or more doped regions having a conductivity type opposite to that of the drain region 1314 are formed and connected to the drain region, as Figure 15 shown.

[0102] More specifically, Figure 15 is a cross - sectional view showing at least a part of an exemplary semiconductor structure 1500, which is consistent with the structure 1300 shown in Figure 13 . According to one or more embodiments of the present invention, it is modified to increase the input capacitor 1302 of the high - side MOSFET device 1304. As the structure 1300 shown in Figure 13 , it is assumed that the high - side MOSFET device 1304 is turned on, for example, by applying a voltage potential greater than the threshold voltage of the device between the gate and source terminals.

[0103] As Figure 15 shown, an inversion layer 1502 is formed in the NDD region 1306, which is close to the upper surface of the NDD region and under at least a part of the insulating layer 1308 of the input capacitor 1302. The characteristics of the inversion layer 1502 depend on a plurality of parameters, including the doping concentration near the junction position between the insulating layer 1308 and the NDD region 1306 in the NDD region, and the bias voltage applied between the polysilicon layer 1310 and the NDD region. In this exemplary embodiment, the inversion layer 1502 includes holes formed by the applied bias voltage. In one or more embodiments, the concentration of the inversion layer 1502 can reach about 5×10 17 -5×10 19 atoms per cubic centimeter (cm -3 ), and embodiments of the present invention are not limited to any specific concentration level. The change in the concentration of the inversion layer 1502 mainly depends on the level of the applied bias voltage. The NDD region 1306 is preferably doped with n - type impurities, and its doping concentration level is about 5×10 15 -1×10 18 cm -3, embodiments of the present invention are not limited to any specific impurity type or doping concentration level. Doping can be achieved using standard implantation processes (such as ion implantation) or similar processes. Comparing the doping concentration level of the NDD region 1306 with the exemplary doping concentration of the body region 1503, which is a p-type body region (P-BODY) in this exemplary embodiment and in which the source region of the MOSFET device 1304 is formed, its doping concentration level is about 5×10 16 -5×10 18 cm -3 。

[0104] Similar to a p-n junction, the dominant principle for forming a depletion layer and an inversion layer is charge neutrality. If the NDD region 1306 is n-type doped, then electrons are depleted to a depth w, exposing sufficient positive donors to precisely balance the charge on the polysilicon layer 1310. Assuming there are N D number of donors per unit volume, charge neutrality requires the depletion width w to satisfy the following relationship:

[0105] Q = qN D w,

[0106] where q is the electron charge.

[0107] If the depletion width w becomes wide enough, then holes will appear in a very thin layer at the semiconductor-oxide junction, which is called the inversion layer because they have opposite charges to the dominant electrons in the n-type NDD region 1306. When the inversion layer forms, the depletion layer width no longer expands with the increase of charge Q. In this case, electrical neutrality is achieved by attracting more holes into the inversion layer. In a MOSFET device, this inversion layer is called the channel.

[0108] In the present exemplary embodiment, one or more doped regions 1504, preferably having a p-type conductivity type (P+), are formed in the NDD region 1306, which is located at opposite ends of the inversion layer 1502 in a region near the upper surface of the NDD region and adjacent to the corresponding drain region 1314. The doped regions 1504 can be formed using a standard implantation process or other similar processes and are used as pick-up rings to provide an electrical connection between the inversion layer and the adjacent drain region 1314. The doped regions 1504 are mainly required because the carriers in the inversion layer 1502 are holes and thus cannot be directly connected to the n+ drain region 1314. There is a p-n junction barrier between the p-type material and the n-type material. Therefore, the P+ doped regions 1504 are electrically connected to the inversion layer 1502. Preferably, each doped region 1504 has a conductivity type opposite to that of the drain region 1314 (e.g., the P+ doped region in this embodiment) and is electrically connected to the adjacent drain region through a silicide layer 1506 formed on at least a portion of the upper surfaces of the respective drain and doped regions. Other alternative technical solutions for electrically connecting the doped region and the drain region are also contemplated in the present invention. In one or more embodiments, the doping concentration level of the doped regions 1504 is about 10 18 -10 21 cm -3 ³

[0109] Continuing to refer to Figure 15 , the formation of the P+ doped regions 1504 connected to the drain region 1314 creates a current path from the inversion layer 1502 to the drain region 1314, which in turn is connected to the input voltage V IN DD. When configured in this way, the depletion capacitance element C DEP 1322 is effectively bypassed (i.e., short-circuited), leaving only the oxide capacitance element C OX 1320 connected between the input voltage V IN (i.e., the drain of the high-side MOSFET device) and ground. Figure 16 shows an exemplary equivalent input capacitor circuit illustrating this technical solution. Therefore, the total input capacitance C IN in is approximately equivalent to the oxide capacitance C OX (i.e., C IN in≈C OX ox), which has the advantage that it is much larger than the total input capacitance considering the depletion capacitance defined by the above expression (1).

[0110] Figure 17 is a cross-sectional view that depicts Figure 15At least a portion of the exemplary semiconductor structure 1500 as shown, as in one or more embodiments of the present invention, is in a situation where the high-side MOSFET device 1304 is turned off. As shown in FIG. 17, when the high-side MOSFET device is turned off, the depletion region 1316 extends vertically into the substrate and laterally under the polysilicon gate. However, when the bias input capacitor 1302 is such that the polysilicon layer 1310 is connected to ground and the drain region 1314 and the P+ doped region 1504 are connected to V IN , an inversion layer 1502 will still form below the insulating layer 1308 of the POS capacitor, near the upper surface of the NDD region 1306, which provides a current conduction path between the NDD region (forming the bottom plate of the input capacitor 1302) and V IN . Additionally, the depletion capacitance element C DEP 1322 has substantially no conduction path to the drain region 1314, thus effectively eliminating C DEP as a possible factor for the input capacitor C IN . Therefore, according to the various aspects of the present invention, regardless of whether the high-side MOSFET device is on or off, the total capacitance between V IN and ground remains almost equivalent to the oxide capacitance C OX 1320.

[0111] The semiconductor structure in the exemplary embodiment described above in conjunction with Figures 13 to 17 where the input capacitor C IN or at least a portion thereof is directly integrated into the high-side MOSFET device ( Figure 12 M1 in). According to an embodiment of the present invention, in a similar manner, the input capacitor C IN or at least a portion thereof can be directly integrated into the low-side MOSFET device ( Figure 12 M2 in). According to one or more embodiments of the present invention, by way of example only and not to be construed restrictively, Figure 18 a cross-sectional view of at least a portion of an exemplary semiconductor structure 1800 is described, the exemplary semiconductor structure 1800 including an input capacitor 1802 embedded with a DC-DC converter of a low-side MOSFET device 1804. The input capacitor 1802 includes a polysilicon layer 1806 that is formed on at least a portion of the upper surface of an insulating layer 1808, and the insulating layer 1808 can be an oxide (e.g., S i O2). The polysilicon layer 1806 forms the first plate of the input capacitor 1802. A silicide layer 1810 can optionally be formed on at least a portion of the upper surface of the polysilicon layer 1806 for low-resistance electrical connection with the area below the polysilicon layer.

[0112] In the present exemplary embodiment, the semiconductor layer 1812 below the insulating layer 1808, preferably made of silicon, is doped with a p-type material (such as boron or aluminum). Other embodiments of the present invention contemplate that the semiconductor layer may be doped with an n-type material (such as phosphorus or arsenic). It is obvious to those skilled in the art that the semiconductor layer 1812 can be formed as a p-type substrate (P-SUB), or alternatively, can be formed as a p-type epitaxial layer (P-EPI) or a p-type well (PW). The semiconductor layer 1812 forms the second plate of the input capacitor 1802. When configured in this way, the polysilicon layer 1806, the oxide layer 1808, and the semiconductor layer 1812 form a POS capacitor, as indicated by reference numeral 1814. The polysilicon layer 1806 is preferably adapted to receive the applied input voltage V IN , and the semiconductor layer 1812 is grounded through one or more source regions 1816 of the low-side MOSFET device 1804.

[0113] Each source region 1816 is disposed in a dopant region 1818 which is preferably a p-type body region (P-BODY) in the present exemplary embodiment, formed in the semiconductor layer 1812, near the upper surface of the semiconductor layer, and adjacent to the NDD region in the low-side MOSFET device 1804. In this embodiment, the source region 1816 has an n-type conductivity type (N+), and the source regions in the embodiments of the present invention are not limited to N+. One or more first doping regions 1820, having a conductivity type opposite to that of the source region 1816, are preferably P+ regions in this embodiment, formed in the body region 1818 near the upper surface of the body region and adjacent to the source region. One or more second doping regions 1822, having a conductivity type opposite to that of the first doping region 1820, are preferably N+ regions in this embodiment, partially formed in the body region 1818 and partially formed in the semiconductor layer 1812, near the upper surfaces of the body region and the semiconductor layer, and adjacent to the first doping region. The function of the second doping region 1822 is to act as an N+ pick-up ring, which surrounds the polysilicon layer 1806 of the input capacitor 1802. By forming an inversion layer 1824 in the substrate (semiconductor layer) 1812, as shown in Figure 15 , in a manner consistent with that integrated in the input capacitor 1302 of the high-side MOSFET device, the inversion layer 1824 is formed directly below the insulating layer 1808 of the input capacitor and between the N+ doped region 1822.

[0114] The characteristics of the inversion layer 1824 depend on multiple parameters, including the doping concentration of the p-type semiconductor layer 1812 (P-SUB or P-EPI or P-WELL) adjacent to the dielectric layer 1808, and the bias voltage applied between the polysilicon layer 1806 and the p-type region (P-SUB or P-EPI or P-WELL). In one or more embodiments, the concentration of the inversion layer 1824 can reach approximately 5×10 17 -5×10 19 cm -3 , and the embodiments of the present invention are not limited to any specific doping concentration level. As is known to those skilled in the art, the source region 1816, the body region 1818, and the first and second doped regions 1820 and 1822 are also preferably formed using standard implantation processes. By way of example only and not by way of limitation, the body region 1818 is preferably doped with an impurity concentration level of approximately 5×10 16 -5×10 18 cm -3 , the second doped (N+) region 1822 is doped with an impurity concentration level of approximately 10 18 -10 21 cm -3 , and the embodiments of the present invention are not limited to any specific impurity type or doping concentration level.

[0115] As previously described, the semiconductor layer 1812 under the input capacitor is not limited to any specific material or conductivity type. For example, as Figure 18 shown, although the second plate of the input capacitor 1802 is formed including the p-type substrate 1812 under the polysilicon layer 1806, an n-type semiconductor layer may also be formed under the polysilicon layer in the input capacitor. More specifically, according to one or more embodiments of the present invention, Figure 19 a cross-sectional view of at least a portion of an exemplary semiconductor structure 1900 is described, which includes an input capacitor 1902 embedded in the low-voltage side MOSFET device 1804 of a DC-DC converter, and the input capacitor includes an n-type semiconductor layer serving as the second plate of the input capacitor.

[0116] As Figure 19 shown, the input capacitor 1902 is in the same manner as Figure 18Formed in a manner consistent with the exemplary input capacitor 1802 shown, except for the area under the polysilicon layer 1806, it further includes an n-type semiconductor layer 1904 formed on at least a portion of the upper surface of the substrate (P-SUB) 1812. In one or more embodiments, the n-type semiconductor layer 1904 preferably includes an NDD region, which can be formed in a manner consistent with the NDD region in the low-voltage side MOSFET device 1804. The n-type semiconductor layer 1904 is grounded through the N+ doped region 1822, which surrounds the polysilicon layer 1806 of the input capacitor 1902.

[0117] The entire chip area is generally not as uniform as in the ideal case, so it is desirable to distribute the input capacitors over the entire chip area as much as possible. According to the described exemplary structure, at least a portion of the input capacitor is directly integrated within the high-voltage side power MOSFET device (e.g., Figure 15 shown) and / or within the low-voltage side power MOSFET device (e.g., Figure 18 and 19 shown). In one or more embodiments, the input capacitor structure can be separated from the power MOSFET device (whether it is a high-voltage side device or a low-voltage side device).

[0118] Figure 20 A cross-sectional view of at least a portion of an exemplary semiconductor structure 2000 is described. According to one or more embodiments of the present invention, the exemplary semiconductor structure 2000 includes an input capacitor 2002, which is integrated on the same substrate as one or more power devices 2004 (high-voltage side or low-voltage side MOSFET devices), but is electrically isolated from the power device. More specifically, referring to Figure 20 , for example, the p-type substrate (P-SUB) in this exemplary embodiment, the semiconductor structure 2000 includes at least one capacitor 2002 and one or more power devices 2004 formed on a common substrate 1812. The power device 2004 is electrically isolated from the POS capacitor 2002 by an isolation structure 2006, and the isolation structure 2006 can use, for example, a shallow trench isolation (STI) structure, a local oxidation of silicon isolation (LOCOS) structure, a junction or a dielectric isolation structure, etc. The isolation structure 2006 is formed in the substrate 1812, near the upper surface of the substrate, and each isolation structure is arranged between the capacitor 2002 and the power device 2004.

[0119] The input capacitor 2002 includes a polysilicon layer 1806, on which a silicide layer 1810, a semiconductor layer 1812, and an insulating layer 1808 are selectively formed. The insulating layer 1808 is sandwiched between the polysilicon layer and the semiconductor layer to form a POS capacitor. Compared with Figure 18Consistent with the exemplary semiconductor structure 1800 shown, in this embodiment, the semiconductor layer 1812 (e.g., silicon) under the insulating layer 1808 is doped with a p-type material (e.g., boron or aluminum). Other embodiments of the present invention contemplate that the semiconductor layer may be doped with an n-type material (e.g., phosphorus or arsenic), which will be described in further detail below in conjunction with Figure 21 The semiconductor layer 1812 may be formed as a p-type substrate (P-SUB), or may be formed as a p-type epitaxial layer (P-EPI) or a p-type well (PW) in a standard manner. In this exemplary embodiment, the input capacitor 2002 is configured to have a polysilicon layer 1806 connected to the input voltage V IN , and the semiconductor layer 1812 is grounded through the first and second doping regions 1820 and 1822, respectively.

[0120] Figure 21 A cross-sectional view of at least a portion of an exemplary semiconductor structure 2100 is described. According to one or more other embodiments of the present invention, the exemplary semiconductor structure 2100 includes an input capacitor 2102, which is integrated on the same substrate as one or more power devices 2004 (whether high-side MOSFET devices or low-side MOSFET devices) and is electrically isolated from the power devices. Similar to Figure 20 the exemplary semiconductor structure 2000 described, the semiconductor structure 2100 includes at least one POS capacitor 2102 and one or more power devices 2004 (e.g., high-side and / or low-side power MOSFET devices) formed on the same substrate 1812, which is preferably a p-type substrate (P-SUB) in this embodiment. The power device 2004 is electrically isolated from the POS capacitor 2102 by an isolation structure 2006 (e.g., STI structure, LOCOS structure, junction or dielectric isolation structure, etc.). The isolation structure 2006 preferably containing an oxide is formed in the substrate 1812 near the upper surface of the substrate, and each isolation structure is arranged between the capacitor 2102 and the power device 2004.

[0121] The capacitor 2102 includes a polysilicon layer 1806, and a silicide layer 1810 is selectively formed above it. In this exemplary embodiment, the region below the polysilicon layer 1806 includes an n-type semiconductor layer 2104 (e.g., doped with n-type impurities at a specified concentration level, such as phosphorus or arsenic), which is formed on at least a portion of the upper surface of the substrate (P-SUB) 1812. In one or more embodiments, the n-type semiconductor layer 2104 preferably includes a material that can be Figure 19The NDD regions are formed in a manner consistent with the exemplary semiconductor structure 1900 shown. In this embodiment, the n-type semiconductor layer 2104 is grounded through the N+ doped region 1822 that surrounds the polysilicon layer 1806 of the capacitor 2102. The capacitor 2102 also includes an insulating layer 1808 disposed between the polysilicon layer 1806 and the semiconductor layer 2104.

[0122] Figure 22 is a cross-sectional view depicting at least a portion of the exemplary semiconductor structure 2100 as Figure 21 shown, where the polysilicon layer 1806 of the capacitor 2102 is grounded through the silicide layer 1810, and the semiconductor layer 2104 is connected to V through the first and second doped regions 1820, 1822 IN . According to one or more embodiments of the present invention. Referring to Figure 22 , the capacitor 2102 includes a first doped region 1820 that is doped with p-type impurities at a specific doping concentration level. The first doped region 1820 is formed in the NDD region 2104 near the upper surface of the NDD region and is adjacent to the second doped region 1822, which is formed in a manner consistent with the formation of the first and second doped regions in the semiconductor structure 2000 as Figure 20 shown.

[0123] According to Figure 21 and Figure 22 the different connection arrangements of the exemplary semiconductor structure 2100 shown, it is apparent that the capacitor 2102 configured in a manner independent of other circuit elements in the semiconductor structure is not limited to being implemented as an input capacitor in a DC-DC converter circuit, but can be applicable to any circuit that requires a capacitor with high density and small area.

[0124] At least a portion of the technology of the present invention can be implemented in an integrated circuit. During the formation of an integrated circuit, identical chips are typically fabricated on the surface of a semiconductor wafer in a repetitive manner. Each wafer includes the devices described in this application and may also include other structures and / or circuits. Individual chips are cut or diced from the wafer and then packaged into an integrated circuit. Those skilled in the art should know how to cut and package wafers to produce integrated circuits. Any exemplary structure or device or a portion thereof shown in the drawings can be part of an integrated circuit. Therefore, an integrated circuit manufactured using the technical solution of the present invention is considered part of the present invention.

[0125] Those skilled in the art know that the above exemplary structure can be distributed in raw form (i.e., a single wafer with multiple unpackaged chips), as a bare die, in packaged form, or incorporated as part of an intermediate or final product that benefits from a high-density integrated capacitor device formed according to one or more embodiments of the present invention, such as a DC-DC converter, a radio frequency power amplifier, etc.

[0126] The integrated circuit disclosed according to the present invention can basically be used in any high-frequency, high-power application and / or electronic system. Systems suitable for the embodiments of the present invention include, but are not limited to, DC-DC converters. Systems incorporating such an integrated circuit are considered to be part of the present invention. Given the disclosure provided by the present invention, those skilled in the art will be able to conceive of other embodiments and applications of the embodiments of the present invention.

[0127] The illustrations of the embodiments of the invention described in this application are intended to provide a general understanding of the various embodiments and do not serve as a complete description of all elements and features of the devices and systems that may use the circuits and techniques described in this application. Given the disclosure herein, many other embodiments will become obvious to those skilled in the art; other embodiments can be utilized and derived therefrom, and structural and logical substitutions and changes can be made without departing from the scope of the present disclosure. The drawings are also merely representative and are not drawn to scale. Therefore, their specifications and images should be regarded as explanatory rather than restrictive.

[0128] The term "embodiments" used in this application, whether singular or plural, is for convenience of description only. If this application actually describes more than one embodiment or inventive concept, it is not intended to limit the scope of this application to any one embodiment or inventive concept. Therefore, although specific embodiments have been illustrated and described in this application, it should be understood that other embodiments that achieve the same purpose can replace the specific embodiments shown; that is, the present disclosure is intended to cover any and all adaptations or variations of the various embodiments. Combinations of the above embodiments, as well as other embodiments not specifically described herein, will become obvious to those skilled in the art through the disclosure of this application.

[0129] The terms used in this application are only for describing specific embodiments and are not intended to limit the present invention. Unless the context clearly indicates otherwise, the singular forms "a", "the", and "said" used in this application also include their plural forms. It should be further understood that when the terms "comprises" and / or "comprising" are used in this application, only the presence of the stated features, steps, operations, elements, and / or components is specified, but the presence or addition of one or more other features, steps, operations, elements, components, and / or their groups is not excluded. Terms such as "above", "below", "above", and "below" are used to indicate the relative positional relationship between elements or structures, rather than the absolute position.

[0130] In the claims, the corresponding structures, materials, steps, and equivalents of all method or act-plus-function elements are intended to include any structure, material, or act for performing the recited function in combination with other elements recited in the claim. The description of the various embodiments is provided for purposes of illustration and description only and is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments selected for description herein are chosen in order to best explain the principles of the invention and its practical application and to enable others of ordinary skill in the art to understand the invention with various modifications that are suited to the particular use contemplated..

[0131] The abstract is provided to comply with 37 C.F.R. § 1.72(b), which requires the abstract to enable the reader to quickly ascertain the nature of the technical disclosure. The submission of the abstract is on the premise that it will not be used to interpret or limit the scope or meaning of the claims. Further, in the foregoing specification, it can be seen that for the purpose of streamlining the disclosure, various features are combined in a single embodiment. This manner of disclosure should not be interpreted as requiring more features than are expressly recited in each claim. Rather, as reflected in the appended claims, the inventive subject matter lies not in the features of any single embodiment but in the claims as a whole. Accordingly, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate claim for protection.

[0132] Given the description of the embodiments of the invention provided herein, those of ordinary skill in the art will be able to conceive of other implementations and applications of the technology of the embodiments of the invention. Although the exemplary embodiments of the invention have been described with reference to the accompanying drawings, it should be understood that the embodiments of the invention are not limited to such exact embodiments and that various other changes and modifications may be made by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A capacitor, characterized in that, Integrated with at least one metal oxide semiconductor field effect transistor (MOSFET) device formed on the same substrate, the capacitor includes: A first electrode plate, including a doped semiconductor layer having a first conductivity type; An insulating layer, formed on the upper surface of at least a part of the doped semiconductor layer; A second electrode plate, including a polysilicon layer formed on the upper surface of at least a part of the insulating layer, wherein, An inversion layer is formed in the doped semiconductor layer, the inversion layer is located below at least a part of the insulating layer and close to the upper surface of the doped semiconductor layer, and the inversion layer is formed according to the voltage applied between the first electrode plate and the second electrode plate; and At least one doped region, having a second conductivity type, the doped region is formed in the doped semiconductor layer and close to the upper surface of the doped semiconductor layer, and the doped region is adjacent to one of the drain region and the source region having the first conductivity type formed in the MOSFET device, the doped region is electrically connected to the inversion layer, and the second conductivity type is opposite in polarity to the first conductivity type.

2. The capacitor according to claim 1, wherein At least one of the doped regions of the second conductivity type includes first and second doped regions of the second conductivity type, the first and second doped regions are electrically connected to the inversion layer in the doped semiconductor layer and serve as the boundary of the inversion layer.

3. The capacitor according to claim 1, characterized in that, The doped semiconductor layer includes a substrate, an epitaxial layer, and a well having a first conductivity type.

4. The capacitor according to claim 1, wherein The insulating layer includes an oxide.

5. The capacitor according to claim 1, characterized in that, It further includes a silicide layer, the silicide layer is formed on the upper surface of at least a part of the polysilicon layer and on the upper surface of at least a part of at least one of the doped regions.

6. The capacitor according to claim 5, characterized in that, The silicide layer is formed on the upper surface of at least a part of the drain region or the source region of the MOSFET device, and the silicide layer electrically connects the drain region or the source region of the MOSFET device to at least one of the doped regions.

7. The capacitor according to claim 1, wherein The doped semiconductor layer of the first conductivity type forms a drain drift region in the MOSFET device.

8. The capacitor according to claim 1, characterized in that, The doped semiconductor layer of the first conductivity type forms a body region in the MOSFET device.

9. The capacitor according to claim 1, wherein, The first conductivity type is n-type, and the second conductivity type is p-type.

10. The capacitor according to claim 1, characterized in that, The MOSFET device is configured as a high-side transistor in a DC-DC voltage regulation circuit, the drain region of the MOSFET device and the first electrode plate of the capacitor are connected to the input voltage of the circuit, and the second electrode plate of the capacitor is grounded.

11. The capacitor according to claim 1, wherein The MOSFET device is configured as a low-side transistor in a DC-DC voltage regulation circuit, the source region of the MOSFET device and the first electrode plate of the capacitor are grounded, and the second electrode plate of the capacitor is connected to the input voltage of the circuit.

12. The capacitor according to claim 1, wherein, It further includes one or more isolation structures formed in the doped semiconductor layer, the isolation structures are arranged between the capacitor and at least one of the MOSFET devices to electrically isolate the capacitor from the MOSFET devices.

13. The capacitor according to claim 12, characterized in that, The isolation structures include at least one of a shallow trench isolation (STI) structure, a local oxidation of silicon isolation (LOCOS) structure, a junction isolation structure, and a dielectric isolation structure.

14. A method for forming a capacitor, characterized in that, The method is integrated and configured with at least one metal-oxide-semiconductor field-effect transistor (MOSFET) device, and the method includes: Forming a first electrode plate, which includes a doped semiconductor layer of a first conductivity type; Forming an insulating layer on the upper surface of at least a part of the doped semiconductor layer; Forming a second electrode plate, which includes a polysilicon layer on the upper surface of at least a part of the insulating layer, wherein an inversion layer is formed in the doped semiconductor layer, the inversion layer is located below at least a part of the insulating layer and close to the upper surface of the doped semiconductor layer, and the inversion layer is formed according to the voltage applied between the first electrode plate and the second electrode plate; and Forming at least one doped region, which has a second conductivity type, is formed in the doped semiconductor layer, and is close to the upper surface of the doped semiconductor layer, and is adjacent to one of the drain region and the source region of the first conductivity type formed in the MOSFET device, the doped region is electrically connected to the inversion layer, and the second conductivity type is opposite to the polarity of the first conductivity type.

15. The method according to claim 14, wherein Forming at least one doped region includes forming first and second doped regions of the second conductivity type, and the first and second doped regions are electrically connected to the inversion layer in the doped semiconductor layer and serve as the boundary of the inversion layer.

16. The method according to claim 14, wherein The doped semiconductor layer includes a substrate, an epitaxial layer, and a well of the first conductivity type.

17. The method according to claim 14, wherein It further includes forming a silicide layer on the upper surface of at least a part of the polysilicon layer and on the upper surface of at least a part of at least one of the doped regions.

18. The method according to claim 17, wherein It further includes a silicide layer formed on the upper surface of at least a part of the drain region or the source region of the MOSFET device.

19. The method according to claim 14, wherein It further includes forming a drain drift region in the MOSFET device from the doped semiconductor layer of the first conductivity type.

20. The method according to claim 14, wherein It further includes forming a body region in the MOSFET device from the doped semiconductor layer of the first conductivity type.

21. A DC-DC voltage converter circuit, characterized in that, It includes: A first metal-oxide-semiconductor field-effect transistor (MOSFET) device, which has a drain coupled to the input node of the converter circuit, a source coupled to the switch node of the converter circuit, and a gate, and the input node is adapted to receive the input voltage applied to the converter circuit; A second MOSFET device, which has a drain coupled to the switch node of the converter circuit, a source coupled to the recovery voltage of the converter circuit, and a gate; A controller circuit, which is coupled to the first and second MOSFET devices, and the controller circuit is configured to generate first and second control signals, and the first and second control signals are provided to the gates of the first and second MOSFET devices to control the activation of the MOSFET devices; At least one energy storage element, which is coupled between the switch node and the output terminal of the converter circuit; An input capacitor is coupled between an input node of the converter circuit and a return voltage. The input capacitor is integrated with at least one of the first and second MOSFET devices. The input capacitor includes: A first plate including a doped semiconductor layer having a first conduction type. The doped semiconductor layer forms at least one of a drift drain region and a body region of the first and second MOSFET devices; An insulating layer formed on an upper surface of at least a part of the doped semiconductor layer; A second plate including a polysilicon layer formed on an upper surface of at least a part of the insulating layer. An inversion layer is formed in the doped semiconductor layer. The inversion layer is located under at least a part of the insulating layer and close to the upper surface of the doped semiconductor layer. The inversion layer is formed according to a voltage applied between the first plate and the second plate; and At least one doped region having a second conduction type. The doped region is formed in the doped semiconductor layer and close to the upper surface of the doped semiconductor layer, and is adjacent to one of a drain region and a source region having the first conduction type formed in the MOSFET device. The doped region is electrically connected to the inversion layer. The second conduction type is opposite in polarity to the first conduction type.

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