Display panel and preparation method of display panel

Abstract

Embodiments of the present application provide a display panel and a preparation method. The display panel comprises a shielding layer, a thin film transistor device layer, and a first via hole, a second via hole and a third via hole arranged correspondingly, wherein the first via hole and the third via hole are arranged as stepped holes, and the first via hole, the second via hole and the third via hole are etched by the same etching process. One mask processing is adopted, the number of masks is saved, and the production cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of display panel design and manufacturing technology, specifically to a display panel and a method for preparing the display panel. Background Technology

[0002] With the development of display technologies such as display panel manufacturing processes, people have put forward higher requirements for the performance and quality of display panels and devices.

[0003] Organic light-emitting diodes (OLEDs) are widely used in numerous fields due to their advantages over traditional liquid crystal displays (LCDs), including lighter weight, wider viewing angles, and higher luminous efficiency. OLED devices consist of an array substrate containing multiple thin-film transistors (TFTs). The performance of these TFTs directly impacts the overall performance of the OLED. With the development of wearable devices and wearable displays, the power consumption requirements for display devices are increasing. Currently, low-temperature polycrystalline-Si oxide (LTPO) and indium gallium zinc oxide (IGZO) processes are used to fabricate display panels with fast response times and lower power consumption. However, existing technologies cannot fully integrate these processes when fabricating these devices, and the fabrication process is complex, requiring multiple layers and numerous etching passes, resulting in high costs and hindering the improvement of the overall panel performance.

[0004] In summary, the fabrication process of light-emitting devices prepared in the existing technology is relatively complex and the fabrication cost is relatively high, which is not conducive to improving the overall performance of light-emitting devices. Summary of the Invention

[0005] This invention provides a display panel and a method for manufacturing the display panel, which effectively improves the manufacturing process of the display panel and reduces the production cost of the display panel.

[0006] To solve the above-mentioned technical problems, the technical methods provided by the embodiments of the present invention are as follows:

[0007] A first aspect of the present invention provides a display panel, including a display area and a binding area disposed on one side of the display area, the display panel comprising:

[0008] Substrate;

[0009] A shielding layer disposed on the substrate;

[0010] A thin film transistor device layer disposed above the shielding layer, the thin film transistor device layer comprising a first thin film transistor disposed in the display area, and a second thin film transistor electrically connected with the first thin film transistor, a first source / drain of the first thin film transistor being electrically connected with a first active layer through a first via, a second source / drain of the second thin film transistor being electrically connected with a second active layer through a second via;

[0011] The display panel further comprises a third via penetrating through the film layers between the second source / drain and the substrate, the first via, the second via and the third via are arranged as stepped holes, and the distance between the top of the first via and the third via and the first step platform corresponding to the stepped hole is the same.

[0012] According to an embodiment of the present application, at least one step platform in the stepped hole corresponding to the first via, the second via and the third via is located on the same film layer.

[0013] According to an embodiment of the present application, the third via comprises a first step platform and a second step platform, the first step platform is located above the second step platform, and the aperture of the third via gradually decreases from the first step to the second step platform.

[0014] According to an embodiment of the present application, the distance between the opening surface of the third via and the first step platform is smaller than the distance between the first step platform and the second step platform, and the distance between the first step platform and the second step platform is greater than the distance between the second step platform and the bottom of the third via.

[0015] According to an embodiment of the present application, the first step platform is arranged in the same layer as the second active layer of the second thin film transistor.

[0016] According to an embodiment of the present application, the second step platform is arranged in the film layer corresponding to the first active layer, and the second step platform is located inside the film layer.

[0017] According to an embodiment of the present application, the aperture of the third via is greater than the apertures of the first via and the second via.

[0018] According to an embodiment of the present application, the display panel further comprises a metal layer and a fourth via, the metal layer is arranged between the second thin film transistor and the third via, and the metal layer is electrically connected with the shielding layer through the fourth via.

[0019] According to an embodiment of the present application, the fourth via is a stepped via, and the first via, the second via, the third via and the fourth via are formed by the same etching process.

[0020] According to an embodiment of the present application, the fourth via corresponds to a stepped via having the same number of steps as the third via, and a step platform in the fourth via is at the same height as a step platform in the third via.

[0021] According to an embodiment of the present application, the metal layer, the first source / drain and the second source / drain are on the same film layer.

[0022] According to an embodiment of the present application, the first via, the second via, the third via and the fourth via have the same distance from their opening surfaces to the first step platform of the stepped via.

[0023] According to an embodiment of the present application, the first via, the second via, the third via and the fourth via have the same distance from their opening surfaces to the first step platform of the stepped via.

[0024] According to an embodiment of the present application, the first active layer is a polysilicon oxide semiconductor, and the second active layer is an indium gallium zinc oxide semiconductor.

[0025] According to a second aspect of the embodiments of the present application, a display panel is also provided, and a preparation method thereof includes the following steps:

[0026] A substrate is provided, and a shielding layer is prepared on the substrate.

[0027] A thin film transistor device layer is prepared on the shielding layer, and the thin film transistor device layer includes a first thin film transistor and a second thin film transistor.

[0028] A photoresist is prepared on the thin film transistor device layer, and the photoresist is treated by a photo mask to form openings with different depths in the areas corresponding to the source / drain of the thin film transistor, and a fourth opening and a third opening are formed in the shielding layer and the corresponding position of the bonding area, respectively.

[0029] The thin film transistor device layer is etched, and a third via and a fourth via and a corresponding first step platform are formed in the corresponding positions of the third opening and the fourth opening.

[0030] Etching the openings of different depths in the source / drain corresponding region and etching the thin film transistor device layer at the corresponding openings at the same time to form the first via, the fifth via, and etching to the first step platform height corresponding to each via, and etching the third via and the fourth via to the second step platform position;

[0031] Etching the photoresist and the corresponding film layer in each via to form the second via, and etching the first via, the second via and the fifth via to the active layer surface, etching the third via to the substrate surface, and etching the fourth via to the shielding layer surface;

[0032] Preparation of a metal layer in the corresponding via, and preparation of a planarization layer on the metal layer, and the planarization layer fills the third via;

[0033] Preparation of a pixel electrode on the planarization layer and packaging, and completion of the preparation of the display panel.

[0034] In summary, the beneficial effects of the embodiment of the present application are:

[0035] The embodiment of the present application provides a display panel and a preparation method of the display panel. The display panel comprises a shielding layer, a thin film transistor device layer, a first thin film transistor and a second thin film transistor arranged in the thin film transistor device layer, a first via and a second via corresponding to the thin film transistor, and a third via structure arranged in the binding area of the display panel. The first via, the second via and the third via are all arranged as stepped holes, and the first via and the third via are etched by the same etching process. Therefore, the same etching process is used to form multiple different via structures in the thin film transistor device layer, so as to effectively save the number of masks, improve the preparation process of the display panel, and reduce the production cost. BRIEF DESCRIPTION OF DRAWINGS

[0036] The technical scheme and other beneficial effects of the present application will be more apparent through the following detailed description of the specific embodiments of the present application in combination with the drawings.

[0037] Figure 1 The film layer structure schematic diagram of the display panel provided by the embodiment of the present application is shown in the figure;

[0038] Figure 2 The schematic diagram corresponding to the via structure provided by the embodiment of the present application is shown in the figure;

[0039] Figure 3 The local film layer structure schematic diagram corresponding to the first via provided by the embodiment of the present application is shown in the figure;

[0040] Figures 4-7 The film layer structure schematic diagram corresponding to the preparation process of the display panel provided by the embodiment of the present application is shown in the figure;

[0041] Figure 8 A preparation flowchart of the display panel provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0042] The following disclosure provides different embodiments or examples to realize different structures of the present application, with reference to the accompanying drawings of the embodiments of the present application. In order to simplify the present application, the components and settings of specific examples are described below. In addition, the present application provides various specific examples of processes and materials, which can be realized by other processes by those skilled in the art without creative labor. All other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0043] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0044] With the continuous development of display panel preparation technology, people have put forward higher requirements on the performance and quality of display panels. It is hoped that the prepared display panel not only has good quality, but also has good comprehensive performance.

[0045] The prior art usually needs multiple preparation processes to prepare a high-performance display panel. Especially for preparing a display panel with a composite structure, such as preparing a low-temperature polycrystalline oxide thin film transistor and an indium gallium zinc oxide thin film transistor, a large number of etching processes are often required, the preparation process is complex, and the production cost is high.

[0046] The embodiment of the present application provides a display panel to effectively simplify the preparation process of the display panel and prepare a high-performance display panel.

[0047] As shown in FIG. 1, Figure 1 Figure 1 ​A schematic diagram of a film layer structure of a display panel is provided in the embodiment of the present application. The display panel comprises a substrate 100, a shielding layer 132 and a thin film transistor device layer 30. Specifically, the shielding layer 132 is arranged on the substrate 100, and the thin film transistor device layer 30 is arranged above the shielding layer 132. In the embodiment of the present application, the material of the substrate 100 can be a glass substrate, and the material of the shielding layer 132 can be a metal material, preferably Mo, Al or the like. By arranging the metal shielding layer 132 at the bottom of the display panel, the static electricity inside the display panel is shielded, and the performance of the display panel is improved.

[0048] Further, the thin film transistor device layer 30 further comprises a second substrate 101, a buffer layer 102, and a first thin film transistor 11 and a second thin film transistor 12 arranged in the thin film transistor device layer 30.

[0049] Specifically, the second substrate 101 is arranged on the shielding layer 132, and the second substrate 101 completely covers the shielding layer 132. Meanwhile, the second substrate 101 can be a flexible substrate, and the buffer layer 102 is arranged on the second substrate 101. The buffer layer 102 is preferably a polyimide film layer.

[0050] In the embodiment of the present application, the first thin film transistor 11 and the second thin film transistor 12 are arranged in the thin film transistor device layer 30. The second thin film transistor 12 is arranged on one side of the first thin film transistor 11. The first thin film transistor 11 and the second thin film transistor 12 are arranged in the display area of the display panel. Specifically, the first thin film transistor 11 comprises a first active layer 114, a first source electrode 112, a first drain electrode 113, a first gate electrode 115, a first gate electrode 116 and an interlayer dielectric layer arranged between each electrode layer. Correspondingly, the second thin film transistor 12 comprises a second active layer 117, a second source electrode 119, a second drain electrode 120, a second gate electrode 122 and an interlayer dielectric layer arranged between each electrode layer.

[0051] Specifically, the first active layer 114 is arranged on the buffer layer 102, the first gate insulating layer 103 is arranged on the buffer layer 102, and the first gate insulating layer 103 covers the first active layer 114. The first gate electrode 115 is arranged on the first gate insulating layer 103 and corresponds to the first active layer 114. The second gate insulating layer 104 is arranged on the first gate insulating layer 103, and the second gate insulating layer 104 completely covers the first gate electrode 115. Meanwhile, the first gate electrode 116 is arranged on the second gate insulating layer 104 and corresponds to the region above the first gate electrode 115. In this way, the first thin film transistor 11 forms a double-gate structure, so as to effectively improve the performance of the thin film transistor.

[0052] Simultaneously, a passivation layer 105 is disposed on the second gate insulating layer 104 and completely covers the first gate 116. A third gate insulating layer 106 is disposed on the passivation layer 105, a second passivation layer 107 is disposed on the third gate insulating layer 106, and a metal layer is disposed on the second passivation layer 107. In this embodiment of the invention, the metal layer mainly serves as the source / drain electrode and signal line of the thin-film transistor, wherein the source / drain electrode and signal line are all disposed on the second passivation layer 107 and are made of the same material.

[0053] Specifically, the metal layer 125 includes a first source 112 and a first drain 113, which are disposed on the second passivation layer 107 and are correspondingly disposed in the regions on both sides of the first active layer 114.

[0054] The display panel includes a first via 20 and a first via 21. The first source 112 is electrically connected to the first active layer 114 through the first via 20, and the first drain 113 is electrically connected to the first active layer 114 through the first via 21, thereby forming the main structure of the first thin film transistor 11.

[0055] Furthermore, the second thin-film transistor 12 is disposed on one side of the first thin-film transistor 11 and at different heights of the thin-film transistor device layer 30. Specifically, the second active layer 117 of the second thin-film transistor 12 is disposed on the passivation layer 105, the second gate 122 is disposed on the third gate insulating layer 106, and the second passivation layer 107 completely covers the second gate 122.

[0056] Meanwhile, the metal layer 125 also includes a second source 119 and a second drain 120. The second source 119 and the second drain 120 are disposed on the second passivation layer 107 and are disposed in the same layer as the first source 112 and the first drain 113.

[0057] Furthermore, the display panel also includes a second via 23 and a second via 26. The second via 23 and the second via 26 are respectively disposed in the region above the second active layer 117. The second source 119 is electrically connected to one end of the second active layer 117 through the second via 23, and the second drain 120 is electrically connected to the other end of the second active layer 117 through the second via 26. This ultimately forms the structure of the second thin-film transistor 12.

[0058] In the embodiment of the present application, the second active layer 117 is arranged in the region above the first gate 116, and the first thin film transistor 11 is electrically connected with the second thin film transistor 12. Specifically, the second source 119 is electrically connected with the first active layer 114 through the fifth via hole 22. In this way, one side of the second source 119 is electrically connected with the first active layer 114 of the first thin film transistor through the fifth via hole 22, and the other side of the second source 119 is electrically connected with the second active layer 117 of the second thin film transistor through the second via hole 23.

[0059] Further, the display panel further comprises a fourth via hole 24 arranged on one side of the second thin film transistor 12 and close to the binding region 17. A metal layer 125 is arranged in the region corresponding to the fourth via hole 24, and the metal layer 125 is electrically connected with the bottom shielding layer 132 through the fourth via hole 24, thereby effectively shielding the static electricity formed in the thin film transistor, so as to improve the performance of the device.

[0060] Further, the third via hole 25 is further arranged in the binding region 17 on one side of the display region 16 of the display panel. The third via hole 25 penetrates the thin film transistor device layer 30 and exposes the surface of the bottom substrate 100.

[0061] In the embodiment of the present application, the first via hole 20, the first via hole 21, the second via hole 23, the second via hole 26, the third via hole 25, the fourth via hole 24 and the fifth via hole 22 are all arranged as stepped holes, and all the above via holes are formed through the same photo mask etching. In this way, the multiple via hole structures in the display panel are simplified to one-time photo mask process, so as to reduce the preparation process of the display panel and reduce the production cost.

[0062] Specifically, the fourth via hole 24 and the third via hole 25 are arranged as deep holes, and the first via hole 20, the first via hole 21, the second via hole 23, the second via hole 26 and the fifth via hole 22 are arranged as shallow hole structures. Among the stepped holes corresponding to the above via holes, at least one step platform is located on the same film layer and at the same height. Preferably, the first step platform corresponding to the above via holes is arranged above the passivation layer 105 film layer.

[0063] As shown in Figure 2 , Figure 2 the via hole structure provided in the embodiment of the present application. Among them, Figure 2The third via hole 25 and the fourth via hole 24 are taken as examples for description. In the embodiment, the third via hole 25 includes a first step platform 241 and a second step platform 242, wherein the first step platform 241 is located above the second step platform 242, and the aperture of the third via hole 25 gradually decreases from the first step platform 241 to the second step platform 242. Correspondingly, the fourth via hole 24 also has the above-mentioned corresponding relationship, and the third via hole is taken as an example for description in the following embodiment.

[0064] In the embodiment, the first step platform 241 is arranged on the passivation layer 105, and the second step platform 242 is arranged in the buffer layer 102 and has a certain distance from the surface of the buffer layer 102. That is, the second step platform 242 is etched to the inside of the buffer layer 102. In the embodiment, the width of the horizontal platform on both sides of each step platform is set to 0.5-2 um, so as to ensure the connection effect of the electrode in the via hole.

[0065] When the first step platform 241 in the third via hole 25 and the corresponding first step platform 241 in the fourth via hole 24 are etched, they are formed by the same etching process. When the second step platform 242 in the third via hole 25 and the corresponding second step platform 242 in the fourth via hole 24 are etched, they are also formed by the same etching process, so that the first step platform 241 is arranged in the same layer as the second active layer and has the same height as the second active layer.

[0066] Specifically, the distance between the opening surface of the third via hole 25 and the first step platform 241 is h1, and the distance between the first step platform 241 and the second step platform 242 is h2. Meanwhile, in the fourth via hole 24, the distance between the second step platform 242 and the upper surface of the shielding layer 132 is h3, and in the third via hole 25, the distance between the second step platform 242 and the exposed surface of the buffer layer 102 is h4, that is, the surface of the buffer layer 102 is the third step platform 243. In the embodiment, in order to ensure the performance of the display panel, the height of h1 is set to 0.5-2 um, the height of h2 is set to 0.5-2 um, the height of h3 is set to 0.5-2 um, and the height of h4 is set to 0.5-2 um.

[0067] Further, as shown in FIG. 6, the third step platform 243 is arranged in the buffer layer 102, and the fourth step platform 244 is arranged on the shielding layer 132. Figure 3 Figure 3 ​​​​A local film layer structure schematic diagram corresponding to the first via hole provided by the embodiment of the present application is shown in the figure. In the embodiment of the present application, the first via hole 20, the first via hole 21 and the fifth via hole 22 have the same height and are all step holes, and the first via hole 20, the first via hole 21 and the fifth via hole 22 are formed by etching through the same photomask, so the structures of the above-mentioned via holes can be set to be the same. Taking the first via hole 20 as an example for description. Correspondingly, the height h1 thereof can be set to be the same height as the height h1 in the third via hole. And the distance h2 between the first step platform 241 of the first via hole 20 and the surface of the first active layer 114 is set to be Therefore, the comprehensive performance of the display panel is effectively improved.

[0068] Further, the display panel further comprises a first planarization layer 150, the first planarization layer 150 is arranged on the passivation layer 105 and covers the metal layer 125, and the first planarization layer 150 fills the third via hole 25. And an electrode connection layer 111 and a second planarization layer 108, the electrode connection layer 111 is arranged on the first planarization layer 150, the second planarization layer 108 is arranged on the first planarization layer 150, and a cathode layer 110 electrically connected with the electrode connection layer 111 and a dielectric layer 109 arranged on the second planarization layer 108.

[0069] Further, the embodiment of the present application further provides a preparation method of the display panel. Specifically, as shown in Figure 8 , the preparation method comprises the following steps: Figure 8 A preparation flow diagram of the display panel provided by the embodiment of the present application is shown in the figure. The preparation method comprises the following steps:

[0070] S100: providing a substrate, and preparing a shielding layer on the substrate;

[0071] S101: preparing a thin film transistor device layer on the shielding layer, and the thin film transistor device layer comprises a first thin film transistor and a second thin film transistor;

[0072] S102: preparing a photoresist on the thin film transistor device layer, performing a photo mask treatment on the photoresist and forming different depth openings in the areas corresponding to the source / drain electrodes of the thin film transistors, and forming a fourth opening and a third opening at the positions corresponding to the shielding layer and the binding area respectively;

[0073] S103: etching the thin film transistor device layer, and etching to form a third via hole and a fourth via hole and a corresponding first step platform at the positions corresponding to the third opening and the fourth opening;

[0074] S104: etching the openings with different depths in the source / drain corresponding region, and etching the thin film transistor device layer at the corresponding openings at the same time, forming the first via, the fifth via, and etching to the first step platform height corresponding to each via, and etching the third via and the fourth via to the second step platform position;

[0075] S105: etching the photoresist and the corresponding film layer in each via to form the second via, and etching the first via, the second via and the fifth via to the active layer surface, etching the third via to the substrate surface, and etching the fourth via to the shielding layer surface;

[0076] S106: preparing a metal layer in the corresponding via, and preparing a planarization layer on the metal layer, and making the planarization layer fill the third via;

[0077] S107: preparing a pixel electrode on the planarization layer and packaging, completing the preparation of the display panel.

[0078] Specifically, as shown in Figures 4-7 , Figures 4-7 The preparation process of the display panel provided by the embodiment of the present application is shown in the corresponding film layer structure diagram. First, a substrate 100 is provided, a metal shielding layer 132 is prepared on the substrate 100, and a thin film transistor device layer 30 is prepared and formed on the shielding layer 132.

[0079] In the embodiment of the present application, the thin film transistor device layer is provided with a first thin film transistor 11 and a second thin film transistor 12, wherein the first active layer 114 in the first thin film transistor 11 is a polycrystalline silicon oxide semiconductor material, and the second active layer 117 in the second thin film transistor 12 is an indium gallium zinc oxide semiconductor material.

[0080] The thin film transistor device layer 30 is also provided with a gate layer and an interlayer dielectric layer, which can be seen in detail in the film layer structure of the display panel in Figure 1 , which will not be described in detail here. After the setting is completed, a photoresist 400 is prepared on the thin film transistor device layer.

[0081] For details, see Figure 4The photoresist 400 is then photomasked to create openings of varying depths. Specifically, a first opening is formed above the source / drain region corresponding to the first thin-film transistor 11, corresponding to the subsequently formed first vias 20 and 21. A second opening is formed above the source / drain region corresponding to the second thin-film transistor 12, corresponding to the subsequently formed second vias 23 and 26. A fifth opening is also formed, corresponding to the subsequently formed fifth via 22. Furthermore, a third via 25 and a fourth via 24 are formed on one side of the thin-film transistor device layer.

[0082] Specifically, the third via 25 and the fourth via 24 penetrate the photoresist 400. Meanwhile, the opening depths of the first and fifth openings can be the same, and both are greater than the opening depth of the second opening.

[0083] In this embodiment of the invention, when processing the photoresist 400 with a photomask, a semi-mask process is used to form photoresist structures with openings of different depths as shown in the figure.

[0084] After the photoresist mask is processed, other etching processes are carried out. See details. Figure 5 As shown, the film layers in the corresponding areas of the third via 25 and the fourth via 24 are etched. Specifically, the film layers can be etched using a plasma gas etching process. During this etching process, the third via 25 and the fourth via 24 are etched to the position of the first step platform 241. In this embodiment of the invention, the first step platform 241 is located at the same height as the second active layer of the second thin-film transistor 12, that is, the first step platform 241 is located on the third gate insulating layer 106.

[0085] After the first step platform 241 is etched, the film layer is further processed. See details. Figure 6 As shown, the opening on the photoresist 400 in the corresponding region of the first thin-film transistor 11 is etched, so that... Figure 4 In this region, a shallow opening is formed on the photoresist layer to form a via, and the thin film transistor device layer is etched at the corresponding via to form the first via 20, the first via 21, and the fifth via 22.

[0086] In this embodiment of the invention, the vias are etched in the same etching process, and the first via 20, the first via 21 and the fifth via 22 are all etched to the same height as the first step platform 241, that is, the vias are etched onto the third gate insulating layer 106.

[0087] Meanwhile, the third via hole 25 and the fourth via hole 24 continue to be etched downward. Specifically, the third via hole 25 and the fourth via hole 24 are etched from the first step platform 241 to the second step platform 242. In the embodiment of the present application, the second step platform 242 is located in the buffer layer 102, i.e., the second step platform 242 has a height difference with the surface of the buffer layer 102. The first step platform 241 and the second step platform 242 and the height difference can refer to the specific values in the embodiment of the present application. Figures 2-3

[0088] After the etching, the first step platform 241 corresponding to the first via hole 20, the first via hole 21, the fifth via hole 22, the third via hole 25 and the fourth via hole 24 is located at the same height.

[0089] As shown in FIG. 6, the film layers are further processed. Further, the opening corresponding to the second thin film transistor 12 is etched, and the photoresist 400 in the region forms a via hole corresponding to the second via hole 23 and the second via hole 26. After the via hole is formed, the film layers in the thin film transistor device layer are etched based on the via hole. Figure 7

[0090] Specifically, the first via hole 20, the first via hole 21, the second via hole 23, the second via hole 26, the fifth via hole 22 and the third via hole 25 are etched by using the plasma gas etching method. In the embodiment of the present application, the first via hole 20, the first via hole 21 and the fifth via hole 22 are etched from the first step platform 241 to the first active layer 114 of the first thin film transistor, and the second via hole 23 and the second via hole 26 are etched from the surface of the film layer to the second active layer of the second thin film transistor 12, thereby forming the via hole structure corresponding to the source / drain of each thin film transistor.

[0091] Meanwhile, the third via hole 25 and the fourth via hole 24 continue to be etched, the third via hole 25 is etched from the second step platform 242 to the surface of the substrate 100, and the fourth via hole 24 is etched from the second step platform 242 to the surface of the shielding layer 132.

[0092] Finally, the etching of all the via hole structures in the display panel is completed. In the embodiment of the present application, only one photomask processing is needed, which effectively saves the number of photomasks and the process of exposure and etching, thereby simplifying the preparation process and reducing the production cost of the display panel.

[0093] ​​Further, after each via hole etching is completed, a metal layer is prepared in the first via hole 20, the first via hole 21, the second via hole 23, the second via hole 26, the fifth via hole 22 and the fourth via hole 24 respectively, so as to form the source / drain electrode of the thin film transistor, and meanwhile, the first planarization layer is prepared on the metal layer and the third via hole 25 is filled with the first planarization layer. Then, other film layers, such as the pixel electrode and the like, are prepared on the first planarization layer, and packaging is performed, so as to finally form the structure of the display panel provided in the embodiment of the present application.

[0094] The display panel and the preparation method of the display panel provided in the embodiment of the present application are described in detail above, and the principle and the implementation manner of the present application are described by applying specific examples in this paper, and the above embodiment is only used for helping to understand the technical scheme of the present application and the core idea thereof; it should be understood by those skilled in the art that the technical scheme recorded in each of the above embodiments can be modified or some technical features can be replaced equivalently; and the modification or the replacement does not make the essence of the corresponding technical scheme deviate from the scope of the technical scheme of each embodiment of the present application.

Claims

1. A display panel, characterized by, The display panel includes a display area and a binding area disposed on one side of the display area. Substrate; A shielding layer disposed on the substrate; A thin-film transistor device layer disposed on the shielding layer, the thin-film transistor device layer including a first thin-film transistor disposed in the display area and a second thin-film transistor electrically connected to the first thin-film transistor, the first source / drain of the first thin-film transistor being electrically connected to the first active layer through a first via, and the second source / drain of the second thin-film transistor being electrically connected to the second active layer through a second via; The display panel further includes a third via located in the bonding area. The third via penetrates the film layer between the second source / drain and the substrate. The third via penetrates the thin film transistor device layer and exposes the surface of the substrate at the bottom. The first via, the second via, and the third via are all configured as stepped vias, and the distance between the top of the first via and the third via and the first step platform corresponding to the stepped via is the same. The display panel further includes a metal layer and a fourth via. The metal layer is disposed between the second thin-film transistor and the third via, and the metal layer is electrically connected to the shielding layer through the fourth via. The fourth via is a stepped via, and the number of steps of the stepped via is the same as the number of steps of the third via. The stepped platform in the fourth via is at the same height as the stepped platform in the third via.

2. The display panel of claim 1, wherein, The third via includes a first step platform and a second step platform. The first step platform is located above the second step platform, and the diameter of the third via gradually decreases from the first step to the second step platform.

3. The display panel of claim 2, wherein, The distance between the top of the third via and the first step platform is less than the distance between the first step platform and the second step platform, and the distance between the first step platform and the second step platform is greater than the distance between the second step platform and the bottom of the third via.

4. The display panel of claim 2, wherein, The first step platform is disposed on the same layer as the second active layer of the second thin film transistor.

5. The display panel of claim 1, wherein, The first via, the second via, the third via, and the fourth via are formed by the same etching process.

6. The display panel of claim 1, wherein, The metal layer, the first source / drain electrode, and the second source / drain electrode are located on the same film layer.

7. The display panel of claim 1, wherein, At least one stepped platform in the stepped holes corresponding to the first via, the second via, and the third via is located on the same film layer.

8. The display panel of claim 1, wherein, The diameter of the third via is larger than the diameters of the first via and the second via.

9. The display panel of any one of claims 1-8, wherein, The opening surfaces of the first through hole, the second through hole, the third through hole, and the fourth through hole are all at the same distance from the first step platform of the stepped hole.

10. The display panel of claim 9, wherein, A distance between an opening surface of the first via, the second via, the third via, and the fourth via to the first step terrace of the stepped via is 11. The display panel of claim 1, wherein, The first active layer is a polycrystalline silicon oxide semiconductor, and the second active layer is an indium gallium zinc oxide semiconductor.

12. A method for manufacturing a display panel, characterized by, Includes the following steps: A substrate is provided, and a shielding layer is formed on the substrate; A thin-film transistor device layer is fabricated on the shielding layer, the thin-film transistor device layer comprising a first thin-film transistor and a second thin-film transistor; A photoresist is fabricated on the thin-film transistor device layer. The photoresist is processed and openings of different depths are formed in the regions corresponding to the source / drain of the thin-film transistor. A fourth opening and a third opening are formed at the corresponding positions of the shielding layer and the bonding region, respectively. The thin-film transistor device layer is etched to form a third via and a fourth via, as well as a corresponding first step platform, at the positions corresponding to the third opening and the fourth opening. Etch openings of different depths in the corresponding regions of the source / drain, and simultaneously etch the thin-film transistor device layer at the corresponding openings to form the first via and the fifth via, and etch to the height of the first step platform corresponding to each via, and etch the third via and the fourth via to the position of the second step platform; The photoresist and the corresponding film layers in each via are etched to form a second via. The first via, the second via, and the fifth via are etched to the surface of the active layer. The third via is etched to the surface of the substrate. The fourth via is etched to the surface of the shielding layer. The third and fourth vias are both stepped vias. The number of steps in the stepped via corresponding to the fourth via is the same as the number of steps in the third via. The stepped platform in the fourth via is at the same height as the stepped platform in the third via. A metal layer is prepared in each corresponding via, and a planarization layer is prepared on the metal layer. The metal layer is electrically connected to the shielding layer through the fourth via, and the planarization layer fills the third via. Pixel electrodes are fabricated on the planarization layer and then encapsulated to complete the fabrication of the display panel.

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