Partially silicided non-volatile memory devices and integration schemes

Abstract

This invention relates to partially silicided non-volatile memory devices and integration schemes. A non-volatile memory device is provided. The non-volatile memory device includes an active region, an n-well region, and an isolation region separating the active region and the n-well region. A floating gate may be disposed. The floating gate may be disposed over a portion of the active region and a first portion of the n-well region. A first doped region in the active region may be laterally shifted relative to the floating gate on a first side, and a second doped region in the active region may be laterally shifted relative to the floating gate on a second side opposite to the first side. A contact may be disposed over the n-well region, wherein the contact may be laterally shifted relative to a first corner of the floating gate above the first portion of the n-well region. A silicide repulsion layer may be disposed at least partially over the floating gate.

Description

Technical Field

[0001] The disclosed embodiments relate generally to semiconductor memory devices, and more particularly to partially silicided nonvolatile memory devices with improved data retention and good contact resistance. Background Art

[0002] Even if the power is turned off, the non-volatile memory device will retain the stored data. Multi-time programmable (MTP) non-volatile memory includes electrically erasable programmable read-only memory (EEPROM) and flash EEPROM. The memory device includes a memory transistor having a gate electrode separated from an active area by a dielectric layer. The drain region in the active area can be adjacent to a first side of the gate electrode of the memory transistor, and the source region in the active area can be adjacent to a second side of the gate electrode opposite to the drain region. The gate electrode can be a floating gate. An n-well capacitor coupled to the gate electrode can be used to bias the floating gate. The n-well capacitor can include a portion of the floating gate located above the n-well capacitor as a first electrode, and include an n-well region as a second electrode. A contact can be provided above the n-well region to couple the n-well capacitor to an input terminal.

[0003] A silicide layer may be formed over a floating gate, over a source region, over a drain region, and over an n-well region of an n-well capacitor to reduce the contact resistance of a non-volatile memory device. Forming a silicide layer over a portion of a floating gate near a contact of an n-well capacitor may result in a leakage path in the non-volatile memory device, resulting in poor data retention. Non-volatile memory devices without a silicide layer have improved data retention, but the device contact resistance is high and the device performance is poor. Therefore, an improved non-volatile memory device is needed to overcome the above challenges. Summary of the invention

[0004] In one aspect of the present disclosure, a nonvolatile memory device is provided. The device includes an active region, an n-well region, and an isolation region separating the active region from the n-well region. A floating gate is provided, and the floating gate is arranged above a portion of the active region and a first portion of the n-well region. A first doped region in the active region is laterally displaced relative to the floating gate on a first side. A second doped region in the active region is laterally displaced relative to the floating gate on a second side opposite to the first side. A contact is arranged above the n-well region, wherein the contact is laterally displaced relative to a first corner of the floating gate above the first portion of the n-well region. A silicide exclusion layer is at least partially arranged above the floating gate.

[0005] In another aspect of the present disclosure, a nonvolatile memory device is provided. The device includes a first active region, a second active region, an n-well region between the first active region and the second active region, and an isolation region separating the first active region, the second active region and the n-well region. A first floating gate and a second floating gate are arranged above a portion of the first active region, and a third floating gate and a fourth floating gate are arranged above a portion of the second active region, wherein each floating gate is arranged above a side of the n-well region. A first doped region in each active region is laterally displaced relative to each floating gate on a first side. A second doped region in each active region is laterally displaced relative to each floating gate on a second side opposite to the first side. A contact is arranged above the n-well region, wherein the contact is laterally displaced relative to a first corner of each floating gate above the side of the n-well region. A silicide repelling layer is at least partially arranged above each floating gate, wherein the silicide repelling layer covers the first corner of each floating gate above the side of the n-well region, wherein the first corner is close to the contact above the n-well region.

[0006] In another aspect of the present disclosure, a method for manufacturing a memory device is provided. The method includes providing an active region, an n-well region, and an isolation region separating the active region from the n-well region. A floating gate arranged above a portion of the active region and above a first portion of the n-well region may be provided. A first doped region in the active region that is laterally displaced relative to the floating gate on a first side may be provided, and a second doped region in the active region that is laterally displaced relative to the floating gate on a second side opposite to the first side may be provided. A silicide repelling layer at least partially located above the floating gate may be provided. A contact may be provided above the n-well region, wherein the contact is laterally displaced relative to a first corner of the floating gate above the first portion of the n-well region.

[0007] Many advantages can be provided in the embodiments described below. Embodiments provide a non-volatile memory device with improved data retention and good contact resistance while maintaining device size. A spacer structure can be formed at the sidewall of the floating gate to isolate the floating gate from the n-well region and the active area. The spacer structure may not be perfectly formed at the corner of the floating gate. The silicide layer formed above the floating gate can form a current leakage path from the spacer structure at the corner of the floating gate to the n-well region. Therefore, the silicide repelling layer above the first corner of the floating gate close to the n-well contact prevents the formation of a current leakage path due to the silicide process. The silicide repelling layer acts as an additional insulating layer to electrically isolate the floating gate from the n-well region and the n-well contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments will be better understood by reading the following detailed description in conjunction with the accompanying drawings:

[0009] Figure 1A is a top view of a nonvolatile memory device according to an embodiment of the present disclosure.

[0010] Figure 1B According to the embodiment of the present disclosure Figure 1A A cross-sectional view of an n-well capacitor taken along section line AA' of the nonvolatile memory device is shown.

[0011] Figure 1C According to the embodiment of the present disclosure Figure 1A The nonvolatile memory device is shown as a cross-sectional view of a memory transistor taken along a section line BB'.

[0012] Figure 1D According to the embodiment of the present disclosure Figure 1A A cross-sectional view of a contact of an n-well capacitor taken along section line CC' of the nonvolatile memory device is shown.

[0013] FIG. 2A to FIG. 4A Some embodiments of the present disclosure are shown Figure 1B The manufacturing process flow of the n-well capacitor is shown.

[0014] Figures 2B to 4B Some embodiments of the present disclosure are shown Figure 1C The manufacturing process flow of the memory transistor is shown.

[0015] Figure 5A is a top view of a nonvolatile memory device according to another embodiment of the present disclosure.

[0016] Figure 5B According to another embodiment of the present disclosure Figure 5A A cross-sectional view of an n-well capacitor taken along section line DD' of the nonvolatile memory device is shown.

[0017] Fig. 6A is a top view of a nonvolatile memory device according to another embodiment of the present disclosure.

[0018] Figure 6B According to another embodiment of the present disclosure Fig. 6A The nonvolatile memory device is shown as a cross-sectional view of a memory transistor taken along a section line EE'.

[0019] Fig. 7A is a top view of a nonvolatile memory device according to another embodiment of the present disclosure.

[0020] Figure 7BAccording to another embodiment of the present disclosure Fig. 7A The nonvolatile memory device is shown as a cross-sectional view of a memory transistor taken along the section line GG'.

[0021] Fig. 8A is a top view of a nonvolatile memory device according to another embodiment of the present disclosure.

[0022] Figure 8B According to another embodiment of the present disclosure Fig. 8A The nonvolatile memory device is shown as a cross-sectional view of a memory transistor taken along the section line HH'.

[0023] For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and specific descriptions and details of known features and technologies may be omitted to avoid unnecessarily obscuring the discussion of the embodiments of the described devices. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the sizes of some elements in the drawings may be enlarged relative to other elements to help improve the understanding of the embodiments of the device. The same reference numerals in different drawings represent the same elements, and similar reference numerals may, but do not necessarily, represent similar elements. DETAILED DESCRIPTION

[0024] The following detailed description is exemplary in nature and is not intended to limit the device or the application and uses of the device. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the device or the following detailed description.

[0025] Figure 1A is a top view of a nonvolatile memory device 100 according to an embodiment of the present disclosure. Figure 1A, the nonvolatile memory device 100 includes a first active region 108a, a second active region 108b, an n-well region 110 between the first active region 108a and the second active region 108b, and an isolation region 106 separating the first active region 108a, the second active region 108b, and the n-well region 110. The isolation region 106 may be formed in the substrate 102. A first floating gate 182a and a second floating gate 182b may be disposed over a portion of the first active region 108a. A third floating gate 182c and a fourth floating gate 182d may be disposed over a portion of the second active region 108b. Each of the floating gates 182a, 182b, 182c, and 182d may be disposed over a side portion of the n-well region 110. The first doped region 152 in each active region 108a and 108b may be laterally displaced relative to each floating gate 182a, 182b, 182c, and 182d, respectively, at a first side 190. The second doped region 156 in each active region 108a and 108b may be laterally displaced relative to each floating gate 182a, 182b, 182c, and 182d, respectively, at a second side 192 opposite to the first doped region 152 and the first side 190. Although not shown for simplicity, an interlayer dielectric (ILD) layer may be formed over the top surface of each active region 108a and 108b, the n-well region 110, each floating gate 182a, 182b, 182c, and 182d, and over the isolation structure 106. A contact 158 ​​may be disposed over the first doped region 152 for connection to an external terminal. A contact 160 may be disposed over the second doped region 156 for connection to an external terminal. The contact 150 may be disposed over the n-well region 110, whereby the contact 150 may be laterally and diagonally shifted relative to the first corner 138 of each floating gate 182a, 182b, 182c, and 182d over the side of the n-well region 110. The contacts 150, 158, and 156 may be disposed in the interlayer dielectric layer. The silicide repelling layer 186 may be at least partially disposed over each floating gate 182a, 182b, 182c, and 182d. In one embodiment, the silicide repelling layer 186 may cover the first corner 138 of each floating gate 182a, 182b, 182c, and 182d over the side of the n-well region 110. The first corner 138 of each floating gate 182a, 182b, 182c, and 182d may be close to the contact 150 over the n-well region 110. The silicide repelling layer 186 may extend over the central portion 128 of the n-well region 110 adjacent to the side of the n-well region below each floating gate 182a, 182b, 182c, and 182d. The central portion 128 of the n-well region is illustrated as a dashed outline. In one embodiment, the silicide repelling layer 186 may surround the contact 150. In another embodiment, the silicide repelling layer 186 may extend under the contact 150.In one embodiment, the first corner 138 of each floating gate 182a, 182b, 182c, and 182d may be faceted. In another embodiment, the first corner 138 may be rounded. The term "silicide repelling layer" may refer to a dielectric or insulating material layer disposed above a semiconductor layer to prevent metal silicide from forming on the semiconductor layer.

[0026] Each floating gate 182a, 182b, 182c and 182d located above each active region 108a and 108b, respectively, provides a gate of a memory transistor. The first doped region 152 can be a source of a memory transistor, and the second doped region 156 can be a drain of a memory transistor. Each floating gate 182a, 182b, 182c and 182d and the n-well region 110 provide an n-well capacitor. The contact 150 provides a contact that connects the n-well capacitor to an external terminal. The term "floating gate" can refer to a gate electrode that is electrically isolated from an input terminal but can be capacitively coupled to an input terminal. During a read operation, no DC current flows from the input terminal to the floating gate.

[0027] The arrangement of the silicide repelling layer 186 as described above provides an additional insulating layer between each floating gate 182a, 182b, 182c, and 182d, the central portion 128 of the n-well region 110, and the contact 150. In addition, the arrangement of the silicide repelling layer 186 according to an aspect of the present invention eliminates or at least reduces the possibility of a leakage path being formed between the floating gates 182a, 182b, 182c, and 182d, the n-well region 110, and the contact 150, particularly where a silicide layer would otherwise be formed at the first corner 138 of each floating gate 182a, 182b, 182c, and 182d. The silicide repelling layer 186 protects a portion of the floating gate 182a, 182b, 182c, or 182d below the layer 186 from subsequent chemical cleaning, thereby preventing silicide from invading the floating gate 182a, 182b, 182c, or 182d through the surrounding insulating layer (e.g., spacer structure). This results in improved data retention of the nonvolatile memory device 100. According to another aspect of the present invention, the silicide layer disposed over the doped region in the active area not covered by the silicide repelling layer 186, a portion of the n-well region, and a portion of each floating gate provides good contact resistance for the nonvolatile memory device 100.

[0028] Figure 1B According to the embodiment of the present disclosure Figure 1A FIG. 1 is a cross-sectional view of an n-well capacitor taken along a section line AA′ of the nonvolatile memory device 100. Figure 1B, the silicide repelling layer 186 may be at least partially disposed over the first floating gate 182a, over the central portion 128 of the n-well region 110 adjacent to the side portion 120a of the n-well region 110 below the first floating gate 182a, and over the spacer structure 162 adjacent to the sidewall of the first floating gate 182a. The silicide repelling layer 186 may include silicon dioxide, silicon nitride, hafnium oxide (HfO2), or any other suitable dielectric material.

[0029] The silicide layer 176 may be disposed over a portion 116a of the first floating gate 182a and adjacent to the silicide repelling layer 186. The silicide layer 178 may be disposed over an edge portion 132 of the n-well region 110 adjacent to the portion 116a of the first floating gate 182a. The spacer structure 162 may separate the silicide layers 176 and 178. In one embodiment, the central portion 128 and the edge portion 132 of the n-well region 110 may be n+ doped regions. The isolation structure 106 may be disposed adjacent to the edge portion 132 of the n-well region 110. The gate dielectric layer 180 may be disposed between the first floating gate 182a and the n-well region 110.

[0030] Figure 1C According to the embodiment of the present disclosure Figure 1A FIG. 1 is a cross-sectional view of a memory transistor taken along a section line BB′ of the nonvolatile memory device 100. Figure 1C , a silicide layer 176 may be disposed over a portion 116a of a first floating gate 182a. A spacer structure 162 may be disposed over a sidewall of the first floating gate 182a. A silicide layer 168 may be disposed over a first doped region 152 in the first active region 108a, and a silicide layer 170 may be disposed over a second doped region 156 in the first active region 108a. A gate dielectric layer 180 may be disposed between the first floating gate 182a and the first active region 108a. Although not shown, contacts 158 and 160 may be formed over the silicide layers 168 and 170, respectively, for connection to an external input terminal.

[0031] Figure 1D According to the embodiment of the present disclosure Figure 1A FIG. 1 is a cross-sectional view of a contact 150 of an n-well capacitor taken along a section line CC′ of the nonvolatile memory device 100. Figure 1D , a silicide repelling layer 186 may be disposed over the central portion 128 of the n-well region 110. An interlayer dielectric (ILD) layer 196 may be disposed over the silicide repelling layer 186, and a contact 150 may be disposed in the interlayer dielectric layer 196 and over the central portion 128 of the n-well region 110. A lower portion of the contact 150 may penetrate the silicide repelling layer 186 to contact the central portion 128 of the n-well region 110.

[0032] FIG. 2A to FIG. 4B 1 shows various steps of a manufacturing process of a semiconductor device 100 according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, Figure 2A After forming the isolation structure 106 and the n-well region 110, Figure 1A The nonvolatile memory device 100 is shown as a cross-sectional view of a partially completed n-well capacitor taken along the section line AA'. Figure 2B After forming the first active region 108a in the substrate 102, Figure 1A The nonvolatile memory device 100 is shown as a cross-sectional view of a partially completed memory transistor taken along section line BB′.

[0033] First, a semiconductor substrate 102 is provided. The substrate 102 may be made of a suitable semiconductor material, such as silicon, or any other suitable semiconductor. An isolation structure 106 may be first formed in the substrate 102, Figure 2A A portion of substrate 102 is shown. The formation of isolation structure 106 may include forming an opening in substrate 102 by a standard photolithography process and a wet or dry etching process. The standard photolithography process may include depositing a layer of photoresist material over the top surface of substrate 102, followed by exposure and development to form a suitable photoresist pattern. A wet or dry etching process may be used to remove a portion of substrate 102 not covered by the photoresist pattern, thereby forming an opening in substrate 102. A layer of a suitable dielectric material, such as silicon dioxide (SiO2), may be deposited in the opening. A suitable planarization process, such as chemical mechanical planarization (CMP), may be used to remove a portion of the silicon dioxide layer from the top surface of substrate 102, leaving another portion of the silicon dioxide layer in the opening, thereby forming isolation structure 106. An n-well region 110 may be formed in substrate 102 adjacent to isolation structure 106. The formation of the N-well region 110 may include doping the substrate 102 with a suitable dopant, such as phosphorus (P) or arsenic (As) or any other suitable n-type dopant, to form the n-well region 110 .

[0034] Reference now Figure 2B , a first active region 108a surrounded by an isolation structure 106 is formed in the substrate 102, as shown Figure 1A The formation of the active region 108a may include doping a portion of the substrate 102 with a suitable dopant (eg, boron (B) or any other suitable p-type dopant) to form the first active region 108a. The second active region 108b may also be formed at this time.

[0035] Figure 3A is along Figure 1AThe nonvolatile memory device 100 is shown as a cross-sectional view of a partially completed n-well capacitor taken along the section line AA'. Figure 3B is in the subsequent stages of the manufacturing process along Figure 1A The nonvolatile memory device 100 is shown as a cross-sectional view of a partially completed memory transistor taken along section line BB′.

[0036] refer to Figure 3A A suitable dielectric material (e.g., silicon dioxide (SiO2) or any other suitable dielectric material) layer may be formed over the top surface of the n-well region 110 by thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable oxidation or deposition process. An n+ doped polysilicon layer may be deposited over the silicon dioxide layer by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable deposition process. The doped polysilicon and silicon dioxide layers may be patterned by conventional photolithography and wet or dry etching processes to form a first floating gate 182a and a gate dielectric layer 180, respectively. The spacer structure 162 is formed by depositing a suitable dielectric material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or any other suitable dielectric material, and then performing anisotropic etching to form the spacer structure 162, which is formed on the sidewalls of the first floating gate 182a and on the side surfaces of the gate dielectric layer 180. The term "anisotropic etching" may refer to an etching process that is directional in nature.

[0037] refer to Figure 3B The gate dielectric layer 180, the first floating gate 182a and the spacer structure 162 of the memory transistor can be formed respectively with Figure 3A The formation of the gate dielectric layer 180, the first floating gate 182a, and the spacer structure 162 of the n-well capacitor shown is performed simultaneously. The gate dielectric layer 180 can be formed above the top surface of the first active region 108a and below the first floating gate 182a. The spacer structure 162 can be formed on the sidewalls of the first floating gate 182a. Although not shown, an extended doped region can be formed in the upper surface of the first active region 108a, the extended doped region being laterally displaced relative to the first floating gate 182a on a first side and a second side opposite to the first side. The extended doped region can extend slightly laterally offset below the first floating gate 182a.

[0038] Figure 4A is along Figure 1A The nonvolatile memory device 100 is shown as a cross-sectional view of a partially completed n-well capacitor taken along the section line AA'. Figure 4B is in the subsequent stages of the manufacturing process along Figure 1A The nonvolatile memory device 100 is shown as a cross-sectional view of a partially completed memory transistor taken along section line BB′.

[0039] refer to Figure 4A The formation of the central portion 128 of the n-well region 110 and the edge portion 132 of the n-well region 110 includes doping the n-well region 110 with a suitable n-type dopant (e.g., phosphorus (P) or arsenic (As) or any other suitable n-type dopant) to form an n+ doped region adjacent to the first floating gate 182a, thereby forming the central portion 128 of the n-well region 110 and the edge portion 132 of the n-well region 110. The formation of the silicide repelling layer 186 may include depositing a suitable dielectric material (e.g., silicon dioxide (SiO2)) layer over the top surface of the first floating gate 182a, over the spacer structure 162 adjacent to the sidewall of the first floating gate 182a, and over the top surface of the central portion 128 of the n-well region 110 by a suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or any other suitable deposition process. The silicon dioxide layer may be patterned using conventional photolithography processes and wet or dry etching processes to leave a portion of the silicon dioxide layer over at least a portion of the top surface of the first floating gate 182a, over the spacer structure 162 adjacent to the sidewall of the first floating gate 182a, and over the top surface of the central portion 128 of the n-well region 110, thereby forming a silicide repelling layer 186. A portion 116a of the first floating gate 182a adjacent to the silicide repelling layer 186 and an edge portion 132 of the n-well region 110 may be exposed after patterning the silicon dioxide layer.

[0040] refer to Figure 4B The formation of the first doping region 152 and the second doping region 156 of the memory transistor can be related to Figure 4A The formation of the center portion 128 of the n-well region 110 and the edge portion 132 of the n-well region 110 of the illustrated n-well capacitor is performed simultaneously.

[0041] Return to reference Figure 1B, a silicide layer 176 may be formed over a portion 116a of the first floating gate 182a, and a silicide layer 178 may be formed over an edge portion 132 of the n-well region 110. The formation of the silicide layers 176 and 178 may include depositing a suitable metal layer, such as cobalt, titanium, nickel (Ni), or any other suitable metal layer, over a top surface of a portion 116a of the first floating gate 182a and over a top surface of the edge portion 132 of the n-well region 110. The silicide layer may be formed over a portion 116a of the first floating gate 182a and over an edge portion 132 of the n-well region 110 using a suitable heating process, such as furnace annealing, rapid thermal annealing, laser heating, or any other suitable heating process. The unreacted cobalt layer may be removed to leave a silicide layer over a portion 116a of the first floating gate 182a and over an edge portion 132 of the n-well region 110, thereby forming silicide layers 176 and 178, respectively.

[0042] Figure 1C FIG. 1 shows a schematic diagram of a process for forming silicide layers 176, 168, and 170 according to an embodiment of the present disclosure. Figure 1A The cross-sectional view of the memory transistor of the nonvolatile memory device 100 is taken along the section line BB'. Return to Reference Figure 1C The formation of the silicide layers 176, 168, and 170 over a portion 116a of the first floating gate 182a of the memory transistor, over the first doped region 152, and over the second doped region 156 may be related to Figure 1B The formation of silicide layers 176 and 178 of the n-well capacitor is shown to be performed simultaneously.

[0043] Return to reference Figure 1A Although not shown for simplicity, an interlayer dielectric (ILD) layer 196 may be formed over the top surface of each active region 108a and 108b, the n-well region 110, each floating gate 182a, 182b, 182c, and 182d, and over the isolation structure 106. The formation of the interlayer dielectric (ILD) layer 196 is well known in the art and will not be described in further detail. An opening may be formed in the interlayer dielectric (ILD) layer 196 over the central portion 128 of the n-well region 110, over the first doped region 152 in each active region 108a and 108b, and over the second doped region 156 by conventional photolithography processes and wet or dry etching. Suitable conductive materials, such as tungsten (W), copper (Cu), may be deposited in the openings and planarized by a suitable planarization process (e.g., chemical mechanical planarization (CMP)) to leave a tungsten layer in the openings, thereby forming contacts 150, 158, and 160, respectively.

[0044] Figure 5A A top view of a nonvolatile memory device 200 according to another embodiment of the present disclosure is shown. Figures 1A to 1D The same reference numerals in Figure 5A and Figure 5B The same features as Figure 1A In contrast to the illustrated nonvolatile memory device 100, the nonvolatile memory device 200 shows a silicide repelling layer 286 that completely covers a portion of each floating gate 182a, 182b, 182c, and 182d over the side of the n-well region 110. The silicide repelling layer 286 may cover a first corner 138 and a second corner 136 opposite the first corner 138 of each floating gate 182a, 182b, 182c, and 182d, such that the first corner 138 and the second corner 136 of each floating gate 182a, 182b, 182c, and 182d are located over the side of the n-well region 110. The silicide repelling layer may also extend over a central portion 228 of the n-well region 110 adjacent to the side of the n-well region 110 below each floating gate 182a, 182b, 182c, and 182d. The central portion 228 of the N-well region 110 is shown as a dashed outline. The first active region 108a and the second active region 108b, the floating gates 182a, 182b, 182c and 182d, the first doped region 152 and the second doped region 156, the contacts 150, 158 and 160, and the isolation structure are shown. Figure 1A Same as shown.

[0045] In one embodiment, the silicide repelling layer 286 may surround the contact 150. In another embodiment, the silicide repelling layer 286 may extend under the contact 150. The nonvolatile memory device 200 may provide improved data retention because the silicide repelling layer 286 covers a larger portion of each floating gate 182a, 182b, 182c, and 182d and a larger portion of the n-well region 110.

[0046] Figure 5B According to the embodiment of the present disclosure Figure 5A FIG. 2 is a cross-sectional view of an n-well capacitor taken along a section line DD′ of the nonvolatile memory device 200. Figure 5B The silicide repelling layer 286 may be disposed over a portion of the first floating gate 182a over the side portion 120a of the n-well region 110 , over the spacer structure 162 adjacent to the sidewall of the first floating gate 182a , and over the central portion 228 of the n-well region 110 .

[0047] The formation of the first active region 108a, the second active region 108b, the n-well region 110, the floating gates 182a, 182b, 182c and 182d, the spacer structure 162, the first doped region 152 and the second doped region 156 is similar to the formation of Figure 2A and Figure 3A as well as Figure 2B , FIG. 3B to FIG. 4B and Figure 1C The process flow of the non-volatile memory device 100 is shown in FIG. Figure 5B , the formation of the central portion 228 of the n-well region 110 is similar to Figure 4A The formation of the central portion 128 of the n-well region is shown. The formation of the silicide repelling layer 286 may include depositing a suitable dielectric material (e.g., silicon dioxide (SiO2)) layer over the first floating gate 182a, over the spacer structure 162, and over the central portion 228 of the n-well region 110. The silicide repelling layer 286 may be formed by patterning the silicon dioxide layer using conventional photolithography and wet or dry etching processes to leave a portion of the silicon dioxide layer at least partially over the first floating gate 182a, over the spacer structure 162, and over the central portion 228 of the n-well region 110.

[0048] Fig. 6A is a top view of a nonvolatile memory device 300 according to another embodiment of the present disclosure. Figure 1A and Figure 5A In contrast to the illustrated nonvolatile memory devices 100 and 200, the nonvolatile memory device 300 shows a silicide repelling layer 376 at least partially located over a first floating gate 182a and a second floating gate 182b over a portion of the first active region 108a. The silicide repelling layer 376 may also be at least partially located over a third floating gate 182c and a fourth floating gate 182d over a portion of the second active region 108b, and over the first doped region 152 of each active region 108a and 108b. The first active region 108a and the second active region 108b, the floating gates 182a, 182b, 182c, and 182d, the first doped region 152 and the second doped region 156, the contacts 150, 158, and 160, and the isolation structure are shown in FIG. Figure 1A Same as shown.

[0049] The silicide repelling layer 376 may be at least partially disposed over each floating gate 182a, 182b, 182c, and 182d. The silicide repelling layer 376 may completely cover a portion of each floating gate 182a, 182b, 182c, and 182d over the side of the n-well region 110. The silicide repelling layer 376 may extend over a central portion 328 of the n-well region 110 adjacent to the side of the n-well region 110 under each floating gate 182a, 182b, 182c, and 182d. The central portion 328 of the n-well region 110 is shown as a dotted outline. Although not shown, the silicide repelling layer 376 may extend over an isolation region between each active region 108a and 108b and the n-well region 110.

[0050] Figure 6B According to another embodiment of the present disclosure Fig. 6A The cross-sectional view of the memory transistor of the nonvolatile memory device 300 is taken along the section line EE'. Figure 6B , the silicide repelling layer 376 may be at least partially disposed over the first floating gate 182a, over the spacer structure 162 adjacent to the sidewall of the first floating gate 182a, and over the first doped region 152 of the first active region 108a. The silicide layer 366 may be disposed over a portion 396a of the first floating gate 182a and adjacent to the silicide repelling layer 376. The silicide layer 170 is similar to Figure 1C Silicide layer 170 is shown.

[0051] The fabrication of each active region 108a and 108b, the n-well region 110, each floating gate 182a, 182b, 182c and 182d, the spacer structure 162, the first doping region 152 and the second doping region 156 is similar to Figures 2A to 3A as well as Figure 2B , FIG. 3B to FIG. 4B The manufacturing process flow is shown in Figure 2. Fig. 6A , the formation of the central portion 328 of the n-well region 110 is similar to Figure 5B The formation of the central portion 228 of the n-well region 110 is shown. Fig. 6A and Figure 6B The formation of the silicide repelling layer 376 at least partially located over each floating gate 182a, 182b, 182c, and 182d, over the central portion 328 of the n-well region 110, and over the first doped region 152 of each active region 108a and 108b can be performed simultaneously. A suitable dielectric layer, such as a silicon dioxide layer, can be deposited over each floating gate 182a, 182b, 182c, and 182d, over the n-well region 110, and over the first doped region 152 of each active region 108a and 108b. The silicon dioxide layer can be patterned by conventional photolithography processes and wet or dry etching to leave a portion of the silicon dioxide layer at least partially over each floating gate 182a, 182b, 182c and 182d, over the central portion 328 of the n-well region 110, and over the first doped region 152 of each active area 108a and 108b, thereby forming a silicide repelling layer 376.

[0052] Fig. 7A is a top view of a nonvolatile memory device 400 according to another embodiment of the present disclosure. Figure 1AIn contrast to the illustrated nonvolatile memory device 100, the nonvolatile memory device 400 includes a silicide repelling layer 498 at least partially disposed over a first floating gate 182a and a second floating gate 182b over a portion of a first active region 108a. The silicide repelling layer 498 may also be at least partially disposed over a third floating gate 182c and a fourth floating gate 182d over a portion of a second active region 108b. The silicide repelling layer 498 may also be disposed over a second doped region 156 of each active region 108a and 108b. The first and second active regions 108a and 108b, the floating gates 182a, 182b, 182c, and 182d, the first and second doped regions 152 and 156, the contacts 150, 158, and 160, and the isolation structure are Figure 1A Same as shown.

[0053] refer to Fig. 7A , a silicide repelling layer 498 may be at least partially formed over each floating gate 182a, 182b, 182c, and 182d over the side of the n-well region 110. The silicide repelling layer 498 may cover the first corner 138 of each floating gate 182a, 182b, 182c, and 182d over the side of the n-well region 110, whereby the first corner 138 may be close to the contact 150 over the n-well region 110. The silicide repelling layer 498 may extend over a central portion 428 of the n-well region 110 adjacent to the side of the n-well region 110 under each floating gate 182a, 182b, 182c, and 182d. The central portion 428 of the n-well region 110 is shown as a dashed outline. Although not shown, the silicide repelling layer 498 may extend over an isolation region between each active region 108a and 108b and the n-well region 110.

[0054] Figure 7B According to another embodiment of the present disclosure Fig. 7A FIG. 4 is a cross-sectional view of a memory transistor taken along a section line G-G' of the nonvolatile memory device 400. Figure 7B , a spacer structure 162 may be disposed over the sidewall of the first floating gate 182a. A silicide repelling layer 498 may be disposed at least partially over the first floating gate 182a, over the spacer structure 162 disposed over the sidewall of the first floating gate 182a, and over the second doped region 156 of the first active region 108a. A silicide layer 476 may be disposed over a portion 416a of the first floating gate 182a and adjacent to the silicide repelling layer 498. The silicide layer 168 is similar to Figure 1C Silicide layer 168 is shown.

[0055] The fabrication of each active region 108a and 108b, the n-well region 110, each floating gate 182a, 182b, 182c and 182d, the spacer structure 162, the first doping region 152 and the second doping region 156 is similar to Figures 2A to 3A as well as Figure 2B , FIG. 3B to FIG. 4B The manufacturing process flow is shown. Fig. 7A The formation of the center portion 428 of the n-well region 110 and the edge portion 432 of the n-well region 110 are similar to Figure 4A The formation of the central portion 128 and the edge portion 132 of the n-well region 110 is shown. The formation of the silicide repelling layer 498 can include depositing a suitable dielectric material layer, such as a silicon dioxide (SiO2) layer, over each floating gate 182a, 182b, 182c, and 182d, over the central portion 428 of the n-well region 110, and over the second doped region 156 of each active region 108a and 108b. The silicon dioxide layer can be patterned by conventional photolithography processes and wet or dry etching to leave a portion of the silicon dioxide layer at least partially over each floating gate 182a, 182b, 182c, and 182d, over the central portion 428 of the n-well region 110, and over the second doped region 156 of each active region 108a and 108b, thereby forming the silicide repelling layer 498.

[0056] Fig. 8A is a top view of a nonvolatile memory device 500 according to another embodiment of the present disclosure. Fig. 6A In contrast to the nonvolatile memory device 300 shown, the nonvolatile memory device 500 includes a silicide repelling layer 592 disposed above each floating gate 182a, 182b, 182c, and 182d. The first active region 108a and the second active region 108b, the floating gates 182a, 182b, 182c, and 182d, the first doped region 152 and the second doped region 156, the contacts 150, 158, and 160, and the isolation structure are connected to the first active region 108a and the second active region 108b. Figure 1A Same as shown.

[0057] refer to Fig. 8A , a silicide repelling layer 592 may be disposed over each floating gate 182a, 182b, 182c, and 182d, whereby the silicide repelling layer 592 may completely cover each floating gate 182a, 182b, 182c, and 182d, including the first corner 138 over the side of the n-well region 110. The silicide repelling layer 592 may extend over a central portion 528 of the n-well region 110 adjacent to the side of the n-well region 110 under each floating gate 182a, 182b, 182c, and 182d. The central portion 528 of the n-well region 110 is shown as a dashed outline.

[0058] Figure 8B According to another embodiment of the present disclosure Fig. 8A The cross-sectional view of the memory transistor of the nonvolatile memory device 500 is taken along the section line H-H'. Figure 8B , a spacer structure 162 may be disposed over the sidewall of the first floating gate 182a. A silicide repelling layer 592 may be disposed over the top surface of the first floating gate 182a. The gate dielectric layer 180 and the silicide layers 168 and 170 are similar to Figure 1C Gate dielectric layer 180 and silicide layers 168 and 170 are shown.

[0059] The fabrication of each active region 108a and 108b, the n-well region 110, each floating gate 182a, 182b, 182c and 182d, the spacer structure 162, the first doping region 152 and the second doping region 156 is similar to Figures 2A to 3A as well as Figure 2B , FIG. 3B to FIG. 4B The manufacturing process of the central portion 528 of the n-well region 110 is similar to Figure 5B The manufacturing process of the central portion 228 of the n-well region 110 is shown.

[0060] refer to Fig. 8A The formation of the silicide repelling layer 592 may include depositing a suitable dielectric material layer, such as a silicon dioxide (SiO2) layer, over each floating gate 182a, 182b, 182c, and 182d and over the central portion 528 of the n-well region 110. The silicon dioxide layer may be patterned by conventional photolithography processes and subsequent wet or dry etching to leave a portion of the silicon dioxide layer over each floating gate 182a, 182b, 182c, and 182d and over the central portion 528 of the n-well region 110, thereby forming the silicide repelling layer 592.

[0061] The terms "first", "second", "third", etc. (if any) in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a specific order or time sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the devices described herein can, for example, be operated in a sequence different from that shown or otherwise described herein. The terms "left", "right", "front", "rear", "top", "bottom", "above", "below", etc. (if any) in the specification and claims are used for descriptive purposes and are not necessarily used to describe permanent relative positions. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the devices described herein can, for example, be operated in an orientation different from that shown or otherwise described herein. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and specific steps of the steps can be omitted and / or some other specific steps not described herein can be added to the method. In addition, the terms "comprises," "comprising," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0062] Although several exemplary embodiments have been given in the above detailed description of the device, it will be understood that there are many variations. It will also be understood that the embodiments are merely examples and are not intended to limit the scope, applicability, size or configuration of the device in any way. Rather, the above detailed description will provide those skilled in the art with a convenient guide to implementing exemplary embodiments of the device, and it will be understood that various changes may be made to the functions and arrangements of the elements described in the exemplary embodiments and methods of making the same without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A non-volatile memory device, comprising: An active region, an n-well region, and an isolation region separating the active region from the n-well region; a floating gate located over a portion of the active region and a first portion of the n-well region; a first doped region in the active region laterally displaced relative to the floating gate at a first side; a second doped region in the active region laterally displaced relative to the floating gate at a second side opposite the first side; a contact over the n-well region, wherein the contact is laterally displaced relative to a first corner of the floating gate over the first portion of the n-well region; as well as A silicide repelling layer is at least partially located over the floating gate.

2. The nonvolatile memory device of claim 1, wherein the silicide repelling layer covers the first corner of the floating gate over the first portion of the n-well region, wherein the first corner is close to the contact over the n-well region.

3. The nonvolatile memory device of claim 2, wherein the silicide repelling layer extends over a second portion of the n-well region adjacent to the first portion of the n-well region under the floating gate and surrounds the contact.

4. The nonvolatile memory device according to claim 3, further comprising: A silicide layer is located over a portion of the floating gate and is adjacent to the silicide repelling layer.

5. The nonvolatile memory device according to claim 4, further comprising: A silicide layer is located over a third portion of the n-well region adjacent to the second portion of the n-well region.

6. The nonvolatile memory device according to claim 5, further comprising: A silicide layer is located above the first doped region and above the second doped region in the active region.

7. The nonvolatile memory device of claim 2, wherein the silicide repelling layer completely covers a portion of the floating gate over the first portion of the n-well region.

8. The nonvolatile memory device of claim 2, wherein the silicide repelling layer extends over a portion of the floating gate over the active region. 9 . The nonvolatile memory device of claim 8 , wherein the silicide repelling layer extends over the first doped region in the active region.

10. The nonvolatile memory device according to claim 8, further comprising: A silicide layer is partially located over the floating gate over the active area.

11. The nonvolatile memory device of claim 7, wherein the silicide repelling layer completely covers the portion of the floating gate above the active region.

12. The nonvolatile memory device according to claim 11, further comprising: A silicide layer is located above the first doped region and above the second doped region in the active region.

13. The nonvolatile memory device of claim 10, wherein the silicide repelling layer extends over the second doped region in the active region.

14. The nonvolatile memory device according to claim 13, further comprising: A silicide layer is located above the first doped region in the active region.

15. A non-volatile memory device comprising: A first active region, a second active region, an n-well region between the first active region and the second active region, and an isolation region separating the first active region, the second active region and the n-well region; a first floating gate and a second floating gate located over a portion of the first active region and a third floating gate and a fourth floating gate located over a portion of the second active region, wherein each floating gate is located over a side portion of the n-well region; a first doped region in each active area laterally displaced relative to each floating gate at a first side; a second doped region in each active region and laterally displaced relative to each floating gate at a second side opposite the first side; a contact over the n-well region, wherein the contact is laterally displaced relative to a first corner of each floating gate over the side of the n-well region; as well as A silicide repelling layer is at least partially located over each floating gate, wherein the silicide repelling layer covers the first corner of each floating gate over the side of the n-well region, wherein the first corner is proximate to the contact over the n-well region.

16. The nonvolatile memory device of claim 15, wherein the silicide repelling layer extends over a central portion of the n-well region adjacent to the side portions of the n-well region under each floating gate and surrounds the contact.

17. The nonvolatile memory device according to claim 16, further comprising: A silicide layer is located over a portion of each floating gate and is adjacent to the silicide repelling layer.

18. A method of manufacturing a non-volatile memory device, comprising: Providing an active region, an n-well region, and an isolation region separating the active region from the n-well region; disposing a floating gate over a portion of the active region and over a first portion of the n-well region; a first doped region disposed in the active region at a first side and laterally displaced relative to the floating gate; a second doped region disposed in the active region at a second side opposite to the first side and laterally displaced relative to the floating gate; disposing a silicide repelling layer at least partially over the floating gate; as well as A contact is disposed over the n-well region, wherein the contact is laterally displaced relative to a first corner of the floating gate over the first portion of the n-well region.

19. The method of claim 18, wherein disposing a silicide repelling layer at least partially over the floating gate further comprises: forming a silicide repelling layer at least partially over the floating gate; as well as A silicide layer is formed over a portion of the floating gate and adjacent to the silicide repelling layer.

20. The method of claim 19, wherein providing a contact over the n-well region, wherein the contact is laterally displaced relative to a first corner of the floating gate over the first portion of the n-well region further comprises: forming a silicide repelling layer over a second portion of the n-well region adjacent to the first portion of the n-well region below the floating gate; forming a silicide layer over a third portion of the n-well region adjacent to the second portion of the n-well region; as well as A contact is formed over the n-well region and through the silicide repelling layer, wherein the contact is laterally displaced relative to the first corner of the floating gate over the first portion of the n-well region.

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