Switching power supply and control method thereof

Abstract

A switching power supply and a control method thereof. The switching power supply comprises a transformer, a first switching circuit, a second switching circuit, a third switching circuit, a fourth switching circuit and a clamping capacitor; the primary side controller comprises a first switching control signal output end, a second switching control signal output end, a third switching control signal output end, a fourth switching control signal output end, an input voltage detection port and a zero voltage detection port; the primary side controller is adapted to control the first switching circuit, the second switching circuit, the third switching circuit and the fourth switching circuit based on the detection values of the input voltage detection port and the zero voltage detection port, so as to realize zero voltage turn-on. The above scheme can improve the power density of the switching power supply.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of switching power supply, in particular to a switching power supply and a control method thereof. BACKGROUND

[0002] In order to improve the power density of switching power supply, especially the popularization of high-power mobile phone fast charger, the flyback converter based on quasi-resonant control has been widely concerned in the industry.

[0003] The core components of the flyback converter include a transformer, a main switch located at the primary side of the transformer, and a diode and a capacitor located at the secondary side of the transformer. By turning on and off the main switch, a high-frequency square wave signal is generated at both ends of the primary side coil of the transformer. The transformer transmits the generated square wave signal to the secondary side coil in a magnetic field induction manner, and the signal received by the secondary side coil is filtered and rectified by the diode and the capacitor, and a stable DC output is obtained at the output end.

[0004] However, the switching frequency of the existing switching power supply still cannot meet the demand, which affects the power density of the switching power supply. SUMMARY

[0005] The problem to be solved by the present application is how to improve the power density of the switching power supply.

[0006] To solve the above problems, the embodiments of the present application provide a switching power supply, which comprises a flyback converter and a primary side controller; wherein the flyback converter comprises a transformer, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit and a clamping capacitor; the primary side controller comprises a first switch control signal output end, a second switch control signal output end, a third switch control signal output end, a fourth switch control signal output end, an input voltage detection port and a zero voltage detection port.

[0007] The first end of the first switch circuit is connected with a DC input voltage output end; the second end of the first switch circuit is connected with the transformer and the input voltage detection port of the primary side controller; and the control end of the first switch circuit is connected with the first switch control signal output end.

[0008] The first end of the second switch circuit is connected with the second end of the first switch circuit and the input voltage detection port of the primary side controller; the second end of the second switch circuit is connected with the second end of the fourth switch circuit and a ground wire; and the control end of the second switch circuit is connected with the second switch control signal output end.

[0009] The first end of the third switch circuit is connected with the second end of the first switch circuit and an input voltage detection port of the primary side controller; the second end of the third control circuit is connected with the first end of the fourth switch circuit; the control end of the third control circuit is connected with the third switch control signal output end; the third switch circuit is connected with the transformer through the clamping capacitor;

[0010] The first end of the fourth switch circuit is connected with the transformer and a zero voltage detection port of the primary side controller; the second end of the fourth switch circuit is connected with a current sampling port of the primary side controller; the control end of the fourth switch circuit is connected with the fourth switch control signal output end;

[0011] The primary side controller is adapted to control the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit based on the detection values of the input voltage detection port and the zero voltage detection port, so as to realize zero voltage turn-on.

[0012] The embodiment of the present application also provides a control method of a flyback converter, and the method comprises:

[0013] When the second switch circuit is off, the first switch circuit is controlled to perform zero voltage turn-on;

[0014] When the first switch circuit is off and the second switch circuit meets the zero voltage turn-on condition, the second switch circuit is controlled to perform zero voltage turn-on;

[0015] After the fourth switch circuit is off and the third switch circuit meets the zero voltage turn-on condition, the third switch circuit is controlled to perform zero voltage turn-on;

[0016] After the third switch circuit is off and the fourth switch circuit meets the zero voltage turn-on condition, the fourth switch circuit is controlled to perform zero voltage turn-on.

[0017] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0018] According to the scheme of the present application, the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit can realize zero voltage turn-on under the control of the primary side controller, so that the switching loss of the flyback converter can be reduced, the switching frequency of the switching power supply can be improved, and the power density of the switching power supply can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is a circuit structure schematic diagram of a switching power supply;

[0020] Figure 2is a timing relationship diagram between the drain voltage, the gate voltage and the primary current of the main switch under heavy load and light load conditions;

[0021] Figure 3 is a schematic diagram of a switching power supply circuit structure of a flyback converter with secondary feedback in an embodiment of the present application;

[0022] Figure 4 is a schematic diagram of a switching power supply circuit structure of a flyback converter with secondary feedback in an embodiment of the present application;

[0023] Figure 5 is a schematic diagram of a switching power supply circuit structure of a flyback converter with secondary feedback in an embodiment of the present application;

[0024] Figure 6 is a timing relationship diagram of signals of a switching power supply in a discontinuous mode in an embodiment of the present application;

[0025] Figure 7 is a timing relationship diagram of signals of a switching power supply in a critical mode in an embodiment of the present application;

[0026] Figure 8 is a schematic diagram of a switching power supply circuit structure of a flyback converter with primary feedback in an embodiment of the present application;

[0027] Figure 9 is a schematic diagram of a switching power supply circuit structure of a flyback converter with secondary feedback in an embodiment of the present application;

[0028] Figure 10 is a schematic diagram of a switching power supply circuit structure of a flyback converter with primary feedback in an embodiment of the present application. DETAILED DESCRIPTION

[0029] A switching power supply generally includes a flyback converter and a primary controller. In the current switching power supply, the main switch for controlling the operation of the transformer is hard switching, which has large turn-on loss, thereby resulting in large switching loss of the flyback converter. In addition to the turn-on loss of the main switch, the RCD snubber circuit in the flyback converter also increases the switching loss of the flyback converter. The following describes the specific switching power supply structure:

[0030] Figure 1 is a schematic diagram of a circuit structure of a switching power supply. Referring to Figure 1 , the switching power supply can include a transformer, a primary control circuit, a rectification and voltage stabilization circuit and an RCD snubber circuit on the primary side of the transformer, a secondary control circuit and a rectification and filtering circuit on the secondary side of the transformer.

[0031] The actual transformer in the circuit can be equivalent to an ideal transformer T1, a leakage inductance Ls and excitation inductance L m Among them, leakage inductance L s This refers to the inductance formed when the magnetic field lines generated by the primary coil Np of an actual transformer cannot be transmitted to the secondary coil Ns, resulting in leakage flux. The magnetizing inductance L is also mentioned. m This refers to the primary inductance of an ideal transformer T, which is the inductance formed by the magnetic field lines generated by the primary coil Np of a real transformer being transmitted to the secondary coil Ns. The turns ratio of the primary coil Np to the secondary coil Ns is n:1.

[0032] The primary-side control circuit may include a primary-side controller 11 and a main switch Q. The primary-side controller 11 has a GATE port, a CS port, an FB port, and a QR port. The GATE port of the primary-side controller 11 is connected to the gate of the main switch Q. The CS port of the primary-side controller 11 is connected to the source terminal of the main switch Q. The FB port of the primary-side controller 11 is connected to a receiving optocoupler 12. The receiving optocoupler 12 is used to receive the optical signal generated by the transmitting optocoupler 13 in the secondary-side control circuit. Based on the optical signal received by the receiving optocoupler 12, the FB port of the primary-side controller 11 can obtain the voltage after rectification by diode D1 (i.e., the output voltage of the transformer) and load information. The QR port of the primary-side controller 11 is connected to an auxiliary coil Na through a resistor R1, and the other end of resistor R1 is connected to a resistor R2. The auxiliary coil Na can sense the voltage V at the end of the transformer connected to the main switch Q. sw The change. The main switch Q in the circuit can be equivalent to: a fully controlled switch, a body diode, and a junction capacitance C. ds .

[0033] Primary-side controller 11 is based on the source voltage of the main switch Q and the output voltage V of the flyback converter. o The voltage V at one end of the transformer connected to the main switch Q. sw The changes in voltage at the GATE port control the output voltage of the main switch Q, thereby controlling whether the main switch Q is turned off or on.

[0034] exist Figure 1 In the circuit, the rectifier and voltage regulator circuit includes: AC rectifier 14 and voltage regulator capacitor C. BULK .

[0035] When the main switch Q is turned on, the mains voltage VAC is rectified by AC rectifier 14 to obtain the DC input voltage V. IN Connecting the primary winding of the transformer increases the current in the primary winding Np and the magnetic field in the transformer core, storing energy in the core. At this time, the voltage generated in the secondary winding Ns is reverse-biased, causing diode D1 to be reverse-biased and unable to conduct, allowing energy to flow from capacitor C0 to the load R. L Provide voltage V o and current Id .

[0036] After the main switch Q is turned off, the primary current I p in the primary winding Np is 0, at the same time, the magnetic field in the transformer magnetic core begins to decline, a positive voltage is induced on the secondary winding Ns. At this time, the diode D1 is in a positive bias state, the current I d flows into the capacitor C o and the load R L . The energy stored in the transformer magnetic core is transferred to the capacitor C o and the load R L .

[0037] The secondary side control circuit can include a secondary side controller 15 and a light emitting optocoupler 13. The secondary side controller 15 has a VDD port, an OPTO port and a CS port. The VDD port of the secondary side controller 15 is connected with the load R o of the capacitor C L , for obtaining the output voltage V o of the flyback converter, the CS port of the secondary side controller 15 is used for sampling the current flowing through the resistor R CS . The OPTO port of the secondary side controller 15 is connected with the cathode of the diode D1 through the light emitting optocoupler 13. The secondary side controller 15 can control the light emitting optocoupler 13 to generate a corresponding light signal based on the cathode voltage of the diode D1, so as to transmit the cathode voltage of the diode D1 to the light receiving optocoupler 12.

[0038] The RCD absorption circuit is composed of a resistor R C , a capacitor C C and a diode D2, for absorbing the spike voltage generated by the transformer leakage inductance L s when the main switch Q is turned off.

[0039] Figure 2 The left side shows the timing relationship between the drain voltage V L , the gate voltage GATE and the primary current I sw of the main switch Q under the heavy load (i.e. the load R p has a small resistance). Figure 2 The right side shows the timing relationship between the drain voltage V L , the gate voltage GATE and the primary current I sw of the main switch Q under the light load (i.e. the load R p has a large resistance).

[0040] Referring to Figure 2 , in order to reduce the turn-on loss of the main switch Q, before the main switch Q is turned on, the drain voltage V swThe resonance reaches the valley and the main switch Q is turned on. sw The minimum turn-on loss P of the main switch Q sw_on As shown in the following formula:

[0041]

[0042] Wherein, f s Indicates the switching frequency of the main switch Q.

[0043] At the same time, the loss of the RCD absorption circuit is:

[0044]

[0045] Wherein, I pmax Indicates the maximum value of the primary side current, V cmax The difference between the drain voltage V sw Of the main switch Q and the DC input voltage V IN .

[0046] The turn-on loss P of the main switch Q sw_on And the loss of the RCD absorption circuit, together as the switching loss of the flyback converter. From formula (1), (2), when the DC input voltage V IN Of the flyback converter is higher, the turn-on loss of the flyback converter is greater.

[0047] Therefore, at present, in order to avoid the switching loss of the flyback converter being too large, the DC input voltage V IN Of the flyback converter usually needs to be limited, thereby resulting in that the highest switching frequency of the main switch Q is generally limited within 300 kHz.

[0048] In view of the problem, the application provides a switching power supply, wherein a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit are arranged in a flyback converter of the switching power supply, and the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit can realize zero voltage turn-on under the control of the primary side controller, that is, a full soft switch circuit structure of the four switch circuits is adopted to replace the existing flyback converter realized by hard switch, which can reduce the switching loss of the switch circuit on the one hand, improve the switching frequency of the switching power supply, thereby improving the power density of the switching power supply, and on the other hand, when the four switch circuits are realized by gallium nitride devices, the full soft switch scheme can completely avoid the influence of the change rate of the hard switch voltage on the gate reliability of the gallium nitride device.

[0049] In order to make the above-mentioned purposes, characteristics and advantages of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the drawings.

[0050] The embodiment of the present application provides a switching power supply. The switching power supply comprises a flyback converter and a primary side controller. The flyback converter comprises a transformer, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit and a clamping capacitor. The primary side controller comprises a first switch control signal output end, a second switch control signal output end, a third switch control signal output end, a fourth switch control signal output end, an input voltage detection port and a zero voltage detection port.

[0051] The first end of the first switch circuit is connected with a direct current input voltage output end; the second end of the first switch circuit is connected with the transformer and the input voltage detection port of the primary side controller; and the control end of the first switch circuit is connected with the first switch control signal output end.

[0052] The first end of the second switch circuit is connected with the second end of the first switch circuit and the input voltage detection port of the primary side controller; the second end of the second switch circuit is connected with the second end of the fourth switch circuit and a ground wire; and the control end of the second switch circuit is connected with the second switch control signal output end.

[0053] The first end of the third switch circuit is connected with the second end of the first switch circuit and the input voltage detection port of the primary side controller; the second end of the third control circuit is connected with the first end of the fourth switch circuit; the control end of the third control circuit is connected with the third switch control signal output end; and the third switch circuit is connected with the transformer through the clamping capacitor.

[0054] The first end of the fourth switch circuit is connected with the transformer and the zero voltage detection port of the primary side controller; the second end of the fourth switch circuit is connected with the current sampling port of the primary side controller; and the control end of the fourth switch circuit is connected with the fourth switch control signal output end.

[0055] The primary side controller is adapted to control the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit based on the detection values of the input voltage detection port and the zero voltage detection port, so as to realize zero voltage turn-on.

[0056] In the specific implementation, the zero voltage turn-on refers to that the voltage difference between the two ends of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit belongs to a low voltage range when the switch circuits are turned on. Generally, the low voltage range is usually a voltage less than 1V, close to 0 voltage, and the control of the switch circuits in the low voltage range is turn-on at zero voltage (ZVS). For example, it can be 0.3V or 0.7V, etc., and it may fluctuate slightly with the current flowing through the switch circuits. The turn-on loss of the switch circuits turned on in the low voltage range is close to 0.

[0057] Due to the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit, low-voltage range can be realized under the control of the primary side controller, so the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit are all soft switches. Soft switch can alleviate the sudden change of instantaneous voltage or current when the switch is turned on or off. At the same time, soft switch can make the switching frequency of the switching power supply no longer limited by the switching loss of the switch circuit, so the switching frequency of the switching power supply can still be improved. The improvement of the switching frequency can significantly reduce the volume of passive devices such as transformers and capacitors, and improve the power density of the switching power supply.

[0058] In an embodiment of the present application, at least one of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit can be realized by MOS tube or GaN device. For example, the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit can all be realized by MOS tube. For another example, the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit can all be realized by GaN device. For another example, part of the switch circuit is realized by MOS tube, and the remaining part of the switch circuit is realized by GaN device.

[0059] In specific implementation, the MOS tube can be NMOS tube or PMOS tube. It can be understood that whether it is NMOS tube or PMOS tube, it can be used as a switch tube. Using MOS tube as switch circuit can obtain higher switching frequency limit and lower switching loss, conduction loss, etc.

[0060] Of course, in specific implementation, other switching devices can also be used for implementation, which is not limited.

[0061] In an embodiment of the present application, one end of the clamping capacitor is connected to the second end of the third switch circuit, and the other end is connected to the first end of the fourth switch circuit.

[0062] In another embodiment of the present application, one end of the clamping capacitor is connected to the first end of the third switch circuit, and the other end is connected to the second end of the first switch circuit.

[0063] The clamping capacitor is used as a storage and recycling element for transformer leakage inductance current, which can eliminate leakage inductance resonance ringing, reduce the stress of switching devices, and reduce energy loss and improve conversion efficiency.

[0064] In specific implementation, the input voltage detection port of the primary side controller is adapted to detect the input voltage of the transformer. The zero voltage detection port of the primary side controller is adapted to detect the voltage of the same name end of the primary side coil of the transformer.

[0065] In an embodiment of the present application, the flyback converter can further comprise a current sampling resistor. The primary side controller can further comprise a current sampling port. The second end of the second switch circuit is connected to the current sampling port of the primary side controller and the second end of the fourth switch circuit through the current sampling resistor. Of course, in some embodiments, the current sampling resistor can not be provided, so that the second switch circuit is directly connected to the fourth switch circuit. The current sampling resistor serves as a transformer primary current detection element, and can achieve peak current control of the switching power supply, and can also achieve overcurrent protection of the primary side current.

[0066] In some embodiments, the primary side controller can further comprise an output voltage feedback port for feeding back the output voltage of the transformer and load information.

[0067] In specific implementations, the flyback converter can be a secondary side feedback flyback converter structure or a primary side feedback flyback converter structure. The secondary side feedback flyback converter structure refers to that the output voltage of the transformer is fed back to the primary side of the transformer through an optocoupler. The primary side feedback flyback converter structure refers to that the output voltage of the transformer is detected by the primary side controller of the transformer, and an optocoupler is not required on the secondary side of the transformer.

[0068] The secondary side feedback flyback converter structure and the primary side feedback flyback converter structure will be described in detail below, taking the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit as NMOS tubes for example:

[0069] In an embodiment of the present application, the flyback converter can be a secondary side feedback flyback converter structure.

[0070] For example, referring to Figure 3 , the first switch circuit in the flyback converter is implemented by a first NMOS tube Q1, the second switch circuit is implemented by a second NMOS tube Q2, the third switch circuit is implemented by a third NMOS tube Q3, and the fourth NMOS tube is implemented by a fourth NMOS tube Q4. At this time, the first end of the switch circuit can be the drain end of the NMOS tube. The second end of the switch circuit can also be the source end of the NMOS tube. The control end of the switch circuit can be the gate end of the NMOS tube.

[0071] Among them, the NMOS tube can be equivalent to a fully controlled switch, a body diode and a junction capacitor in the circuit. The junction capacitor of the first NMOS tube Q1 is C1, the junction capacitor of the second NMOS tube Q2 is C2, the junction capacitor of the third NMOS tube Q3 is C3, and the junction capacitor of the fourth NMOS tube Q4 is C4.

[0072] To achieve zero-voltage turn-on of the NMOS transistor, the voltage drop from its drain to its source must be less than the forward voltage of the body diode. Since this voltage drop is less than the forward voltage of the body diode, the body diode is turned off, allowing current to flow through the fully controlled switch and putting the NMOS transistor on. In this state, the turn-on loss of the NMOS transistor is very small.

[0073] The primary-side controller U1 includes: a first switch control signal output terminal, a second switch control signal output terminal, a third switch control signal output terminal, a fourth switch control signal output terminal, and a zero-voltage detection port V. B and input voltage detection port V A Specifically, the first switch control signal output terminal outputs a first switch control signal GT1. The second switch control signal output terminal outputs a second switch control signal GT2. The third switch control signal output terminal outputs a third switch control signal GT3. The fourth switch control signal output terminal outputs a fourth switch control signal GT4.

[0074] The primary-side controller U1 may also be equipped with a current sampling port CS, which is connected to the fourth switching circuit and the current sampling resistor R. CS By connecting the circuit, the voltage V at the second terminal of the fourth switching circuit can be obtained. CS .

[0075] In practical implementation, the equivalent circuit of the transformer includes: transformer T1, leakage inductance L s and excitation inductance L m In this embodiment of the invention, the transformer refers to transformer T1. The turns ratio of the primary winding to the secondary winding of transformer T1 is n:1, and the refracted voltage of the output voltage of transformer T1 is n*V. o .

[0076] exist Figure 3 In the illustrated embodiment, the third NMOS transistor Q3 is clamped by capacitor C. c It is connected to the first NMOS transistor Q1. In other embodiments, refer to... Figure 4 The third NMOS transistor Q3 can also be directly connected to the first NMOS transistor Q1. In this case, the clamping capacitor C... c Connected in series with the third NMOS transistor Q3, clamping capacitor C c The other end is connected to transformer T1. Regardless of the clamping capacitor C... c The specific connection method is as long as it allows for connection of the magnetizing inductor L. m The voltage can be clamped.

[0077] Continue to refer to Figure 3The drain end of the first NMOS tube Q1 is connected with the direct current input voltage output end, and is adapted to input the direct current input voltage V IN The source end is connected with the leakage inductor Ls, and the gate end inputs the first switch control signal GT1.

[0078] The drain end of the second NMOS tube Q2 is connected with the leakage inductor Ls, the source end is connected with the current sampling resistor R CS and the ground wire, and the control end is adapted to input the second switch control signal GT2. CS When there is no current sampling resistor R c , the source end of the second NMOS tube Q2 can be directly connected with the source end of the fourth switch circuit Q4.

[0079] The drain end of the third NMOS tube Q3 is connected with the leakage inductor Ls through the clamping capacitor C c , the source end is connected with the excitation inductor L m and the drain end of the fourth NMOS tube Q4, and the control end is adapted to input the third switch control signal GT3.

[0080] The drain end of the fourth NMOS tube Q4 is connected with the excitation inductor L m , the source end is connected with the current sampling resistor R CS , and the control end is adapted to input the fourth switch control signal GT4.

[0081] In a specific implementation, for the flyback converter structure of the secondary side feedback, the flyback converter usually further comprises a secondary side control circuit and a rectification filter circuit located at the secondary side of the transformer; wherein the rectification filter circuit is connected with the transformer T1, and the secondary side control circuit is connected with the rectification filter circuit. Of course, in some embodiments, the rectification filter circuit can not be arranged, and the output voltage of the converter is directly output to the load R L .

[0082] In an embodiment of the present application, referring to Figure 3 , the rectification filter circuit can comprise a rectification diode D1 and a filter capacitor C o . The rectification diode D1 can be arranged at the same name end of the secondary side coil of the transformer T1. One end of the filter capacitor C o is connected with the same name end of the secondary side coil of the transformer T1, and the other end is connected with the different name end of the secondary side coil of the transformer T1. The rectification filter circuit can rectify and filter the output signal of the transformer T1, and then output to the load RL.

[0083] In an embodiment of the present application, in order to further improve the switching frequency of the flyback converter, the primary side controller can control the rectification diode D1 to realize zero current turn-off. The so-called low current range turn-off is that the secondary side current I dThe low current range is close to 0, the control rectifier diode D1 is turned off in the low current range, zero current switching (ZCS) of the rectifier diode D1 is realized, and thus the energy loss in the diode recovery time, i.e. the switching loss, and the larger dv / dt and di / dt, i.e. the stress of the switching device, can be reduced, so that the switching frequency of the flyback converter can be further improved.

[0084] In a specific implementation, the primary side controller U1 can control the secondary side current I d by controlling the second NMOS tube Q2 and the third NMOS tube Q3, so that the secondary side current I d is changed when the secondary side current I o is in the low current range, the PN junction inside the rectifier diode D1 is turned off due to the reverse voltage, so that the rectifier diode D1 is turned off.

[0085] In an embodiment of the present application, referring to Figure 5 , the rectification and filtering circuit can include a synchronous rectifier M1 and a filtering capacitor C o . The synchronous rectifier M1 can be arranged at the opposite end of the secondary side coil of the transformer T1. One end of the filtering capacitor C o is connected to the same end of the secondary side coil of the transformer T1, and the other end is connected to the opposite end of the secondary side coil of the transformer T1. The rectification and filtering circuit can rectify and filter the output signal of the transformer T1 and then output to the load R L .

[0086] In a specific implementation, the synchronous rectifier M1 can be an NMOS tube, the drain end of the NMOS tube is connected to the transformer T1, the source end is connected to the filtering capacitor C o , and the gate end is connected to the secondary side controller U2. At this time, the secondary side controller U2 can be provided with a driving port DRV, and the secondary side controller U2 can control whether the synchronous rectifier M1 is turned on by controlling the output voltage of the driving port DRV, so as to more conveniently drive the synchronous rectifier M1 and control the operation of the rectification and filtering circuit.

[0087] In an embodiment of the present application, in order to further improve the conversion efficiency of the flyback converter, the rectification and filtering circuit can also use the secondary side controller to control the synchronous rectifier M1 switch to realize.

[0088] In a specific implementation, the secondary side control circuit can include a secondary side controller U2 and a light emitting optocoupler 11. The secondary side controller U2 has a VDD port, an OPTO port and a CS port. The VDD port of the secondary side controller U2 is connected to the load R L of the capacitor C o , for obtaining the output voltage V s of the flyback converter, and the CS port of the secondary side controller 15 is used to control the current flowing through the resistor Rs The current sampling port CS of the secondary side controller 15 is connected with the anode of the diode D1 through the light emitting optocoupler 13.

[0089] In the embodiment, the zero voltage detection port V B The output voltage feedback port FB of the primary side controller U1 is connected with the ground through the light receiving optocoupler 12, which is adapted to feedback the output voltage of the transformer T1. The input voltage detection port V A of the primary side controller U1 is connected with the second end of the first switch circuit, i.e. the source of the first NMOS Q1, which is adapted to detect the input voltage V IN .

[0090] For the convenience of description, the voltage detected by the zero voltage detection port V B is denoted as V B , the voltage detected by the input voltage detection port V A is denoted as V A . V B is also the voltage of the same name end of the primary side coil of the transformer T1, and is also the drain voltage of the fourth NMOS Q4. V A is also the source voltage of the first NMOS Q1, and is also the drain voltage of the first NMOS Q2.

[0091] The secondary side controller U2 can control the light emitting optocoupler 11 to generate a corresponding light signal based on the cathode voltage of the rectifier diode D1, so as to transmit the cathode voltage of the rectifier diode D1 to the light receiving optocoupler 12. The primary side controller U1 generates the first switch control signal GT1 to the fourth switch control signal GT4 based on the voltage values input by the zero voltage detection port V B , the output voltage feedback port FB, the input voltage detection port V A and the current sampling port CS.

[0092] In the embodiment, the rectification and voltage stabilization circuit comprises an AC rectifier 14 and a voltage stabilization capacitor C BULK . IN .

[0093] In the embodiment, the primary side controller U1 can adopt various structures and control methods to realize the zero voltage turn-on of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit, and the specific implementation is not limited.

[0094] In one embodiment of the present invention, a control method for a switching power supply is provided. The method may include: controlling the first switching circuit to turn on when the second switching circuit is turned off and the first switching circuit meets the zero-voltage turn-on condition; controlling the second switching circuit to turn on when the first switching circuit is turned off and the second switching circuit meets the zero-voltage turn-on condition; controlling the third switching circuit to turn on after the fourth switching circuit is turned off and the third switching circuit meets the zero-voltage turn-on condition; and controlling the fourth switching circuit to turn on after the third switching circuit is turned off and the fourth switching circuit meets the zero-voltage turn-on condition.

[0095] In one embodiment of the present invention, when the second and third switching circuits are both turned on, and the first and fourth switching circuits are turned off, the negative current value generated by the magnetizing inductor is determined based on the magnitude of the input voltage or the output voltage of the flyback converter.

[0096] Reference Figure 3 Taking the NMOS transistor to implement each switching circuit as an example, since the flyback converter input voltage V IN When the voltage is large, the energy required for the first NMOS transistor Q1 to turn on at zero voltage is large, therefore the negative current required to achieve the zero-voltage turn-on of the first NMOS transistor Q1 is large. In this case, the magnetizing inductance L can be increased. m The resulting negative current value can thus increase V. A The voltage value ensures that the first NMOS transistor Q1 is turned on at zero voltage.

[0097] Similarly, at the flyback converter output voltage V o When the voltage is relatively small, the voltage V at the same terminal of the primary winding of transformer T1 is... B The energy available to enable zero-voltage turn-on of the first NMOS transistor Q1 is relatively small, resulting in a larger negative current required for Q1 to turn on at zero voltage. In this case, the magnetizing inductance L can be increased. m The resulting negative current value can also raise V. A The voltage value ensures that the first NMOS transistor Q1 is turned on at zero voltage.

[0098] In one embodiment of the present invention, when the first switch circuit and the third switch circuit are turned off, the primary-side controller can control the second switch circuit and the fourth switch circuit to be turned on until the first switch circuit is turned on.

[0099] When using NMOS transistors to implement various switching circuits, the turn-on and turn-off conditions of each NMOS transistor are shown in Table 1:

[0100] Table 1

[0101]

[0102] In the embodiment of the present application, the first NMOS tube Q1 and the fourth NMOS tube Q4 serve as main power tubes, which determine whether the transformer is in the excitation stage or the demagnetization stage, and control the energy storage or transmission. The second NMOS tube Q2 and the third NMOS tube Q3 serve as clamping tubes, which can clamp the voltage at both ends of the excitation inductor L m .

[0103] Based on the size of the excitation inductor current I mag when the first NMOS tube Q1 is initially operated, the operation mode of the flyback converter can be divided into a critical mode and a discontinuous mode. When the excitation inductor current I mag <0 reaches a set negative value, and the first NMOS tube Q1 is not immediately turned on, the flyback converter operates in the discontinuous mode. When the excitation inductor current I mag <0 reaches a set negative value, and the first NMOS tube Q1 is immediately turned on, the flyback converter operates in the critical mode. Whether it is the discontinuous mode or the critical mode, I mag <0 is a necessary condition for Q1 to achieve ZVS, and the duration is the main factor for distinguishing the mode.

[0104] Figure 6 and Figure 7 are timing diagrams of signals in the flyback converter. Figure 3 Figure 6 is a timing diagram of signals in the flyback converter in the discontinuous mode. Figure 7 Figure 3 , Figure 6 and Figure 7 , the control process of the primary side controller U1 is described in detail:

[0105] 1) from t0 to t1: the voltage drop between the drain and the source of the first NMOS tube Q1 meets the zero-voltage turn-on condition, the first NMOS tube Q1 is turned on with zero voltage, the voltage drop between the drain and the source of the fourth NMOS tube Q4 meets the zero-voltage turn-on condition, the fourth NMOS tube Q4 is turned on, the second NMOS tube Q2 and the third NMOS tube Q3 are turned off, V A = V IN , the transformer T1 is excited, the excitation inductor current I mag linearly rises until the peak value. The secondary rectifier diode D1 is cut off.

[0106] 2) from t1 to t2: the first NMOS tube Q1, the second NMOS tube Q2, the third NMOS tube Q3, and the fourth NMOS tube Q4 are all turned off, the excitation inductor current I mag ​​The junction capacitor C1 of the first NMOS tube Q1, the junction capacitor C2 of the second NMOS tube Q2 and the junction capacitor C4 of the fourth NMOS tube Q4 are charged and discharged, and the source voltage V A of the first NMOS tube Q1 drops to about 0V, which is the preparation condition for the zero-voltage turn-on of the second NMOS tube Q2. The voltage V B of the same name end of the primary coil of the transformer T1 rises to n*V o , which is the preparation condition for the zero-voltage turn-on of the third NMOS tube Q3. At this time, the secondary rectifier diode D1 is cut off.

[0107] 3) From the time t2 to the time t3: the voltage drop between the drain and the source of the second NMOS tube Q2 and the third NMOS tube Q3 meets the zero-voltage turn-on condition, the second NMOS tube Q2 and the third NMOS tube Q3 are turned on at zero voltage, and the excitation inductance L m is clamped at -n*V o . At this time, the transformer T1 starts to demagnetize, and the primary inductance current I mag linearly decreases, but the secondary current I d is greater than 0, and the secondary rectifier diode D1 is turned on.

[0108] 4) From the time t3 to the time t4: the transformer T1 ends demagnetization at the time t3, and the secondary current I d = 0, and the rectifier diode D1 is turned off at zero current. At this time, since the third NMOS tube Q3 is turned on, the voltage Vc across the clamping capacitor C c is applied to L m , and a negative current Izvs1 is generated by reverse excitation.

[0109] Let Tzvs1 = t4-t3, and Tzvs1 is adaptively generated by the primary controller U1 according to the input voltage V IN and the output voltage V o , so as to realize the zero-voltage turn-on of the first NMOS tube Q1. For example, when the input voltage V IN is large or the output voltage V o is very low, Tzvs1 is increased, so that the absolute value of the negative current Izvs1 can be increased, thereby raising the source voltage V A of the first NMOS tube Q1, and ensuring that the first NMOS tube Q1 can be turned on at zero voltage.

[0110] 5) From the time t4 to the time t5: after the third NMOS tube Q3 is turned off, the energy in the junction capacitor C4 of the fourth NMOS tube Q4 is transferred to the excitation inductance L m through the second NMOS tube Q2. Let Tzvs2 = t5-t4, and the primary inductance current I mag gradually decreases to Izvs2, and the voltage V BWhen the voltage drops to near 0V, since the drain voltage of the fourth NMOS transistor Q4 is close to 0V, zero-voltage turn-on can be achieved. Therefore, the primary-side controller can control the primary-side inductor current I. mag The descent has ended.

[0111] 6) From time t5 to time t6: Refer to Figure 6 When the flyback converter operates in discontinuous mode, the fourth NMOS transistor Q4 is turned on at zero voltage, while the first NMOS transistor Q1 and the third NMOS transistor Q3 are turned off, and the negative current Izvs2 remains unchanged; (Refer to...) Figure 7 When the flyback converter operates in critical mode, there is no negative current holding mode, and it directly enters the zero-voltage turn-on preparation state of the first NMOS transistor Q1.

[0112] 7) From time t6 to t7: The second NMOS transistor Q2 is turned off, and the negative current Izvs2 charges and discharges the junction capacitance C1 of the first NMOS transistor Q1 and the junction capacitance C2 of the second NMOS transistor Q2 through the fourth NMOS transistor Q4. The source voltage V of the first NMOS transistor Q1... A Gradually increase to the input voltage V IN This is to prepare for the zero-voltage turn-on of the first NMOS transistor Q1;

[0113] 8) From time t7 to time t9: This is the periodic repetition of the state from time t0 to time t2 mentioned above.

[0114] From steps 1) to 8), it can be seen that the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 all achieve zero-voltage turn-on, and the secondary rectifier diode D1 also achieves zero-current turn-off. Using the above flyback converter, the power supply switching frequency can be increased to over 1MHz, the size of the transformer and capacitor can be reduced, and the power density of the switching power supply can be improved.

[0115] Furthermore, in the aforementioned flyback converter, the negative current Izvs2 required for the soft switching of the first NMOS transistor Q1 is supplied by the clamping capacitor C. c The voltage Vc across Tzvs1 is related to the magnetizing inductor L. m The reverse excitation generates Izvs1 and Tzvs2, and the junction capacitance C4 transfers energy to the excitation inductor L. m The magnetic energy transfer energy is generated together, and the value of the negative current Izvs1 is adaptively generated based on the input voltage and output voltage of the flyback converter, which allows for a wider range of input and output voltages for the flyback converter.

[0116] Furthermore, existing flyback converters, such as Figure 2 As mentioned above, when the load becomes lighter, the number of resonant valleys increases. Due to the existence of damping, a higher number of valleys results in higher valley voltages and a higher resonant center voltage V. INThe closer, the turn-on loss of a single switch cycle increases with the increase of the resonance valley, thereby reducing the conversion efficiency of the medium and small load section.

[0117] The application can make the negative current Izvs2 required by the soft switching of the first NMOS tube Q1 remain in the transformer T1 through the turn-on of the second NMOS tube Q2 and the fourth NMOS tube Q4 after the turn-off of the first NMOS tube Q1 and the third NMOS tube Q3, so that the soft switching can be realized in the light load frequency reduction mode.

[0118] Further, in the prior art, gallium nitride (GaN) devices are widely concerned in the industry due to excellent high-frequency switching characteristics. However, the existing technical solutions limit their application range, and the reasons are as follows: first, the existing control technology belongs to hard switching technology, which results in large turn-on loss of the gallium nitride device and limited working frequency; second, the existing control technology reduces the reliability of the gallium nitride device, and the voltage change rate (dV / dt) generated by the hard switching work is coupled to the gate of the gallium nitride device, thereby affecting the reliability of the gate-source; under the existing control technology, the gallium nitride drain-source voltage is the superposition of the stress input voltage, the output reflected voltage and the drain inductance oscillation voltage, and when the power grid fluctuates or lightning occurs, the gallium nitride device drain-source stress is easy to exceed the standard and be damaged.

[0119] And by adopting the scheme of the application, the maximum voltage stress borne by the first NMOS tube Q1 and the fourth NMOS tube Q4 of the main power tube is respectively the input voltage V IN and Vcmax (i.e. the maximum value of V B and the difference between V IN , which is approximately nVo); the maximum stress borne by the second NMOS tube Q2 and the third NMOS tube Q3 of the clamping tube is respectively the input voltage V IN and V IN +Vcmax.

[0120] Compared with the prior art, the first to fourth switching circuits in the application can improve the application reliability of wide-bandgap devices gallium nitride when gallium nitride devices are used, and the full-soft switching technology can completely avoid the voltage change rate (dV / dt) generated by the hard switching work, which affects the gate of the gallium nitride device. The voltage stress of the main power tube is reduced from V IN +Vcmax to below Vcmax, and the voltage stress of the second NMOS tube Q2 is only V IN , which can make up for the defect of insufficient avalanche capability of the gallium nitride device and promote the mass production of gallium nitride devices in the high-voltage industry.

[0121] In an embodiment of the present application, the flyback converter can be a primary feedback flyback converter structure.

[0122] Referring to Figure 8 , unlike the secondary feedback flyback converter structure shown in Figure 3 , in Figure 7 , the zero voltage detection port V B and the output voltage feedback port FB of the primary controller U1 are both connected with the first end of the fourth switch circuit, that is, the drain end of the fourth NMOS Q4. Among them, the zero voltage detection port V B is adapted to detect the voltage of the connection end of the transformer T1 and the fourth switch circuit, and the output voltage feedback port FB is adapted to feedback the output voltage of the transformer T1.

[0123] The input voltage detection port V A of the primary controller U1 is connected with the second end of the first switch circuit, that is, the source end of the first NMOS Q1, and is adapted to detect the input voltage V IN of the transformer T1.

[0124] At this time, the output voltage feedback port FB of the primary controller U1 is connected to the drain end of the fourth NMOS Q4, that is, the drain end of the fourth NMOS Q4 as the output voltage feedback node, thereby a set of secondary feedback control circuit and a pin of the primary controller U1 can be saved.

[0125] In Figure 8 , based on the drain voltage of the fourth NMOS Q4, the output voltage of the transformer T1 can be obtained through corresponding calculation. When the second NMOS Q2 and the third NMOS Q3 are turned on at the same time, the drain voltage of the fourth NMOS Q4 is the refractive voltage of the output voltage of the transformer T1, that is, n*Vo, wherein n is the primary-secondary turn ratio of the transformer, and V o is the output voltage.

[0126] As for the specific working process of the primary feedback flyback converter in Figure 8 , reference can be made to the above description of the specific working process of the secondary feedback flyback converter, which will not be repeated here.

[0127] It should be noted that in specific implementation, whether it is a primary feedback flyback converter or a secondary feedback flyback converter, when the input voltage V IN of the flyback converter is large, the first switch circuit and the transformer drain inductance L sAt least one voltage dividing circuit can be arranged between the two ends. One end of the voltage dividing circuit is connected to the second end of the first switch circuit, and the other end is grounded. At this time, the intermediate voltage of the voltage dividing circuit (for example, when the voltage dividing circuit is a resistor string formed by two resistors in series, the intermediate voltage of the voltage dividing circuit can be the voltage at the connection of the two resistors) can be input to the primary controller input voltage detection port. Similarly, when the voltage at the drain end of the fourth NMOS tube Q4 is high, a voltage dividing circuit can also be arranged between the drain end of the fourth NMOS tube Q4 and the ground wire, and the intermediate voltage of the voltage dividing circuit can be input to the primary controller zero voltage detection port.

[0128] The embodiment of the present application also provides a primary side controller suitable for the flyback converter. The primary side controller can control the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit to be turned on in a low voltage range.

[0129] Specifically, referring to Figure 9 , the primary side controller comprises a first signal generating circuit 91 and a second signal generating circuit 92; wherein:

[0130] The first signal generating circuit 91 is connected to the output voltage feedback port FB and the current sampling port CS, and is adapted to generate a first switch control signal GT1 and output it to the first switch control signal output end, and generate a second switch control signal GT2 and output it to the second switch control signal output end;

[0131] The second signal generating circuit 92 is connected to the zero voltage detection port V B and the input voltage detection port V A , and is adapted to generate a third switch control signal GT3 and output it to the third switch control signal output end, and generate a fourth switch control signal GT4 and output it to the fourth switch control signal output end.

[0132] The first switch control signal GT1 is adapted to control the first switch circuit to be turned on when the second switch circuit is turned off; the second switch control signal GT2 is adapted to control the second switch circuit to be turned on when the first switch circuit is turned off and the second switch circuit meets the zero voltage turn-on condition; the third switch control signal GT3 is adapted to control the third switch circuit to be turned on after the fourth switch circuit is turned off and the third switch circuit meets the zero voltage turn-on condition; and the fourth switch control signal GT4 is adapted to control the fourth switch circuit to be turned on after the third switch circuit is turned off and the fourth switch circuit meets the zero voltage turn-on condition.

[0133] In a specific implementation, the first signal generation circuit 91 can be implemented in various structures, and is not specifically limited as long as it can generate the first switch control signal GT1 and the second switch control signal GT2 and meet the corresponding timing relationship restrictions.

[0134] In an embodiment of the present application, the first signal generation circuit 91 can include a first comparison circuit 911, a first latch circuit 912, and a first output circuit 913, wherein:

[0135] The first comparison circuit 911 is connected with the output voltage feedback port FB and the current sampling port CS at the input end and connected with the first latch circuit 912 at the output end, and is adapted to compare the output voltage sampling value V os of the transformer with the voltage value V CS input by the current sampling port and output the comparison result to the first latch circuit 912.

[0136] The first latch circuit 912 is connected with the first comparison circuit 911 at the input end and connected with the first output circuit 913 at the output end, and is adapted to output a high-level signal when the fourth switch circuit is turned on and the voltage-controlled oscillator 912a outputs a high signal, and otherwise output a low-level signal.

[0137] The first output circuit 913 is adapted to perform dead zone adjustment and driving processing on the output signal of the first latch circuit 912, and output the first switch control signal GT1 and the second switch control signal GT2, wherein the logic values of the first switch control signal GT1 and the second switch control signal GT2 are opposite.

[0138] In a specific implementation, the first comparison circuit 911 can be implemented in various structures, and is not specifically limited.

[0139] In an embodiment of the present application, the first comparison circuit 911 can include an output voltage receiving sub-circuit 911a, a filtering sub-circuit 911b, and a first comparator 911c, wherein:

[0140] The output voltage obtaining sub-circuit 911a is connected with the output voltage feedback port FB and the current sampling port CS, and is adapted to obtain the sampling value V o of the stable output voltage V os .

[0141] The filtering sub-circuit 911b is adapted to perform low-pass filtering on the obtained sampling value V o of the output voltage V os .

[0142] The first comparator 911c is adapted to compare the output voltage V othe sampling value V os the low-pass filtered voltage value, and the voltage value V CS are compared to obtain a first comparison result signal.

[0143] In specific implementation, the first latch circuit can have various structures, and the specific structure is not limited.

[0144] In an embodiment of the present application, the first latch circuit 912 includes a voltage-controlled oscillator 912a, a first AND gate circuit G1, and a latch 912b.

[0145] The voltage-controlled oscillator 912a is connected to the output terminal of the filter sub-circuit 911b.

[0146] The first input terminal of the first AND gate circuit G1 is connected to the output terminal of the voltage-controlled oscillator 912a, and the second input terminal is connected to the second signal generation circuit 92.

[0147] The latch 912b has a set terminal S connected to the output terminal of the first AND gate circuit G1, a reset terminal R connected to the output terminal of the first comparator 911c, and an output terminal connected to the first output circuit 913.

[0148] In specific implementation, the voltage-controlled oscillator 912a can generate a clock signal related to the transformer output voltage V o . The first AND gate circuit G1 can generate an output signal based on the input signal of the fourth driver and the clock signal. The input signal of the fourth driver has the same phase as the fourth switch control signal. When the input signal of the fourth driver and the clock signal are both high, the first AND gate circuit G1 outputs a high signal, and vice versa.

[0149] In specific implementation, the latch 912b is an RS latch. When the set terminal S is high, the output terminal outputs a high signal. When the reset terminal R is high, the output terminal outputs a low signal.

[0150] Therefore, when the first AND gate circuit G1 outputs a high signal, that is, the period conduction signal arrives and the fourth switch control circuit is turned on, the first switch control circuit is turned on, and at this time, the second switch control circuit is turned off.

[0151] In specific implementation, the first output circuit 913 can be implemented in various structures, and the specific structure is not limited.

[0152] In an embodiment of the present application, the first output circuit 913 can include a first delay timer T1, a second delay timer T2, a second AND gate circuit G2, a first inverter G3, a third AND gate circuit G4, a first driver K1, and a second driver K2.

[0153] The first delay unit T1 has its input terminal connected to the latch 912b and its output terminal connected to the first input terminal of the second AND gate circuit G2.

[0154] The second AND gate circuit G2 has its second input terminal connected to the latch 912b and its output terminal connected to the first driver K1; the output terminal of the first driver K1 serves as the first switch control signal output terminal.

[0155] The first inverter G3 has its input terminal connected to the latch 912b and its output terminal connected to the first input terminal of the third AND gate circuit G4 and the second delay circuit T2.

[0156] The output terminal of the second delay T2 is connected to the second input terminal of the third AND gate circuit G4; the output terminal of the third AND gate circuit G4 is connected to the second driver K2; the output terminal of the second driver K2 serves as the output terminal of the second switch control signal.

[0157] In a specific implementation, the output signal of the latch 912b is delayed by the first delay timer T1 before being ANDed with the output signal of the latch 912b. This adjusts the dead time of the output signal of the latch 912b, improving the energy consumption between the control signals of the first switch control signal GT1 and the second switch control signal GT2, thereby improving the conversion efficiency. The output signal PWM1 of the second AND gate circuit G2, driven by the first driver K1, can obtain the first switch control signal GT1 with the same phase but a higher amplitude.

[0158] The output signal of latch 912b is inverted, then passed through the second delay T2, and input to the third AND gate circuit G4. G4 is then ANDed with the inverted output signal of latch 912b to obtain signal PWM2. Signal PWM2, after passing through the second driver K2, yields the second switch control signal GT2, which has the same phase but a higher amplitude.

[0159] In a specific implementation, for a flyback converter with secondary-side feedback, the output voltage acquisition sub-circuit 911a may include a first resistor R. PU The first resistor R PU With the first reference voltage output terminal V REF1 A connection is provided to set the initial value of the output voltage of the feedback and to provide a pull-up network. os After low-pass filtering, the voltage value V is input to the negative input terminal of the first comparator 911c, and the current sampling port input voltage value V. cs The input is given to the positive input of the first comparator 911c. When V... os Less than V csWhen the output voltage Vout is higher than the input voltage Vin, the first comparator 911c flips from low level signal to high level signal.

[0160] In a specific implementation, referring to Figure 10 For the primary feedback flyback converter, the output voltage acquisition sub-circuit 911a can include a first scaling module X1, a first switch module S1, a first AND gate module G5, a first capacitor C1, and an error amplifier module.

[0161] The first scaling module X1 is connected with the output voltage feedback port FB, and the output end is connected with one end of the first switch module S1; the output end of the first AND gate module G5 is connected with the control end of the first switch module S1; the other end of the first switch module S1 is connected with the first capacitor C1 and the error amplifier module; and the error amplifier module is connected with the filter sub-circuit.

[0162] The first AND gate module G5 can perform an AND operation on the input signal PWM2 of the second driver and the input signal PWM3 of the third driver, and control the on-off of the first switch module S1 through the operation result. The input signal PWM2 of the second driver and the second switch control signal GT2 are signals with the same phase but different amplitudes. The input signal PWM3 of the third driver and the third switch control signal GT3 are signals with the same phase but different amplitudes.

[0163] The first switch module S1, the first AND gate module G5, and the first capacitor C1 constitute a voltage sampling structure. When the input signal PWM3 of the third driver and the input signal PWM2 of the second driver are both high level, the first switch module S1 is closed, the input voltage adjusted by the first scaling module X1 is obtained, and the first capacitor C1 is charged. When the first switch module S1 is open, the error amplifier module compares the charging voltage of the first capacitor C1 with the first reference voltage input end V REF1 The output voltage is compared, so as to perform error adjustment, and is output to the filter sub-circuit for filtering. By integrating the error amplifier module from the secondary side controller into the primary side controller, the primary feedback is realized.

[0164] In an embodiment of the present application, the second signal generation circuit 92 can include a second comparison circuit 921, a second latch circuit 922, and a second output circuit 923; wherein:

[0165] The second comparison circuit 921 has input ends connected with the zero voltage detection port V B and the input voltage detection port V A , and is adapted to compare the output voltage V o of the transformer with the input voltage V INthe size between the output voltage V o of the transformer and the input voltage V IN of the transformer, and output the comparison result to the second latch circuit 922;

[0166] The second latch circuit 922 is connected with the second comparison circuit 921 at the input end and with the second output circuit 923 at the output end, and is adapted to output a high level signal when the second switch circuit is turned on or the fourth switch circuit is turned off, and output a low level signal otherwise.

[0167] The second output circuit 923 is adapted to perform dead zone adjustment and driving processing on the output signal of the second latch circuit 922, and output the third switch control signal and the fourth switch control signal, the logic value of the third switch control signal being opposite to that of the fourth switch control signal.

[0168] In a specific implementation, the second comparison circuit 921 can have various circuit structures, and the specific implementation is not limited.

[0169] In an embodiment of the present application, the second comparison circuit 921 can include a zero voltage detection sub-circuit, an input voltage detection sub-circuit, a second comparator and a reset sub-circuit, wherein:

[0170] The zero voltage detection sub-circuit is adapted to obtain the voltage V B of the transformer T1 at the connection end of the fourth switch circuit when the first switch circuit is turned off, and output to the second comparator 921a;

[0171] The input voltage detection sub-circuit is adapted to obtain the input voltage V IN of the transformer when the first switch circuit is turned on, and output to the second comparator 921a;

[0172] The second comparator 921a is adapted to compare the size between the output voltage V o of the transformer and the input voltage V IN of the transformer, and obtain a second comparison result signal;

[0173] The reset sub-circuit is connected with the zero voltage detection sub-circuit 921a and the input voltage detection sub-circuit, and is adapted to reset the two input ends of the second comparator 921a.

[0174] In a specific implementation, if the voltage output from the input voltage detection sub-circuit to the second comparator 921a is less than the voltage V B of the transformer T1 at the connection end of the fourth switch circuit, the second comparator 921a is flipped from a low level to a high level.

[0175] In an embodiment of the present application, the input voltage detection sub-circuit can comprise: a second scaling module X2, a second switch module S2, a first voltage-controlled current source VCCS1, a second capacitor C2, a third switch module S3, and a third capacitor C3; wherein:

[0176] The second scaling module X2 is connected with the input voltage detection port V A ; the second switch module S2 is connected with the second scaling module X2; the first voltage-controlled current source VCCS1 is connected with the second switch module S2; the second capacitor C2 is connected with the first voltage-controlled current source VCCS1 and the second switch module S2; the third capacitor C3 is connected in parallel with the third switch module S3, and is connected with the first voltage-controlled current source VCCS1 and the second comparator 921a.

[0177] In an embodiment of the present application, the zero detection sub-circuit can comprise: a third scaling module X3, a fourth switch module S4, a second voltage-controlled current source VCCS2, a fourth capacitor C4, a fifth switch module S5, and a fifth capacitor C5; wherein:

[0178] The third scaling module X3 is connected with the zero voltage detection port V B ; the fourth switch module S4 is connected with the third scaling module X3; the second voltage-controlled current source VCCS2 is connected with the fourth switch module S4; the fourth capacitor C4 is connected with the second voltage-controlled current source VCCS2 and the fourth switch module S4; the fifth switch module S5 is connected in parallel with the fifth capacitor C5, and is connected with the second voltage-controlled current source VCCS2 and the second comparator 921a.

[0179] In specific implementation, the transconductance coefficients of the first voltage-controlled current source VCCS1 and the second voltage-controlled current source VCCS2 are the same. The scales of the second scaling module X2 and the third scaling module X3 are the same, the capacitances of the second capacitor C2 and the fourth capacitor C4 are the same, and the capacitances of the third capacitor C3 and the fifth capacitor C5 are the same.

[0180] In specific implementation, the second switch module S2 and the fourth switch module S4 can be controlled to be turned on or off by the input signal PWM1 of the first driver. Specifically, when the input signal PWM1 of the first driver is high (i.e., the first switch circuit is turned on), V A = V IN , the first voltage-controlled current source VCCS1 outputs a current in a proportional relationship with V IN to charge the third capacitor C3, and then maintains.

[0181] When the input signal PWM1 of the first driver is low (i.e., the first switch circuit is turned off), V B= N*Vo, the second voltage-controlled current source VCCS2 outputs a current proportional to N*Vo to charge the fifth capacitor C5, and when the voltage on the fifth capacitor C5 reaches the voltage held on the third capacitor C3, the output of the second comparator 921a flips from low to high.

[0182] Due to the volt-second balance law in the flyback converter, the moment when the second comparator 921a flips, i.e. the moment when the transformer T1 demagnetizes, is also the moment when the current I d flowing through the rectifier diode D1 is exactly 0.

[0183] In an embodiment of the present application, the reset sub-circuit can comprise a second inverter G7, a third delay timer T3, and a fourth AND gate circuit G8; wherein:

[0184] The second inverter G7 is connected to the third delay timer T3; the first input end of the fourth AND gate circuit G8 is connected to the input end of the second inverter G7, and the second input end is connected to the output end of the third delay timer T3; the output end of the fourth AND gate circuit G8 outputs a reset signal, which controls the third switch module S3 and the fifth switch module S5 through the reset signal.

[0185] In a specific implementation, the second inverter G7, the third delay timer T3, and the fourth AND gate circuit G8 constitute a periodic zero-reset signal for the third capacitor C3 and the fifth capacitor C5, so that the second comparator can generate the off signal of the third switch circuit every switching period.

[0186] In an embodiment of the present application, the second comparison circuit 921 can further comprise a divider, a fourth scaling module X4, and an adder; wherein:

[0187] The dividend input end of the divider is connected to the input end of the first voltage-controlled current source VCCS1, and is adapted to be connected to the input voltage V CA of the first voltage-controlled current source VCCS1. The divisor input end of the divider is connected to the input end of the second voltage-controlled current source VCCS2, and is adapted to be connected to the input voltage V CB of the second voltage-controlled current source VCCS2. The output end of the divider is connected to the fourth scaling module X4. The output end of the fourth scaling module X4 is connected to the first input end of the adder; the second input end of the adder is connected to the third capacitor C3; and the output end of the adder is connected to the second comparator 921a.

[0188] In a specific implementation, the input voltage V CA of the first voltage-controlled current source VCCS1 and the input voltage V CB of the second voltage-controlled current source VCCS2 are connected to the divider, and VCA is the dividend, V CB is the divisor.

[0189] By superimposing the voltage outputted by the fourth scaling module X4 on the holding voltage of the third capacitor C3, the flipping time of the second comparator 921a can be delayed, that is, the third switch circuit is turned off after a period of time after the transformer demagnetization is completed, thereby forming a negative inductive current.

[0190] When the input voltage V CA is very high, the energy required for the first switch circuit to realize ZVS is large, and the negative current required is large, so that when the third switch circuit is turned off, the delay time needs to be more. When the output voltage VCB is very low (that is, the refractive voltage n*Vo is very low), the energy provided by the same name end voltage of the primary winding of the transformer for the first switch circuit to realize ZVS is small, and the negative current required is large. Therefore,

[0191] By adjusting the gain between the negative current value and V IN or n*V o through the fourth scaling module X4, the absolute value of the negative current can be changed, so that the first switch circuit can realize zero voltage turn-on.

[0192] In an embodiment of the present application, the second latch circuit 922 can include an or gate circuit G9 and a second latch 922a, wherein:

[0193] The or gate circuit G9 is connected with the first signal generating circuit 91 and the second comparator 921a at the input end, and is connected with the reset end of the second latch 922a at the output end.

[0194] The set end S of the second latch 922a is connected with the first output circuit 913, and the output end is connected with the second output circuit 923.

[0195] In a specific implementation, the signal generated by the first AND gate circuit G1 is subjected to an or operation with the signal outputted by the second comparator 921a. The output signal of the or gate circuit G9 is connected to the reset end R of the latch 912b. The set end of the second latch 922a is connected to the input signal PWM2 of the second driver.

[0196] When the output signal of the or gate circuit G9 is at a high level, the reset end R is at a high level, and the second latch 922a outputs a low level signal. When the input signal PWM2 of the second driver is at a high level, the set end S is at a high level, and the output end is at a high level signal.

[0197] In an embodiment of the present application, the second output circuit 923 can comprise a fourth delay module T4, a fifth AND gate G10, a third inverter G11, a sixth AND gate G12, a fifth scaling module X5, a third comparator 921a, a third driving module K3 and a fourth driving module K4; wherein:

[0198] The input terminal of the fourth delay module T4 is connected with the output terminal of the second latch circuit 922; the output terminal of the fourth delay module T4 is connected with the first input terminal of the fifth AND gate G10; the second input terminal of the fifth AND gate G10 is connected with the output terminal of the second latch circuit 922; the output terminal of the fifth AND gate G10 is connected with the input terminal of the third driving module K3, and the output terminal of the third driving module K3 is as the third switch control signal output terminal.

[0199] The input terminal of the third inverter G11 is connected with the output terminal of the second latch circuit 922; the output terminal of the third inverter G11 is connected with the first input terminal of the sixth AND gate G12; the input terminal of the fifth scaling module X5 is connected with the zero voltage detection port V B ; the output terminal of the fifth scaling module X5 is connected with the third comparator 921a; the input terminal of the third comparator 921a is also connected with the second reference voltage output terminal V REF2 ; the output terminal of the third comparator 921a is connected with the second input terminal of the sixth AND gate G12; the output terminal of the sixth AND gate G12 is connected with the fourth driving module K4; the output terminal of the fourth driving module K4 is as the fourth switch control signal output terminal.

[0200] In a specific implementation, the fifth AND gate G10 performs an AND operation on the output signal of the latch 922a and the output signal of the latch 922a after being delayed by the fourth delay module T4, so that the dead zone of the third switch control signal can be adjusted.

[0201] When the voltage value detected by the zero voltage detection port V B is less than the voltage value output by the second reference voltage output terminal V REF2 , the sixth AND gate G12 outputs a high-level signal to control the fourth switch circuit to be turned on, so that the zero voltage turn-on of the fourth switch circuit can be realized.

[0202] After the output signal of the fifth AND gate G10 is driven by the third driving module K3, the third switch control signal with the same phase but increased amplitude is obtained. After the output signal of the sixth AND gate G12 is driven by the fourth driving module K4, the fourth switch control signal with the same phase but increased amplitude is obtained.

[0203] In a specific implementation, the first reference voltage output end V REF1 And the second reference voltage output end V REF2 Can be the reference voltage generated inside the primary side controller U1, which is a constant voltage value.

[0204] It should be noted that in the embodiments of the present application, the connection can be direct connection or indirect connection.

[0205] From the above, it can be seen that the flyback converter, the control circuit and the control method in the embodiments of the present application add the first switch circuit and the second switch circuit on the basis of the traditional flyback converter, and change the RCD absorption circuit to active clamping. By adaptively controlling the switching state of each switch circuit, the four switch circuits can be turned on with zero voltage (ZVS) and the rectifier diode D1 can be turned off with zero current (ZCS) under any input voltage and load. Since all power semiconductor devices are approximately zero switching loss, and the transformer leakage energy is recovered, the flyback converter operating frequency can be increased to more than 1MHz, thereby significantly reducing the volume of passive devices such as transformers, capacitors, etc., and improving the power density of the switching power supply.

[0206] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A switching power supply, characterized by comprising: The application relates to a flyback converter and a primary side controller. The flyback converter comprises a transformer, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit and a clamping capacitor. The first end of the first switch circuit is connected with a direct current input voltage output end; the second end of the first switch circuit is connected with the input voltage detection port of the transformer and the primary side controller; and the control end of the first switch circuit is connected with the first switch control signal output end. The first end of the second switch circuit is connected with the second end of the first switch circuit and the input voltage detection port of the primary side controller; the second end of the second switch circuit is connected with the second end of the fourth switch circuit and a ground wire; and the control end of the second switch circuit is connected with the second switch control signal output end. The first end of the third switch circuit is connected with the second end of the first switch circuit and the input voltage detection port of the primary side controller; the second end of the third switch circuit is connected with the first end of the fourth switch circuit; the control end of the third switch circuit is connected with the third switch control signal output end; and the third switch circuit is connected with the transformer through the clamping capacitor. The first end of the fourth switch circuit is connected with the transformer and the zero voltage detection port of the primary side controller; the second end of the fourth switch circuit is connected with the current sampling port of the primary side controller; and the control end of the fourth switch circuit is connected with the fourth switch control signal output end. The primary side controller is adapted to control the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit based on the detection values of the input voltage detection port and the zero voltage detection port, so as to realize zero voltage turn-on. The zero voltage detection port is connected with the same name end of the transformer primary side coil and is adapted to detect the voltage of the same name end of the transformer primary side coil.

2. The switching power supply of claim 1, wherein One end of the clamping capacitor is connected with the second end of the third switch circuit, and the other end is connected with the first end of the fourth switch circuit; or one end of the clamping capacitor is connected with the first end of the third switch circuit, and the other end is connected with the second end of the first switch circuit.

3. The switching power supply of claim 1, wherein The application further relates to a current sampling resistor. The primary side controller further comprises a current sampling port; the second end of the second switch circuit is connected with the current sampling port of the primary side controller and the second end of the fourth switch circuit through the current sampling resistor. At least one of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit is an NMOS tube or a gallium nitride device.

4. The switching power supply of claim 1, wherein When at least one of the first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit is an NMOS tube, the voltage drop between the drain and the source of the NMOS tube is smaller than the conduction voltage of the body diode in the NMOS tube when the NMOS tube is turned on.

5. The switching power supply of claim 4, wherein ​ 6. Switching power supply according to any of claims 1 to 5, characterized in that The primary side controller further comprises an output voltage feedback port and a current sampling port; the primary side controller comprises a first signal generating circuit and a second signal generating circuit; wherein: The first signal generating circuit is connected with the output voltage feedback port and the current sampling port, and is adapted to generate a first switch control signal and output the first switch control signal to the first switch control signal output end, and generate a second switch control signal and output the second switch control signal to the second switch control signal output end; The second signal generating circuit is connected with the zero voltage detection port and the input voltage detection port, and is adapted to generate a third switch control signal and output the third switch control signal to the third switch control signal output end, and generate a fourth switch control signal and output the fourth switch control signal to the fourth switch control signal output end; The first switch control signal is adapted to control the first switch circuit to be turned on when the second switch circuit is turned off and the first switch circuit meets the zero voltage turn-on condition; the second switch control signal is adapted to control the second switch circuit to be turned on when the first switch circuit is turned off and the second switch circuit meets the zero voltage turn-on condition; the third switch control signal is adapted to control the third switch circuit to be turned on after the fourth switch circuit is turned off and the third switch circuit meets the zero voltage turn-on condition; and the fourth switch control signal is adapted to control the fourth switch circuit to be turned on after the third switch circuit is turned off and the fourth switch circuit meets the zero voltage turn-on condition.

7. The switching power supply of claim 6, wherein The zero voltage detection port and the output voltage feedback port of the primary side controller are both connected with the first end of the fourth switch circuit.

8. The switching power supply of claim 6, wherein The zero voltage detection port of the primary side controller is connected with the first end of the fourth switch circuit, and the output voltage feedback port of the primary side controller is connected with the ground through a light receiving optocoupler.

9. The switching power supply of claim 8, wherein The second signal generating circuit comprises a second comparison circuit, a second latch circuit and a second output circuit; wherein: The second comparison circuit is connected with the zero voltage detection port and the input voltage detection port of the primary side controller, and is adapted to compare the size between the output voltage of the transformer and the input voltage of the transformer, and output the comparison result to the second latch circuit; The second latch circuit is connected with the second comparison circuit at the input end, and is connected with the second output circuit at the output end, and is adapted to output a high level signal when the second switch circuit is turned on or the fourth switch circuit is turned off, and output a low level signal otherwise; The second output circuit is adapted to perform dead zone adjustment and driving processing on the output signal of the second latch circuit, and output the third switch control signal and the fourth switch control signal, and the logic value of the third switch control signal is opposite to that of the fourth switch control signal.

10. The switching power supply of claim 9, wherein The second comparison circuit comprises a zero voltage detection sub-circuit, an input voltage detection sub-circuit, a second comparator and a reset sub-circuit; wherein: The zero voltage detection sub-circuit is adapted to acquire the voltage at the connection end of the transformer and the fourth switch circuit when the first switch circuit is turned off, and output the voltage to the second comparator; The input voltage detection sub-circuit is adapted to obtain the input voltage of the transformer when the first switch circuit is turned on and output to the second comparator. The second comparator is adapted to compare the size between the output voltage of the transformer and the input voltage of the transformer to obtain a second comparison result signal. The reset sub-circuit is connected with the zero voltage detection sub-circuit and the input voltage detection sub-circuit and is adapted to reset the two input ends of the second comparator.

11. The switching power supply of claim 10, wherein The input voltage detection sub-circuit comprises a second proportional scaling module, a second switch module, a first voltage-controlled current source, a second capacitor, a third switch module and a third capacitor. The second proportional scaling module is connected with the input voltage detection port of the primary side controller; the second switch module is connected with the second proportional scaling module; the first voltage-controlled current source is connected with the second switch module; the second capacitor is connected with the first voltage-controlled current source and the second switch module; the third capacitor is connected in parallel with the third switch module and is connected with the first voltage-controlled current source and the second comparator.

12. The switching power supply of claim 11, wherein The zero voltage detection sub-circuit comprises a third proportional scaling module, a fourth switch module, a second voltage-controlled current source, a fourth capacitor, a fifth switch module and a fifth capacitor. The third proportional scaling module is connected with the zero voltage detection port of the primary side controller; the fourth switch module is connected with the third proportional scaling module; the second voltage-controlled current source is connected with the fourth switch module; the fourth capacitor is connected with the second voltage-controlled current source and the fourth switch module; the fifth switch module is connected in parallel with the fifth capacitor and is connected with the second voltage-controlled current source and the second comparator.

13. The switching power supply of claim 12, wherein The second comparison circuit further comprises a divider, a fourth proportional scaling module and an adder. The divisor input end of the divider is connected with the input end of the first voltage-controlled current source, the divisor input end is connected with the input end of the second voltage-controlled current source, and the output end is connected with the fourth proportional scaling module; the output end of the fourth proportional scaling module is connected with the first input end of the adder; the second input end of the adder is connected with the third capacitor; and the output end of the adder is connected with the second comparator.

14. The switching power supply of claim 12, wherein, The reset sub-circuit comprises a second inverter, a third delay and a fourth AND gate circuit. The second inverter is connected with the third delay; the first input end of the fourth AND gate circuit is connected with the input end of the second inverter, and the second input end is connected with the output end of the third delay; the output end of the fourth AND gate circuit outputs a reset signal, and the third switch module and the fifth switch module are controlled through the reset signal.

15. The switching power supply of claim 9, wherein the control circuit is configured to control the switching frequency of the switching power supply to be within a range of 100 kHz to 1 MHz. The second latch circuit comprises an OR gate circuit and a second latch. The input end of the OR gate circuit is connected with the first signal generation circuit and the second comparator, and the output end is connected with the reset end of the second latch; The set end of the second latch is connected with the first output circuit, and the output end is connected with the second output circuit.

16. The switching power supply of claim 9, wherein The second output circuit comprises a fourth delay module, a fifth AND gate circuit, a third inverter, a sixth AND gate circuit, a fifth scaling module, a third comparator, a third driving module and a fourth driving module. The input end of the fourth delay module is connected with the output end of the second latch circuit; the output end of the fourth delay module is connected with the first input end of the fifth AND gate circuit; the second input end of the fifth AND gate circuit is connected with the output end of the second latch circuit; the output end of the fifth AND gate circuit is connected with the input end of the third driving module, and the output end of the third driving module is used as the third switch control signal output end. The input end of the third inverter is connected with the output end of the second latch circuit; the output end of the third inverter is connected with the first input end of the sixth AND gate circuit; the input end of the fifth scaling module is connected with the zero voltage detection port; the output end of the fifth scaling module is connected with the third comparator; the input end of the third comparator is also connected with the second reference voltage output end; the output end of the third comparator is connected with the second input end of the sixth AND gate circuit; the output end of the sixth AND gate circuit is connected with the fourth driving module; and the output end of the fourth driving module is used as the fourth switch control signal output end.

17. A control method of the switching power supply as claimed in any one of claims 1 to 16, characterized by, Comprise: When the second switch circuit is off, the first switch circuit is controlled to be turned on at zero voltage; When the first switch circuit is off and the second switch circuit meets the zero voltage turn-on condition, the second switch circuit is controlled to be turned on at zero voltage; After the fourth switch circuit is off, and when the third switch circuit meets the zero voltage turn-on condition, the third switch circuit is controlled to be turned on at zero voltage; After the third switch circuit is off, and when the fourth switch circuit meets the zero voltage turn-on condition, the fourth switch circuit is controlled to be turned on at zero voltage.

18. The control method according to claim 17, characterized by, Also comprise: When the second switch circuit and the third switch circuit are both turned on, and the first switch circuit and the fourth switch circuit are turned off, the negative current value generated by the excitation inductance is adaptively adjusted and determined based on the size of the flyback converter input voltage or the flyback converter output voltage, so as to ensure that the first switch circuit meets the zero voltage turn-on condition.

19. The control method according to claim 17, characterized by, Also comprise: When the first switch circuit and the third switch circuit are turned off, the second switch circuit and the fourth switch circuit are controlled to be turned on until the first switch circuit is turned on.

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