A fault processing method, device and computer readable storage medium

Abstract

Embodiments of the present application disclose a fault processing method and device and a computer readable storage medium, comprising: receiving first information including information of a fault device including a fault, determining a first patch unit fault according to the first information, and sending second information including information of the first patch unit to the fault device so that the fault device disables the first patch unit, thereby reducing the influence of the patch problem on the service.

Description

Technical Field

[0001] This application relates to the field of software technology, and in particular to a fault handling method, apparatus, and computer-readable storage medium. Background Technology

[0002] Patches are small programs released to fix vulnerabilities exposed during the use of large software systems. Currently, after a patch is installed, if there are software defects or compatibility issues, the entire patch package needs to be rolled back, causing all the updated content in the patch package to become invalid, thus affecting the business operations related to the patch package. Summary of the Invention

[0003] This application discloses a fault handling method, apparatus, and computer-readable storage medium to reduce the impact of patch issues on services.

[0004] The first aspect discloses a fault handling method, which can be applied to a fault analysis device or to a module (e.g., a chip) within the fault analysis device. The following description uses a fault analysis device as an example. The fault handling method may include: receiving first information from a faulty device, the first information including fault information; determining a fault in a first patch unit based on the first information, the patch unit being the smallest functional unit in a patch; and sending second information to the faulty device, the second information including information about the first patch unit, the second information being used to disable the first patch unit.

[0005] In this embodiment of the application, after the fault analysis device receives fault information from the faulty device, when it determines that the fault is caused by a patch unit, it can send information about the patch unit that caused the fault to the faulty device, so that the faulty device can enable the faulty patch unit instead of enabling the entire patch. This can reduce the de-enabling time, and after de-enabling, it will not affect the operation of the services corresponding to the patch units that have not been de-enabled in the patch, thereby reducing the impact of patch problems on services.

[0006] As one possible implementation, the first information may also include user information, the patch configuration information includes the permission group of the patch unit, and the fault analysis device sends the second information to the fault device by sending the second information to the fault device when the permission group corresponding to the first patch unit includes the user corresponding to the user information.

[0007] In this embodiment of the application, the fault analysis device sends information about the patch unit that caused the fault to the faulty device only when the current user of the faulty device has the permission to disable it, so that the faulty device can disable the patch unit with the fault, thereby ensuring that only users with the necessary permissions can enable it.

[0008] As one possible implementation, the patch configuration information may include the status of the patch unit, and the fault handling method may further include: receiving third information from the faulty device, the third information including result information after the first patch unit is deenabled; and updating the status of the first patch unit according to the third information.

[0009] In this embodiment of the application, after the faulty device is deenabled, the result of the deenabled function can be returned to the fault analysis device so that the fault analysis device can update the status of the patch unit according to the result of the deenabled function, and thus determine the latest status of the patch unit by querying the status of the patch unit.

[0010] As one possible implementation, the patch configuration information may further include a tree structure, the second information may further include information about the second patch unit, the second patch unit being a patch unit in the patch configuration information that belongs to the same tree structure as the first patch unit, the second information is also used to disable the second patch unit, and the third information may further include the result information after the second patch unit is disabled; the fault handling method may further include: updating the state of the second patch unit according to the third information.

[0011] In this embodiment, not only can the patch unit that causes the fault be deenabled, but also the patch units that are dependent on the patch unit can be enabled. This avoids the problem that the faulty device needs to process the service corresponding to the patch unit that is dependent on the patch unit, but cannot successfully process it due to the dependency relationship with the patch unit, thereby reducing unnecessary processing.

[0012] As one possible implementation, the fault information may include interrupt vectors and register information. The fault analysis device determines the first patch unit fault based on the first information by: determining the first patch unit fault based on the interrupt vectors and register information.

[0013] In this embodiment, the fault analysis device can determine that a patch unit has failed based on the interrupt vector and register information, which can improve the efficiency of determining that a patch unit has failed.

[0014] As one possible implementation, the fault information may also include exception stack information. The fault analysis device determines the first patch unit fault based on the interrupt vector and register information by: determining the first patch unit fault based on the interrupt vector, register information and exception stack information.

[0015] In this embodiment, the fault analysis device can determine that the patch unit has failed based on the interrupt vector, register information and exception stack information, which can improve the accuracy of determining that the patch unit has failed.

[0016] As one possible implementation, the register information may include a first instruction address, which is the instruction address corresponding to the fault. The fault analysis device determines the fault of the first patch unit based on the interrupt vector and the register information by: determining the interrupt type corresponding to the interrupt vector; obtaining patch configuration information, which includes an instruction address and an instruction code; and determining the fault of the first patch unit when the interrupt type is a software interrupt and the patch configuration information includes the first instruction address, where the first patch unit is the instruction code corresponding to the first instruction address in the patch configuration information.

[0017] As one possible implementation, the register information may include a first instruction address, which is the instruction address corresponding to the fault. The fault analysis device determines the first patch unit fault based on the interrupt vector, register information, and exception stack information by: determining the interrupt type corresponding to the interrupt vector; obtaining patch configuration information, which includes instruction address and instruction code; and determining the first patch unit fault when the interrupt type is a software interrupt, the patch configuration information includes the first instruction address, and the exception stack information includes the first instruction address. The first patch unit is the instruction code corresponding to the first instruction address in the patch configuration information.

[0018] The second aspect discloses a fault handling method, which can be applied to a faulty device or a module (e.g., a chip) within the faulty device. The following description uses a faulty device as an example. The fault handling method may include: when a fault is detected in the faulty device, sending first information to a fault analysis device, the first information including fault information, used by the fault analysis device to determine that a first patch unit is faulty, the patch unit being the smallest functional unit in a patch; receiving second information from the fault analysis device, the second information including information about the first patch unit; and enabling the first patch unit based on the second information.

[0019] In this embodiment of the application, when a faulty device malfunctions, the faulty device can send fault information to a fault analysis device so that the fault analysis device can determine that the fault is caused by a patch unit. Upon receiving information about the faulty patch unit from the fault analysis device, the faulty patch unit can be deenabled instead of the entire patch, which can reduce the de-enabling time. Moreover, after de-enabling, the operation of the services corresponding to the patch units that have not been de-enabled will not be affected, thereby reducing the impact of patch problems on services.

[0020] In one possible implementation, the first information may also include user information, and the patch configuration information may include the permission group of the patch unit. The first information is also used by the fault analysis device to determine that the permission group corresponding to the first patch unit includes the user information corresponding to the user.

[0021] In this embodiment of the application, the faulty device can only receive information about the faulty patch unit from the fault analysis device and can disable the faulty patch unit when the current user of the faulty device has the permission to disable it, thereby ensuring that only authorized users can enable it.

[0022] As one possible implementation, the patch configuration information may include the status of the patch unit. The fault handling method may also include: sending third information to the fault analysis device, the third information including the result information after the first patch unit is deenabled, and the third information being used by the fault analysis device to update the status of the first patch unit.

[0023] In this embodiment of the application, after the faulty device is deenabled, the result of the deenabled function can be returned to the fault analysis device so that the fault analysis device can update the status of the patch unit according to the result of the deenabled function, and thus determine the latest status of the patch unit by querying the status of the patch unit.

[0024] As one possible implementation, the patch configuration information may further include a tree structure, and the second information may further include information about the second patch unit, wherein the second patch unit is a patch unit in the patch configuration information that belongs to the same tree structure as the first patch unit; the fault handling method may further include: enabling the second patch unit according to the second information, and the third information may further include the result information after the second patch unit is enabled, and the third information is also used for the fault analysis device to update the status of the second patch unit.

[0025] In this embodiment, not only can the patch unit that causes the fault be deenabled, but also the patch units that are dependent on the patch unit can be enabled. This avoids the problem that the faulty device needs to process the service corresponding to the patch unit that is dependent on the patch unit, but cannot successfully process it due to the dependency relationship with the patch unit, thereby reducing unnecessary processing.

[0026] As one possible implementation, the fault information may include interrupt vectors and register information. The first information is used by the fault analysis device to determine the fault of the first patch unit, including: interrupt vectors and register information are used by the fault analysis device to determine the fault of the first patch unit.

[0027] In this embodiment, the fault analysis device can determine that a patch unit has failed based on the interrupt vector and register information, which can improve the efficiency of determining that a patch unit has failed.

[0028] As one possible implementation, the fault information may also include exception stack information, interrupt vectors, and register information for the fault analysis device to determine the fault of the first patch unit.

[0029] In this embodiment, the fault analysis device can determine that the patch unit has failed based on the interrupt vector, register information and exception stack information, which can improve the accuracy of determining that the patch unit has failed.

[0030] As one possible implementation, the register information may include a first instruction address, which is the instruction address corresponding to the fault. The interrupt vector and register information are used by the fault analysis device to determine the fault of the first patch unit, including: the interrupt vector and the first instruction address are used by the fault analysis device to determine the fault of the first patch unit.

[0031] As one possible implementation, the register information may include a first instruction address, which is the instruction address corresponding to the fault. The interrupt vector, register information, and exception stack information are used by the fault analysis device to determine the fault of the first patch unit.

[0032] As one possible implementation, the fault handling method may further include: receiving a first command, the first command carrying information about a third patch unit; and enabling the third patch unit according to the first command.

[0033] In this embodiment, the faulty device can enable only the patch units that need to be disabled according to the user's input command, instead of enabling the entire patch. This reduces the time required for de-enabling, and the operation of services corresponding to the patch units that were not disabled in the patch will not be affected after de-enabling, thereby reducing the impact of patch problems on services.

[0034] The third aspect discloses a fault handling apparatus, which can be a fault analysis device or a module (e.g., a chip) within a fault analysis device. The fault handling apparatus may include:

[0035] A receiving unit is configured to receive first information from a faulty device, the first information including fault information;

[0036] The determining unit is used to determine the fault of the first patch unit based on the first information, wherein the patch unit is the smallest functional unit in the patch;

[0037] A sending unit is configured to send second information to the faulty device, the second information including information of the first patching unit, and the second information is configured to disable the first patching unit.

[0038] In one possible implementation, the first information further includes user information, and the patch configuration information includes the permission group of the patch unit. The sending unit is specifically used to send the second information to the faulty device when the permission group corresponding to the first patch unit includes the user corresponding to the user information.

[0039] As one possible implementation, the patch configuration information includes the status of the patch unit. The receiving unit is also configured to receive third information from the faulty device, the third information including result information after the first patch unit is deenabled.

[0040] The fault handling device may also include:

[0041] An update unit is used to update the state of the first patch unit based on the third information.

[0042] As one possible implementation, the patch configuration information further includes a tree structure, the second information further includes information about a second patch unit, the second patch unit being a patch unit in the patch configuration information that belongs to the same tree structure as the first patch unit, the second information is also used to disable the second patch unit, the third information further includes result information after the second patch unit is disabled; the update unit is also used to update the state of the second patch unit according to the third information.

[0043] As one possible implementation, the fault information includes an interrupt vector and register information, and the determining unit is specifically used to determine the fault of the first patch unit based on the interrupt vector and the register information.

[0044] As one possible implementation, the fault information also includes exception stack information, and the determining unit determines the first patch unit fault based on the interrupt vector and the register information, including:

[0045] The fault in the first patch unit is determined based on the interrupt vector, the register information, and the exception stack information.

[0046] As one possible implementation, the register information includes a first instruction address, which is the instruction address corresponding to the fault. The determining unit determines the first patch unit fault based on the interrupt vector and the register information as follows:

[0047] Determine the interrupt type corresponding to the interrupt vector;

[0048] Obtain patch configuration information, which includes instruction address and instruction code;

[0049] When the interrupt type is a software interrupt and the patch configuration information includes the first instruction address, the first patch unit is determined to be faulty, and the first patch unit is the instruction code corresponding to the first instruction address in the patch configuration information.

[0050] As one possible implementation, the register information includes a first instruction address, which is the instruction address corresponding to the fault. The determining unit determines the first patch unit fault based on the interrupt vector, the register information, and the exception stack information, including:

[0051] Determine the interrupt type corresponding to the interrupt vector;

[0052] Obtain patch configuration information, which includes instruction address and instruction code;

[0053] When the interrupt type is a software interrupt, the patch configuration information includes the first instruction address, and the exception stack information includes the first instruction address, the first patch unit is determined to be faulty. The first patch unit is the instruction code corresponding to the first instruction address in the patch configuration information.

[0054] The fourth aspect discloses a fault handling device, which can be a faulty device or a module (e.g., a chip) within the faulty device, and the fault handling device may include:

[0055] The sending unit is used to send first information to the fault analysis device when a faulty device is detected to have a fault. The first information includes fault information. The first information is used by the fault analysis device to determine that the first patch unit is faulty. The patch unit is the smallest functional unit in the patch.

[0056] A receiving unit is configured to receive second information from the fault analysis device, the second information including information from the first patching unit;

[0057] The de-enable unit is used to enable the first patch unit according to the second information.

[0058] In one possible implementation, the first information further includes user information, the patch configuration information includes the permission group of the patch unit, and the first information is also used by the fault analysis device to determine that the permission group corresponding to the first patch unit includes the user corresponding to the user information.

[0059] As one possible implementation, the patch configuration information includes the status of the patch unit. The sending unit is also used to send third information to the fault analysis device. The third information includes the result information after the first patch unit is deenabled. The third information is used by the fault analysis device to update the status of the first patch unit.

[0060] As one possible implementation, the patch configuration information further includes a tree structure, and the second information further includes information about a second patch unit, wherein the second patch unit is a patch unit in the patch configuration information that belongs to the same tree structure as the first patch unit; the de-enable unit is further used to de-enable the second patch unit according to the second information, and the third information further includes result information after the second patch unit is de-enabled, and the third information is further used by the fault analysis device to update the status of the second patch unit.

[0061] As one possible implementation, the fault information includes interrupt vectors and register information, the first information being used by the fault analysis device to determine that the first patch unit fault includes:

[0062] The interrupt vector and the register information are used by the fault analysis device to determine the fault of the first patch unit.

[0063] As one possible implementation, the fault information also includes exception stack information, and the interrupt vector and register information are used by the fault analysis device to determine the fault of the first patch unit, including:

[0064] The interrupt vector, the register information, and the exception stack information are used by the fault analysis device to determine the fault of the first patch unit.

[0065] In one possible implementation, the register information includes a first instruction address, which is the instruction address corresponding to the fault. The interrupt vector and the register information are used by the fault analysis device to determine the fault of the first patch unit, including:

[0066] The interrupt vector and the first instruction address are used by the fault analysis device to determine the fault of the first patch unit.

[0067] As one possible implementation, the register information includes a first instruction address, which is the instruction address corresponding to the fault. The interrupt vector, the register information, and the exception stack information are used by the fault analysis device to determine the fault of the first patch unit, including:

[0068] The interrupt vector, the first instruction address, and the exception stack information are used by the fault analysis device to determine the fault of the first patch unit.

[0069] In one possible implementation, the receiving unit is further configured to receive a first command, the first command carrying information about the third patching unit;

[0070] The de-enable unit is also configured to de-enable the third patch unit according to the first command.

[0071] The fifth aspect discloses a fault handling apparatus, which may be a fault analysis device or a module (e.g., a chip) within a fault analysis device. The fault handling apparatus may include a processor, a memory, an input interface, and an output interface. The input interface is used to receive information from other devices besides the fault handling apparatus, and the output interface is used to output information to other devices besides the fault handling apparatus. When the processor executes a computer program stored in the memory, the processor performs the fault handling method disclosed in the first aspect or any embodiment of the first aspect.

[0072] The sixth aspect discloses a fault handling apparatus, which can be a faulty device or a module (e.g., a chip) within the faulty device. The fault handling apparatus may include a processor, a memory, an input interface, and an output interface. The input interface is used to receive information from other devices besides the fault handling apparatus, and the output interface is used to output information to other devices besides the fault handling apparatus. When the processor executes a computer program stored in the memory, the processor performs the fault handling method disclosed in the second aspect or any embodiment of the second aspect.

[0073] The seventh aspect discloses a fault handling system, which includes the fault handling apparatus of the fifth aspect and the fault handling apparatus of the sixth aspect.

[0074] The eighth aspect discloses a computer-readable storage medium storing a computer program or computer instructions that, when executed, implement the fault handling methods disclosed in the above aspects.

[0075] The ninth aspect discloses a chip including a processor for executing a computer program stored in a memory, which, when executed, causes the chip to perform the methods described above.

[0076] As one possible implementation, the memory is located outside the chip. Attached Figure Description

[0077] Figure 1 This is a schematic diagram of a network architecture disclosed in an embodiment of this application;

[0078] Figure 2 This is a schematic diagram of a patch disclosed in an embodiment of this application;

[0079] Figure 3 This is a schematic diagram illustrating the generation of patch configuration information as disclosed in an embodiment of this application;

[0080] Figure 4 This is a flowchart illustrating a fault handling method disclosed in an embodiment of this application;

[0081] Figure 5 This is a flowchart illustrating a method for determining a fault type disclosed in an embodiment of this application;

[0082] Figure 6 This is a flowchart illustrating another method for determining fault types disclosed in an embodiment of this application;

[0083] Figure 7 This is a flowchart illustrating another fault handling method disclosed in an embodiment of this application;

[0084] Figure 8 This is a schematic diagram of the structure of a fault handling device disclosed in an embodiment of this application;

[0085] Figure 9 This is a schematic diagram of another fault handling device disclosed in the embodiments of this application;

[0086] Figure 10 This is a schematic diagram of the structure of another fault handling device disclosed in the embodiments of this application;

[0087] Figure 11 This is a schematic diagram of the structure of another fault handling device disclosed in the embodiments of this application. Detailed Implementation

[0088] This application discloses a fault handling method, apparatus, and computer-readable storage medium to reduce the impact of patch issues on services. These are described in detail below.

[0089] To better understand the embodiments of this application, the application scenarios of these embodiments are described below. Currently, after a device has installed a patch, if the patch has software defects or compatibility issues, it may cause damage to basic business functions. Therefore, to solve the above problems, the entire patch package can be rolled back, that is, all installed parts of the patch package need to be rolled back to the state before installation, causing all updated content in the patch package to become invalid, thus damaging the services related to the patch package and causing secondary impact on the services. Alternatively, the patch can be upgraded and optimized; however, upgrades and optimizations take time, which may damage the services corresponding to the fault. Therefore, after the patch is installed, how to reduce the impact of patch problems on services has become an urgent technical problem to be solved.

[0090] For example, with the large-scale commercialization of 5G core networks, customers require core networks to have microservice-based patching capabilities, enabling rapid fixes of software defects and rapid commercial deployment for lightweight applications. Therefore, ensuring that the core network's basic service functions are unaffected by patch issues after patch installation has become a pressing technical problem.

[0091] It should be understood that the 5G core network is merely an illustrative description of the application scenario for the fault handling method in this application, and is not intended to limit it.

[0092] It should be understood that the fault handling method of this application can be applied to various software usage scenarios, and is not limited here.

[0093] Furthermore, because it cannot identify the location of defects, compatibility issues, or other problems in the patches, it cannot automatically roll back the patches, requiring manual rollback, which reduces rollback efficiency.

[0094] To better understand the fault handling method, apparatus, and computer-readable storage medium disclosed in the embodiments of this application, the network architecture used in the embodiments of this application is described below. Please refer to... Figure 1 , Figure 1 This is a schematic diagram of a network architecture disclosed in an embodiment of this application. For example... Figure 1 As shown, the network architecture may include a faulty device 101 and a fault analysis device 102. The faulty device 101 is used to send fault information to the fault analysis device 102 when a fault is detected. The fault analysis device 102 is used to receive the fault information from the faulty device 101, determine whether the fault is caused by a patch unit, and if so, send information about the patch unit to be rolled back to the faulty device 101. The faulty device 101 is also used to receive the information about the patch unit to be rolled back from the fault analysis device 102, disable the corresponding patch unit, and send the result information of the disabling to the fault analysis device 102 after disabling. The fault analysis device 102 is also used to receive the result information from the faulty device 101 and update the status of the corresponding patch unit based on the result information.

[0095] The faulty device is one that can install and update software and communicate with other devices, such as mobile phones, access and mobility management function (AMF) network elements, and session management function (SMF) network elements.

[0096] Fault analysis equipment is a device that can identify the fault type based on fault information. When the fault type is caused by a patch unit, it can determine the corresponding patch unit.

[0097] To better understand this application, the terms or concepts used in this application will be described below.

[0098] 1. Patch Unit

[0099] To address the issue of needing to roll back the entire patch package when software defects or compatibility problems exist during patch installation, this application divides patches into different patch units. A patch unit is the smallest functional unit within a patch, such as a function. Please refer to... Figure 2 , Figure 2 This is a schematic diagram of a patch disclosed in an embodiment of this application. For example... Figure 2 As shown, different incremental patches in a microservice patch can be broken down into different patch units. Therefore, when a patch fails during installation, the fault analysis device can determine which patch unit caused the failure.

[0100] It should be understood that Figure 2 This is merely an illustrative example of dividing patches into patch units and does not constitute a limitation on dividing patches into patch units.

[0101] 2. Patch Configuration Information

[0102] The status information of a patch unit can include its state, information (info), tree structure, access, and auto. The state of a patch unit can include enabled and disabled. When a patch unit is enabled, it indicates that the patch unit has been successfully installed and can be used normally. When a patch unit is disabled, it indicates that the patch unit was first installed and then uninstalled. The information of a patch unit can include basic information such as the instruction address (i.e., entry address) and instruction code (i.e., code segment). The instruction code is the computer instruction code used to identify the code of an instruction in the instruction set. The instruction address is the address information of the instruction code. For example, the information of patch unit 1 can be 0X00C0FFEE:1A2B3C4D, where 0X00C0FFEE represents the instruction address and 1A2B3C4D represents the instruction code. The tree structure of a patch unit is used to identify the tree structure to which the patch unit belongs. For example, the tree structure to which patch unit 2 belongs can be ARM01001. The access information for a patch unit is used to identify the group information of the permission group to which the patch unit belongs, that is, to identify the group information that has the permission to disable the patch unit. For example, if the access information for patch unit 3 is G01, it means that only members of the group corresponding to G01 have the permission to disable patch unit 3. The automatic access information for a patch unit is used to identify whether it has an intelligent disable function. When a patch unit has an intelligent disable function, after the fault analysis device determines that the fault is caused by the patch unit, it can allow the faulty device to disable the patch unit. When a patch unit does not have an intelligent disable function, after the fault analysis device determines that the fault is caused by the patch unit, it cannot allow the faulty device to disable the patch unit.

[0103] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating the generation of patch configuration information as disclosed in an embodiment of this application. For example... Figure 3 As shown, the state, info, tree, access, and auto of all patch units in a patch can be input into the patch configuration information generator. The patch configuration generator can then output the patch configuration information, as shown in Table 1.

[0104] index state info tree access auto 1 Enable 0X00C00020:1A2B3C4D ARM01001 G01 Y 2 Enable 0X00C0008A:5A6B7C8D ARM01002 G01 Y … … … … … …

[0105] Table 1 Patch Configuration Information

[0106] Therefore, patch configuration information can also include indexes of patch units. In one possible implementation, the patch configuration information generator can be a standalone device or a device located within a dedicated device. In one case, such as... Figure 3As shown, the fault analysis device needs to import patch configuration information generated by the patch configuration information generator. In another scenario, the fault analysis device can obtain patch configuration information from the device or equipment where the patch configuration information generator is located when needed. In yet another possible implementation, the patch configuration information generator can be located within the fault analysis device. The fault analysis device can import the state, info, tree, access, and auto of all patch units in the patch, and then the patch configuration information generator can generate the patch configuration information.

[0107] It should be understood that the status information of a patch unit may include parts of the patch unit's state, info, tree, access, and auto. For example, when the status information of a patch unit includes the patch unit's state, info, tree, and access, the patch configuration information can be as shown in Table 2:

[0108] index state info tree access 1 Enable 0X00C00020:1A2B3C4D ARM01001 G01 2 Enable 0X00C0008A:5A6B7C8D ARM01002 G01 … … … … …

[0109] Table 2 Patch Configuration Information

[0110] The fault analysis device can default to having intelligent disable functionality for all patch units. When the status information of a patch unit includes its state, info, and tree, the patch configuration information can be as shown in Table 3:

[0111] index state info tree 1 Enable 0X00C00020:1A2B3C4D ARM01001 2 Enable 0X00C0008A:5A6B7C8D ARM01002 … … … …

[0112] Table 3 Patch Configuration Information

[0113] The fault analysis device can default to having the intelligent disable function for all patch units, and all users have the permission to disable patch units.

[0114] It should be understood that there can be one patch corresponding to one patch configuration information, two or more patches corresponding to one patch configuration information, or all patches corresponding to one patch configuration information; no restrictions are imposed here.

[0115] It should be understood that a patch can be a patch package.

[0116] It should be understood that the above is merely an illustrative description of the status information and configuration information of the patch unit, and does not constitute a limitation.

[0117] 3. Interrupt vector

[0118] An interrupt is a situation that occurs during computer operation, requiring host intervention. The machine automatically stops the currently running program and switches to a program to handle the new situation. After handling the situation, it returns to the originally suspended program to continue running. An interrupt vector is information used to identify an interrupt. An interrupt vector can be understood as information about a malfunctioning device. An interrupt vector can be the entry address of an interrupt service routine, or other information that uniquely identifies the interrupt.

[0119] 4. Register Information

[0120] Registers are small storage areas within the central processing unit (CPU) used to temporarily store data involved in computation and the results of computation. In this application, registers can store the address of the currently executing instruction code. Registers can be routing information protocol (RIP) registers, program counter (PC) registers, or other registers that store the address of the currently executing instruction code; no limitation is made here. Register information can be the information stored in the registers. Instruction codes can be executed serially; correspondingly, only one instruction code is executed at a time, and therefore, only one instruction address of the currently executing instruction code is stored in the register. Instruction codes can also be executed in parallel; correspondingly, multiple instruction codes can be executed at a time, and therefore, multiple instruction addresses of the currently executing instruction codes can be stored in the register.

[0121] 5. Exception stack information

[0122] A stack is a linear data structure with restricted computation. An exception stack represents the stack containing information about a faulty device when it malfunctions. Exception stack information can be understood as the information contained within the exception stack corresponding to the faulty device when it malfunctions.

[0123] Based on the above network architecture, please refer to Figure 4 , Figure 4 This is a flowchart illustrating a fault handling method disclosed in an embodiment of this application. Figure 4 As shown, the fault handling method may include the following steps.

[0124] 401. When a fault is detected in a faulty device, the faulty device sends the first information to the fault analysis device.

[0125] Faulty equipment can monitor itself in real time. Faulty equipment can be equipped with a fault monitoring mechanism, which, once activated, allows it to monitor itself. This mechanism can be activated upon power-on, upon receiving fault information from a fault analysis device, or upon detecting other information, instructions, or messages that could trigger the fault monitoring mechanism; there are no specific limitations on this.

[0126] When a faulty device detects a fault, it can first determine the first piece of information and then send it to the fault analysis device. The first piece of information may include fault information, which may include interrupt vectors and register information. The fault information may also include exception stack information. Detailed descriptions of interrupt vectors, register information, and exception stack information can be found in the aforementioned descriptions and will not be repeated here. Register information may include a first instruction address. The first instruction address is the instruction address corresponding to the fault; it can be understood as the address of the instruction code stored in the register at the time the fault occurred, or as the address of the instruction code being executed at the time the fault occurred.

[0127] The first piece of information may also include user information. This user information may be the information of the user currently using the faulty device. The user information may be a username, an account, or other information that uniquely identifies the user.

[0128] The first piece of information may also include information about the patch corresponding to the fault. This patch can be understood as the patch that was being installed or running at the time the fault occurred. The patch information can include the patch's name, version, and other unique identifiers.

[0129] Accordingly, the fault analysis equipment receives the first information from the faulty equipment.

[0130] 402. The fault analysis equipment determines the fault of the first patch unit based on the first information.

[0131] After receiving the first information from the faulty device, the fault analysis equipment can determine the fault of the first patch unit based on the first information. A patch unit fault can be understood as a fault generated or caused by the patch unit.

[0132] In one possible implementation, the fault analysis device can determine the first patch unit fault based on the interrupt vector and register information. (See also...) Figure 5 , Figure 5 This is a flowchart illustrating a method for determining a fault type disclosed in an embodiment of this application. Figure 5As shown, the fault analysis device can first determine the interrupt type corresponding to the interrupt vector. For example, the fault analysis device can first determine the vector number corresponding to the interrupt vector, and then determine the interrupt type corresponding to the vector number as the interrupt type corresponding to the interrupt vector. The fault analysis device can then determine whether the interrupt type is a software interrupt. When the interrupt type is determined to be a hardware interrupt, it indicates that the fault is hardware-related, and the fault analysis device can discard the first piece of information. When the interrupt type is determined to be a software interrupt, it indicates that the fault is software-related, and the fault analysis device can obtain patch configuration information. When different patches correspond to the same patch configuration information, the fault analysis device can directly obtain the patch configuration information. When different patches may correspond to different patch configuration information, the fault analysis device can obtain the patch configuration information based on the patch information, that is, obtain the patch configuration information corresponding to the patch information. The patch configuration information can be stored in the fault analysis device or in other devices or equipment, without limitation. The fault analysis device can obtain patch configuration information locally or from other devices or equipment. The patch configuration information may include instruction addresses and instruction codes.

[0133] The fault analysis device can then determine whether the patch configuration information includes the first instruction address. If the patch configuration information does not include the first instruction address, it indicates that the fault is a software fault, but not caused by a patch unit, and the fault analysis device can discard the first information. If the patch configuration information includes the first instruction address, the fault analysis device can determine that the fault is a software fault and that it is caused by a patch unit, i.e., it determines that the first patch unit is faulty. The first patch unit is the instruction code corresponding to the first instruction address in the patch configuration information. The first patch unit can be understood as the patch unit corresponding to the fault, or it can be understood as the patch unit that was running when the fault occurred.

[0134] In another possible implementation, the fault analysis device can determine the first patch unit fault based on the interrupt vector, register information, and exception stack information. (See also...) Figure 6 , Figure 6 This is a flowchart illustrating another method for determining fault types disclosed in an embodiment of this application. Figure 6As shown, the fault analysis device can first determine the interrupt type corresponding to the interrupt vector, and then determine whether the interrupt type is a software interrupt. When the interrupt type is determined to be a hardware interrupt, the fault analysis device can discard the first information. When the interrupt type is determined to be a software interrupt, the fault analysis device can obtain patch configuration information. Patch configuration information may include instruction address and instruction code. The fault analysis device can then continue to determine whether the patch configuration information includes the first instruction address and whether the exception stack information includes the first instruction address. When it is determined that the patch configuration information does not include the first instruction address, or the exception stack information does not include the first instruction address, it indicates that the fault is a software fault, but not caused by the patch unit, and the fault analysis device can discard the first information. When it is determined that the patch configuration information includes the first instruction address and the exception stack information includes the first instruction address, the fault device can determine that the fault is a software fault and that the fault is caused by the patch unit, i.e., it determines that the first patch unit is faulty. The description of relevant information can be found in [reference needed]. Figure 5 The relevant descriptions will not be elaborated here.

[0135] Patch configuration information can also include a tree structure. Because patch units belonging to the same tree structure have dependencies, when the first patch unit is disabled, other patch units within the same tree structure cannot process services correctly. Therefore, patch units within the same tree structure can be disabled together. The fault analysis equipment can then identify the second patch unit. The second patch unit is the patch unit in the patch configuration information that belongs to the same tree structure as the first patch unit.

[0136] For example, function A calls function B, and function B calls function C. Functions A, B, and C are different patch units belonging to the same tree structure. When the fault is caused by function C, after disabling function C, functions A and B will not function properly because of the calling relationship between them. Therefore, functions A and B, along with function C, can be identified as patch units that need to be disabled.

[0137] It should be understood that the examples above are merely illustrative and do not constitute a limitation.

[0138] 403. The fault analysis equipment sends a second message to the faulty equipment.

[0139] After the fault analysis device determines that the first patch unit is faulty based on the first information, it can send second information to the faulty device. The second information may include information about the first patch unit. Furthermore, the second information may also include information about the second patch unit.

[0140] In one implementation, the fault analysis device can directly send second information to the faulty device.

[0141] In another implementation, the patch configuration information may also include the permission group of the patch unit. Not all users have the permission to enable a particular patch unit. Therefore, the fault analysis device can first determine whether the permission group of the first patch unit includes the user corresponding to the user information, that is, whether the user corresponding to the user information belongs to the permission group corresponding to the first patch unit, or whether the user corresponding to the user information is a member of the permission group corresponding to the first patch unit. When it is determined that the permission group of the first patch unit includes the user corresponding to the user information, it indicates that the user corresponding to the patch has the permission to enable the first patch unit, and the fault analysis device can send the second information to the faulty device. When it is determined that the permission group of the first patch unit does not include the user information, it indicates that the user corresponding to the patch does not have the permission to enable the first patch unit, and the fault analysis device may not send the second information to the faulty device.

[0142] Similarly, if the second information includes information about the second patch unit, the fault analysis device also needs to determine whether the permission group of the second patch unit includes the user corresponding to the user information. When it is determined that the permission group of the first patch unit includes the user corresponding to the user information, and the permission group of the second patch unit also includes the user corresponding to the user information, the fault analysis device can send the second information to the faulty device.

[0143] Fault analysis equipment can send secondary information to the faulty device via requests, messages, signaling, etc. For example, the fault analysis equipment can send secondary information to the faulty device via a network configuration protocol (Netconf) request.

[0144] Accordingly, the faulty device receives second information from the fault analysis device.

[0145] 404. The faulty device enables the first patch unit based on the second information.

[0146] After receiving the second information from the fault analysis device, the faulty device can enable the first patch unit based on the second information. When the second information only includes information about the first patch unit, the faulty device can enable the first patch unit corresponding to the information included in the second information, that is, revert the first patch unit corresponding to the second information to a state where the first patch unit is not installed. When the second information also includes information about the first patch unit and a tree structure, the faulty device can first determine the position of the first patch unit in the tree based on the tree structure, then determine the position of the first patch unit in the tree based on the information of the first patch unit, and finally enable it.

[0147] If the second information also includes information about the second patch unit, the faulty device can also enable the second patch unit based on the second information. For a detailed description, please refer to the description of enabling the first patch unit.

[0148] For example, suppose the interrupt vector is A and the register information is B. The fault analysis device determines that the interrupt type corresponding to A is a software interrupt, finds the patch unit X corresponding to B in the patch configuration information, and the current user has the permission to enable patch unit X. Therefore, the faulty device can enable patch unit X.

[0149] The relevant content in steps 401-404 can be referenced from each other and is not limited to the corresponding steps.

[0150] Based on the above network architecture, please refer to Figure 7 , Figure 7 This is a flowchart illustrating another fault handling method disclosed in an embodiment of this application. Figure 7 As shown, the fault handling method may include the following steps.

[0151] 701. Establish a connection between the faulty equipment and the fault analysis equipment.

[0152] A faulty device can establish a connection with a fault analysis device, that is, an interactive tunnel is established between the faulty device and the fault analysis device. This connection can be established after the faulty device powers on, when the faulty device needs the fault analysis device to disable a patch fault, when the fault analysis device needs to disable a patch fault on the faulty device, or for other reasons; there are no restrictions on this. The establishment of this connection can be initiated by either the faulty device or the fault analysis device; there are no restrictions on this. The connection between the faulty device and the fault analysis device can be a Transmission Control Protocol (TCP) connection or any other communication-enabled connection; there are no restrictions on this.

[0153] 702. The faulty equipment activates the fault monitoring mechanism.

[0154] After the faulty device establishes a connection with the fault analysis device, a fault monitoring mechanism can be activated so that the faulty device can monitor itself in real time. The faulty device can be configured with a fault monitoring mechanism, which, once activated, allows it to monitor itself. This fault monitoring mechanism can be activated upon power-on, upon receiving fault monitoring information from the fault analysis device, upon establishing a connection with the fault analysis device, or upon detecting other information, instructions, or messages that could trigger the fault monitoring mechanism; there are no specific limitations on this.

[0155] 703. When a fault is detected in a faulty device, the faulty device sends the first information to the fault analysis device.

[0156] When a faulty device detects a fault, it can first determine the first piece of information and then send it to the fault analysis device. The first piece of information may include fault information, which may include interrupt vectors and register information. The fault information may also include exception stack information. Detailed descriptions of interrupt vectors, register information, and exception stack information can be found in the aforementioned descriptions and will not be repeated here. Register information may include a first instruction address. The first instruction address is the instruction address corresponding to the fault; it can be understood as the address of the instruction code stored in the register at the time the fault occurred.

[0157] The first piece of information may also include user information. This user information may be the information of the user currently using the faulty device. The user information may be a username, an account, or other information that uniquely identifies the user.

[0158] The first piece of information may also include information about the patch corresponding to the fault. This corresponding patch can be understood as the patch that was being installed at the time the fault occurred. The patch information can include the patch's name, version, and other uniquely identifying information.

[0159] Accordingly, the fault analysis equipment receives the first information from the faulty equipment.

[0160] 704. The fault analysis equipment determines the fault of the first patch unit based on the first information.

[0161] Step 704 is the same as step 402. For a detailed description, please refer to step 402. It will not be repeated here.

[0162] 705. The fault analysis equipment sends a second message to the faulty equipment.

[0163] Step 705 is the same as step 403. For a detailed description, please refer to step 403. It will not be repeated here.

[0164] 706. The faulty device enables the first patch unit based on the second information.

[0165] Step 706 is the same as step 404. For a detailed description, please refer to step 404. It will not be repeated here.

[0166] 707. The faulty device sends third information to the fault analysis device.

[0167] After the faulty device disables the first patch unit, it can send third information to the fault analysis device. The third information may include the result information after disabling the first patch unit. The third information may also include the result information after disabling the second patch unit. The third information may include information indicating that the first patch unit was successfully disabled, or information indicating that the first patch unit failed to be disabled. The third information may also include information indicating that the second patch unit was successfully disabled, or information indicating that the first patch unit (and both patch units) failed to be disabled.

[0168] Accordingly, the fault analysis equipment can receive third-party information from the faulty equipment.

[0169] 708. The fault analysis equipment updates the status of the first patch unit based on the third information.

[0170] When the status information of a patch unit includes the status of the patch unit, the fault analysis device can update the status of the first patch unit based on the third information. When the third information includes information indicating that the first patch unit was successfully deenabled, if the status of the first patch unit in the patch configuration information is enabled, then the status of the first patch unit is updated to disabled. When the third information includes information indicating that the first patch unit failed to be deenabled, if the status of the first patch unit in the patch configuration information is enabled, then the status of the first patch unit does not need to be updated. Therefore, the fault analysis device only needs to update the status of the first patch unit in the patch configuration information when the status of the first patch unit in the patch configuration information differs from the current status of the first patch unit. The fault analysis device can also update the status of the second patch unit based on the third information.

[0171] After receiving the third message from the faulty device, if the third message includes information indicating that the first patch unit failed to be enabled, the faulty device can send the second message again to the faulty device so that the faulty device can re-enable the first patch unit. If multiple attempts to enable the patch unit fail, the fault analysis system can output a message to the user indicating a problem with the patch unit, allowing the user to resolve the issue. This output message can be displayed on the fault analysis device, issued as an alarm, sent to the user's corresponding terminal device, sent to the user's email address, or any other method; no limitation is made here.

[0172] In one implementation, the fault analysis device can maintain a fault identification table. When it is determined that the fault is caused by a patch unit, the fault information can be recorded in the fault identification table. The fault identification table can be as shown in Table 4.

[0173] index Interruption vector Register information Exception stack information Faulty equipment information De-enable result 1 Vector 1 A1 B1 Equipment 1 success 2 Vector 1 A2 B2 Equipment 2 fail … … … … … …

[0174] Table 4 Fault Identification Table

[0175] Table 4 is merely an illustrative example of the fault identification table and does not constitute a limitation thereof.

[0176] Fault analysis equipment can count the number of times a patch unit fails based on a fault identification table. When the number of failures reaches a threshold, it indicates that this patch unit will inevitably cause a failure. The fault analysis equipment can output a prompt message to the user indicating that this patch unit has a problem, so that software developers can improve the patch based on the prompt message. In addition, when the number of failures reaches the threshold and it is confirmed that a device is installing the patch corresponding to this patch unit, the device can be directly enabled to enable this patch unit.

[0177] In one implementation, the faulty device can receive a first command carrying information about a third patch unit. The third patch unit can then be enabled based on the first command, meaning the third patch unit corresponding to that information can be enabled. When a software developer believes a patch unit has a problem, they can input the first command into the faulty device, or send the first command to the faulty device from another device. The aforementioned problem can be one that causes a fault or one that does not. For example, if a softkey developer modifies the charging rules during softkey development, and the modified charging rules are incorrect but do not cause a fault, the corresponding patch unit can be enabled to restore the correct charging rules. The above example is merely illustrative and does not constitute a limitation on problems that will not cause a fault.

[0178] In one implementation, after the faulty device successfully disables the patch unit, it can detect whether disabling the patch unit will affect the faulty device's services. If it is detected that disabling the patch unit will affect the faulty device's services, it can output prompts to the user that the services cannot run, so that the user can resolve the issue in a timely manner.

[0179] For a detailed description of steps 701-708, please refer to the corresponding descriptions above.

[0180] It should be understood that the above Figure 4 and Figure 7 In the corresponding fault handling method, the functions performed by the faulty device can also be performed by modules (e.g., chips) in the faulty device, and the functions performed by the fault analysis device can also be performed by modules (e.g., chips) in the fault analysis device.

[0181] Based on the above network architecture, please refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of a fault handling device disclosed in an embodiment of this application. Figure 8 As shown, the fault handling device may include:

[0182] The receiving unit 801 is used to receive first information from the faulty device, the first information including fault information;

[0183] Determining unit 802 is used to determine the fault of the first patch unit based on the first information, wherein the patch unit is the smallest functional unit in the patch;

[0184] The sending unit 803 is used to send second information to the faulty device. The second information includes information about the first patching unit and is used to disable the first patching unit.

[0185] In one embodiment, the first information may further include user information, the patch configuration information may include the permission group of the patch unit, and the sending unit 803 is specifically used to send the second information to the faulty device when the permission group corresponding to the first patch unit includes the user corresponding to the user information.

[0186] In one embodiment, the patch configuration information may include the status of the patch unit. The receiving unit 801 is also used to receive third information from the faulty device. The third information includes the result information after the first patch unit is deenabled.

[0187] The fault handling device may also include:

[0188] Update unit 804 is used to update the status of the first patch unit based on the third information.

[0189] In one embodiment, the patch configuration information may further include a tree structure, and the second information may further include information about a second patch unit, wherein the second patch unit is a patch unit in the patch configuration information that belongs to the same tree structure as the first patch unit. The second information is also used to disable the second patch unit, and the third information further includes the result information after the second patch unit is disabled.

[0190] Update unit 804 is also used to update the status of the second patch unit based on the third information.

[0191] In one embodiment, the fault information may include interrupt vector and register information, and the determining unit 802 is specifically used to determine the fault of the first patch unit based on the interrupt vector and register information.

[0192] In one embodiment, the fault information may further include exception stack information. The determining unit 802 determines the fault of the first patch unit based on the interrupt vector and register information, including:

[0193] The fault in the first patch unit was determined based on the interrupt vector, register information, and exception stack information.

[0194] In one embodiment, the register information may include a first instruction address, which is the instruction address corresponding to the fault. The determining unit 802 determines the first patch unit fault based on the interrupt vector and register information, including:

[0195] Determine the interrupt type corresponding to the interrupt vector;

[0196] Obtain patch configuration information, which includes instruction addresses and instruction codes;

[0197] When the interrupt type is software interrupt and the patch configuration information includes the first instruction address, the first patch unit is determined to be faulty. The first patch unit is the instruction code corresponding to the first instruction address in the patch configuration information.

[0198] In one embodiment, the register information may include a first instruction address, which is the instruction address corresponding to the fault. The determining unit 802 determines the first patching unit fault based on the interrupt vector, register information, and exception stack information, including:

[0199] Determine the interrupt type corresponding to the interrupt vector;

[0200] Obtain patch configuration information, which includes instruction addresses and instruction codes;

[0201] When the interrupt type is a software interrupt, the patch configuration information includes the first instruction address, and the exception stack information includes the first instruction address, the first patch unit is determined to be faulty. The first patch unit is the instruction code corresponding to the first instruction address in the patch configuration information.

[0202] For a more detailed description of the receiving unit 801, determining unit 802, sending unit 803, and updating unit 804, please refer directly to the above description. Figure 4 and Figure 7 The description of the fault analysis device in the method embodiment shown is directly obtained and will not be repeated here.

[0203] Based on the above network architecture, please refer to Figure 9 , Figure 9 This is a schematic diagram of another fault handling device disclosed in an embodiment of this application. Figure 9 As shown, the fault handling device may include:

[0204] The sending unit 901 is used to send first information to the fault analysis device when a faulty device is detected to have a fault. The first information includes fault information. The first information is used by the fault analysis device to determine that the first patch unit is faulty. The patch unit is the smallest functional unit in the patch.

[0205] The receiving unit 902 is used to receive second information from the fault analysis device, the second information including information from the first patching unit;

[0206] De-enable unit 903 is used to de-enable the first patch unit based on the second information.

[0207] In one embodiment, the first information may further include user information, the patch configuration information may include the permission group of the patch unit, and the first information is also used by the fault analysis device to determine that the permission group corresponding to the first patch unit includes the user information corresponding to the user.

[0208] In one embodiment, the patch configuration information may include the status of the patch unit. The sending unit 901 is also used to send third information to the fault analysis device. The third information includes the result information after the first patch unit is deenabled. The third information is used by the fault analysis device to update the status of the first patch unit.

[0209] In one embodiment, the patch configuration information may further include a tree structure, and the second information may further include information about a second patch unit, wherein the second patch unit is a patch unit in the patch configuration information that belongs to the same tree structure as the first patch unit.

[0210] The de-enable unit 903 is also used to enable the second patch unit according to the second information. The third information may also include the result information after the second patch unit is de-enabled. The third information is also used by the fault analysis device to update the status of the second patch unit.

[0211] In one embodiment, the fault information may include interrupt vectors and register information, wherein the first information is used by the fault analysis device to determine that the first patch unit is faulty, including:

[0212] Interrupt vectors and register information are used by the fault analysis device to determine the fault of the first patch unit.

[0213] In one embodiment, the fault information may further include exception stack information, interrupt vectors, and register information used by the fault analysis device to determine the fault of the first patch unit, including:

[0214] Interrupt vectors, register information, and exception stack information are used by the fault analysis device to determine the fault of the first patch unit.

[0215] In one embodiment, the register information includes a first instruction address, which is the instruction address corresponding to the fault. The interrupt vector and register information are used by the fault analysis device to determine the fault of the first patch unit, including:

[0216] The interrupt vector and the first instruction address are used by the fault analysis device to determine the fault of the first patch unit.

[0217] In one embodiment, the register information includes a first instruction address, which is the instruction address corresponding to the fault. The interrupt vector, register information, and exception stack information are used by the fault analysis device to determine the fault of the first patch unit, including:

[0218] Interrupt vector, first instruction address, and exception stack information are used by the fault analysis device to determine the fault of the first patch unit.

[0219] In one embodiment, the receiving unit 902 is further configured to receive a first command, the first command carrying information of the third patching unit;

[0220] The de-enable unit 903 is also used to de-enable the third patch unit according to the first command.

[0221] For a more detailed description of the aforementioned transmitting unit 901, receiving unit 902, and deactivation unit 903, please refer directly to the above description. Figure 4 and Figure 7 The description of the faulty device in the method embodiment shown is obtained directly and will not be repeated here.

[0222] Based on the above network architecture, please refer to Figure 10 , Figure 10 This is a schematic diagram of the structure of another fault handling device disclosed in the embodiments of this application. For example... Figure 10 As shown, the fault handling device may include a processor 1001, a memory 1002, an input interface 1003, an output interface 1004, and a connecting cable 1005. The memory 1002 may be independent and connected to the processor 1001 via the bus 1005. Alternatively, the memory 1002 may be integrated with the processor 1001. The connecting cable 1005 is used to connect these components.

[0223] In one embodiment, the fault handling device can be a fault analysis device or a module (e.g., a chip) within the fault analysis device. When the computer program instructions stored in the memory 1002 are executed, the processor 1001 is used to control the receiving unit 801 and the sending unit 803 to perform the operations performed in the above embodiment. The processor 1001 is also used to execute the operations performed by the determining unit 802 and the updating unit 804 in the above embodiment. The input interface 1003 is used to execute the operations performed by the receiving unit 801 in the above embodiment, and the output interface 1004 is used to execute the operations performed by the sending unit 803 in the above embodiment. The fault analysis device or the module within the fault analysis device can also be used to perform the above... Figure 4 and Figure 7 The various methods executed by the fault analysis device in the method embodiments will not be described in detail.

[0224] In one embodiment, the fault handling device can be a faulty device or a module (e.g., a chip) within the faulty device. When the computer program instructions stored in the memory 1002 are executed, the processor 1001 controls the transmitting unit 901 and the receiving unit 902 to perform the operations performed in the above embodiment. The processor 1001 is also used to execute the operations performed by the de-enable unit 903 in the above embodiment. The input interface 1003 is used to execute the operations performed by the receiving unit 902 in the above embodiment, and the output interface 1004 is used to execute the operations performed by the transmitting unit 901 in the above embodiment. The faulty device or the module within the faulty device can also be used to perform the above... Figure 4 and Figure 7 The various methods executed by the faulty device in the method embodiments will not be described in detail.

[0225] Based on the above network architecture, please refer to Figure 11 , Figure 11 This is a schematic diagram of the structure of another fault handling device disclosed in the embodiments of this application. For example... Figure 11As shown, the fault handling device may include an input interface 1101, a logic circuit 1102, and an output interface 1103. The input interface 1101 and the output interface 1103 are connected via the logic circuit 1102. The input interface 1101 is used to receive information from other devices, and the output interface 1103 is used to output, schedule, or send information to other devices. The logic circuit 1102 is used to perform operations other than those of the input interface 1101 and the output interface 1103, such as implementing the functions of the processor 1001 in the above embodiments. The fault handling device may be a fault analysis device or a module of a fault analysis device, or it may be a fault device or a module of a fault device. A more detailed description of the input interface 1101, the logic circuit 1102, and the output interface 1103 can be directly obtained by referring to the relevant descriptions of the fault analysis device or the fault device in the above method embodiments, and will not be repeated here.

[0226] This application also discloses a computer-readable storage medium storing computer instructions that, when executed, perform the methods described in the above method embodiments.

[0227] This application also discloses a computer program product including computer instructions, which, when executed, perform the methods described in the above method embodiments.

[0228] This application also discloses a fault handling system, which includes fault equipment and fault analysis equipment, as detailed in the following description. Figure 4 and Figure 7 .

[0229] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of this application should be included within the scope of protection of this application.

Claims

1. A fault handling method, characterized in that, include: Receive first information from the faulty device. The first information includes fault information, which includes interrupt vectors and register information. The register information includes a first instruction address, which is the instruction address corresponding to the instruction code being executed at the time of the fault. The first information also includes information about the fault-corresponding patch, which is a patch being installed or running at the time of the fault. Determine the interrupt type corresponding to the interrupt vector; When the interrupt type is determined to be a software interrupt, the patch configuration information is obtained based on the patch information. When the patch configuration information includes the first instruction address, the fault is determined to be caused by a patch unit; the instruction code corresponding to the first instruction address in the patch configuration information is determined to be the first patch unit of the fault; the patch unit is the smallest functional unit in the patch; Send a second message to the faulty device. The second message includes information about the first patch unit. The second message is used to disable the first patch unit. Disabling the first patch unit includes: reverting the first patch unit to a state where the first patch unit is not installed.

2. The method according to claim 1, characterized in that, The first information also includes user information, and the patch configuration information includes the permission group of the patch unit. Sending the second information to the faulty device includes: When the permission group corresponding to the first patch unit includes the user corresponding to the user information, the second information is sent to the faulty device.

3. The method according to claim 1, characterized in that, The patch configuration information includes the status of the patch unit, and the method further includes: Receive third information from the faulty device, the third information including result information after the first patch unit is disabled; The state of the first patch unit is updated based on the third information.

4. The method according to claim 3, characterized in that, The patch configuration information also includes a tree structure. The second information also includes information about a second patch unit, which is a patch unit in the patch configuration information that belongs to the same tree structure as the first patch unit. The second information is also used to disable the second patch unit. The third information also includes the result information after the second patch unit is disabled. The method further includes: The state of the second patch unit is updated based on the third information.

5. The method according to claim 1, characterized in that, The fault information also includes exception stack information. The step of determining that the fault is caused by a patch unit when the patch configuration information includes the first instruction address includes: When the patch configuration information includes the first instruction address and the exception stack information includes the first instruction address, the fault is determined to be a fault caused by the patch unit.

6. A fault handling method, characterized in that, include: When a fault is detected in a device, first information is sent to a fault analysis device. This first information includes fault information, which includes an interrupt vector and register information. The register information includes a first instruction address, which is the address of the instruction code being executed at the time of the fault. The first information also includes information about a corresponding patch, which is either a patch being installed or running at the time of the fault. The interrupt vector is used by the fault analysis device to determine the interrupt type. When the interrupt type is a software interrupt, the patch information is used by the fault analysis device to obtain patch configuration information. When the patch configuration information includes the first instruction address, it is determined that the fault is caused by a patch unit, and the instruction code corresponding to the first instruction address in the patch configuration information is the first patch unit of the fault. Receive second information from the fault analysis device, the second information including information from the first patching unit; To enable the first patch unit based on the second information, the first patch unit is deactivated by: reverting the first patch unit to a state where the first patch unit is not installed.

7. The method according to claim 6, characterized in that, The first information also includes user information, and the patch configuration information includes the permission group of the patch unit. The first information is also used by the fault analysis device to determine that the permission group corresponding to the first patch unit includes the user corresponding to the user information.

8. The method according to claim 6, characterized in that, The patch configuration information includes the status of the patch unit, and the method further includes: The fault analysis device sends a third message, which includes the result information after the first patch unit is deenabled. The third message is used by the fault analysis device to update the status of the first patch unit.

9. The method according to claim 8, characterized in that, The patch configuration information also includes a tree structure, and the second information also includes information about a second patch unit, wherein the second patch unit is a patch unit in the patch configuration information that belongs to the same tree structure as the first patch unit. The method further includes: The second patch unit is enabled based on the second information. The third information also includes the result information after the second patch unit is disabled. The third information is also used by the fault analysis device to update the status of the second patch unit.

10. The method according to claim 6, characterized in that, The fault information also includes exception stack information. When the patch configuration information includes the first instruction address, determining that the fault is caused by a patch unit includes: When the patch configuration information includes the first instruction address and the exception stack information includes the first instruction address, the fault is determined to be a fault caused by the patch unit.

11. The method according to any one of claims 6-10, characterized in that, The method further includes: Receive a first command, which carries information about the third patch unit; Enable the third patch unit according to the first command.

12. A fault handling device, characterized in that, The apparatus includes a unit for performing the method as described in any one of claims 1-5.

13. A fault handling device, characterized in that, The apparatus includes a unit for performing the method as described in any one of claims 6-11.

14. A fault handling device, characterized in that, The device includes a processor, a memory, an input interface, and an output interface. The input interface is used to receive information from other devices outside the device, and the output interface is used to output information to other devices outside the device. The processor calls a computer program stored in the memory to implement the method as described in any one of claims 1-5.

15. A fault handling device, characterized in that, The device includes a processor, a memory, an input interface, and an output interface. The input interface is used to receive information from other devices outside the device, and the output interface is used to output information to other devices outside the device. The processor calls a computer program stored in the memory to implement the method as described in any one of claims 6-11.

16. A fault handling system, characterized in that, Includes the apparatus as described in claim 12 and the apparatus as described in claim 13.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or computer instructions that, when executed, implement the method as described in any one of claims 1-11.

18. A chip, characterized in that, The device includes a processor for executing a computer program stored in a memory, which, when executed, causes the chip to perform the method as described in any one of claims 1-11.

19. A computer program product comprising computer instructions, characterized in that, When the computer instructions are executed, they are used to perform the method as described in any one of claims 1-11.

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