A chip verification method, device, electronic device, and storage medium

Abstract

Embodiments of the present invention disclose a chip verification method, device, electronic device, and storage medium, which relate to the field of electronic design automation and can effectively improve the chip verification efficiency. The method includes: monitoring the operation progress of the verification operation on the chip to be verified, where the verification operation includes at least one of the following: verification environment initialization operation, test case simulation operation; setting a checkpoint at a preset time point after the start of the verification operation and before the end of the verification operation according to the operation progress, and recording the circuit simulation state corresponding to the checkpoint; and based on the simulation instruction, starting from the checkpoint, re-performing the verification operation on the chip to be verified based on the circuit simulation state. The present invention is applicable to chip verification.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation, and particularly to a chip verification method and apparatus, an electronic device, and a storage medium. Background Art

[0002] In the field of integrated circuit technology, before a chip is delivered to a foundry for manufacturing, it usually undergoes a series of verifications to ensure that the manufactured chip can meet the design requirements. With the rapid development of integrated circuit technology, the design schemes of chips have become increasingly complex, and correspondingly, the requirements for chip verification schemes have also become higher. Especially for the system-level verification of SOC (System-on-Chip), the requirement for its simulation speed is also getting higher and higher.

[0003] Regarding the existing SOC-level verification environment, generally, systemverilog + system c languages are used to build the verification environment, that is, the basic components of the verification environment are written in systemverilog language, while the initialization sequence and test case sequence are written in system c language. The basic components call the initialization sequence and test case sequence respectively through the DPI (Direct Programming Interface) call method. In this way, after changing the initialization sequence or test case, only the corresponding dynamic link library needs to be regenerated, and then the simulation can be performed again. This avoids the process of recompiling when changing systemverilog components, thus saving several hours of time.

[0004] However, as the SOC system becomes larger and larger, even though the compilation time is saved, the time for the initialization sequence and the time for executing the test case sequence are still as long as several hours or even dozens of hours. Therefore, the verification efficiency of the SOC system still needs to be further improved. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a chip verification method and apparatus, an electronic device, and a computer-readable storage medium, which can effectively improve the chip verification efficiency.

[0006] In a first aspect, an embodiment of the present invention provides a chip verification method, including: monitoring the operation progress of a verification operation on a chip to be verified, where the verification operation includes at least one of the following: verification environment initialization operation, test case simulation operation; setting a checkpoint at a preset time point after the start of the verification operation and before the end of the verification operation according to the operation progress, and recording the circuit simulation state corresponding to the checkpoint; and based on the circuit simulation state, restarting the verification operation on the chip to be verified from the checkpoint according to a simulation instruction.

[0007] Optionally, monitoring the operation progress of the verification operation on the chip to be verified includes: monitoring the operation progress of the verification operation by monitoring a preset function for calling a test case; according to the operation progress, setting checkpoints at preset time points after the start of the verification operation and before the end of the verification operation, and recording the circuit simulation state corresponding to the checkpoints includes: when it is monitored that the preset function calls the test case, setting the checkpoints in the verification operation and recording the circuit simulation state corresponding to the checkpoints.

[0008] Optionally, monitoring the operation progress of the verification operation on the chip to be verified includes: loading a compiled file corresponding to the verification operation, where the compiled file includes at least two compiled sub-files, and each of the compiled sub-files is divided according to the sequence of simulation time; monitoring the operation progress of the verification operation by monitoring whether each of the compiled sub-files has been executed.

[0009] Optionally, according to the operation progress, setting checkpoints at preset time points after the start of the verification operation and before the end of the verification operation, and recording the circuit simulation state corresponding to the checkpoints includes: when it is monitored that a preset compiled sub-file has ended execution or is about to start execution, setting the checkpoints in the verification operation and recording the circuit simulation state corresponding to the checkpoints.

[0010] Optionally, the number of the preset compiled sub-files is one or more, and the number of the checkpoints corresponds to the number of the preset compiled sub-files.

[0011] Optionally, according to the operation progress, setting checkpoints at preset time points after the start of the verification operation and before the end of the verification operation, and recording the circuit simulation state corresponding to the checkpoints includes: according to the operation progress, setting checkpoints at at least two time points after the start of the verification operation and before the end of the verification operation, and recording the circuit simulation state corresponding to the checkpoints; according to the simulation instruction, starting from the checkpoints, re-verifying the chip to be verified based on the circuit simulation state includes: according to the simulation instruction, selecting a target checkpoint from the checkpoints corresponding to the at least two time points; starting from the target checkpoint, re-verifying the chip to be verified based on the circuit simulation state corresponding to the target checkpoint.

[0012] Second aspect, an embodiment of the present invention further provides a chip verification device, including: a monitoring unit, configured to monitor the operation progress of the verification operation on the chip to be verified, where the verification operation includes at least one of the following: verification environment initialization operation, test case simulation operation; a setting unit, configured to set a checkpoint at a preset time point after the verification operation starts and before the verification operation ends according to the operation progress, and record the circuit simulation state corresponding to the checkpoint; a re-verification unit, configured to re-perform the verification operation on the chip to be verified from the checkpoint based on the circuit simulation state according to a simulation instruction.

[0013] Optionally, the monitoring unit is specifically configured to monitor the operation progress of the verification operation by monitoring a preset function for calling a test case; the setting unit is specifically configured to set the checkpoint in the verification operation and record the circuit simulation state corresponding to the checkpoint when it is monitored that the preset function calls the test case.

[0014] Optionally, the monitoring unit includes: a loading module, configured to load a compiled file corresponding to the verification operation, where the compiled file includes at least two compiled sub-files, and each of the compiled sub-files is divided according to the sequence of simulation time; a monitoring module, configured to monitor the operation progress of the verification operation by monitoring whether each of the compiled sub-files has been executed.

[0015] Optionally, the setting unit is specifically configured to set the checkpoint in the verification operation and record the circuit simulation state corresponding to the checkpoint when it is monitored that a preset compiled sub-file finishes execution or is about to start execution.

[0016] Optionally, the number of the preset compiled sub-files is one or more, and the number of the checkpoints corresponds to the number of the preset compiled sub-files.

[0017] Optionally, the setting unit is specifically configured to set checkpoints at at least two time points after the verification operation starts and before the verification operation ends according to the operation progress, and record the circuit simulation states corresponding to the checkpoints; the re-verification unit includes: a selection module, configured to select a target checkpoint from the checkpoints corresponding to the at least two time points according to the simulation instruction; a re-verification module, configured to re-perform the verification operation on the chip to be verified from the target checkpoint based on the circuit simulation state corresponding to the target checkpoint.

[0018] In a third aspect, an embodiment of the present invention further provides an electronic device, including: a housing, at least one processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is configured to supply power to each circuit or device of the above-mentioned electronic device; the memory is used for storing executable program codes; the at least one processor runs a program corresponding to the executable program codes by reading the executable program codes stored in the memory, and is configured to execute any one of the chip verification methods provided by the embodiments of the present invention.

[0019] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement any one of the chip verification methods provided by the embodiments of the present invention.

[0020] The chip verification method, device, electronic device, and computer-readable storage medium provided by the embodiments of the present invention can monitor the operation progress of the verification operation on the chip to be verified, set checkpoints at preset time points after the verification operation starts and before it ends according to the operation progress, record the circuit simulation status corresponding to the checkpoints, and according to the simulation instruction, start from the checkpoints and re-perform the verification operation on the chip to be verified based on the circuit simulation status. Since the verification operation can include verification environment initialization operation and / or test case simulation operation, after setting checkpoints at preset time points after the verification operation starts and before it ends, it is possible to re-perform the verification operation on the chip to be verified from these checkpoints during the iterative verification process, without having to start from the initial verification environment initialization every time. That is to say, during the iterative verification process, the verification operations before the checkpoints do not need to be repeated, thus effectively improving the verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0022] Figure 1 It is a flowchart of a chip verification method provided by an embodiment of the present invention;

[0023] Figure 2 It is a detailed flowchart of a chip verification method provided by an embodiment of the present invention;

[0024] Figure 3A schematic structural diagram of a chip verification device provided by an embodiment of the present invention;

[0025] Figure 4 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0026] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0028] To enable those skilled in the art to better understand the technical conceptions, implementation schemes, and beneficial technical effects of the embodiments of the present invention, the following will be described in detail through specific embodiments.

[0029] In a first aspect, an embodiment of the present invention provides a chip verification method, which can effectively improve the chip verification efficiency.

[0030] As Figure 1 shown, the chip verification method provided by an embodiment of the present invention may include:

[0031] S11. Monitor the operation progress of the verification operation on the chip to be verified, where the verification operation includes at least one of the following: verification environment initialization operation, test case simulation operation;

[0032] The verification of the chip may go through multiple operation processes. In the embodiments of the present invention, in order to improve the chip verification efficiency, the operation progress of some of them can be monitored so that corresponding checkpoints can be set according to needs in subsequent steps. Here, the operation progress may refer to the degree of progress of the operation. Specifically, in the embodiments of the present invention, the verified operations to be monitored may include a verification environment initialization operation and / or a test case simulation operation. In specific implementation, the monitoring of the above operation progress can be realized through a scripting language supported by a chip verification tool, such as a tcl (Tool Command Language) scripting language.

[0033] During the chip verification process, various verification operations have a strict execution order. For example, the verification environment initialization operation can be executed in the pre-main stage of the verification operation, and the test case simulation operation can be executed in the main stage of the verification operation, where the pre-main stage precedes the main stage. Specifically, in the monitored verification operation, the verification environment initialization operation can include, for example, assigning default values to each register in the verification environment. After the verification environment initialization operation is completed, the test case simulation operation can be performed. In the test case simulation operation, various signals provided in the test case can be loaded, and various responses of the chip under verification to these signals can be detected. Due to the large scale of the chip, neither the verification environment initialization operation nor the test case simulation operation can be completed in one go and both require a relatively long period of time. The chip verification method provided by the embodiments of the present invention can know the progress of each verification operation by monitoring the operation process of the verification operation, so as to perform further operations.

[0034] Optionally, in the embodiments of the present invention, when monitoring the verification operation, either only the verification environment initialization operation can be monitored, or only the test case simulation operation can be monitored, or the entire process from the verification environment initialization operation to the test case simulation operation can be monitored.

[0035] S12. Set checkpoints at preset time points after the start and before the end of the verification operation according to the operation progress, and record the circuit simulation state corresponding to the checkpoints;

[0036] After learning the operation progress of the verification operation in step S11, in this step, checkpoints can be set at preset time points after the start and before the end of the verification operation, and the circuit simulation state corresponding to the checkpoints can be recorded. It can be understood that the verification operation generally takes a long time from the start of execution to the end of execution. In this step, according to needs, corresponding checkpoints can be set at any one or more time points within this time period. Each time a checkpoint is set, the circuit simulation state of the chip under verification corresponding to the time point of the checkpoint can be recorded. For example, the states of each register in the circuit at this time point can be recorded. According to the different verification operations specifically monitored, the setting positions of the checkpoints can also be correspondingly different. They can be set in the verification environment initialization operation, or in the test case simulation operation, or checkpoints can be set in both the verification environment initialization operation and the test case simulation operation.

[0037] S13. According to the simulation instruction, start from the checkpoint and re-perform the verification operation on the chip under verification based on the circuit simulation state.

[0038] During the chip verification process, when using test cases to simulate the circuit, verification failures or errors may occur for various reasons. Therefore, after making corresponding adjustments to the circuit or test cases, the simulation can be performed again. That is to say, the simulation operations in chip verification are often iterative. In the embodiments of the present invention, since checkpoints are set in the verification operations and the circuit simulation states corresponding to the checkpoints are recorded, during the iterative process, it is not necessary to start the execution from the initialization of the original verification environment every time. Instead, it only needs to start from the set checkpoints and execute based on the corresponding circuit simulation states, thereby effectively reducing the repeated verification operations in the iteration.

[0039] The chip verification method provided by the embodiments of the present invention can monitor the operation progress of the verification operations on the chip to be verified. According to the operation progress, checkpoints are set at preset time points after the start of the verification operations and before the end of the verification operations, and the circuit simulation states corresponding to the checkpoints are recorded. According to the simulation instructions, starting from the checkpoints, the verification operations on the chip to be verified are restarted based on the circuit simulation states. Since the verification operations can include verification environment initialization operations and / or test case simulation operations, after setting checkpoints at preset time points after the start of the verification operations and before the end of the verification operations, during the iterative verification process, the verification operations on the chip to be verified can be restarted from these checkpoints without having to start from the initialization of the original verification environment every time. That is to say, during the iterative verification process, the verification operations before the checkpoints do not need to be repeated, thus effectively improving the verification efficiency.

[0040] In the embodiments of the present invention, although the monitored verification operations can include verification environment initialization operations and / or test case simulation operations, each specific operation can include many specific operation steps. By monitoring the operation progress of the verification operations, it can be known which step the current program is running at, and checkpoints can be set at the corresponding steps as needed, thereby achieving more refined process control in the iterative verification and effectively improving the verification efficiency.

[0041] Optionally, in the embodiments of the present invention, the monitoring of the operation progress of the verification operation can be implemented in multiple ways. For example, in one embodiment of the present invention, the monitoring of the operation progress of the verification operation on the chip to be verified in step S11 may include: monitoring the operation progress of the verification operation by monitoring the preset function for calling the test case; based on this, in step S12, according to the operation progress, setting checkpoints at preset time points after the verification operation starts and before the verification operation ends, and recording the circuit simulation state corresponding to the checkpoints may include: when it is monitored that the preset function calls the test case, setting the checkpoints in the verification operation and recording the circuit simulation state corresponding to the checkpoints. In this embodiment, when performing the verification operation, whether it is the verification environment initialization operation or the test case simulation operation, it can be implemented through specific functions. Obviously, the functions used for the initialization operation are different from the functions used for the test case simulation. Therefore, the monitoring of the operation progress can be achieved by monitoring the preset function for calling the test case. When the preset function is monitored, it indicates that the current operation process is transitioning from the verification environment initialization operation to the test case simulation operation. The verification environment initialization operation has ended, and the test case simulation operation has just started and has not yet had an actual effect on the circuit. At this time, setting checkpoints in the verification operation and recording the circuit simulation state corresponding to the checkpoints is to set checkpoints between the verification environment initialization operation and the test case simulation operation, and record the circuit simulation state when the initialization operation ends and the test case simulation operation has not yet taken effect. In this way, when subsequent iterative simulation is required, there is no need to re-execute the verification environment initialization operation, and only the test case simulation operation needs to be executed starting from that point. Compared with the traditional SOC test case verification method, several hours to dozens of hours of simulation time can be saved in a normal simulation iteration process of the test case, greatly improving the efficiency of SOC-level verification.

[0042] Further, in addition to monitoring the progress of the verification operation by monitoring a preset function, the chip verification method provided by the embodiments of the present invention can also monitor the operation progress in other ways. For example, in an embodiment of the present invention, monitoring the operation progress of the verification operation on the chip to be verified in step S11 may include: loading the compiled file corresponding to the verification operation, where the compiled file includes at least two compiled sub-files, and each of the compiled sub-files is divided according to the sequence of simulation time; monitoring whether each of the compiled sub-files has been executed to monitor the operation progress of the verification operation. Based on this, in step S12, setting a checkpoint at a preset time point after the verification operation starts and before the verification operation ends according to the operation progress, and recording the circuit simulation state corresponding to the checkpoint may include: when it is monitored that a preset compiled sub-file has ended or is about to start execution, setting the checkpoint in the verification operation and recording the circuit simulation state corresponding to the checkpoint.

[0043] In the embodiments of the present invention, each basic component of the verification environment can be written in the systemverilog language, and the initialization sequence and the test case sequence can be written in the system c language. After the initialization sequence and the test case sequence are written, the corresponding compiled files can be pre-compiled, such as dynamic link library files, etc. Each basic component can call the above-mentioned compiled files respectively through the DPI call method to perform the corresponding verification environment initialization operation and / or test case simulation operation. For the convenience of monitoring the operation process of the verification operation, in an embodiment of the present invention, when compiling the initialization sequence and the test case sequence, multiple compiled sub-files can be generated according to the sequence of simulation time, and the multiple compiled sub-files form a compiled file. When calling, each compiled sub-file can be connected in sequence and executed in the order of simulation time, so as to implement the corresponding verification operation. When monitoring, it is possible to know the operation progress of the current verification operation by monitoring whether each compiled sub-file has been executed.

[0044] For example, in one embodiment of the present invention, the initialization sequence generates four compiled sub-files of init1.dll, init2.dll, init3.dll, and init4.dll after compilation, and the test case sequence generates three compiled sub-files of test1.dll, test2.dll, and test3.dll after compilation. It can be known through monitoring that the current init1.dll, init2.dll, init3.dll, init4.dll, and test1.dll have been executed, while test2.dll and test3.dll have not yet been executed, then it can be known that the operation progress of the current verification operation is that the verification environment initialization operation has been completed, and the test case simulation operation has been executed in part. If it is pre-specified that test1.dll is a preset compiled sub-file, then at this time (when test1.dll has been executed and test2.dll and test3.dll have not yet been executed), the corresponding checkpoint can be set. During the subsequent iterative simulation, the test case simulation operation can be directly executed backwards from this checkpoint, and the verification environment initialization operation and part of the test case simulation operation before this checkpoint do not need to be repeated, thereby effectively improving the verification efficiency.

[0045] In this embodiment, the preset compiled sub-file is test1.dll, but the embodiments of the present invention are not limited to this. Optionally, in other embodiments of the present invention, the number of preset compiled sub-files can be one or more, and the number of checkpoints can correspond to the number of preset compiled sub-files. For example, if N preset compiled sub-files are pre-designated as preset compiled sub-files in each compiled sub-file, corresponding checkpoints can also be inserted when these N preset compiled sub-files start or end execution.

[0046] Furthermore, the number of compiled sub-files, the size of each compiled sub-file, and the number and location of checkpoints can be set and adjusted as needed. For example, in one embodiment of the present invention, a checkpoint can also be set after each compiled sub-file is run, and the embodiment of the present invention does not limit this.

[0047] In the embodiment of the present invention, when a checkpoint is set in step S12, step S13 can re-verify the circuit to be verified from the checkpoint according to the instruction input by the user, such as a rerun instruction. In other cases, in order to facilitate comprehensive verification and analysis of the circuit, multiple checkpoints can be set during the verification process. Each time an iterative simulation is performed, a different checkpoint can be selected as a target checkpoint according to actual needs, and the iterative simulation can be re-performed from the target checkpoint, thereby further improving the verification efficiency.

[0048] Specifically, in an embodiment of the present invention, in step S12, according to the operation progress, setting checkpoints at preset time points after the start of the verification operation and before the end of the verification operation, and recording the circuit simulation states corresponding to the checkpoints may include: setting checkpoints at at least two time points after the start of the verification operation and before the end of the verification operation according to the operation progress, and recording the circuit simulation states corresponding to the checkpoints; based on this, in step S13, according to the simulation instruction, starting from the checkpoint, re-verifying the chip to be verified based on the circuit simulation state may specifically include: according to the simulation instruction, selecting a target checkpoint from the checkpoints corresponding to the at least two time points; starting from the target checkpoint, re-verifying the chip to be verified based on the circuit simulation state corresponding to the target checkpoint.

[0049] The chip verification method provided by the embodiments of the present invention will be described in detail below through specific embodiments.

[0050] As Figure 2 shown, the chip verification method provided by the embodiments of the present invention may include:

[0051] S201. Start the verification environment with a graphical interface and call a pre-written tcl script.

[0052] S202. The tcl script monitors the operation progress of the verification operation by monitoring a preset function for calling test cases.

[0053] S203. When it is monitored that the preset function calls a test case, set the checkpoint in the verification operation and record the circuit simulation state corresponding to the checkpoint.

[0054] S204. If an error occurs in the simulation, modify the test case and regenerate the compiled file of the test case.

[0055] S205. Receive the rerun command input by the user, and jump to the checkpoint position according to the rerun command, so as to avoid repeating the verification environment initialization operation.

[0056] S206. According to the circuit simulation state recorded by the checkpoint, perform the simulation operation on the modified test case.

[0057] Correspondingly, in the second aspect, the embodiments of the present invention provide a chip verification device, which can effectively improve the chip verification efficiency.

[0058] As Figure 3 shown, the chip verification device provided by the embodiments of the present invention may include:

[0059] The monitoring unit 31 is used to monitor the operation progress of the verification operation on the chip to be verified, and the verification operation includes at least one of the following: verification environment initialization operation, test case simulation operation;

[0060] The setting unit 32 is used to set checkpoints at preset time points after the start of the verification operation and before the end of the verification operation according to the operation progress, and record the circuit simulation state corresponding to the checkpoints;

[0061] The re-verification unit 33 is used to re-perform the verification operation on the chip to be verified from the checkpoint based on the circuit simulation state according to the simulation instruction.

[0062] The chip verification device provided by the embodiment of the present invention can monitor the operation progress of the verification operation on the chip to be verified, set checkpoints at preset time points after the start of the verification operation and before the end of the verification operation according to the operation progress, record the circuit simulation state corresponding to the checkpoints, and re-perform the verification operation on the chip to be verified from the checkpoint based on the circuit simulation state according to the simulation instruction. Since the verification operation can include a verification environment initialization operation and / or a test case simulation operation, after setting checkpoints at preset time points after the start of the verification operation and before the end of the verification operation, it is possible to re-perform the verification operation on the chip to be verified from this checkpoint during the iterative verification process, without having to start from the initial verification environment initialization every time. That is to say, during the iterative verification process, the verification operations before the checkpoint do not need to be repeated, thus effectively improving the verification efficiency.

[0063] Optionally, the monitoring unit 31 can be specifically used to monitor the operation progress of the verification operation by monitoring a preset function for calling test cases; the setting unit 32 can be specifically used to set the checkpoint in the verification operation and record the circuit simulation state corresponding to the checkpoint when it is monitored that the preset function calls the test case.

[0064] Optionally, the monitoring unit 31 may include:

[0065] A loading module for loading the compiled file corresponding to the verification operation, where the compiled file includes at least two compiled sub-files, and each of the compiled sub-files is divided according to the sequence of simulation time;

[0066] A monitoring module for monitoring the operation progress of the verification operation by monitoring whether each of the compiled sub-files has been executed.

[0067] Optionally, the setting unit 32 can be specifically used to set the checkpoint in the verification operation and record the circuit simulation state corresponding to the checkpoint when it is monitored that the execution of a preset compiled sub-file ends or is about to start.

[0068] Optionally, the number of the preset compiled sub-files is one or more, and the number of the checkpoints corresponds to the number of the preset compiled sub-files.

[0069] Optionally, a setting unit 32 is configured to set checkpoints at at least two time points after the verification operation starts and before the verification operation ends according to the operation progress, and record the circuit simulation states corresponding to the checkpoints.

[0070] The re-verification unit 33 may include:

[0071] a selection module, configured to select a target checkpoint from the checkpoints corresponding to the at least two time points according to the simulation instruction;

[0072] a re-verification module, configured to start from the target checkpoint and re-perform a verification operation on the chip to be verified based on the circuit simulation state corresponding to the target checkpoint.

[0073] In a third aspect, as Figure 4 shown, an embodiment of the present invention further provides an electronic device, including: a housing 100, at least one processor 110, a memory 120, a circuit board 130, and a power supply circuit 140, wherein the circuit board 130 is disposed inside the space surrounded by the housing 100, and the processor 110 and the memory 120 are disposed on the circuit board 130; the power supply circuit 140 is configured to supply power to each circuit or device of the foregoing electronic device; the memory 120 is configured to store an executable program code; the processor 110 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 120, and is configured to execute any one of the chip verification methods provided in the foregoing embodiments. The specific execution process of the foregoing steps by the processor 110 and the further steps executed by the processor 110 by running the executable program code may refer to the description of the foregoing embodiments and will not be elaborated herein.

[0074] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement any one of the chip verification methods provided in the foregoing embodiments. The specific execution process of the foregoing steps by the processor and the further steps executed by the processor by running the executable program code may refer to the description of the foregoing embodiments and will not be elaborated herein.

[0075] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0076] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments.

[0077] In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiments.

[0078] For the convenience of description, the above device is described by dividing its functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be realized in one or more software and / or hardware.

[0079] Those of ordinary skill in the art can understand that all or part of the processes of the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0080] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A chip verification method, characterized in that, Comprising: Monitoring the operation progress of the verification operation on the chip to be verified, where the verification operation includes a verification environment initialization operation and a test case simulation operation, and the test case simulation operation is performed after the verification environment initialization operation; According to the operation progress, setting checkpoints at preset time points after the start and before the end of the verification operation, and recording the circuit simulation state corresponding to the checkpoints; The setting of checkpoints at preset time points after the start and before the end of the verification operation includes: setting a checkpoint between the verification environment initialization operation and the test case simulation operation, and / or setting a checkpoint during the test case simulation operation; According to the simulation instruction, starting from the checkpoint, re-verifying the chip to be verified based on the circuit simulation state; The monitoring of the operation progress of the verification operation on the chip to be verified includes: loading the compiled file corresponding to the verification operation, where the compiled file includes at least two compiled sub-files, and each of the compiled sub-files is divided according to the sequence of simulation time; monitoring the operation progress of the verification operation by monitoring whether each of the compiled sub-files has been executed.

2. The method according to claim 1, characterized in that, The monitoring of the operation progress of the verification operation on the chip to be verified includes: Monitoring the operation progress of the verification operation by monitoring the preset function for calling the test case; The setting of checkpoints at preset time points after the start and before the end of the verification operation according to the operation progress, and recording the circuit simulation state corresponding to the checkpoints includes: When it is monitored that the preset function calls the test case, setting the checkpoint in the verification operation and recording the circuit simulation state corresponding to the checkpoint.

3. The method according to claim 1, wherein The setting of checkpoints at preset time points after the start and before the end of the verification operation according to the operation progress, and recording the circuit simulation state corresponding to the checkpoints includes: When it is monitored that the execution of a preset compiled sub-file ends or is about to start, setting the checkpoint in the verification operation and recording the circuit simulation state corresponding to the checkpoint.

4. The method according to claim 3, characterized in that, The number of the preset compiled sub-files is one or more, and the number of the checkpoints corresponds to the number of the preset compiled sub-files.

5. The method according to claim 1, wherein The setting of checkpoints at preset time points after the start and before the end of the verification operation according to the operation progress, and recording the circuit simulation state corresponding to the checkpoints includes: setting checkpoints at at least two time points after the start and before the end of the verification operation according to the operation progress, and recording the circuit simulation state corresponding to the checkpoints; The re-verifying the chip to be verified based on the circuit simulation state starting from the checkpoint according to the simulation instruction includes: According to the simulation instruction, selecting a target checkpoint from the checkpoints corresponding to the at least two time points; Starting from the target checkpoint, re-verifying the chip to be verified based on the circuit simulation state corresponding to the target checkpoint.

6. A chip verification device, characterized in that, Comprising: A monitoring unit, configured to monitor the operation progress of a verification operation on a chip to be verified, where the verification operation includes a verification environment initialization operation and a test case simulation operation, and the test case simulation operation is performed after the verification environment initialization operation; A setting unit, configured to set checkpoints at preset time points after the start and before the end of the verification operation according to the operation progress, and record the circuit simulation state corresponding to the checkpoints; The setting of the checkpoints at preset time points after the start and before the end of the verification operation includes: setting a checkpoint between the verification environment initialization operation and the test case simulation operation, and / or setting a checkpoint during the test case simulation operation; A re-verification unit, configured to re-perform the verification operation on the chip to be verified from the checkpoint based on the circuit simulation state according to a simulation instruction; The monitoring unit includes: a loading module, configured to load a compiled file corresponding to the verification operation, where the compiled file includes at least two compiled sub-files, and each of the compiled sub-files is divided according to the sequence of simulation time; a monitoring module, configured to monitor the operation progress of the verification operation by monitoring whether each of the compiled sub-files has been executed.

7. The device according to claim 6, characterized in that, The monitoring unit is specifically configured to monitor the operation progress of the verification operation by monitoring a preset function for calling a test case; The setting unit is specifically configured to, when it is monitored that the preset function calls a test case, set the checkpoint in the verification operation and record the circuit simulation state corresponding to the checkpoint.

8. The device according to claim 6, wherein The setting unit is specifically configured to, when it is monitored that a preset compiled sub-file finishes execution or is about to start execution, set the checkpoint in the verification operation and record the circuit simulation state corresponding to the checkpoint.

9. The device according to claim 8, characterized in that, The number of the preset compiled sub-files is one or more, and the number of the checkpoints corresponds to the number of the preset compiled sub-files.

10. The device according to claim 6, characterized in that, The setting unit is specifically configured to set checkpoints at at least two time points after the start and before the end of the verification operation according to the operation progress, and record the circuit simulation state corresponding to the checkpoints; The re-verification unit includes: A selection module, configured to select a target checkpoint from the checkpoints corresponding to the at least two time points according to the simulation instruction; A re-verification module, configured to re-perform the verification operation on the chip to be verified from the target checkpoint based on the circuit simulation state corresponding to the target checkpoint.

11. An electronic device, characterized in that, including: A housing, at least one processor, a memory, a circuit board, and a power supply circuit, where the circuit board is disposed inside the space surrounded by the housing, the processor and the memory are disposed on the circuit board; the power supply circuit is configured to supply power to each circuit or device of the above electronic device; the memory is configured to store executable program code; the at least one processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is configured to execute the method according to any one of the preceding claims 1-5.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method described in any one of the foregoing claims 1-5.

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