A circuit model for simulating eFuse and a simulation method based on eFuse

Abstract

The present invention provides a circuit model for simulating an eFuse and a simulation method based on the eFuse. The circuit model includes: an initialization module configured to set all bits in a register space to a first bit state; a synchronous write logic module configured to receive a write operation instruction and, based on the write operation instruction and according to a first input address signal, write the first bit state of the corresponding bit in the register space to a second bit state to obtain a fixed register space; a synchronous read logic module configured to receive a read operation instruction and, based on the read operation instruction, output a second input address signal; and a synchronous hold module configured to receive a read address instruction and a second input address signal and, based on the read address instruction and according to the second input address signal, output a bit sequence using the fixed register space so that an external device can verify the bit sequence. The present invention meets the need for pre-verification of a binary sequence to be burned into an eFuse.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a circuit model for simulating an eFuse and a simulation method based on the eFuse. Background Art

[0002] Chip secure boot is to ensure that the chip only runs user-specified programs. In the chip's secure boot process, software signatures need to be verified step by step to form a secure boot chain. Failure of the signature verification at any link will terminate the chip boot. The hardware and software entities that initially perform signature verification in the secure boot chain must ensure their own legality and have not been tampered with. This entity is the chip's boot trust root. The boot trust root can be a section of code solidified in ROM (Read-Only Memory). This section of code is solidified into the chip during chip manufacturing. After the chip is manufactured, the software cannot be changed. During the chip's power-on initialization process, the code in this ROM is executed first, and the subsequent software signature verification is performed by this ROM code.

[0003] Generally speaking, the chip has a Boot ROM for starting the read-only storage area (a small mask ROM or write-protected flash memory embedded in the processor chip). The hardware design will ensure that the chip is powered on and started from this read-only or even invisible Boot ROM.

[0004] All chips that support secure boot have a Boot ROM program embedded in the chip. The first instruction executed by the chip after power is at the entry point of the Boot ROM. The Boot ROM has the highest execution privileges. It initializes the secure boot security mechanism, loads the secure boot key, loads and verifies the First Stage Bootloader (FSBL) from Flash, and finally jumps into the FSBL. The Boot ROM is completely read-only, which is hardcoded when the chip leaves the factory. The Boot ROM is usually mapped to a dedicated memory address.

[0005] All chips that support secure boot have a small, one-time programmable memory module called an eFuse (one-time programmable memory) because it works similarly to a real-world fuse. When the chip leaves the factory, all bits in this eFuse are set to "0." Programming a bit to "1" permanently fixes that bit, making it impossible to change its value and thus never write back to "0."

[0006] The eFuse capacity is typically around 1KB. After the chip is installed in a product, a specific binary sequence is typically burned into the eFuse for development, testing, and production. The Boot ROM reads the binary sequence burned into the eFuse, determines the current operating mode, parses the chip's configuration information, and initializes the various internal modules to achieve a secure boot. The eFuse can only be burned once, programming the desired bit to "1" and leaving all other bits "0." If the value read after the programming is not "1," the programming process fails and is irreversible.

[0007] Since eFuse can only be programmed once, if you are not familiar with the process or make mistakes in the binary sequence and software programming, the chip will not work properly. Therefore, you must be very careful when programming eFuse. Try to verify the binary sequence before programming the eFuse, and then program the corresponding binary sequence into the actual eFuse.

[0008] The binary sequence to be burned into the eFuse chip can be verified using an FPGA (Field Programmable Gate Array) prototyping platform. FPGA prototyping is an FPGA-based chip verification method. It is typically performed after the front-end RTL (Register Transfer Level) design and RTL simulation phases are completed, but before the chip is tape-out. The FPGA prototype provides a verification platform that simulates chip behavior, helping both hardware and software developers improve their work efficiency.

[0009] The eFuse devices used in chips are peripheral devices provided by the chip manufacturer. During the chip design phase, the manufacturer's process library files are used. However, these process library files are not synthesizable and cannot be directly used in FPGA prototype platforms. During the chip front-end verification phase, an RTL behavioral simulation model of the eFuse devices is used. This RTL behavioral simulation model is based on combinational logic and contains a large number of latch circuits. While it works well in chips, using latch circuits in FPGAs can severely affect timing performance and should be avoided. This requires the design of an RTL circuit model that is synthesizable in FPGA prototypes and suitable for FPGA use to simulate the behavior of the eFuse devices and meet the binary sequence verification requirements of chip verifiers. Summary of the Invention

[0010] In view of this, the purpose of the present invention is to propose a circuit model for simulating eFuse and a simulation method based on eFuse, so as to simulate eFuse devices in an FPGA prototype verification platform, thereby meeting the verification requirements of the binary sequence to be burned in the eFuse device.

[0011] Based on the above objectives, the present invention provides a circuit model for simulating an eFuse, including:

[0012] an initialization module configured to set all bits in the register space to a first bit state;

[0013] a synchronous write logic module configured to receive a write operation instruction, and write a first bit state of a corresponding bit in the register space to a second bit state based on the write operation instruction and according to a first input address signal, so as to obtain a fixed register space;

[0014] a synchronous read logic module configured to receive a read operation instruction and output a second input address signal based on the read operation instruction; and

[0015] The synchronization holding module is configured to receive a read address instruction and a second input address signal output by the synchronous read logic module, and output a bit sequence using a fixed register space based on the read address instruction and according to the second input address signal, so that an external device can verify the bit sequence.

[0016] In some embodiments, the first input address corresponding to the first input address signal includes a byte address and a bit address, and the second input address corresponding to the second input address signal includes a bit address.

[0017] In some embodiments, the base of the value corresponding to the number of bits in the register space is two, and the power thereof is the sum of the number of binary digits of the byte address and the number of binary digits of the bit address.

[0018] In some embodiments, the base of the value corresponding to the number of bits in the bit sequence is two, and the power of the value is the number of binary bits in the byte address.

[0019] In some embodiments, the first bit state is 0 and the second bit state is 1.

[0020] In some embodiments, the synchronization holding module is further configured to use a flip-flop to hold the states of all bits in the fixed register space.

[0021] In some embodiments, the circuit model further includes:

[0022] The bit output module is configured to receive the bit sequence output by the synchronization holding module and output the bit sequence to an external device connected to the circuit model, so that the external device verifies the bit sequence.

[0023] In some embodiments, the circuit model further includes:

[0024] The address signal terminal is configured to receive a first input address signal and a second input address signal.

[0025] In some embodiments, the circuit model further includes:

[0026] an enable terminal configured to receive a read / write enable signal and output a write operation instruction or a read operation instruction based on the read / write enable signal; and

[0027] The chip select terminal is configured to receive a chip select signal and control the validity or invalidity of the read and write enable signal based on the chip select signal.

[0028] Another aspect of the present invention further provides an eFuse-based simulation method, comprising the following steps:

[0029] Setting all bits in the register space to the first bit state through the initialization module;

[0030] Writing, by a synchronous write logic module, a first bit state of a corresponding bit in the register space to a second bit state based on a received write operation instruction and according to a first input address signal, so as to obtain a fixed register space;

[0031] Outputting the second input address signal to the synchronization holding module based on the received read operation instruction through the synchronous read logic module;

[0032] The synchronization holding module outputs a bit sequence using a fixed register space based on the received read address instruction and according to the second input address signal, so that an external device verifies the bit sequence.

[0033] The present invention has at least the following beneficial technical effects:

[0034] The embodiment of the present invention designs a circuit model that simulates eFuse in an FPGA prototype platform, replacing the non-synthesizable process library files provided by chip manufacturers. This allows chip software designers and verifiers to verify the bit sequence output by the circuit model without burning the eFuse device, thereby pre-verifying the binary sequence to be burned into the eFuse and the corresponding software function. Compared with the traditional eFuse behavior simulation model used in the front-end verification stage of the chip, this circuit model uses a sequential circuit design and is used in FPGA prototypes. It is more in line with FPGA design specifications and has better timing performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 A schematic diagram of a circuit model for simulating an eFuse according to an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of the structure of a circuit model for simulating an eFuse according to an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of the operation flow of a circuit model simulating an eFuse according to an embodiment of the present invention;

[0039] Figure 4 Schematic diagram of an eFuse-based simulation method provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0041] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. Therefore, "first" and "second" are used for convenience of expression only and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product, or device that includes a series of steps or units.

[0042] Based on the above objectives, a first aspect of an embodiment of the present invention provides an embodiment of a circuit model for simulating an eFuse. Figure 1 FIG. 1 is a schematic diagram of an embodiment of a circuit model for simulating eFuse provided by the present invention. Figure 1 As shown, the circuit model of the analog eFuse in the embodiment of the present invention includes:

[0043] an initialization module 10, configured to set all bits in the register space to a first bit state;

[0044] a synchronous write logic module 20 configured to receive a write operation instruction, and write a first bit state of a corresponding bit in the register space to a second bit state based on the write operation instruction and according to a first input address signal, so as to obtain a fixed register space;

[0045] a synchronous read logic module 30 configured to receive a read operation instruction and output a second input address signal based on the read operation instruction; and

[0046] The synchronization maintaining module 40 is configured to receive a read address instruction and a second input address signal output by the synchronous read logic module, and output a bit sequence based on the read address instruction and the second input address signal using a fixed register space to enable an external device to verify the bit sequence.

[0047] The embodiment of the present invention designs a circuit model that simulates eFuse in an FPGA prototype platform, replacing the non-synthesizable process library files provided by chip manufacturers. This allows chip software designers and verifiers to verify the bit sequence output by the circuit model without burning the eFuse device, thereby pre-verifying the binary sequence to be burned into the eFuse and the corresponding software function. Compared with the traditional eFuse behavior simulation model used in the front-end verification stage of the chip, this circuit model uses a sequential circuit design and is used in FPGA prototypes. It is more in line with FPGA design specifications and has better timing performance.

[0048] Traditional eFuse behavioral simulation models used in chip front-end verification are latch-based circuits with poor timing performance. Using them in FPGA (Field Programmable Gate Array) prototypes can produce numerous glitches and unsatisfactory bit setting performance, with some bits failing to set to "1." Furthermore, front-end simulation can only perform module-level simulation and cannot be combined with upper-layer software for system-level simulation, resulting in inadequate verification.

[0049] In some embodiments, the first input address corresponding to the first input address signal includes a byte address and a bit address, and the second input address corresponding to the second input address signal includes a bit address.

[0050] In some embodiments, the base of the value corresponding to the number of bits in the register space is two, and the power thereof is the sum of the number of binary digits of the byte address and the number of binary digits of the bit address.

[0051] In some embodiments, the base of the value corresponding to the number of bits in the bit sequence is two, and the power of the value is the number of binary bits in the byte address.

[0052] In some embodiments, the first bit state is 0 and the second bit state is 1.

[0053] In some embodiments, the synchronization maintaining module 40 is further configured to maintain the states of all bits in the fixed register space using flip-flops.

[0054] In some embodiments, the circuit model further includes: a bit output module configured to receive the bit sequence output by the synchronization maintaining module and output the bit sequence to an external device connected to the circuit model, so that the external device verifies the bit sequence.

[0055] In some embodiments, the circuit model further includes: an address signal terminal configured to receive a first input address signal and a second input address signal.

[0056] In some embodiments, the circuit model also includes: an enable end, configured to receive a read / write enable signal and output a write operation instruction or a read operation instruction based on the read / write enable signal; and a chip select end, configured to receive a chip select signal and control the validity or invalidity of the read / write enable signal based on the chip select signal.

[0057] The following is a specific embodiment of the circuit model of the simulated eFuse of the present invention:

[0058] This circuit model is an eFuse RTL circuit model based on sequential circuit design and can simulate the behavior of a real eFuse device.

[0059] eFuse is a one-time programmable non-volatile memory. The information stored in eFuse will not be lost due to system power failure, and each bit can only be programmed once.

[0060] In integrated circuit design, RTL (Register Transfer Level) is used to abstractly describe the operation of synchronous digital circuits.

[0061] Figure 2 FIG. 1 shows a schematic diagram of a circuit model for simulating eFuse according to an embodiment of the present invention. Figure 2 As shown, the input and output ports of the circuit model are defined as follows:

[0062] CLK: Input clock signal, serving as the working clock of the eFuse RTL circuit model, driving all sequential logic modules in the circuit model.

[0063] PD: Power Down input signal. The signal width is 1 bit and is valid at a high level. When PD is high, the eFuse RTL circuit model is disabled; when PD is low, the eFuse RTL circuit model is enabled.

[0064] CSB: Chip select input signal, 1 bit wide, valid at low level. A low level indicates that the read or write operation of the eFuse RTL circuit model is about to be started; a high level indicates that the read or write operation of the eFuse RTL circuit model is not started.

[0065] LOAD: Input read and write enable signal, high level indicates read enable, low level indicates write enable.

[0066] A: Input address signal, the address bit width (ie the number of binary bits) is M.

[0067] Q: Output data signal, data bit width is 2 m The value of m depends on the bit width of the output signal read at one time by the actual simulated eFuse (ie, the number of bits in the output bit sequence).

[0068] Read and write operation logic: When the CLK clock signal's rising edge arrives, and PD, CSB, and LOAD are low, a write operation is performed, setting the corresponding binary bit to "1" according to the input address signal. When the CLK clock signal's rising edge arrives, and PD, CSB, and LOAD are low, a read operation is performed, outputting the corresponding binary bit according to the input address signal. When write and read operations are invalid, the synchronization hold module maintains the current bit state.

[0069] In the eFuse RTL circuit model, a two-dimensional register space Fuse_array[2 m -1:0][2 n -1:0], used to store the binary sequence (i.e. bit sequence) of eFuse. The register space is 2 m Row, 2 n The capacity is X bits. The specific value of X depends on the actual emulated eFuse capacity.

[0070] In the eFuse RTL circuit model, design an input address A[M-1:0] with a bit width of M.

[0071] The input address is divided into byte address and bit address. Among them, the byte address is A m , the bit width (ie, the number of binary digits) is m; the bit address is A n , the bit width (ie, the number of binary digits) is n. The bit width of address A is M, and the byte address A is m Bit width m, bit address A n The relationship between the bit width n is shown in Formula 1:

[0072] M=m+n (Formula 1)

[0073] Address A, Byte Address A m , bit address A n The relationship is shown in Formula 2 and Formula 3:

[0074] A[n-1:0]=A n (Formula 2)

[0075] A[M-1:n]=A m (Formula 3)

[0076] The relationship between the binary bit capacity X of fuse_array and the bit width M of address A is shown in formula 4:

[0077] X=2 M (Formula 4)

[0078] For example, assuming m=5, n=3, the byte address is a binary number with 5 bits, and the bit address is a binary number with 3 bits. The register space at this time is 2 5 Row, 2 3 Columns, that is, 32 rows and 8 columns.

[0079] In the eFuse RTL circuit model, the output signal Q[2 m -1:0], output the read bit, the bit width is 2 m .

[0080] Define the internal signals for write operation (PD is low, CSB is low, LOAD is low), as shown in Formula 5:

[0081] WRITE_EN= ～ PD&& ～ CSB&& ～ LOAD (Formula 5)

[0082] For each write operation, a specific byte address A is given. m , bit address A n , the corresponding bit position in Fuse_array will be set to "1".

[0083] Byte Address A m , bit address A n The mapping relationship with Fuse_array is shown in Formula 6:

[0084] Fuse_array[{A m ,A n}]=“1” (Formula 6)

[0085] Define the internal signals for the read operation (PD is low, CSB is low, and LOAD is high), as shown in Formula 7:

[0086] READ_EN= ～ PD&& ～ CSB&&LOAD (Formula 7)

[0087] For each read operation, a specific bit address A is given n , will output 2 from Q terminal at the same time m bits.

[0088] Bit address A n The mapping relationship with the output signal Q is shown in Formula 8:

[0089] Q[i]=Fuse_array[{i,A n}] Where i = 0, 1, 2, ..., 2 m -1 (Formula 8)

[0090] For the register space with 32 rows and 8 columns (0, 1, 2, ..., 7) mentioned above, specify a bit address "101", and output the bit state of the 5th column of each of the 32 rows (the binary number 101 converted to decimal is 5).

[0091] Figure 3 Schematic diagram of the operation flow of the circuit model of the simulated eFuse according to the embodiment of the present invention. Figure 3 As shown in the figure, the operation process of the circuit model is as follows:

[0092] Step 1: Power-on state, which is the initial state of the eFuse RTL circuit model.

[0093] Step 2: After the power-on state is completed, the initialization module 10 is entered, and the initialization module 10 sets all the binary bits of the eFuse RTL model to "0".

[0094] Step 3: After the binary bit initialization is completed, enter the write operation or read operation judgment logic and wait for the write operation or read operation instruction.

[0095] Step 4: When a write or read operation instruction arrives, a read / write logic judgment is performed. If it is a write operation, the synchronous write logic module 20 is entered; if it is a read operation, the synchronous read logic module 30 is entered.

[0096] Step 5: If a write instruction arrives, the process enters the synchronous write logic module 20. Based on the input write address, upon the rising edge of the CLK clock signal, the synchronous write logic module 20 sets the designated bit to "1" and then enters the synchronization hold module 40. If a read instruction arrives, the process enters the synchronous read logic module 30. Upon the rising edge of the CLK clock signal, the synchronous read logic module 30 outputs the input read address to the synchronization hold module 40.

[0097] Step 6: When the rising edge of the CLK clock signal arrives, the synchronization holding module 40 uses a flip-flop to hold the current value of the binary bit and synchronously monitors the read address instruction. When a read address instruction arrives, the corresponding bit sequence is output to the bit output module.

[0098] Step 7: The bit output module outputs the bit sequence corresponding to the read address.

[0099] At this point, the eFuse RTL circuit model simulates the real eFuse device and realizes the circuit function of the eFuse.

[0100] The second aspect of the embodiment of the present invention further provides a simulation method based on eFuse. Figure 4 FIG. 1 is a schematic diagram of an embodiment of the eFuse-based simulation method provided by the present invention. Figure 4 As shown, an eFuse-based simulation method includes the following steps:

[0101] Step S10: setting all bits in the register space to the first bit state through the initialization module;

[0102] Step S20: writing the first bit state of the corresponding bit in the register space to the second bit state based on the received write operation instruction and the first input address signal by the synchronous write logic module to obtain a fixed register space;

[0103] Step S30: outputting the second input address signal to the synchronization maintaining module based on the received read operation instruction through the synchronous read logic module;

[0104] Step S40: The synchronization maintaining module outputs a bit sequence using a fixed register space based on the received read address instruction and the second input address signal, so that an external device verifies the bit sequence.

[0105] Finally, it should be noted that the computer-readable storage medium (e.g., memory) herein may be a volatile memory or a non-volatile memory, or may include both a volatile memory and a non-volatile memory. By way of example and not limitation, the non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory may include a random access memory (RAM), which may act as an external cache memory. By way of example and not limitation, RAM may be obtained in a variety of forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.

[0106] It will also be appreciated by those skilled in the art that the various exemplary logic blocks, modules, circuits and algorithmic steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given of the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0107] The various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure herein may be implemented or executed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and / or any other such configuration.

[0108] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless expressly limited to the singular.

[0109] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0110] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples. Within the spirit of the embodiments of the present invention, the technical features of the above embodiments or different embodiments may be combined, and there are many other variations of different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the scope of protection of the embodiments of the present invention.

Claims

1. A circuit model for simulating an eFuse, characterized in that: The circuit model is an eFuse RTL circuit model designed based on a sequential circuit. It is used to simulate the behavior of a real eFuse device. In the circuit model, there is a two-dimensional register space with a capacity of X bits. The specific value of X depends on the actual simulated eFuse capacity. The circuit model includes: an initialization module configured to set all bits in the register space to a first bit state; a synchronous write logic module configured to receive a write operation instruction, and write the first bit state of the corresponding bit in the register space to a second bit state based on the write operation instruction and a first input address signal to obtain a fixed register space; a synchronous read logic module configured to receive a read operation instruction and output a second input address signal based on the read operation instruction; and A synchronization holding module is configured to receive a read address instruction and the second input address signal output by the synchronous read logic module, and output a bit sequence using the fixed register space based on the read address instruction and according to the second input address signal, so that an external device can verify the bit sequence.

2. The circuit model according to claim 1, wherein: The first input address corresponding to the first input address signal includes a byte address and a bit address, and the second input address corresponding to the second input address signal includes the bit address.

3. The circuit model according to claim 2, wherein: The number of bits of the register space is a value whose base is two and whose power is the sum of the number of binary digits of the byte address and the number of binary digits of the bit address.

4. The circuit model according to claim 2, wherein: The number of bits in the bit sequence is a value whose base is two and whose power is the number of binary digits of the byte address.

5. The circuit model according to claim 1, wherein: The first bit state is 0, and the second bit state is 1.

6. The circuit model according to claim 1, wherein: The synchronization maintaining module is further configured to maintain the states of all bits in the fixed register space using a trigger.

7. The circuit model according to claim 1, wherein: Also includes: A bit output module is configured to receive the bit sequence output by the synchronization maintaining module and output the bit sequence to the external device connected to the circuit model, so that the external device verifies the bit sequence.

8. The circuit model according to claim 1, wherein: Also includes: The address signal terminal is configured to receive the first input address signal and the second input address signal.

9. The circuit model according to claim 1, wherein: Also includes: An enable terminal configured to receive a read / write enable signal and output the write operation instruction or the read operation instruction based on the read / write enable signal; as well as The chip select terminal is configured to receive a chip select signal and control the validity or invalidity of the read / write enable signal based on the chip select signal.

10. A simulation method based on eFuse, characterized in that: Applied to the circuit model according to any one of claims 1 to 9, the method comprises the following steps: Setting all bits in the register space to the first bit state through the initialization module; Writing the first bit state of the corresponding bit in the register space to a second bit state based on the received write operation instruction and the first input address signal by a synchronous write logic module to obtain a fixed register space; Outputting the second input address signal to the synchronization holding module based on the received read operation instruction through the synchronous read logic module; The synchronization maintaining module outputs a bit sequence using the fixed register space based on the received read address instruction and according to the second input address signal, so that an external device verifies the bit sequence.

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