Through-signal line layout processing method and device, chip and storage medium

Abstract

The embodiments of the present application disclose a signal line layout processing method and device, chip and storage medium, including: performing a first layout planning processing based on original design data to determine a first logic block layout structure corresponding to a chip to be designed; determining multiple groups of connection logic units corresponding to multiple logic blocks respectively according to the first logic block layout structure; wherein each group of connection logic units is used to characterize the corresponding connection relationship of each logic block; performing a first signal line planning processing based on the multiple groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure; and performing signal line layout processing at least according to the number of first signal lines and a preset target layout condition.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design automation, and in particular to a method and device for processing the layout of a through signal line, a chip and a storage medium. Background Art

[0002] As system applications become more complex, the excessive number of logic gates in the design of ultra-large-scale chips has led to the adoption of a top-down, or hierarchical, design approach for chip design. However, since the hierarchical chip design approach divides the chip into different sub-modules for separate processing, that is, the original timing path is distributed in different sub-modules, there is an interconnection between different sub-modules of the chip.

[0003] At present, based on the hierarchical design method, the interconnection relationship between different sub-modules is usually processed at the top level; and in order to reduce the area consumed by the interconnection lines between the sub-modules on the top level, different modules are no longer interconnected through reserved channels, but directly use the method of penetrating signal lines to pass these interconnection lines through other modules to achieve interconnection between sub-modules.

[0004] Since the design of the through-signal lines will indirectly affect the implementation difficulty and area requirements in the chip, how to better plan and layout the through-signal lines when designing the chip back-end is an issue that needs to be urgently addressed in the current status of the entire back-end design. Summary of the invention

[0005] The embodiments of the present application provide a method and device for processing the layout of a through signal line, a chip and a storage medium, which optimize the planning process of the through signal line to a great extent, shorten the planning time and increase the efficiency, further accelerating the chip development cycle.

[0006] The technical solution of the embodiment of the present application is implemented as follows:

[0007] In a first aspect, an embodiment of the present application provides a method for processing a layout of a through signal line, the method comprising:

[0008] Performing a first layout planning process based on the original design data to determine a first logic block layout structure corresponding to the chip to be designed;

[0009] Determine a plurality of groups of connection logic units corresponding to a plurality of logic blocks respectively according to the first logic block layout structure; wherein each group of connection logic units is used to characterize the corresponding connection relationship of each logic block;

[0010] Performing first signal line planning processing based on the plurality of groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure;

[0011] Signal line layout processing is performed according to at least the first number of signal lines and a preset target layout condition.

[0012] In a second aspect, an embodiment of the present application provides a through signal line layout processing device, the layout processing device comprising: a first processing unit, a determination unit, a second processing unit and a third processing unit,

[0013] The first processing unit is used to perform a first layout planning process based on the original design data to determine a first logic block layout structure corresponding to the chip to be designed;

[0014] The determining unit is used to determine a plurality of groups of connection logic units corresponding to a plurality of logic blocks respectively according to the first logic block layout structure; wherein each group of connection logic units is used to represent a corresponding connection relationship of each logic block;

[0015] The second processing unit is used to perform first signal line planning processing based on the multiple groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure;

[0016] The third processing unit is used to perform signal line layout processing according to at least the first number of signal lines and a preset target layout condition.

[0017] In a third aspect, an embodiment of the present application provides a through-signal line layout processing device, which includes a processor and a memory storing instructions executable by the processor. When the instructions are executed by the processor, the through-signal line layout processing method described above is implemented.

[0018] In a fourth aspect, an embodiment of the present application provides a chip, comprising a processor and an interface, wherein the processor obtains program instructions through the interface, and the processor is used to run the program instructions to implement the signal line layout processing method as described above.

[0019] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium having a program stored thereon, which is applied to a through-signal line layout processing device. When the program is executed by a processor, the through-signal line layout processing method as described above is implemented.

[0020] The embodiment of the present application provides a signal line layout processing method and device, chip and storage medium, wherein the signal line layout processing device can perform a first layout planning process based on the original design data to determine a first logic block layout structure corresponding to the chip to be designed; determine multiple groups of connection logic units corresponding to multiple logic blocks respectively according to the first logic block layout structure; wherein each group of connection logic units is used to characterize the corresponding connection relationship of each logic block; perform a first signal line planning process based on multiple groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure; perform signal line layout processing at least according to the number of first signal lines and preset target layout conditions. That is to say, in the embodiment of the present application, the signal line layout processing device can create corresponding multiple groups of connection logic unit groups that can characterize the corresponding connection relationship of logic blocks according to the logic block layout structure after performing layout planning process to obtain the logic block layout structure corresponding to the chip to be designed, and perform signal line planning process based on the multiple groups of connection line logic unit groups, and then perform layout processing of the signal line according to the number of signal lines obtained by the planning process and the preset target layout conditions. It can be seen that the present application no longer starts the planning and processing of the through-signal lines after each completion of the layout planning-layout-wiring processing of the chip to be designed, and finally determines the optimal number of through-signal lines after multiple rounds of iteration. Instead, after completing the layout planning and processing of the chip to be designed, by creating a connection logic unit group that inherits the corresponding connection relationship of the logic block, the through-signal lines are planned and processed directly based on the connection logic unit group, and the layout processing of the through-signal lines is further executed in combination with the number of signal lines obtained by the planning processing and the preset target layout conditions, skipping the original layout process and adopting the local wiring processing method of the connection logic unit group, which greatly optimizes the planning and layout processing process of the through-signal lines, shortens the time, and is highly efficient, further accelerating the chip development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A A schematic diagram of the signal line connection relationship between different modules in the related technology;

[0022] Figure 1B A schematic diagram of signal line path planning in related technologies;

[0023] Figure 2 It is a schematic diagram of the planning and processing flow of the signal line in the related technology;

[0024] Figure 3 Schematic diagram 1 of the implementation flow of the signal line layout processing method proposed in the embodiment of the present application;

[0025] Figure 4 A schematic diagram of the layout of the connection logic unit group proposed in the embodiment of the present application;

[0026] Figure 5 Schematic diagram of the implementation process of the signal line layout processing method proposed in the embodiment of the present application Figure 2 ;

[0027] Figure 6 A schematic diagram of the planning and processing flow of a signal line through an embodiment of the present application;

[0028] Figure 7 Schematic diagram 1 of the composition structure of the through signal line layout processing device proposed in an embodiment of the present application;

[0029] Figure 8 Schematic diagram of the structure of the signal line layout processing device proposed in the embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. It is understood that the specific embodiments described herein are only used to explain the related applications, rather than to limit the applications. It should also be noted that, for ease of description, only the parts related to the related applications are shown in the drawings.

[0031] Before further describing the embodiments of the present invention in detail, the nouns and terms involved in the embodiments of the present invention are described. The nouns and terms involved in the embodiments of the present invention are subject to the following interpretations.

[0032] Nowadays, in the chip manufacturing process, chip design is undoubtedly the most important step, which mainly includes front-end design and back-end design. The front-end is mainly responsible for logic implementation, usually using languages ​​such as Verilog and Very-High-Speed ​​Integrated Circuit Hardware Description Language (VHDL) for behavioral description. The back-end is mainly responsible for turning the front-end design into a real schematic and layout (schematic & layout), tape-out, and mass production. To put it in a metaphor, the front-end is like making a blueprint, which can be functional and structural. The back-end turns the blueprint into a real high-rise building.

[0033] As system applications become more complex, the scale of chip design becomes larger and larger, and the development cycle of each chip becomes longer. At present, due to the market's pursuit of low cost and increasingly fierce competition, how to reduce chip costs and shorten the development cycle is crucial for chip design. For the design of ultra-large-scale chips, the excessive number of logic gates makes chip design mostly adopt a top-down, i.e., hierarchical, design method. However, since this hierarchical chip design method divides the chip into different sub-modules for separate processing, that is, the original timing path is distributed in different sub-modules, there is an interconnection relationship between different sub-modules of the chip.

[0034] At present, based on the hierarchical design method, the interconnection relationship between different sub-modules is usually processed at the top level; and in order to reduce the area consumed by the interconnection lines between the sub-modules on the top level, the modules are no longer interconnected through reserved channels, but directly use the method of penetrating signal lines to pass these interconnection lines through other modules to achieve interconnection between sub-modules. Figure 1A Schematic diagram of signal line connection relationship between different modules in related technology, such as Figure 1A As shown in the figure, the chip to be designed is divided into six submodules: A, B, C, D, E and F. Submodules A and F are interconnected, and submodules C and E are interconnected. However, since submodules A and F, and submodules C and E are not adjacent modules, the interconnection lines are more complicated. In order to better realize the interconnection between different submodules, based on Figure 1A The submodules shown are connected. Figure 1B A schematic diagram of signal line path planning in related technologies, such as Figure 1B As shown, submodules A and F are separated by submodules D and C, so the signal line indicated by the right slash fill can be passed through from submodule A to submodule D, then from submodule D to submodule C, and finally from submodule C to submodule F. In other words, the interconnection between submodules A and F is achieved by passing through the middle submodules B and C. Similarly, submodules C and E are separated by submodules B and D, so the signal line indicated by the left slash fill can be passed through the middle submodules B and D to achieve the interconnection between submodules C and E.

[0035] Since there will be hundreds of millions of connection lines between different sub-modules in the chip, and the number of interconnection lines will directly affect the implementation difficulty and area requirements of the module itself, therefore, when designing the chip back-end, how to better plan and layout the through-signal lines to minimize the number of through-signal lines is an important part of the entire back-end design process. Figure 2 It is a schematic diagram of the planning and processing flow of the signal line in the related technology, such as Figure 2As shown, the chip to be designed adopts hierarchical design. First, the original design data required for the chip to be designed is imported, including: gate-level netlist, timing constraints and various pre-configured library files, etc. (step 101). Then, the layout planning (Top Floorplan) processing is performed based on the design data, that is, the chip to be designed is divided into logic function modules of different sizes to determine the size, shape and position of each function module (step 102). Then, based on the layout planning processing result, the standard unit (standard The cell is laid out (step 103) and globally routed (Routing) is processed (step 104), and then based on the current layout and routing results, the through-signal line planning is processed (step 105), and the obtained planning result, i.e., the number of through-signal lines, is judged and processed to determine whether the planning conditions are met (step 106). In order to obtain the minimum number of through-signal lines as much as possible, there are generally multiple iterative processes of layout planning-layout-routing-evaluation through-processing, so as to finally achieve the optimal design of through-signal lines; after the planning conditions are met, the pin allocation (step 107), timing allocation budget (step 108), and block implementation (step 109) are continued, and finally the various partition modules are merged together to complete the sign-off of the full chip, i.e., to obtain Top&PartitionData.

[0036] However, in the related art, when designing the chip hierarchically at the back end, layout usually takes several hours or even more than a day, and wiring processing also takes several hours, and the specific time depends on the size of the chip. And as the chip process becomes more and more advanced, after entering deep submicron design, there will be more and more rule checks for layout. When our design data does not meet these rule checks, it will take longer to repair or even fail to complete the layout, which will also make the planning and layout time of the signal line through longer; at the same time, in the process of chip design, there are generally multiple iterative processes of layout planning-layout-wiring-through planning, and the same execution time needs to be completed multiple times in each iterative process, so that in the chip design process, it usually takes several days or even a week to do this iteration to obtain the layout planning of the optimal design through. It can be seen that in the related art, when designing the chip hierarchically at the back end, the through planning process always has the problem of taking too long, which leads to delays in the entire chip development cycle or even unacceptable defects, and there is a lot of room for optimization.

[0037] In order to solve the problem that the planning and layout of the signal lines through the chip hierarchical design process in the related art takes a long time, the embodiment of the present application provides a signal line through layout processing method and device, chip and storage medium. Specifically, the signal line through layout processing device can create a corresponding multiple groups of connection logic unit groups that can characterize the corresponding connection relationship of the logic blocks according to the logic block layout structure after performing layout planning processing to obtain the logic block layout structure corresponding to the chip to be designed, and perform signal line planning processing based on the multiple groups of connection line logic unit groups, and then perform layout processing of the signal lines through the signal lines according to the number of signal lines obtained by the planning processing and the preset target layout conditions. It can be seen that the present application no longer starts the planning and processing of the through-signal lines after each completion of the layout planning-layout-wiring processing of the chip to be designed, and finally determines the optimal number of through-signal lines after multiple rounds of iteration. Instead, after completing the layout planning and processing of the chip to be designed, by creating a connection logic unit group that inherits the corresponding connection relationship of the logic block, the through-signal lines are planned and processed directly based on the connection logic unit group, and the layout processing of the through-signal lines is further executed in combination with the number of signal lines obtained by the planning processing and the preset target layout conditions, skipping the original layout process and adopting the local wiring processing method of the connection logic unit group, which greatly optimizes the planning and layout processing process of the through-signal lines, shortens the time, and is highly efficient, further accelerating the chip development cycle.

[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0039] It should be noted that, in the embodiments of the present application, the feed-through signal line refers to a FeedThrough signal line.

[0040] It should be noted that the technical solution of the present application mainly relates to the back-end design field in the chip design process; and specifically to the layout planning in the chip design process, which runs through the signal line planning and layout processes.

[0041] It should be noted that in the embodiments of the present application, the chip back-end design adopts a hierarchical design (hierarchy design), which first divides the design into several modules, physically implements these modules separately, and then combines these modules into a complete design; the main process includes floor plan, power plan, placement, clock tree synthesis, routing, and verification simulation to tape-out.

[0042] An embodiment of the present application provides a calculation method. Figure 3Schematic diagram 1 of the implementation flow of the signal line layout processing method proposed in the embodiment of the present application, as shown in FIG. Figure 3 As shown, in an embodiment of the present application, a method for performing timing analysis through a signal line layout processing device may include the following steps:

[0043] Step 201: Perform a first layout planning process based on the original design data to determine a first logic block layout structure corresponding to the chip to be designed.

[0044] In an embodiment of the present application, the signal line layout processing device can obtain original design data corresponding to the chip to be designed, and then perform a first layout planning process based on the original design data, thereby obtaining a first logic block layout structure corresponding to the chip to be designed.

[0045] Optionally, in an embodiment of the present application, the through-signal line layout processing method may be implemented based on an electronic design automation (EDA) tool, that is, the main body that executes the through-signal line layout processing method may be a through-signal line layout processing device based on an EDA tool. It is understandable that an EDA tool may refer to a general computer-aided design (CAD) software package developed by integrating applied electronic technology, computer technology, and intelligent technology using a computer as a working platform.

[0046] It should be noted that in the embodiment of the present application, when the signal line layout processing device performs the back-end layout design of the chip to be designed, it is necessary to first obtain the design parameters corresponding to the chip to be designed, and the acquisition of the design parameters requires starting the chip back-end design process first.

[0047] Optionally, the signal line layout processing device can receive a layout design start instruction based on the user's related operations in the toolbar, and then respond to the instruction to start the back-end design process of the chip to be designed, and at the same time parse the layout design start instruction to obtain the relevant design parameters corresponding to the chip to be designed, that is, the original design data.

[0048] It should be noted that, in the embodiments of the present application, the original design data required for the chip to be designed includes pre-configured library files, gate-level netlists, and timing constraints; wherein the pre-configured library files may be library files of standard cells, macro cells, and I / O Pads provided by a chip foundry (Foundry), which include physical libraries, timing libraries, and netlist libraries, which are provided in the form of .lef, .tlf, and .v, respectively. The gate-level netlist and timing constraints are respectively the circuit netlist generated by the chip front-end design, the script file with timing constraints and clock definitions, and the resulting .gcf constraint file.

[0049] Furthermore, in an embodiment of the present application, after the signal line layout processing device obtains the circuit design parameters such as the pre-configured library file, gate-level netlist, and timing constraints required for the chip to be designed, it can further perform circuit layout planning processing based on these design data to determine a placement method corresponding to the chip to be designed, namely, the first logical layout structure.

[0050] Specifically, the signal line layout processing device can first divide the chip circuit to be designed into multiple functional modules, namely logic blocks, such as: main control core-partition, auxiliary peripheral-partition, IO-partition, RAM-partition, etc., and estimate the area occupied by each logic block, the position and the lead ports required for each block, so as to obtain the first logic layout structure corresponding to the chip to be designed.

[0051] Furthermore, in an embodiment of the present application, after the signal line layout processing device performs a first layout planning process based on the original design data to obtain a first logic block layout structure corresponding to the chip to be designed, it can further create a corresponding connection logic unit group according to the first logic block layout structure.

[0052] Step 202: Determine a plurality of groups of connection logic units corresponding to a plurality of logic blocks respectively according to the first logic block layout structure; wherein each group of connection logic units is used to represent a corresponding connection relationship of each logic block.

[0053] In an embodiment of the present application, after the signal line placement processing device performs a first layout planning process to obtain a corresponding first logic block layout structure, the signal line placement processing device can further determine multiple groups of connection logic units corresponding to multiple logic blocks according to the first logic block layout structure.

[0054] It should be noted that, in the embodiments of the present application, each group of connection logic units refers to the minimum logic unit group that can characterize the corresponding connection relationship of each logic block, that is, the signal line layout processing device can determine the minimum logic unit group that characterizes the corresponding connection relationship of the logic blocks based on the first logic block layout structure.

[0055] Specifically, a plurality of groups of connection logic units are created according to a plurality of groups of connection ports in the logic block layout structure; wherein the connection ports refer to ports for external connection between each logic block and other logic blocks having an interconnection relationship.

[0056] It can be understood that the chip to be designed includes multiple functional modules, and each functional module includes multiple connection ports. Therefore, in an embodiment of the present application, the logic block layout structure obtained after the chip to be designed is processed by floorplanning can include multiple logic blocks, and each logic block corresponds to a group of connection ports.

[0057] Specifically, in an embodiment of the present application, since the area occupied by each logic block, the position and the lead ports required for each block in the first logic block layout structure obtained after the first layout planning process have been temporarily determined, the signal line layout processing device can directly determine the multiple groups of connection ports corresponding to the multiple logic blocks based on the first logic block layout structure, and then establish the minimum logic unit corresponding to the multiple groups of connection ports, which can be used to characterize the corresponding connection relationship of the logic blocks.

[0058] More specifically, the signal line layout processing device may first obtain a script language corresponding to a connection port and used to characterize a circuit connection relationship, namely, a logic code file, and then generate a corresponding connection logic unit according to the logic code file corresponding to the connection port.

[0059] It should be noted that, in the embodiments of the present application, the connection ports correspond one to one with the connection logic units.

[0060] It can be understood that since the connection ports corresponding to each logic block are fixed at the boundary position of the logic block layout, the subsequent processing process with other associated logic blocks, especially the winding process, is more complicated and time-consuming. Therefore, in order to save time, the connection logic units inherit the same connection relationship of the connection ports, can be moved freely, and will not cause any changes to the circuit units Cell and layout of the original logic block layout structure.

[0061] Optionally, in an embodiment of the present application, a group of connection logic units corresponding to each logic block may be gathered at the center of the logic block layout. Figure 4 This is a schematic diagram of the layout of the connection logic unit group proposed in the embodiment of the present application, such as Figure 4 As shown, the connection logic unit groups represented by triangles are arranged at the center of each module.

[0062] Furthermore, in an embodiment of the present application, after determining the multiple groups of connection logic units corresponding to the multiple logic blocks according to the first logic block layout structure, the through-signal line layout processing device can further perform through-signal line planning processing based on the multiple groups of connection logic units to determine the number of the signal lines.

[0063] Step 203 : Perform first signal line planning processing based on the multiple groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure.

[0064] In an embodiment of the present application, after the signal line layout processing device determines the corresponding multiple groups of connection logic units based on the first logic block layout structure, the signal line layout processing device can further perform planning processing of the signal lines based on the multiple groups of connection logic units, and then determine the number of first signal lines corresponding to the first logic block layout structure.

[0065] It is understandable that since the through-mode is used to realize the connection between different modules, that is, between different connection ports, it is not suitable for the mutual connection of standard unit cells within the module. In other words, the planning of through-signal lines only involves the connection ports. Therefore, in order to save planning time, we can only consider the connection method and connection path between the connection ports to carry out the through-signal line planning process.

[0066] It should be noted that, in the embodiment of the present application, since the connection logic unit can represent the corresponding connection relationship of the logic block, the through-signal line layout processing device can perform through-signal line planning processing based on each group of connection logic units placed in the center of each logic block layout. It can be understood that the planning processing of the through-signal line is the process of determining the number of through-signal lines for the logic layout structure.

[0067] Specifically, in the embodiments of the present application, since the placement positions of the logic blocks in different logic layout structures are not the same, the logic blocks with an interconnected relationship may be placed in adjacent positions or in non-adjacent positions. Therefore, when connecting by connecting the logic unit group, there may be a variety of routing results. For example, if they are directly adjacent, they are directly connected. If they are not adjacent, they need to be routed across other modules. Corresponding to different routing results, when performing the through-signal line planning process, the number of through-signal lines obtained is also different.

[0068] It can be seen that different logic block layout structures correspond to different through-signal line planning processing results, that is, correspond to different numbers of through-signal lines.

[0069] Furthermore, in an embodiment of the present application, after performing first signal line planning processing based on multiple groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure, the through-signal line layout processing device can further perform through-signal line layout processing based on the first signal line number.

[0070] Step 204 , performing signal line layout processing at least according to the first number of signal lines and a preset target layout condition.

[0071] In an embodiment of the present application, after determining the number of first signal lines corresponding to the first logic block layout structure, the through-signal line layout processing device can further perform layout processing of the through-signal lines in combination with the first signal line number and a preset target layout condition.

[0072] It is understandable that since the number and path of the through-signal lines will indirectly affect the implementation difficulty and area requirement of the chip to be designed, the number of through-signal lines should be reduced as much as possible. In the embodiments of the present application, the preset target layout condition refers to the number of through-signal lines that can meet the requirements of the optimal layout.

[0073] Specifically, in an embodiment of the present application, if the number of first signal lines meets the preset target layout conditions, it indicates that the first logic block layout structure is the optimal layout result, and the through-signal line layout processing device can directly perform the through-signal line layout processing according to the first logic block layout structure and further execute the layout and routing process in the chip back-end design process.

[0074] Specifically, if the number of first signal lines does not meet the preset target layout conditions, the through-signal line layout processing device can continue to perform the second layout planning processing and the second signal line planning processing based on the above-mentioned original data to update the first logic block layout structure and the number of first signal lines, and obtain the number of second signal lines corresponding to the updated second logic block layout structure, and then perform the layout processing of the through-signal lines in combination with the number of first signal lines, the number of second signal lines and the preset target layout conditions.

[0075] It can be understood that when the number of signal lines corresponding to the layout structure after the update is the same as the number of signal lines corresponding to the layout structure before the update, that is, after the update processing is performed, the number of signal lines has not changed, and the rate of change is zero, the signal line layout processing device can determine that the current number of signal lines is optimal and the current logic block layout structure is optimal. Therefore, in an embodiment of the present application, if the number of second signal lines is the same as the number of first signal lines, that is, it is determined that the current second logic block layout structure is optimal, the signal line layout processing device can directly perform the layout processing of the signal lines according to the second logic block layout structure.

[0076] Further, in an embodiment of the present application, if the second logic block layout structure still does not meet the preset target layout conditions, then the through signal line continues to update the logic block layout structure and the number of signal lines based on the above-mentioned original design data until the number of i-th signal lines corresponding to the i-th logic block layout structure meets the preset target layout conditions, that is, the number of i-th signal lines is equal to the number of (i-1)-th signal lines, and the number of signal lines before and after the update processing no longer changes, and the through signal line layout processing device can determine that the i-th logic block layout structure is the optimal layout result, and the through signal line layout device can further perform through signal line layout processing according to the i-th logic block layout structure and execute the layout and routing process in the chip back-end design process.

[0077] It should be noted that, in an embodiment of the present application, if it is determined that the number of the i-th through signal lines does not meet the preset target layout conditions, that is, it indicates that the i-th logic block layout result is not optimal, then the through signal line layout processing device may need to continue to perform the i+1-th, i+2-th, ..., ..., i+n-th layout planning processing to update the logic block layout structure and the number of signal lines until the preset target layout conditions are met.

[0078] It should be noted that, in the embodiment of the present application, after determining the number of signal lines that meet the preset target layout conditions, the corresponding logic block layout structure can be saved, and the previously created multiple groups of connection logic units can be deleted, and the layout and routing process can be performed based on the logic block layout structure. Among them, deleting the connection logic unit does not cause any changes to the circuit unit Cell and the layout of the corresponding logic block layout structure.

[0079] Specifically, after deleting the connection logic unit, the through signal line layout processing device can perform automatic layout and automatic routing processing according to the optimal logic block layout structure. The automatic routing includes the routing between ordinary adjacent logic blocks and the through signal lines between non-adjacent logic blocks.

[0080] It can be seen that in the embodiment of the present application, the signal line layout processing device performs signal line planning processing directly based on the minimum logic unit group corresponding to each logic block connection port group in the virtual corresponding logic block layout, and then continues to execute the layout and routing process according to the optimal logic block layout structure based on the signal line planning processing result, that is, first perform signal line planning processing based on the minimum logic unit group corresponding to the logic block layout structure, determine the optimal number of signal lines, and then directly perform the global layout and routing process according to the logic block layout structure corresponding to the optimal number. Compared with the multiple iterative processes of layout planning processing-layout-routing-signal line evaluation in the original related technology, directly skipping the layout process and adopting the local wiring processing of the minimum logic unit group optimizes the planning and processing process of the signal line to a great extent, with short time and high efficiency, and further accelerates the chip development cycle.

[0081] The embodiment of the present application provides a method for processing the layout of a through-signal line. The through-signal line layout processing device can create a plurality of corresponding connection logic unit groups that can characterize the corresponding connection relationship of the logic blocks according to the logic block layout structure after performing layout planning processing to obtain the logic block layout structure corresponding to the chip to be designed, and perform signal line planning processing based on the plurality of connection line logic unit groups, and then perform layout processing of the through-signal lines according to the number of signal lines obtained by the planning processing and the preset target layout conditions. It can be seen that the present application is no longer to start the planning processing of the through-signal lines after completing the layout planning-layout-wiring processing of the chip to be designed each time, and finally determine the optimal number of through-signal lines after performing multiple rounds of iterations. Instead, after completing the layout planning processing of the chip to be designed, by creating a connection logic unit group that inherits the corresponding connection relationship of the logic block, directly perform the planning processing of the through-signal lines based on the connection logic unit group, and further perform the layout processing of the through-signal lines in combination with the number of signal lines obtained by the planning processing and the preset target layout conditions, skipping the original layout process, and adopting the local wiring processing method of the connection logic unit group, which greatly optimizes the planning and layout processing process of the through-signal lines, shortens the time, is efficient, and further accelerates the chip development cycle.

[0082] Based on the above embodiment, in another embodiment of the present application, Figure 5 Schematic diagram of the implementation process of the signal line layout processing method proposed in the embodiment of the present application Figure 2 ,like Figure 5 As shown, in an embodiment of the present application, a method for performing first signal line planning processing on a signal line layout processing device based on multiple groups of connection logic units to obtain the number of first signal lines corresponding to a first logic block layout structure may include the following steps:

[0083] Step 203a: Determine signal identifiers corresponding to multiple groups of connection logic units.

[0084] Step 203b: perform wiring processing on the multiple groups of connection logic units according to the signal identifiers to obtain wiring results.

[0085] In an embodiment of the present application, when performing planning processing of through-signal lines based on connection logic units, the through-signal line layout processing device can first determine the signal identifiers corresponding to multiple groups of connection logic units, and perform routing processing based on the signal identifiers, so as to further obtain the routing results.

[0086] It is understandable that, corresponding to the circuit connection relationship represented by the gate-level netlist, each connection port has its corresponding signal identifier, and connection ports with the same signal identifier can be connected to each other. In an embodiment of the present application, based on the connection relationship between the logic blocks corresponding to the connection port inherited by the connection logic unit, each connection logic unit also inherits the signal identifier corresponding to the connection port, and the connection logic unit can interconnect different logic blocks based on the same signal identifier.

[0087] For example, the connection port with the signal identification Q1 in logic block A can be connected to the connection port with the same signal identification Q1 in logic block C, so the connection logic unit with the signal identification Q1 in logic block A can also be connected to the connection logic unit with the signal identification Q1 in logic block C.

[0088] Furthermore, in an embodiment of the present application, the signal line layout processing device can follow the same signal identification, that is, the interconnection rule, to perform wiring processing on the connection logic unit, thereby obtaining a wiring result corresponding to the first logic block layout structure.

[0089] Specifically, in an embodiment of the present application, when performing wiring processing, if two logic blocks with the same signal identifier are non-adjacent logic blocks, that is, the logic blocks with an interconnection relationship are not adjacent, it is necessary to wind across other modules to connect the two logic blocks to each other. In order to save wiring space, the winding result obtained at this time is to change the connection method.

[0090] Specifically, in an embodiment of the present application, when performing routing processing, if two logic blocks with the same signal identifier are adjacent logic blocks, that is, the logic blocks with an interconnection relationship are adjacent, then the two logic blocks can be directly interconnected, and the routing result obtained is to maintain the connection mode.

[0091] Furthermore, in an embodiment of the present application, after determining the routing result, the through-signal line layout processing device can perform through-signal line planning processing based on the routing result to determine the number of through-signal lines.

[0092] Step 203c: perform first signal line planning processing based on the routing result to obtain the number of first signal lines.

[0093] In an embodiment of the present application, the signal line layout processing device may perform first signal line planning processing based on the routing result, and further determine the number of first signal lines corresponding thereto.

[0094] It should be noted that in the embodiments of the present application, when the wiring result is to maintain the connection mode, the wiring mode is optimal and there is no need to pass through the signal line mode; and when the wiring result is to change the connection mode, it indicates that the direct connection mode of the current interconnected logic block needs to be changed to a signal line passing through mode.

[0095] Optionally, the through-signal line layout processing device may be configured with a counter, and the counter is used to count the number of through-signal lines.

[0096] Furthermore, the through-signal line layout processing device can traverse all logic units after the routing processing, replace the connection mode between all signal lines whose routing results are changed connection mode with through-signal lines, and obtain the number of all through-signal lines through a counter.

[0097] The embodiment of the present application provides a through-signal line layout processing method. The through-signal line layout processing device can directly perform routing processing on the minimum logic unit group corresponding to the logic block, and further implement the planning processing of the through-signal line based on the routing result of the minimum logic unit group to determine the corresponding number of through-signal lines, directly skip the layout process and adopt the local wiring processing of the connected logic unit, which greatly optimizes the planning processing process of the through-signal line, the planning process is short in time and high in efficiency, and further accelerates the chip development cycle.

[0098] Based on the above embodiments, in the embodiments of the present application, Figure 6 This is a schematic diagram of the planning and processing flow of the signal line through the embodiment of the present application, such as Figure 6As shown, the chip to be designed adopts a hierarchical design. The signal line layout processing device first imports the original design data required by the chip to be designed, including: gate-level netlist, timing constraints and various pre-configured library files, etc. (step 301), and then performs layout planning based on the design data (Top The design chip is divided into logic function modules of different sizes to determine the size, shape and position of each function module (step 302), and then the corresponding connection logic unit is created based on the logic block layout structure obtained by the floorplanning process, and is placed at the center of the layout of the corresponding logic block (step 303), and then the connection logic unit is processed to obtain the wiring result (step 304); further, the through-signal line layout processing device performs through-signal line planning processing based on the wiring result to obtain the corresponding through-signal line number (step 305), and determines whether the preset target planning condition is met according to the through-signal line number (step 306). If it is not met at present, the next floorplanning process is continued to the through-signal line planning process, that is, the execution of step 302 is jumped until the preset target planning condition is met; if it is met at present, the standard process of chip back-end design such as layout and routing is directly performed based on the logic block layout structure corresponding to the optimal through-signal line number (step 307), until the full chip is signed off and the Top & Partition Data is obtained.

[0099] The embodiment of the present application provides a method for processing the layout of a through-signal line. The through-signal line layout processing device performs through-signal line planning processing directly based on the minimum logic unit group corresponding to the connection port group of each logic block in the virtual corresponding logic block layout, and then directly performs through-signal line planning processing based on the minimum logic unit group corresponding to the different logic block layout structures, determines the optimal number of through-signal lines, and then directly performs a global layout and routing process according to the logic block layout structure corresponding to the optimal number. Compared with the multiple iterations of layout planning processing-layout-routing-through-signal line evaluation in the original related technology, it directly skips the layout process and adopts the local routing processing of the minimum logic unit group, which greatly optimizes the planning and processing process of the through-signal line, shortens the time, and is highly efficient, further accelerating the chip development cycle.

[0100] Based on the above embodiment, in another embodiment of the present application, Figure 7 The first schematic diagram of the structure of the signal line layout processing device proposed in the embodiment of the present application is as follows: Figure 7 As shown, the signal line layout processing device 10 proposed in the embodiment of the present application may include a first processing unit 11, a determination unit 12, a second processing unit 13, and a third processing unit 14.

[0101] The first processing unit 11 is used to perform a first layout planning process based on the original design data to determine a first logic block layout structure corresponding to the chip to be designed;

[0102] The determining unit 12 is used to determine a plurality of groups of connection logic units corresponding to a plurality of logic blocks respectively according to the first logic block layout structure; wherein each group of connection logic units is used to represent a corresponding connection relationship of each logic block;

[0103] The second processing unit 13 is used to perform first signal line planning processing based on the multiple groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure;

[0104] The third processing unit 14 is configured to perform signal line layout processing at least according to the first number of signal lines and a preset target layout condition.

[0105] Furthermore, in an embodiment of the present application, the first processing unit 11 is also used to perform a first signal line planning process based on the multiple groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure, and then perform a second layout planning process based on the original design data.

[0106] Furthermore, in an embodiment of the present application, the second processing unit 13 is further configured to perform second signal line planning processing to obtain the number of second signal lines corresponding to the second logic block layout structure.

[0107] Furthermore, in an embodiment of the present application, the third processing unit 14 is further configured to perform the signal line layout processing at least according to the first number of signal lines, the second number of signal lines, and the preset target layout condition.

[0108] Furthermore, in an embodiment of the present application, each group of connection logic units is placed at the layout center of each logic block.

[0109] Further, in an embodiment of the present application, the determination unit 12 is specifically used to determine the multiple groups of connection ports corresponding to the multiple logic blocks based on the first logic block layout structure; wherein the connection interface is used to interconnect signal lines between different logic blocks, and one logic block corresponds to a group of connection ports; and to establish the multiple groups of connection logic units corresponding to the multiple groups of connection ports; wherein a group of connection ports corresponds to a group of connection logic units.

[0110] Further, in an embodiment of the present application, the determining unit 12 is further specifically configured to obtain logic code files corresponding to the multiple groups of connection ports; and generate the multiple groups of connection logic units according to the logic code files.

[0111] Further, in an embodiment of the present application, the second processing unit 13 is specifically used to determine the signal identifiers corresponding to the multiple groups of connection logic units; and perform winding processing on the multiple groups of connection logic units according to the signal identifiers to obtain winding results; and perform the first signal line planning processing based on the winding results to obtain the first signal line number.

[0112] Furthermore, in an embodiment of the present application, the second processing unit 13 is also specifically used to, when performing the routing processing, if the two logic blocks with the same signal identifier are non-adjacent logic blocks, determine that the routing result is to change the connection mode; and when performing the routing processing, if the two logic blocks with the same signal identifier are adjacent logic blocks, determine that the routing result is to maintain the connection mode.

[0113] Furthermore, in an embodiment of the present application, the second processing unit 13 is also specifically used to change the signal line connection method corresponding to the non-adjacent logic block to a through-signal line when the routing result is the changed connection method, and perform counting processing of the through-signal line; and traverse all connected logic units after the routing processing, and determine the number of the first signal lines through the counting processing.

[0114] Furthermore, in an embodiment of the present application, the third processing unit 14 is specifically used to determine that the preset target planning condition is met when the number of the second signal lines is the same as the number of the first signal lines; and to perform layout processing of the signal lines according to the second logic block layout structure.

[0115] In the embodiments of the present application, further, Figure 8 Schematic diagram of the structure of the signal line layout processing device proposed in the embodiment of the present application Figure 2 ,like Figure 8 As shown, the signal line layout processing device 10 proposed in the embodiment of the present application may also include a processor 15 and a memory 16 storing executable instructions of the processor 15. Further, the signal line layout processing device 10 may also include a communication interface 17 and a bus 18 for connecting the processor 15, the memory 16 and the communication interface 17.

[0116] In the embodiment of the present application, the processor 15 can be at least one of an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a central processing unit (CPU), a controller, a microcontroller, and a microprocessor. It can be understood that for different devices, the electronic device used to implement the function of the processor can also be other, and the embodiment of the present application is not specifically limited. The signal line layout processing device 10 can also include a memory 16, which can be connected to the processor 15, wherein the memory 16 is used to store executable program code, the program code includes computer operation instructions, and the memory 16 may include a high-speed RAM memory, and may also include a non-volatile memory, for example, at least two disk memories.

[0117] In the embodiment of the present application, the bus 18 is used to connect the communication interface 17, the processor 15 and the memory 16, and the mutual communication between these devices.

[0118] In the embodiment of the present application, the memory 16 is used to store instructions and data.

[0119] Further, in an embodiment of the present application, the processor 15 is used to perform a first layout planning process based on the original design data to determine a first logic block layout structure corresponding to the chip to be designed;

[0120] Determine a plurality of groups of connection logic units corresponding to a plurality of logic blocks respectively according to the first logic block layout structure; wherein each group of connection logic units is used to characterize the corresponding connection relationship of each logic block;

[0121] Performing first signal line planning processing based on the plurality of groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure;

[0122] Signal line layout processing is performed according to at least the first number of signal lines and a preset target layout condition.

[0123] In practical applications, the memory 16 may be a volatile memory, such as a random access memory (RAM); or a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk (HDD) or a solid-state drive (SSD); or a combination of the above types of memory, and provide instructions and data to the processor 15.

[0124] In addition, each functional module in this embodiment can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or software functional modules.

[0125] If the integrated unit is implemented in the form of a software function module and is not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) or a processor to perform all or part of the steps of the method of this embodiment. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0126] The embodiment of the present application provides a signal line layout processing device, which can create a corresponding connection logic unit group that can characterize the interconnection relationship between different logic blocks according to the logic block layout structure after performing layout planning processing to obtain the logic block layout structure corresponding to the chip to be designed, and perform signal line planning processing based on the connection line logic unit group, and then perform layout processing of the signal line according to the number of signal lines obtained by planning processing and the preset target layout conditions. It can be seen that the present application is no longer to start the planning processing of the signal line after completing the layout planning-layout-wiring processing of the chip to be designed each time, and finally determine the optimal number of signal lines after performing multiple rounds of iterations. Instead, after completing the layout planning processing of the chip to be designed, by creating a connection logic unit group that inherits the corresponding connection relationship of the logic block, directly perform the planning processing of the signal line based on the connection logic unit group, and combine the number of signal lines obtained by planning processing and the preset target layout conditions, further perform the layout processing of the signal line, skip the original layout process, and adopt the local wiring processing method of the connection logic unit group, which greatly optimizes the planning and layout processing process of the signal line, shortens the time, and is highly efficient, further accelerating the chip development cycle.

[0127] An embodiment of the present application provides a computer-readable storage medium on which a program is stored. When the program is executed by a processor, the above-mentioned through-signal line layout processing method is implemented.

[0128] Specifically, the program instructions corresponding to the through-signal line layout processing method in this embodiment can be stored in a storage medium such as a CD, a hard disk, a USB flash drive, etc. When the program instructions corresponding to the through-signal line layout processing method in the storage medium are read or executed by an electronic device, the following steps are included:

[0129] Performing a first layout planning process based on the original design data to determine a first logic block layout structure corresponding to the chip to be designed;

[0130] Determine a plurality of groups of connection logic units corresponding to a plurality of logic blocks respectively according to the first logic block layout structure; wherein each group of connection logic units is used to characterize the corresponding connection relationship of each logic block;

[0131] Performing first signal line planning processing based on the plurality of groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure;

[0132] Signal line layout processing is performed according to at least the first number of signal lines and a preset target layout condition.

[0133] The embodiment of the present application provides a chip, which includes a processor and an interface, wherein the processor obtains program instructions through the interface, and the processor is used to run the program instructions to implement the above-mentioned through-signal line layout processing method. Specifically, the through-signal line layout processing method includes the following steps:

[0134] Performing a first layout planning process based on the original design data to determine a first logic block layout structure corresponding to the chip to be designed;

[0135] Determine a plurality of groups of connection logic units corresponding to a plurality of logic blocks respectively according to the first logic block layout structure; wherein each group of connection logic units is used to characterize the corresponding connection relationship of each logic block;

[0136] Performing first signal line planning processing based on the plurality of groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure;

[0137] Signal line layout processing is performed according to at least the first number of signal lines and a preset target layout condition.

[0138] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of hardware embodiments, software embodiments, or embodiments in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) that contain computer-usable program code.

[0139] The present application is described with reference to the implementation flow diagram and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each flow and / or box in the flow diagram and / or block diagram can be implemented by computer program instructions, and the combination of the flow diagram and / or box in the block diagram can be implemented. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the function specified in one flow or multiple flows and / or one box or multiple boxes of the block diagram.

[0140] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in implementing one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0141] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes of the flowchart and / or one or more blocks of the block diagram. The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application.

Claims

1. A method for processing a through signal line layout, characterized in that: The method comprises: Performing a first layout planning process based on the original design data to determine a first logic block layout structure corresponding to the chip to be designed; Determine a plurality of groups of connection logic units corresponding to a plurality of logic blocks respectively according to the first logic block layout structure; wherein each group of connection logic units is used to characterize the corresponding connection relationship of each logic block; Performing first signal line planning processing based on the plurality of groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure; performing signal line layout processing according to at least the first number of signal lines and a preset target layout condition; Wherein, after performing first signal line planning processing based on the plurality of groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure, the method further includes: Performing second layout planning processing and second signal line planning processing based on the original design data to obtain the number of second signal lines corresponding to the second logic block layout structure; The signal line layout process is performed at least according to the first number of signal lines, the second number of signal lines, and the preset target layout condition.

2. The method according to claim 1, characterized in that Each set of connected logic cells is placed at the center of the layout of each logic block.

3. The method according to claim 1, characterized in that The step of determining, according to the first logic block layout structure, a plurality of groups of connection logic units corresponding to the plurality of logic blocks respectively comprises: Determine a plurality of groups of connection ports corresponding to the plurality of logic blocks based on the first logic block layout structure; wherein the connection interface is used to interconnect signal lines between different logic blocks, and one logic block corresponds to a group of connection ports; Establishing the multiple groups of connection logic units corresponding to the multiple groups of connection ports; wherein one group of connection ports corresponds to one group of connection logic units.

4. The method according to claim 3, characterized in that The establishing of the plurality of connection logic units corresponding to the plurality of connection ports comprises: Obtaining logic code files corresponding to the multiple groups of connection ports; The plurality of connection logic units are generated according to the logic code file.

5. The method according to claim 1, characterized in that The performing first signal line planning processing based on the plurality of groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure includes: Determining signal identifiers corresponding to the multiple groups of connection logic units; Performing winding processing on the plurality of groups of connection logic units according to the signal identifiers to obtain winding results; The first signal line planning process is performed based on the routing result to obtain the first number of signal lines.

6. The method according to claim 5, characterized in that The step of performing winding processing on the plurality of groups of connection logic units according to the signal identifier to obtain winding results includes: When performing the wiring process, if the two logic blocks with the same signal identifier are non-adjacent logic blocks, determining that the wiring result is to change the connection mode; When performing the routing process, if the two logic blocks with the same signal identifier are adjacent logic blocks, the routing result is determined to be a connection-maintaining mode.

7. The method according to claim 6, characterized in that When the wiring result is the connection mode change, performing the first signal line planning process based on the wiring result to obtain the number of the first signal lines includes: The signal line connection mode corresponding to the non-adjacent logic blocks is replaced with a through signal line, and a counting process of the through signal line is performed; All the connection logic units after the wiring process are traversed, and the number of the first signal lines is determined by the counting process.

8. The method according to claim 1, characterized in that The performing the signal line layout processing at least according to the first number of signal lines, the second number of signal lines and the preset target layout condition comprises: When the number of the second signal lines is the same as the number of the first signal lines, determining that the preset target planning condition is met; The signal line layout process is performed according to the second logic block layout structure.

9. A through signal line layout processing device, characterized in that: The layout processing device comprises: a first processing unit, a determining unit, a second processing unit and a third processing unit. The first processing unit is used to perform a first layout planning process based on the original design data to determine a first logic block layout structure corresponding to the chip to be designed; The determining unit is used to determine a plurality of groups of connection logic units corresponding to a plurality of logic blocks respectively according to the first logic block layout structure; wherein each group of connection logic units is used to represent a corresponding connection relationship of each logic block; The second processing unit is used to perform first signal line planning processing based on the multiple groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure; The third processing unit is used to perform signal line layout processing according to at least the first number of signal lines and a preset target layout condition; The first processing unit is further configured to perform a second layout planning process based on the original design data after performing a first signal line planning process based on the plurality of groups of connection logic units to obtain the number of first signal lines corresponding to the first logic block layout structure; The second processing unit is further used to perform second signal line planning processing to obtain the number of second signal lines corresponding to the second logic block layout structure; The third processing unit is further configured to perform the signal line layout processing at least according to the first number of signal lines, the second number of signal lines, and the preset target layout condition.

10. A through signal line layout processing device, characterized in that: The layout processing device includes a processor and a memory storing instructions executable by the processor. When the instructions are executed by the processor, the method according to any one of claims 1 to 8 is implemented.

11. A chip, characterized in that: The chip includes a processor and an interface, the processor obtains program instructions through the interface, and the processor is used to run the program instructions to execute the method according to any one of claims 1-8.

12. A computer-readable storage medium having a program stored thereon, applied to a through-signal line layout processing device, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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