Redundancy filling method, redundancy filling device, and electronic device

Abstract

An embodiment of the present invention provides a redundancy filling method, a redundancy filling device, and an electronic device. The redundancy filling method includes: providing a first circuit layout; obtaining a first target layout on the first circuit layout to fill redundant patterns on the first target layout; determining a second target layout on the first circuit layout according to the first target layout filled with redundant patterns; and filling redundant patterns on the second target layout. By ensuring that the same redundant patterns are filled on the key areas in the first circuit layout, the embodiment of the present invention avoids the phenomenon that filling offset may occur on the key areas of the circuit layout.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a redundant filling method, a redundant filling device, and an electronic device. Background Art

[0002] In the design process of integrated circuit chips, after the timing and function convergence are completed, it will enter the design for manufacturability (DFM) stage. At this time, the graphic wiring on the chip circuit layout is not uniform. Therefore, a planarization process needs to be performed on the surface of the chip to improve the uniformity of the graphic wiring. However, the planarization process will bring butterfly defects and erosion defects to the chip.

[0003] In related processes, a redundant filling method is generally used to avoid the above-mentioned defects brought by the planarization process to the chip. For example, the circuit layout is divided into several grids with relatively fixed positions and filled, which may cause the filling offset in the key areas on the circuit layout, affecting the manufacturability of the corresponding design. Summary of the Invention

[0004] Embodiments of the present invention provide a redundant filling method, a redundant filling device, and an electronic device, aiming to at least partially solve the problem that the redundant filling method is prone to cause filling offset in the key areas on the circuit layout.

[0005] Embodiments of the present invention provide a redundant filling method, including: providing a first circuit layout; obtaining a first target layout on the first circuit layout to fill redundant patterns on the first target layout; determining a second target layout on the first circuit layout according to the first target layout filled with the redundant patterns; and filling the redundant patterns on the second target layout.

[0006] Wherein, the obtaining the first target layout on the first circuit layout to fill redundant patterns on the first target layout includes: scanning the first circuit layout to obtain the first target layout; determining the area to be filled and the filling scheme in the first target layout; and filling the redundant patterns on the area to be filled according to the filling scheme.

[0007] Wherein, the determining the area to be filled and the filling scheme in the first target layout includes: obtaining the pattern density in the first target layout; and determining the area to be filled and the filling scheme according to the pattern density.

[0008] Among them, determining the second target layout on the first circuit layout according to the first target layout filled with the redundant pattern includes: obtaining all the first target layouts on the first circuit layout according to the first target layout; merging the first target layout with the redundant pattern; using the redundant pattern as a marking pattern, screening out the first target layouts not filled with the redundant pattern from all the first target layouts to determine the second target layout.

[0009] Among them, after filling the redundant pattern on the second target layout, it further includes: merging all the marking patterns corresponding to the redundant pattern to form a marking layer; merging the marking layer with the first circuit layout to generate a second circuit layout.

[0010] Among them, after merging the marking layer with the first circuit layout to generate a second circuit layout, it further includes: performing a design rule check on the second circuit layout.

[0011] Among them, after performing a design rule check on the second circuit layout, it further includes: removing the redundant patterns in the second circuit layout that violate the design rules.

[0012] Among them, the filling scheme includes at least one of the following: the line width of the redundant pattern, the shape of the redundant pattern, and the layout of the redundant pattern.

[0013] An embodiment of the present invention provides an electronic device, which includes one or more memories and one or more processors. The one or more memories store computer-executable programs. When the computer-executable programs are called by the one or more processors, they execute the redundant filling method as described above.

[0014] An embodiment of the present invention further provides a redundant filling device, including: a providing module for providing a first circuit layout; an obtaining module for obtaining a first target layout on the first circuit layout to fill a redundant pattern on the first target layout; a determining module for determining a second target layout on the first circuit layout according to the first target layout filled with the redundant pattern; a filling module for filling the redundant pattern on the second target layout.

[0015] An embodiment of the present invention provides a redundancy filling method, a redundancy filling device, and an electronic device. The redundancy filling method includes: providing a first circuit layout; obtaining a first target layout on the first circuit layout to fill redundant patterns on the first target layout; determining a second target layout on the first circuit layout according to the first target layout filled with the redundant patterns; and filling the redundant patterns on the second target layout. By first obtaining the first target layout from the first circuit layout to determine the redundant patterns to be filled on the first target layout and performing corresponding redundancy filling, and then finding the second target layout on the first circuit layout according to the first target layout and filling the corresponding redundant patterns, it is ensured that the same redundant patterns are filled on the key areas in the first circuit layout, thereby avoiding the phenomenon that the filling may be offset on the key areas of the circuit layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the description of each embodiment according to the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative efforts.

[0017] Figure 1 is a flowchart of the redundancy filling method provided by an embodiment of the present invention;

[0018] Figures 2A - 2F is a schematic diagram of a circuit board in each stage of the redundancy filling method provided by an embodiment of the present invention;

[0019] Figure 3 is another flowchart of the redundancy filling method provided by an embodiment of the present invention;

[0020] Figure 4 is yet another flowchart of the redundancy filling method provided by an embodiment of the present invention;

[0021] Figure 5 is an application schematic diagram of window - type redundancy filling provided by an embodiment of the present invention;

[0022] Figure 6 is a schematic diagram of the structure of the redundancy filling device provided by an embodiment of the present invention;

[0023] Figure 7 is a schematic diagram of the structure of the electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present invention.

[0025] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0026] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, an electrical connection, or a connection that can communicate with each other; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] In the present invention, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features between them. Moreover, the first feature being "above", "over", and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or simply means that the horizontal height of the first feature is higher than that of the second feature. The first feature being "below", "under", and "beneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or simply means that the horizontal height of the first feature is lower than that of the second feature.

[0028] The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art can realize the application of other processes and / or the use of other materials.

[0029] An embodiment of the present invention provides a redundancy filling method, a redundancy filling device, and an electronic device.

[0030] Please refer to Figure 1 , Figure 1 which is a schematic flowchart of the redundancy filling method provided by an embodiment of the present invention. This redundancy filling method can be specifically used in the manufacturability design of an integrated circuit layout. As Figure 1 shown, the method may specifically include the following steps:

[0031] Step S101: Provide a first circuit layout.

[0032] Among them, the schematic structural diagram of the circuit layout after step S101 is completed is as Figure 2A shown. In Figure 2A , taking the shown target pattern 11 and non-target patterns 12 and 13 as representatives, other repeated structures are not all shown.

[0033] Specifically, the first circuit layout 10 is an integrated circuit layout, which schematically shows the planar geometry of the physical situation of the integrated circuit and is the result of the physical design of the underlying steps. In this embodiment, the physical design of the first circuit layout 10 converts the results of logic synthesis into a physical layout file through layout, wiring, etc. The corresponding file format is the GDS (Graphic DataStream) format. The physical layout file contains the shape, area, and position information of each hardware unit on the layout. Further, the first circuit layout 10 is an integrated circuit layout including a metal structure. The metal structure can be a metal wiring layer or a metal interconnection layer. That is, in this embodiment, the first circuit layout 10 can be defined as an integrated circuit layout that has undergone metallization or multi-layer interconnection processes but has not undergone the redundancy filling process. Therefore, Figure 2AThe circuit layout in [it] is the first circuit layout 10 because the redundant filling process is not performed. Since different metal structures play different roles, the metal structures can be further divided into critical patterns and non-critical patterns. In this embodiment, taking the target pattern 11 as the critical pattern and one non-target pattern 12 and another non-target pattern 13 as non-critical patterns as an example, the target pattern 11 has higher requirements for dimensional accuracy, and when its size fluctuates, it has a greater impact on the performance of semiconductor devices. In this embodiment, the distribution state of the target pattern 11 on the first circuit layout 10 can be an array distribution or a random distribution, that is, the target pattern 11 can be selectively set in any area on the first circuit layout 10.

[0034] Step S102: Obtain the first target layout on the first circuit layout to fill redundant patterns on the first target layout.

[0035] Please refer to Figure 3 , Figure 3 which is another schematic flow chart of the redundant filling method provided by the present invention. As Figure 3 shown, this step S102 may specifically include the following steps:

[0036] Step S1021: Scan the first circuit layout to obtain the first target layout.

[0037] Among them, the schematic structural diagram of the circuit board after step S1021 is completed is as Figure 2B shown.

[0038] In this example, the first target layout 101 is obtained by scanning the first circuit layout 10. The first target layout 101 is the smallest layout containing the target pattern 11, and one such first target layout 101 corresponds to a critical area on the first circuit layout 10. As Figure 2B shown, the origin O of the lower left corner area of the first circuit layout 10 can be selected as the scanning starting point, and the first target layout 101 on the first circuit layout 10 is searched in the x direction and y direction as the scanning direction. When the first first target layout 101 is found, the scanning stops. Among them, the position of the first target layout 101 on the first circuit layout 10 can be realized by analyzing the key role played by the target pattern 11 in the first circuit layout 10.

[0039] Step S1022: Determine the area to be filled and the filling scheme in the first target layout.

[0040] Among them, the schematic diagram of the circuit board after step S1022 is completed is as Figure 2C shown.

[0041] After finding a first target layout 101, it is necessary to determine the area 1011 to be filled with the redundant pattern 14 shown in Figure 2D on the current first target layout 101, so as to avoid filling the redundant pattern 14 onto the target pattern 11 during redundant filling, which would exacerbate the distribution difference of the surface topography. Specifically, step S1022 may include: obtaining the pattern density in the first target layout; determining the area to be filled and the filling scheme according to the pattern density. In this embodiment, the pattern density refers to the area occupied by the target pattern 11 in the first target layout 101 divided by the area of the region occupied by the first target layout 101. Among them, the pattern density should meet the minimum density criterion of the internal connection in the metal layer. In this embodiment, when the pattern density is less than the set range, such as 10% - 20%, redundant filling is performed. In addition, the pattern density also reflects the actual distribution of the target pattern 11. Therefore, a corresponding filling scheme is further designed according to the actual distribution of the target pattern 11.

[0042] Step S1023: Fill the redundant pattern on the area to be filled according to the filling scheme.

[0043] After step S1023 is completed, the schematic diagram of the circuit board layout is as shown in Figure 2D shown.

[0044] Specifically, the corresponding filling scheme includes at least one of the following: the line width of the redundant pattern 14, the shape of the redundant pattern 14, and the layout of the redundant pattern 14. Specifically, the purpose of designing a certain filling scheme is, on the one hand, to improve the etching load effect, and on the other hand, to reduce the coupling capacitance brought about by filling the redundant pattern 14. Especially when the redundant filling is applied globally to the circuit board diagram, the increased coupling capacitance becomes more obvious and has a relatively obvious impact on the circuit characteristics. In this embodiment, the shape of the redundant pattern 14 can be specifically set to at least one of a square, a rhombus, and a cross. Among them, compared with setting the redundant pattern 14 as a square, setting the redundant pattern 14 as a cross or a rhombus can further reduce the magnitude of the parasitic coupling capacitance. In addition, it should be noted that the layout and line width design of the redundant pattern 14 are the main ways to solve the etching load effect on the first target layout 101. By reasonably setting the line width and layout of the redundant pattern 14 (the row and column arrangement of the redundant pattern 14), the pattern density of the redundant pattern 14 and the target pattern 11 in the area where the first target layout 101 is located is made uniform. Since the added redundant pattern 14 is not used for the actual connection of the device and is to improve the uniformity of the metal structure in the integrated circuit layout, in this way, defects can be reduced in the Chemical Mechanical Polish (CMP) process, the flatness of the chip surface after the CMP process can be improved, and the etching load effect can be greatly alleviated. After step S102, the redundant pattern 14 has been formed on the first circuit layout 10. According to the definition of the first circuit layout 10, Figure 2D and the circuit layout corresponding to the subsequent drawings is no longer the same as Figures 2A - 2C the corresponding circuit layout in

[0045] Step S103: Determine the second target layout on the first circuit layout according to the first target layout filled with the redundant pattern.

[0046] Among them, the schematic diagram of the circuit layout after step S103 is as shown in Figure 2E shown. The second target layout 102 is actually a set of the first target layouts 101 that are not filled with the redundant pattern 14. The second target layout 102 can include one or more first target layouts 101 that are not filled with the redundant pattern 14. In Figure 2E it is shown that the second target layout 102 can include one first target layout 101 that is not filled with the redundant pattern 14. At this time, the overall shape of the second target layout 102 is the same as the shape of the first target layout 101. In other embodiments of the present invention, the second target layout 102 can also include multiple first target layouts 101 that are not filled with the redundant pattern 14. At this time, the overall shape of the second target layout 102 is different from the shape of the first target layout 101.

[0047] Among them, please refer to Figure 4 , and step S103 may specifically include:

[0048] Step S1031: Obtain all the first target layout patterns on the first circuit layout pattern according to the first target layout pattern.

[0049] Among them, the way to obtain all the first target layout patterns 101 is also to scan the GDS file corresponding to the first circuit layout pattern 10. Since a first target layout pattern 101 has been obtained in step S102, when looking for all the first target layout patterns 101, only need to compare the scanned graphics with the first obtained first target layout pattern 101 to determine the other first target layout patterns 101, rather than analyzing the functions of each scanned target graphic 11 in turn to judge. Therefore, obtaining all the first target layout patterns 101 according to the first target layout pattern 101 can improve the corresponding obtaining speed.

[0050] Step S1032: Merge the first target layout pattern with the redundant graphic.

[0051] Step S1033: Using the redundant graphic as a marker graphic, screen out the first target layout patterns that are not filled with the redundant graphic from all the first target layout patterns to determine the second target layout pattern.

[0052] Among them, after the first target layout pattern 101 is merged with the redundant graphic 14, since the redundant graphic 14 is a marker graphic, therefore, the redundant graphic 14 can play a role in identification, so that among all the first target layout patterns 101, the first target layout patterns 101 filled with the redundant graphic 14 and the first target layout patterns 101 not filled with the redundant graphic 14 can be distinguished, so as to screen out one or more first target layout patterns 101 not filled with the redundant graphic 14 to determine the second target layout pattern 102.

[0053] Step S104: Fill the redundant graphic on the second target layout pattern.

[0054] Among them, the schematic diagram of the circuit layout pattern after step S104 is as Figure 2F shown.

[0055] In this embodiment, the material of the redundant pattern 14 may be polysilicon or metallic copper, where metallic copper is used for the redundant pattern 14 with a smaller line width. According to steps S1021 to S1023, the fillable region 1011 and the filling scheme for the first target layout 101 have been obtained. Therefore, the first target layout 101 in the second target layout 102 that is not filled with the redundant pattern 14 can be redundantly filled in the same manner by referring to the fillable region 1011 and the filling scheme of the first target layout 101 filled with the redundant pattern 14, so that the same redundant pattern 14 is filled on all the first target layouts 101.

[0056] In this embodiment, since all the first target layouts 101 in the first circuit layout 10 are filled with the same redundant pattern 14, that is, all the critical regions in the first circuit layout 10 are filled with the same redundant pattern 14, the phenomenon that the filling may shift in the critical regions on the circuit layout is avoided.

[0057] To further illustrate the differences between the embodiment of the present invention and the grid-based redundant fill (dummy fill), please refer to Figure 5 , the grid redundant fill is a fixed partitioning and filling method, which divides the integrated circuit layout into multiple grids 100 with the same area, as Figure 5 shown. These multiple grids 100 are classified into grid 100A, grid 100B, grid 100C, grid 100D, grid 100E, etc. according to their different distribution positions. Then, redundant filling is performed based on the pattern density of each grid 100. As long as the pattern density of the divided grid 100 does not meet the preset standard (such as grid 100A, grid 100D, and grid 100E), redundant filling is performed on this grid 100. If the pattern density of the divided grid 100 meets the preset standard (such as grid 100B and grid 100C), even if the pattern distribution in this grid 100 is extremely uneven and there are even blank areas (such as area B in grid 100B and area C in grid 100C), redundant filling will not be performed on this blank area. Therefore, as Figure 5 shown, if the grid-based redundant fill is adopted, different redundant patterns will be filled in the same first target layout 101. Therefore, the filling method provided by the embodiment of the present invention can solve this problem.

[0058] Please refer to Figure 4 , after step S104, it further includes:

[0059] Step S105: Merge all the marked patterns corresponding to the redundant pattern to form a marked layer;

[0060] Step S106: Merge the marking layer with the first circuit layout to generate a second circuit layout.

[0061] After the marking layer and the first circuit layout 10 are merged to generate the second circuit layout, the marking layer can identify the position of the redundant pattern 14 itself in the second circuit layout. At the same time, the marking layer can also indirectly indicate the target pattern 11. The second circuit layout (not shown in the figure) is obtained by merging the first circuit layout 10 and the marking layer. The marking layer includes all the marking patterns corresponding to the redundant pattern 14. Therefore, the second circuit layout can be defined as an integrated circuit layout that further includes all the redundant patterns 14 on the basis of the first circuit layout 10.

[0062] As Figure 4 shown, after step S106, it further includes:

[0063] Step S107: Perform a design rule check on the second circuit layout.

[0064] In this embodiment, a design rule check (DRC) is used to scan each first target layout 101 filled with the redundant pattern 14 in the second circuit layout. The design rule check is a software tool used to determine whether the circuit layout complies with a set of design rules. The design rules in this embodiment can be whether the minimum distance between the redundant pattern 14 and the metal structure is less than a fixed value.

[0065] After step S107, it further includes:

[0066] Step S108: Remove the redundant patterns in the second circuit layout that violate the design rules.

[0067] When the minimum distance between the redundant pattern 14 and the metal structure is less than a fixed value, in order to avoid the redundant pattern 14 having a functional impact on the metal structure, the redundant pattern 14 that violates the design rules can be selected to be removed.

[0068] According to the method described in the above embodiment, the embodiment of the present invention will be further described from the perspective of the redundant filling device, and the redundant filling device can be specifically implemented as an independent entity.

[0069] As Figure 6 shown, Figure 6 Specifically describes the redundant filling device provided by the embodiment of the present invention. The redundant filling device may include: a providing module 20, an obtaining module 30, a determining module 40, and a filling module 50, where:

[0070] (1) The providing module 20.

[0071] A providing module 20 for providing a first circuit layout 10.

[0072] Among them, as Figure 2A shown, specifically, the first circuit layout 10 is an integrated circuit layout, which schematically shows the planar geometry of the physical situation of the integrated circuit and is the result of the physical design of the underlying steps. In this embodiment, the physical design of the first circuit layout 10 converts the results of logic synthesis into a physical layout file through layout, wiring, etc., and the corresponding file format is GDS (Graphic Data Stream) format. The physical layout file contains the shape, area, and position information of each hardware unit on the layout. Further, the first circuit layout 10 is an integrated circuit layout including a metal structure, and the metal structure can be a metal wiring layer or a metal interconnect layer. That is, in this embodiment, the first circuit layout 10 can be defined as an integrated circuit layout that has undergone metallization or multi-layer interconnect process but has not undergone a redundant filling process. Therefore, Figure 2A the circuit layout in is the first circuit layout 10 because it has not undergone a redundant filling process. Since the functions of different metal structures are different, the metal structure can be further divided into critical graphics and non-critical graphics. In this embodiment, taking the target graphic 11 as the critical graphic and one non-target graphic 12 and another non-target graphic 13 as non-critical graphics as an example, the target graphic 11 has higher requirements for dimensional accuracy, and when its size fluctuates, it has a greater impact on the performance of semiconductor devices. In this embodiment, the distribution state of the target graphic 11 on the first circuit layout 10 can be an array distribution or a random distribution, that is, the target graphic 11 can be selectively set in any area on the first circuit layout 10.

[0073] (2) An obtaining module 30.

[0074] The obtaining module 30 is used to obtain a first target layout 101 on the first circuit layout 10 to fill redundant graphics 14 on the first target layout 101.

[0075] The obtaining module 30 is specifically used to scan the first circuit layout 10 to obtain the first target layout 101, then determine the area to be filled 1011 and the filling scheme in the first target layout 101, and then fill the redundant graphics 14 on the area to be filled 1011 according to the filling scheme.

[0076] In this example, the first target layout 101 is obtained by scanning the first circuit layout 10. The first target layout 101 is the smallest layout containing the target graphic 11, and one first target layout 101 corresponds to a critical area on the first circuit layout 10. As Figure 2BAs shown, the starting point of the scan can be selected as the origin O in the lower left corner area of the first circuit layout 10, and a first target layout 101 on the first circuit layout 10 can be searched in the x - direction and y - direction of the scan direction. When the first first - target layout 101 is found, the scan is stopped. Among them, obtaining the position of the first target layout 101 on the first circuit layout 10 is achieved by analyzing the key role played by the target pattern 11 in the first circuit layout 10.

[0077] After finding a single first target layout 101, it is necessary to determine the area 1011 to be filled with redundant patterns 14 on the current first target layout 101 to avoid filling the redundant patterns 14 onto the target pattern 11 during redundant filling, which would exacerbate the distribution difference of the surface topography. This can be achieved by first obtaining the pattern density in the first target layout 101, and then determining the area to be filled and the filling scheme based on this pattern density. In this embodiment, the pattern density refers to the area occupied by the target pattern 11 in the first target layout 101 divided by the area of the region occupied by the first target layout 101. Among them, the pattern density should meet the minimum density criterion of the internal connection in the metal layer. In this embodiment, when the pattern density is less than the set range, such as 10% - 20%, redundant filling is performed. In addition, the pattern density also reflects the actual distribution of the target pattern 11. Therefore, a corresponding filling scheme is further designed according to the actual distribution of the target pattern 11.

[0078] Specifically, the corresponding filling scheme includes at least one of the following: the line width of the redundant pattern 14, the shape of the redundant pattern 14, and the layout of the redundant pattern 14. Specifically, the purpose of designing a certain filling scheme is, on the one hand, to improve the etching load effect, and on the other hand, to reduce the coupling capacitance brought about by filling the redundant pattern 14. Especially when the redundant filling is applied globally to the circuit board layout, the increased coupling capacitance becomes more obvious and has a relatively obvious impact on the circuit characteristics. In this embodiment, specifically, the shape of the redundant pattern 14 can be set as at least one of a square, a rhombus, and a cross. Among them, compared with setting the redundant pattern 14 as a square, setting the redundant pattern 14 as a cross or a rhombus can further reduce the magnitude of the parasitic coupling capacitance. In addition, it should be noted that the layout and line width design of the redundant pattern 14 are the main ways to solve the etching load effect that appears on the first target layout 101. By reasonably setting the line width and layout of the redundant pattern 14 (the row and column arrangement of the redundant pattern 14), the pattern density of the redundant pattern 14 and the target pattern 11 in the area where the first target layout 101 is located is made uniform. Since the added redundant pattern 14 is not used for the actual connection of the device and is to improve the uniformity of the metal structure in the integrated circuit layout, in this way, defects can be reduced in the Chemical Mechanical Polish (CMP) process, the flatness of the chip surface after the CMP process can be improved, and the etching load effect can be greatly mitigated. After the redundant filling process has been performed on the first circuit layout 10 and the redundant pattern 14 has been formed on the first circuit layout 10, according to the definition of the first circuit layout 10, Figure 2D and the circuit layout corresponding to the subsequent drawings is no longer equivalent to Figures 2A - 2C the corresponding circuit layout in

[0079] (3) Determination module 40.

[0080] The determination module 40 is configured to determine the second target layout 102 on the first circuit layout 10 according to the first target layout 101 filled with the redundant pattern 14.

[0081] The second target layout 102 is actually a set of first target layouts 101 that are not filled with the redundant pattern 14, and the second target layout 102 may include one or more first target layouts 101 that are not filled with the redundant pattern 14. In Figure 2EAs shown, the second target layout 102 may include a first target layout 101 that does not have the redundant pattern 14 filled therein. At this time, the overall shape of the second target layout 102 is the same as the shape of the first target layout 101. In other embodiments of the present invention, the second target layout 102 may further include a plurality of first target layouts 101 that do not have the redundant pattern 14 filled therein. At this time, the overall shape of the second target layout 102 is different from the shape of the first target layout 101.

[0082] The determining module 40 is specifically configured to obtain all the first target layouts 101 on the first circuit layout 10 according to the first target layout 101, then merge the first target layout 101 with the redundant pattern 14, and then use the redundant pattern 14 as a marked pattern to screen out the first target layout 101 that does not have the redundant pattern 14 filled therein from all the first target layouts 101 to determine the second target layout 102.

[0083] The method of obtaining all the first target layouts 101 is also by scanning the GDS file corresponding to the first circuit layout 10. Since one first target layout 101 has been obtained in step S102, when looking for all the first target layouts 101, only the scanned pattern needs to be compared with the first obtained first target layout 101 to determine the other first target layouts 101, rather than analyzing the functions of each target pattern 11 scanned in sequence to judge. Therefore, obtaining all the first target layouts 101 according to the first target layout 101 can improve the corresponding obtaining speed.

[0084] After the first target layout 101 is merged with the redundant pattern 14, since the redundant pattern 14 is a marked pattern, the redundant pattern 14 can play an identifying role, so that among all the first target layouts 101, the first target layout 101 filled with the redundant pattern 14 and the first target layout 101 not filled with the redundant pattern 14 can be distinguished, so as to screen out one or more first target layouts 101 that do not have the redundant pattern 14 filled therein to determine the second target layout 102.

[0085] (4) Filling module 50.

[0086] The filling module 50 is used to fill the redundant pattern 14 on the second target layout 102.

[0087] In this embodiment, the filling material of the redundant pattern 14 can be polysilicon or metallic copper, wherein metallic copper is used for the redundant pattern 14 with a smaller line width. According to the fillable area 1011 and the filling scheme of the first target layout 101 that have been obtained, therefore, the first target layout 101 in the second target layout 102 that is not filled with the redundant pattern 14 can be redundantly filled in the same manner by referring to the fillable area 1011 and the filling scheme of the first target layout 101 filled with the redundant pattern 14, so that the same redundant pattern 14 is filled on all the first target layouts 101. In this embodiment, since it is ensured that the same redundant pattern 14 is filled on all the first target layouts 101 in the first circuit layout 10, that is, it is ensured that the same redundant pattern 14 is filled on all the critical areas in the first circuit layout 10, thus avoiding the phenomenon that the filling may shift in the critical areas on the circuit layout.

[0088] Please refer to Figure 7 , the embodiment of the present invention also provides an electronic device 70, as Figure 7 shown. The electronic device 70 includes one or more memories 72 and one or more processors 71. The one or more memories 72 store computer-executable programs. When the computer-executable programs are called by the one or more processors 71, the redundant filling method provided in the above embodiment is executed.

[0089] The embodiment of the present invention provides a redundant filling method, a redundant filling device, and an electronic device. The redundant filling method includes: providing a first circuit layout; obtaining a first target layout on the first circuit layout to fill a redundant pattern on the first target layout; determining a second target layout on the first circuit layout according to the first target layout filled with the redundant pattern; and filling the redundant pattern on the second target layout. By first obtaining the first target layout from the first circuit layout to determine the redundant pattern to be filled on the first target layout and performing corresponding redundant filling, and then finding the second target layout on the first circuit layout according to the first target layout and filling the corresponding redundant pattern, it is ensured that the same redundant pattern is filled on the critical areas in the first circuit layout, thus avoiding the phenomenon that the filling may shift in the critical areas on the circuit layout.

[0090] In addition to the above embodiments, the present invention may have other implementation manners. All technical solutions formed by equivalent replacement or equivalent substitution fall within the protection scope required by the present invention.

[0091] In summary, although the preferred embodiments of the present invention have been disclosed above, the above preferred embodiments are not intended to limit the present invention. Those of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A redundant filling method, characterized in that, including: providing a first circuit layout; obtaining a first target layout on the first circuit layout to fill redundant patterns on the first target layout, where the first target layout is the smallest layout containing a target pattern, and the target pattern is a critical pattern; obtaining all the first target layouts on the first circuit layout according to the first target layout; merging the first target layout with the redundant patterns; using the redundant patterns as marking patterns to screen out the first target layouts that are not filled with the redundant patterns from all the first target layouts to determine a second target layout; filling the same redundant patterns as those in the first target layout on the second target layout.

2. The redundant filling method according to claim 1, wherein The obtaining the first target layout on the first circuit layout to fill redundant patterns on the first target layout includes: scanning the first circuit layout to obtain the first target layout; determining a region to be filled and a filling scheme in the first target layout; filling the redundant patterns on the region to be filled according to the filling scheme.

3. The redundant filling method according to claim 2, wherein The determining the region to be filled and the filling scheme in the first target layout includes: obtaining the pattern density in the first target layout; determining the region to be filled and the filling scheme according to the pattern density.

4. The redundant filling method according to claim 1, wherein After filling the same redundant patterns as those in the first target layout on the second target layout, further including: merging all the marking patterns corresponding to the redundant patterns to form a marking layer; merging the marking layer with the first circuit layout to generate a second circuit layout.

5. The redundant filling method according to claim 4, characterized in that, After merging the marking layer with the first circuit layout to generate a second circuit layout, further including: performing a design rule check on the second circuit layout.

6. The redundant filling method according to claim 5, wherein After performing the design rule check on the second circuit layout, further including: removing the redundant patterns in the second circuit layout that violate the design rules.

7. The redundant filling method according to claim 2, wherein The filling scheme includes at least one of the following: the line width of the redundant pattern, the shape of the redundant pattern, and the layout of the redundant pattern.

8. An electronic device, characterized in that, The electronic device includes one or more memories and one or more processors. The one or more memories store computer-executable programs. When the computer-executable programs are called by the one or more processors, they execute the redundant filling method according to any one of claims 1-7.

9. A redundant filling device, characterized in that, including: a providing module for providing a first circuit layout; an obtaining module for obtaining a first target layout on the first circuit layout to fill redundant patterns, where the first target layout is the smallest layout containing a target pattern, and the target pattern is a critical pattern; a determining module for obtaining all the first target layouts on the first circuit layout according to the first target layout; merging the first target layout with the redundant patterns; using the redundant patterns as marking patterns to screen out the first target layouts that are not filled with the redundant patterns from all the first target layouts to determine a second target layout; A filling module, configured to fill the same redundant patterns on the second target layout as those on the first target layout.

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