A data processing method, device, integrated circuit and electronic equipment

Abstract

The application relates to a data processing method and device, integrated circuit and electronic equipment, and belongs to the technical field of image processing. The data processing method comprises the following steps: alternately storing a received to-be-processed data stream into a first memory and a second memory; and continuously reading data from the first memory and the second memory for preprocessing, wherein the data writing rate is greater than the data reading rate, and is not greater than twice the data reading rate. The data processing method can process a high-speed data stream by using a low-speed processing module, thereby saving hardware cost and enhancing the applicability of the scheme.

Description

Technical Field

[0001] This application belongs to the field of image processing technology, specifically relating to a data processing method, apparatus, integrated circuit, and electronic device. Background Technology

[0002] In digital image processing, the planar digital image to be processed can be viewed as a large matrix, with each pixel of the image corresponding to an element in the large matrix. Assuming the resolution of the planar digital image is 1024*768, then the corresponding large matrix has 1024 rows and 768 columns. The filter matrix (also called the convolution kernel) used for filtering is generally a square matrix, meaning the number of rows and columns are the same. Filtering (also called convolution calculation) involves, for each pixel in the large matrix, calculating the product of its surrounding pixels and the corresponding element in the filter matrix, then summing the results. The final value is used as the new value for that pixel, thus completing one filtering operation.

[0003] Convolutional computation is fundamental to deep learning neural networks; only by executing this operation as quickly as possible can deep learning-based applications run efficiently and rapidly. Field-Programmable Gate Arrays (FPGAs) are widely used because they offer higher computational efficiency compared to traditional computer processors such as CPUs and GPUs when handling these operations. However, in FPGAs, low-speed data processing modules cannot handle the data streams from high-speed ports. Using only high-speed processing modules would significantly increase hardware costs. How to utilize low-speed processing modules to handle high-speed data streams is the technical problem this application aims to solve. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a data processing method, apparatus, electronic device, and computer-readable storage medium to achieve the goal of processing high-speed data streams using a low-speed processing module.

[0005] The embodiments of this application are implemented as follows:

[0006] In a first aspect, embodiments of this application provide a data processing method, comprising: alternately storing a received data stream to be processed into a first memory and a second memory; continuously reading data from the first memory and the second memory for preprocessing, wherein the data writing rate is greater than the data reading rate and not greater than twice the data reading rate. In this embodiment, by using two memories to alternately store data, a ping-pong operation is achieved, allowing each memory to have a certain time interval to process unprocessed data, thereby enabling the processing of high-speed data streams using a low-speed processing module.

[0007] In one possible implementation of the first aspect embodiment, the received data stream to be processed is alternately stored in a first memory and a second memory, comprising: dividing the data stream to be processed into segments according to a preset size; and alternately storing each segmented data stream in the first memory and the second memory according to the segmentation order, until all segmented data streams are stored. In this embodiment, by segmenting the data stream to be processed and alternately storing each segmented data stream in the first memory and the second memory according to the segmentation order, the input data can be a complete data stream, further enhancing the applicability of the solution.

[0008] In one possible implementation of the first aspect embodiment, before sequentially segmenting the data stream to be processed according to a preset size, the method further includes: obtaining the storage space size of the first memory and the storage space size of the second memory; selecting the storage space with the smallest storage space among the first memory and the second memory, and determining the preset size based on the smallest storage space. In this embodiment, the preset size is determined by selecting the storage space with the smallest storage space among the first memory and the second memory, so that the segmented data stream can be stored in the memory with the smallest storage space.

[0009] In one possible implementation of the first aspect embodiment, the data stream is a pixel stream of the image to be processed, and the preprocessing is convolution processing. In this embodiment, since convolution calculations involve a large amount of computation, the method provided in this embodiment can effectively reduce the hardware cost of performing convolution processing.

[0010] Secondly, embodiments of this application also provide a data processing apparatus, including: a first memory, a second memory, an input unit, and a data processing unit; the input unit is used to alternately write a received data stream into the first memory and the second memory; the data processing unit is used to continuously read data from the first memory and the second memory for preprocessing, wherein the data writing rate is greater than the data reading rate and not greater than twice the data reading rate.

[0011] In one possible implementation of the second embodiment, the input unit includes: a first selector, configured to alternately write the received data stream into the first memory and the second memory according to an input selection signal.

[0012] In one possible implementation of the second embodiment, the data processing unit includes: a first data processing unit and a second data processing unit; the first data processing unit is connected to the first memory and is used to read data from the first memory for preprocessing, wherein the processing rate of the first data processing unit is less than the data writing rate of the first memory; the second data processing unit is connected to the second memory and is used to read data from the second memory for preprocessing, wherein the processing rate of the second data processing unit is less than the data writing rate of the second memory.

[0013] In one possible implementation of the second embodiment, the data processing unit further includes a second selector, the input of which is connected to the first data processing unit and the second data processing unit respectively, and the second selector is used to alternately output the data output by the first data processing unit and the data output by the second data unit according to the input selection signal.

[0014] Thirdly, embodiments of this application also provide an integrated circuit, which integrates a data processing device as provided in any possible implementation of the second aspect embodiments and / or in combination with the second aspect embodiments.

[0015] Fourthly, embodiments of this application also provide an electronic device, including: a device body and a data processing apparatus provided in any possible implementation of the second aspect embodiments and / or in combination with the second aspect embodiments, or an integrated circuit provided in the third aspect embodiments.

[0016] Fifthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the method provided by any possible implementation of the first aspect embodiments and / or in combination with the first aspect embodiments.

[0017] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The above and other objects, features, and advantages of this application will become clearer through the drawings. The same reference numerals indicate the same parts in all the drawings. The drawings are not intentionally drawn to scale to actual size; the focus is on illustrating the main points of this application.

[0019] Figure 1 A schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application is shown.

[0020] Figure 2 A schematic diagram of the structure of another data processing apparatus provided in an embodiment of this application is shown.

[0021] Figure 3 A timing signal diagram of a data processing apparatus provided in an embodiment of this application.

[0022] Figure 4 A flowchart illustrating a data processing method provided in an embodiment of this application is shown.

[0023] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0024] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0025] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0026] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0027] Given that low-speed data processing modules in the prior art cannot handle data streams from high-speed ports, and that using all high-speed processing modules would greatly increase hardware costs, this application provides a data processing device that enables the use of low-speed processing modules to process high-speed data streams, thereby saving hardware costs and enhancing the applicability of the solution.

[0028] To better understand, let's combine the following... Figure 1 The data processing apparatus provided in the embodiments of this application will be described. For example... Figure 1 As shown. The data processing device includes: an input unit, a first memory, a second memory, and a data processing unit. The input unit is connected to both the first memory and the second memory, and the data processing unit is connected to both the first memory and the second memory.

[0029] The input unit is used to alternately write the received data stream into the first memory and the second memory. The data processing unit is used to continuously read data from the first memory and the second memory for preprocessing. The data writing rate is greater than the data reading rate, but not more than twice the data reading rate. In this embodiment, by using two memories to alternately store data, a ping-pong operation is achieved, allowing each memory to have a certain time interval to process unprocessed data, thereby enabling the processing of high-speed data streams using a low-speed processing module.

[0030] In this embodiment, the first memory and the second memory are memory that support simultaneous writing and reading. The first memory and the second memory can be the same, for example, they can be DDR (Double Data Rate SDRAM), where SDRAM is Synchronous Dynamic Random Access Memory. In this embodiment, the first memory and the second memory can be memory with small storage space to save costs.

[0031] In one optional implementation, the input unit may include a first selector (MUX), which is connected to a first memory and a second memory respectively. The first selector is used to alternately write the received data stream into the first memory and the second memory according to the input selection signal. The first selector includes an input terminal, two output terminals, and a selection terminal. The input terminal is used to receive the data stream to be processed, the selection terminal is used to receive a selection signal, one output terminal is connected to the first memory, and the other output terminal is connected to the second memory.

[0032] In another optional implementation, the input unit may include a logic module, which is used to alternately write the received data stream into the first memory and the second memory. The logic module may be a logic circuit containing two controllable switches, both of which are connected to the input interface of the input unit and to the two output interfaces one-to-one. By alternately controlling the on and off states of the two controllable switches, the received data stream is alternately written into the first memory and the second memory.

[0033] In one implementation, the data processing unit may include a data processing unit with multiple I / O (I-in / Output) ports, capable of simultaneously reading data from both the first memory and the second memory for preprocessing. Alternatively, the data processing unit may include two data processing units, a first data processing unit and a second data processing unit, to reduce the I / O capability requirements.

[0034] The first data processing unit is connected to the first memory and is used to read data from the first memory for preprocessing. The processing rate of the first data processing unit (i.e., the rate at which data is read from the first memory) is less than the rate at which data is written to the first memory.

[0035] The second data processing unit is connected to the second memory and is used to read data from the second memory for preprocessing. The processing rate of the second data processing unit (i.e., the rate at which data is read from the second memory) is less than the rate at which data is written to the second memory.

[0036] The first data processing unit and the second data processing unit can be the same, for example, they can be modules or units with data processing capabilities, such as matrix multipliers, arithmetic logic units (ALUs), processors, etc. The aforementioned data stream can be an image pixel stream; correspondingly, preprocessing can include convolution processing or pixel matrix calculation processing, etc. The specific processing procedures for convolution processing and pixel matrix calculation processing are well known to those skilled in the art and will not be described in detail here.

[0037] In another embodiment, the data processing unit may further include a second selector (MUX), the input terminals of which are respectively connected to the first data processing unit and the second data processing unit. The second selector is used to alternately output data from the first data processing unit and data from the second data processing unit according to an input selection signal. The second selector includes two input terminals, one output terminal, and a selection terminal; one input terminal is connected to the first data processing unit, and the other input terminal is connected to the second data processing unit; the selection terminal is used to receive a selection signal, and the output terminal is used to output data from either the first or second data processing unit.

[0038] It should be noted that the data stream received by the input unit can be a fragmented data stream (i.e., a data stream that has already been fragmented according to a preset size). In one embodiment, the data stream input to the data processing device is itself a fragmented data stream. Of course, if the data stream input to the data processing device is a complete data stream, the data processing device may also include a data segmentation module, used to segment the complete data stream to be processed sequentially according to a preset size, and send each fragmented data stream to the input unit in the segmentation order, so that the input unit can alternately store the received data stream into the first memory and the second memory until all the fragmented data streams are stored.

[0039] The preset size can be set as needed. For example, in one implementation, the storage space size of the first memory and the storage space size of the second memory can be obtained, the storage space with the smallest storage space between the first memory and the second memory can be selected, and the preset size can be determined based on the smallest storage space, so that the segmented data stream can be stored in the memory with the smallest storage space (which can be the first memory or the second memory).

[0040] The data segmentation module mentioned above can be a commonly used module or unit for segmenting data, or it can be a processor or controller.

[0041] In addition, to achieve the above functions, corresponding timing signals are required, including selection signals, write signals required for writing data to the memory, address signals, and read signals and address signals required for reading data. These timing signals can be input externally or generated by the data processing device itself. If generated by the data processing device itself, the data processing device also includes a controller for generating the above timing signals.

[0042] In one embodiment, the structure of the above-described data processing apparatus can be as follows: Figure 2 As shown. It should be noted that, Figure 2 The structure shown is only one of many embodiments of the data processing device and cannot be generalized. Figure 2 The structure shown is to be understood as a limitation of this application.

[0043] To better understand how the aforementioned data processing device processes high-speed data streams using low-speed processing modules, a specific example will be provided below.

[0044] Assuming the image to be processed has 225 (columns) * 225 (rows) pixels, and the memory size of both DDR1 and DDR2 is 8 (columns) * 225 (rows), and assuming the buffer period for ping-pong operations is 10ms, then:

[0045] In the first cycle (10ms), the first selector selects to write the input data stream (size 8*225) to DDR1, assuming that writing 8*225 data takes 10ms.

[0046] During the second cycle (10ms), the data stream switches to DDR2 and writes 8*225 data. During the second cycle, while DDR2 is writing 8*225 data, DDR1 is performing a read operation and outputting the read data to the first data processing unit for preprocessing.

[0047] During the third cycle (10ms), the data stream switches to DDR1, writing 8*225 data. While DDR1 is writing 8*225 data during this third cycle, DDR2 is performing a read operation and outputting the read data to the second data processing unit for preprocessing.

[0048] This process continues in a loop, writing data to one DDR while reading data from another DDR, and then sending the data to the subsequent data processing unit for convolution calculations, until all inputs have been written. It's important to note that while writing data to DDR1 and DDR2, data is also being read from DDR1 and DDR2 simultaneously. To better understand this looping process, the following section will combine... Figure 3 The timing diagram shown illustrates the above process. wr_mode_a is the write signal for DDR1; rd_mode_a is the read signal for DDR1; wr_mode_b is the write signal for DDR2; and rd_mode_b is the read signal for DDR2. Both the read and write signals shown above are active high.

[0049] Continuing with the example above, assuming the write data rate is 100Mbps and the read data rate is 50Mbps, meaning the data processing unit's read rate is 50Mbps, if writing 8*225 data units takes 10ms, then reading 8*225 data units will take 20ms. Specifically:

[0050] Starting from the 6ms of the first cycle, DDR1 can simultaneously write data to addresses 4*225 and read data from the starting address. By the 10ms mark, DDR1 has just finished writing 8*225 data. At this point, DDR1 has read 5ms of data, which is equivalent to reading 2*225 data.

[0051] In the second cycle, DDR2 takes 10ms to write 8*225 data inputs. At this time, DDR1 reads 10ms of data, plus the previous 5ms, for a total of 15ms of data read, reading 6*225 data. In the first 5ms of the third cycle, data can be written to the starting address while reading data from addresses after 6*225, reading for 5ms. At this time, the data stored in the first cycle of DDR1 is completely read, taking a total of 20ms.

[0052] Starting from the 6ms of the third cycle, DDR1 can simultaneously write data to addresses 4*225 and read data from the starting address, and then repeat the above process.

[0053] Similarly, the same applies to DDR2. Starting from the 6ms mark of the second cycle, DDR2 can simultaneously write data to addresses 4*225 and onwards while reading data from the starting address. By the 10ms mark, DDR2 has written 8*225 units of data. At this point, DDR2 has read 5ms of data, totaling 2*225 units of data. In the third cycle, DDR1 takes 10ms to write 8*225 units of data. DDR2 reads 10ms of data during this time, adding to the previous 5ms, for a total of 15ms of data read, totaling 6*225 units of data. In the first 5ms of the fourth cycle, it can simultaneously write data to the starting address and read data from addresses 6*225 and onwards, reading for 5ms. At this point, the data stored in the second cycle of DDR2 is completely read, taking a total of 20ms. Starting from the 6ms mark of the fourth cycle, DDR2 can simultaneously write data to addresses 4*225 and onwards while reading data from the starting address, and then repeat the above process.

[0054] The above examples demonstrate that this application can utilize a low-speed processing module to process high-speed data streams, for example, using a processing module with a rate of 50 Mbps to process a 100 Mbps high-speed data stream.

[0055] It should be noted that the above loop operation can also be reversed, that is: In the first cycle (assuming 10ms), the first selector chooses to write the input data stream (size 8*225) to DDR2, assuming that writing 8*225 data takes 10ms. In the second cycle (10ms), the data stream switches to DDR1, writing 8*225 data. In the second cycle, while DDR1 is writing 8*225 data, DDR2 is also performing a read operation and outputting the read data to the second data processing unit for preprocessing. In the third cycle (10ms), the data stream switches to DDR2, writing 8*225 data. In the third cycle, while DDR2 is writing 8*225 data, DDR1 is performing a read operation and outputting the read data to the first data processing unit for preprocessing. This loop operation continues, writing data to one DDR while reading data from another DDR, and then sending the data to the subsequent data processing unit for convolution calculation, until all inputs are written. At this time, wr_mode_a is the write signal for DDR2; rd_mode_a is the read signal for DDR2; wr_mode_b is the write signal for DDR1; and rd_mode_b is the read signal for DDR2.

[0056] Based on the same inventive concept, this application also provides an integrated circuit, which includes the aforementioned data processing device and main controller. The main controller is used to generate the aforementioned selection signal and timing signals required for writing and reading data, such as read signals, write signals, and address signals. In addition, the main controller can also be used to divide the complete data stream to be processed into segments according to a preset size, and send each segmented data stream to the input unit according to the segmentation order, and to obtain the storage space size of the first memory and the storage space size of the second memory, select the storage space with the smallest storage space in the first memory and the second memory, and determine the preset size based on the smallest storage space.

[0057] The aforementioned integrated circuit can be a SOC (System on Chip) circuit, such as an FPGA (Field Programmable Gate Array) circuit.

[0058] The data processing device provided in the integrated circuit embodiment has the same implementation principle and technical effect as the aforementioned data processing device embodiment. For the sake of brevity, any parts not mentioned in the integrated circuit embodiment can be referred to the corresponding content in the aforementioned data processing device embodiment.

[0059] Based on the same inventive concept, this application also provides an electronic device, which may include the aforementioned data processing device or integrated circuit. This electronic device may be a computer, server, etc. It should be noted that the data processing device or integrated circuit not described in the electronic device embodiments has the same implementation principle and technical effects as the corresponding embodiments described above; please refer to the foregoing content for details.

[0060] Based on the same inventive concept, this application also provides a data processing method, which will be described below in conjunction with... Figure 4 The data processing method provided in the embodiments of this application will be described.

[0061] S1: The received data stream to be processed is alternately stored in the first memory and the second memory.

[0062] The data processing method can be applied to the aforementioned data processing device, in which the input unit alternately stores the received data stream to be processed into the first memory and the second memory.

[0063] S2: Continuously read data from the first memory and the second memory for preprocessing.

[0064] The data processing unit in the data processing device can continuously read data from the first memory and the second memory for preprocessing, wherein the data writing rate is greater than the data reading rate, but not greater than twice the data reading rate. The data stream is the pixel stream of the image to be processed, and the preprocessing is convolution processing.

[0065] In one implementation, the data stream to be processed can be a fragmented data stream or a complete data stream. If it is a complete data stream, the process of alternately storing the received data stream to be processed into the first memory and the second memory can be as follows: the data stream to be processed is fragmented sequentially according to a preset size; and each fragmented data stream is alternately stored into the first memory and the second memory according to the fragmentation order until all fragmented data streams are stored. At this time, the data processing device also includes a data segmentation module (which can be a processor or a controller), which can be used to fragment the complete data stream to be processed sequentially according to a preset size, and send each fragmented data stream to the input unit according to the fragmentation order, so that the input unit can alternately store the received data stream into the first memory and the second memory until all fragmented data streams are stored.

[0066] Optionally, before segmenting the data stream to be processed into segments according to a preset size, the method further includes: obtaining the storage space size of the first memory and the storage space size of the second memory; selecting the storage space with the smallest storage space among the first memory and the second memory, and determining the preset size based on the smallest storage space. This can be achieved by using a data segmentation module to obtain the storage space size of the first memory and the second memory; selecting the storage space with the smallest storage space among the first memory and the second memory; and determining the preset size based on the smallest storage space.

[0067] The data processing method provided in this application embodiment has the same implementation principle and technical effect as the aforementioned data processing device. For the sake of brevity, any parts not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned data processing device embodiment.

[0068] It should be noted that the above method can be executed not only by the data processing device mentioned above, but also by electronic devices.

[0069] like Figure 5 As shown, Figure 5 This diagram illustrates a structural block diagram of an electronic device 200 provided in an embodiment of this application. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

[0070] The transceiver 210, the memory 220, and the processor 240 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store a computer program that executes the above-described data processing method. This computer program includes at least one software functional module that can be stored in the memory 220 in the form of software or firmware or embedded in the operating system (OS) of the electronic device 200. The processor 240 is used to execute the executable module stored in the memory 220. The processor 240 is used to alternately store the received data stream to be processed into the first memory and the second memory; and to continuously read data from the first memory and the second memory for preprocessing, wherein the data writing rate is greater than the data reading rate and not greater than twice the data reading rate.

[0071] The memory 220 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0072] Processor 240 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor, or processor 240 can be any conventional processor.

[0073] Among them, the aforementioned electronic devices 200 include, but are not limited to, computers, servers, etc.

[0074] This application embodiment also provides a non-volatile computer-readable storage medium (hereinafter referred to as the storage medium) storing a computer program, which is executed by a computer such as the electronic device 200 described above to perform the data processing method described above.

[0075] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0076] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0077] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0078] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0079] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized by, The method comprises: alternately storing the received data stream to be processed into a first memory and a second memory, wherein the first memory and the second memory are two independent memories supporting edge writing and edge reading; continuously reading data from the first memory and the second memory for preprocessing, wherein data is read from the first memory and the second memory at the same time when data is written into the first memory and the second memory, wherein the writing rate of data is greater than the reading rate of data, and is not greater than twice the reading rate of data.

2. The method of claim 1, wherein, The method of alternately storing the received data stream to be processed into a first memory and a second memory comprises: sequentially fragmenting the data stream to be processed according to a preset size; according to the fragmentation order, alternately storing each fragmented data stream into the first memory and the second memory until all fragmented data streams are stored.

3. The method of claim 2, wherein, Before sequentially fragmenting the data stream to be processed according to a preset size, the method further comprises: obtaining the storage space size of the first memory and the storage space size of the second memory; selecting the smallest storage space from the first memory and the second memory, and determining the preset size based on the smallest storage space.

4. The method according to any one of claims 1-3, characterized in that, The data stream is a pixel stream of an image to be processed, and the preprocessing is convolution processing.

5. A data processing apparatus, characterized by, The method comprises: a first memory and a second memory, wherein the first memory and the second memory are two independent memories supporting edge writing and edge reading; an input unit for alternately writing the received data stream into the first memory and the second memory; a data processing unit for continuously reading data from the first memory and the second memory for preprocessing, wherein data is read from the first memory and the second memory at the same time when data is written into the first memory and the second memory, wherein the writing rate of data is greater than the reading rate of data, and is not greater than twice the reading rate of data.

6. The data processing apparatus according to claim 5, characterized in that, The input unit comprises: a first selector for alternately writing the received data stream into the first memory and the second memory according to an input selection signal.

7. The data processing apparatus according to claim 5, characterized by The data processing unit comprises: a first data processing unit connected with the first memory for reading data from the first memory for preprocessing, wherein the processing rate of the first data processing unit is less than the writing rate of data of the first memory; a second data processing unit connected with the second memory for reading data from the second memory for preprocessing, wherein the processing rate of the second data processing unit is less than the writing rate of data of the second memory.

8. The data processing apparatus according to claim 7, characterized in that, The data processing unit further comprises: a second selector, wherein the input end of the second selector is connected with the first data processing unit and the second data processing unit, and the second selector is used for alternately outputting the data output by the first data processing unit and the data output by the second data processing unit according to an input selection signal.

9. An integrated circuit, characterized by The integrated circuit integrates the data processing device as claimed in any one of claims 5-8.

10. An electronic device, comprising: The method comprises: The apparatus body and the data processing device as claimed in any one of claims 5-8, or the integrated circuit as claimed in claim 9.

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