A 14T radiation-hardened SRAM memory cell circuit

Abstract

The present invention discloses a 14T radiation-hardened SRAM memory cell circuit, which includes 8 NMOS transistors and 6 PMOS transistors; PMOS transistor P5 and NMOS transistor N3 form the first inverter, and PMOS transistor P6 and NMOS transistor N4 form the second inverter, and these two inverters are cross-coupled; N1 and N2 reinforce the internal storage nodes QB and Q, and both Q and QB are surrounded by NMOS transistors, which constitutes a polarity reinforcement structure; the peripheral nodes S0 and S1 are cross-coupled by P1 and P2, and N5 and N6 serve as pull-down transistors; QB and Q are connected to BLB and BL through N7 and N8, and the gates of N7 and the gate of N8 are both electrically connected to the word line WL. The present invention can improve the single-event upset resistance of the cell, can resist all single-node upsets, can also resist peripheral storage double-node upsets, and the critical charge of the cell is relatively high, and the cell is more stable.

Description

Technical Field

[0001] The present invention relates to the technical field of SRAM (Static Random Access Memory), and particularly to a 14T (14T refers to 14 CMOS transistors) radiation-hardened SRAM memory cell circuit, which is a cell circuit structure that can improve the single event upset (SEU) resistance ability of the cell, hereinafter referred to as HRH-14T. Background Art

[0002] With the rapid development of the integrated circuit industry, the process technology is continuously reduced, and the industry's requirements for the circuit performance and working reliability of devices are constantly increasing. However, in the fields of aerospace, space defense and other cutting-edge technologies, the space environment is particularly complex, and a large number of high-energy charged particles such as electrons and protons in the universe seriously threaten the stable operation of integrated circuits, which poses a severe challenge to the normal operation of aerospace equipment. Among them, the single event effect (SEE) poses a greater threat to the operation of integrated circuits in the space environment, which makes the radiation-hardening technology of integrated circuits become more and more important. SEU is a form of single event effect. When high-energy particles in space hit a semiconductor material, charges are deposited along their incident path, and these charges will be collected by sensitive areas, resulting in node voltage fluctuations, causing the data in the memory cell to flip, and ultimately leading to soft errors in the integrated circuit system.

[0003] At present, SRAM is widely used in a large number of electronic storage devices. However, due to its own structural characteristics, SRAM is particularly sensitive to single event effects and has poor stability in the radiation environment. Therefore, in order to improve the SEU resistance ability of SRAM cells, the following main solutions are included in the prior art:

[0004] (1) As Figure 1 shown, the circuit is a Soft Error Tolerant 10T SRAM BitCell (QUATRO 10T) circuit proposed by Shah M. Jahinuzzamandeng et al. in 2009. On the basis of the traditional six-transistor cell structure, this circuit structure adds 2 PMOS transistors and 2 NMOS transistors, and 2 NOMS transistors are used as transmission transistors. It has better SEU resistance ability than the traditional six-transistor cell structure, but after the internal storage node of this cell is bombarded by particles, it can only recover the flip from '1' to '0', and cannot be completely immune to SEU.

[0005] (2) As Figure 2The circuit shown is a Quadruple Cross-Coupled Latch-Based QUCCE 10T (QUCCE 10T) circuit proposed by Jianwei Jiang in 2018. It consists of 10 transistors, has a relatively small area, but can only self-recover from '0' to '1' single-event upsets (SEUs), and cannot recover all SEUs.

[0006] (3) As Figure 3 shown, the circuit shown is the Writability-Enhanced QUATRO (We-QUATRO 12T) circuit proposed by L.D.T. Dand and J.S. Kim in 2017. This circuit adds a pair of read / write transistors based on the QUATRO circuit, improving the write ability. However, like the QUATRO-10T, it cannot be completely immune to SEUs.

[0007] (4) As Figure 4 shown, the circuit shown is a Power-Optimized SRAM Cell With High Radiation Hardened (RHBD 14T) circuit proposed by Govind Prasad et al. in 2020. This circuit can resist all single-node flips, but its read operation time and write operation time are relatively poor.

[0008] In view of this, the present invention is specifically proposed. Summary of the Invention

[0009] The object of the present invention is to provide a 14T radiation-hardened SRAM memory cell circuit to solve the above-mentioned technical problems existing in the prior art. The present invention can improve the single-event upset resistance of the cell, can resist all single-node flips, can also resist double-node flips in the peripheral memory, and the critical charge of the cell is relatively high, making the cell more stable. Its read operation time and write operation time are better than those of the existing 14-transistor SRAM memory cell circuit.

[0010] The object of the present invention is achieved through the following technical solutions:

[0011] A 14T radiation-hardened SRAM memory cell circuit includes 8 NMOS transistors and 6 PMOS transistors. These 8 NMOS transistors are respectively defined as N1, N2, N3, N4, N5, N6, N7, and N8. These 6 PMOS transistors are respectively defined as P1, P2, P3, P4, P5, and P6. PMOS transistor P5 and NMOS transistor N3 form the first inverter, and PMOS transistor P6 and NMOS transistor N4 form the second inverter. These two inverters are cross-coupled. PMOS transistors P3 and P4 serve as pull-up transistors. An internal storage node QB is provided between the drain of PMOS transistor P5 and the drain of NMOS transistor N3, and an internal storage node Q is provided between the drain of PMOS transistor P6 and the drain of NMOS transistor N4. NMOS transistors N1 and N2 reinforce the internal storage nodes QB and Q. Both the internal storage node Q and the internal storage node QB are surrounded by NMOS transistors, which constitutes a polarity reinforcement structure. The peripheral nodes S0 and S1 are cross-coupled by PMOS transistors P1 and P2, and NMOS transistors N5 and N6 serve as pull-down transistors. The internal storage node QB is connected to the second bit line BLB through NMOS transistor N7, and the internal storage node Q is connected to the first bit line BL through NMOS transistor N8. The gates of NMOS transistor N7 and NMOS transistor N8 are both electrically connected to the word line WL.

[0012] Preferably, the drain of PMOS transistor P5 is electrically connected to the drain of NMOS transistor N1. The source of NMOS transistor N1 and the drain of NMOS transistor N3 are electrically connected to the internal storage node QB, and the source of NMOS transistor N3 is grounded. The drain of PMOS transistor P6 is electrically connected to the drain of NMOS transistor N2. The source of MOS transistor N2 and the drain of NMOS transistor N4 are electrically connected to the internal storage node Q, and the source of NMOS transistor N4 is grounded. The internal storage node QB is electrically connected together with the gates of PMOS transistor P6 and NMOS transistor N4, and the internal storage node Q is electrically connected together with the gates of PMOS transistor P5 and NMOS transistor N3.

[0013] The drain of PMOS transistor P3 is electrically connected to the source of PMOS transistor P5, and the source of PMOS transistor P3 is connected to the voltage VDD. The drain of PMOS transistor P4 is electrically connected to the source of PMOS transistor P6, and the source of PMOS transistor P4 is connected to the voltage VDD.

[0014] The source of PMOS transistor P1 is connected to voltage VDD. The drain of PMOS transistor P1 is electrically connected to the gate of PMOS transistor P2, the gate of NMOS transistor N1, and the drain of NMOS transistor N5 at the peripheral node S0. The gate of NMOS transistor N5 is electrically connected to the internal storage node Q, and the source of NMOS transistor N5 is grounded. The source of PMOS transistor P2 is connected to voltage VDD. The drain of PMOS transistor P2 is electrically connected to the gate of PMOS transistor P1, the gate of NMOS transistor N2, and the drain of NMOS transistor N6 at the peripheral node S1. The gate of NMOS transistor N6 is electrically connected to the internal storage node QB, and the source of NMOS transistor N6 is grounded. The gate of PMOS transistor P1 is electrically connected to the gate of PMOS transistor P3. The gate of PMOS transistor P2 is electrically connected to the gate of PMOS transistor P4.

[0015] The drain of NMOS transistor N7 is electrically connected to the internal storage node QB. The source of NMOS transistor N7 is electrically connected to the second bit line BLB. The gate of NMOS transistor N7 is electrically connected to the word line WL. The drain of NMOS transistor N8 is electrically connected to the internal storage node Q. The source of NMOS transistor N8 is electrically connected to the first bit line BL. The gate of NMOS transistor N8 is electrically connected to the word line WL.

[0016] Compared with the prior art, the present invention includes 8 NMOS transistors and 6 PMOS transistors. The peripheral node S0 and the peripheral node S1 are cross-coupled by the PMOS transistor P1 and the PMOS transistor P2. The NMOS transistor N5 and the NMOS transistor N6 serve as pull-down transistors. The internal storage node QB and the internal storage node Q are cross-coupled by a pair of inverters composed of the PMOS transistor P5, the NMOS transistor N3, the PMOS transistor P6, and the NMOS transistor N4. The PMOS transistor P3 and the PMOS transistor P4 serve as pull-up transistors. The NMOS transistor N1 and the NMOS transistor N2 reinforce the internal storage node QB and the internal storage node Q. The internal storage node Q and the internal storage node QB are all surrounded by NMOS transistors, which constitutes a polarity reinforcement structure. The internal storage node QB is connected to the second bit line BLB through the NMOS transistor N7, and the internal storage node Q is connected to the first bit line BL through the NMOS transistor N8. The turn-on of the NMOS transistors N7 and N8 serving as transfer transistors is controlled by the word line WL. Therefore, the internal storage node Q and the internal storage node QB are designed based on the polarity reinforcement principle that different types of transistors have a single flip characteristic under heavy ion bombardment in space. Using this design ensures the stability of the internal storage node Q and the internal storage node QB. At the same time, the stability of the node data of the peripheral node S0 and the peripheral node S1 ensures that the internal storage node Q and the internal storage node QB can return to the initial state after flipping, which improves the SEU resistance ability of the circuit, improves the single event upset resistance ability of the unit circuit at the cost of a relatively small unit area, can resist all single-node flips, can also resist peripheral storage double-node flips, and the critical charge of the unit is relatively high, making the unit more stable. Its read operation time and write operation time are better than those of the existing 14-transistor SRAM storage unit circuit. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a schematic structural diagram of the QUATRO 10T circuit in the prior art;

[0019] Figure 2 It is a schematic structural diagram of the QUCCE 10T circuit in the prior art;

[0020] Figure 3 It is a schematic structural diagram of the We-QUATRO 12T circuit in the prior art;

[0021] Figure 4 is a schematic structural diagram of the RHBD 14T circuit in the prior art;

[0022] Figure 5 is a schematic structural diagram of the 14T radiation-hardened SRAM memory cell circuit (abbreviation: HRH-14T) provided by an embodiment of the present invention;

[0023] Figure 6 is a timing waveform diagram of the HRH-14T radiation-hardened SRAM memory cell circuit provided by an embodiment of the present invention (simulation conditions: Corner: TT; Temperature: 27 °C; VDD: 1.2 V);

[0024] Figure 7 is a transient waveform simulation diagram of the HRH-14T radiation-hardened SRAM memory cell circuit provided by an embodiment of the present invention when different nodes are injected with double-exponential current source pulses at different times (simulation conditions: VDD: 1.2 V). Detailed implementation manners

[0025] The following describes clearly and completely the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention; obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments, which does not constitute a limitation to the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0026] First, the terms that may be used in this article are described as follows:

[0027] Descriptions with semantic meanings such as "including", "containing", "having", or other similar terms shall be interpreted as non-exclusive inclusion. For example: including a certain technical feature element (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, processes, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products, or products, etc.) shall be interpreted as not only including the clearly listed certain technical feature element, but also including other well-known technical feature elements in the art that are not clearly listed.

[0028] The following provides a detailed description of the 14T radiation-hardened SRAM memory cell circuit provided by the present invention. The content not described in detail in the embodiments of the present invention belongs to the prior art well-known to those of ordinary skill in the art. Conditions not specified in the embodiments of the present invention are carried out according to the conventional conditions in the art or the conditions recommended by the manufacturer. Reagents or instruments not specified in the embodiments of the present invention are all conventional products that can be obtained through commercial purchase.

[0029] Embodiment 1

[0030] As Figure 5 shown, Embodiment 1 of the present invention provides a 14T radiation-hardened SRAM memory cell circuit (abbreviated as HRH-14T), which is a 14T radiation-hardened SRAM memory cell circuit based on polarity hardening technology. Its structure mainly includes 8 NMOS transistors and 6 PMOS transistors; these 8 NMOS transistors are respectively defined as N1, N2, N3, N4, N5, N6, N7, N8; these 6 PMOS transistors are respectively defined as P1, P2, P3, P4, P5, P6.

[0031] PMOS transistor P5, NMOS transistor N3, PMOS transistor P6 and NMOS transistor N4 form a pair of cross-coupled inverters (the fact that PMOS transistor P5, NMOS transistor N3, PMOS transistor P6 and NMOS transistor N4 form a pair of cross-coupled inverters means that PMOS transistor P5 and NMOS transistor N3 form the first inverter, and PMOS transistor P6 and NMOS transistor N4 form the second inverter. These two inverters are cross-coupled, that is, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. This can lock and save the output states of the two inverters, that is, store the state of 1 bit). PMOS transistors P3 and P4 serve as pull-up transistors. An internal storage node QB is provided between the drain of PMOS transistor P5 and the drain of NMOS transistor N3. An internal storage node Q is provided between the drain of PMOS transistor P6 and the drain of NMOS transistor N4. NMOS transistors N1 and N2 reinforce the internal storage nodes QB and Q. Both the internal storage node Q and the internal storage node QB are surrounded by NMOS transistors, which constitutes a polarity hardening structure. The peripheral nodes S0 and S1 are cross-coupled by PMOS transistors P1 and P2. NMOS transistors N5 and N6 serve as pull-down transistors. The internal storage node QB is connected to the second bit line BLB through NMOS transistor N7. The internal storage node Q is connected to the first bit line BL through NMOS transistor N8. The gates of NMOS transistor N7 and NMOS transistor N8 are both electrically connected to the word line WL, that is, the turn-on of NMOS transistor N7 and NMOS transistor N8 is controlled by the word line WL.

[0032] Specifically, the specific structure of the HRH-14T radiation-hardened SRAM memory cell circuit may include: the drain of PMOS transistor P5 is electrically connected to the drain of NMOS transistor N1, the source of NMOS transistor N1 is electrically connected to the drain of NMOS transistor N3 at the internal storage node QB, and the source of NMOS transistor N3 is grounded; the drain of PMOS transistor P6 is electrically connected to the drain of NMOS transistor N2, the source of NMOS transistor N2 is electrically connected to the drain of NMOS transistor N4 at the internal storage node Q, and the source of NMOS transistor N4 is grounded; the internal storage node QB is electrically connected to the gates of PMOS transistor P6 and NMOS transistor N4, and the internal storage node Q is electrically connected to the gates of PMOS transistor P5 and NMOS transistor N3; this constitutes a pair of cross-coupled inverters, and NMOS transistors N1 and N2 reinforce the internal storage nodes QB and Q in this pair of inverters. PMOS transistors P3 and P4 serve as pull-up transistors, that is, the drain of PMOS transistor P3 is electrically connected to the source of PMOS transistor P5, the source of PMOS transistor P3 is connected to the voltage VDD, the drain of PMOS transistor P4 is electrically connected to the source of PMOS transistor P6, and the source of PMOS transistor P4 is connected to the voltage VDD. Thus, this pair of cross-coupled inverters, together with NMOS transistors N1, N2, PMOS transistors P3, and P4, constitute a polarity reinforcement structure. The source of PMOS transistor P1 is connected to the voltage VDD, the drain of PMOS transistor P1 is electrically connected to the gates of PMOS transistor P2, NMOS transistor N1, and the drain of NMOS transistor N5 at the peripheral node S0; the gate of NMOS transistor N5 is electrically connected to the internal storage node Q, and the source of NMOS transistor N5 is grounded; the source of PMOS transistor P2 is connected to the voltage VDD, the drain of PMOS transistor P2 is electrically connected to the gates of PMOS transistor P1, NMOS transistor N2, and the drain of NMOS transistor N6 at the peripheral node S1; the gate of NMOS transistor N6 is electrically connected to the internal storage node QB, and the source of NMOS transistor N6 is grounded; the gate of PMOS transistor P1 is electrically connected to the gate of PMOS transistor P3; the gate of PMOS transistor P2 is electrically connected to the gate of PMOS transistor P4.The drain of the NMOS transistor N7 is electrically connected to the internal storage node QB, the source of the NMOS transistor N7 is electrically connected to the second bit line BLB, and the gate of the NMOS transistor N7 is electrically connected to the word line WL; the drain of the NMOS transistor N8 is electrically connected to the internal storage node Q, the source of the NMOS transistor N8 is electrically connected to the first bit line BL, and the gate of the NMOS transistor N8 is electrically connected to the word line WL; that is to say, the turn-on of the NMOS transistor N7 and the NMOS transistor N8 is controlled by the word line WL, and the NMOS transistor N7 and the NMOS transistor N8 are transfer transistors.

[0033] Further, the principle of the HRH-14T radiation-hardened SRAM memory cell circuit provided in Embodiment 1 of the present invention is as follows: ① In the hold stage, both the first bit line BL and the second bit line BLB are precharged to a high level, the word line WL is at a low level, the circuit inside remains in the initial state, and the circuit does not work. ② When reading data, both the first bit line BL and the second bit line BLB are precharged to a high level, the word line WL is at a high level, and the NMOS transistors N7 and N8 are turned on; if the data stored in this cell circuit is '0', then the first bit line BL discharges to the ground through the NMOS transistors N4 and N8, causing a bit line voltage difference, and then the data is read through the sense amplifier; if the data stored in this cell circuit is '1', then the second bit line BLB discharges to the ground through the NMOS transistors N3 and N7, causing a bit line voltage difference, and then the data is read through the sense amplifier. ③ In the write data stage, the word line WL is at a high level. If the first bit line BL is at a high level and the second bit line BLB is at a low level, then write '1' to the internal storage node Q through the NMOS transistor N8; if the first bit line BL is at a low level and the second bit line BLB is at a high level, then write '0' to the internal storage node Q through the NMOS transistor N8.

[0034] Compared with the prior art, in the HRH-14T radiation-hardened SRAM memory cell circuit provided by Embodiment 1 of the present invention, when only considering the improvement of the radiation-hardened performance by the circuit structure, if the memory node of the circuit is bombarded by particles, since both the internal memory node Q and the internal memory node QB of the circuit are surrounded by NMOS transistors, according to the principle of polarity strengthening, when the space particle bombards the sensitive node NMOS transistor, only a "1-0" voltage pulse is generated at the node, and this pulse cannot affect the states of other transistors due to the existence of the gate capacitance, which enables the internal memory node Q and the internal memory node QB to effectively avoid flipping. At the same time, the stability of the node data of the peripheral nodes S0 and S1 ensures that the internal memory node Q and the internal memory node QB can return to the initial state after flipping, thereby improving the SEU resistance ability of the circuit; if other non-critical nodes are bombarded by particles, then the memory cell is less likely to be affected; therefore, Embodiment 1 of the present invention can improve the single-event upset resistance ability of the cell circuit while sacrificing a small cell area, can resist all single-node flips, and can also resist peripheral memory double-node flips. Moreover, the critical charge of the cell is relatively high, the cell is more stable, and its read operation time and write operation time are better than those of the existing 14-transistor SRAM memory cell circuit.

[0035] The following conducts the following performance comparative analysis on the QUATRO 10T circuit in the prior art as shown in Figure 1 , the QUCCE10T circuit in the prior art as shown in Figure 2 , the We-QUATRO 12T circuit in the prior art as shown in Figure 3 , the RHBD14T circuit in the prior art as shown in Figure 4 and the HRH-14T radiation-hardened SRAM memory cell circuit provided by Embodiment 1 of the present invention as shown in Figure 5 :

[0036] (1) Simulate the HRH-14T radiation-hardened SRAM memory cell circuit provided by Embodiment 1 of the present invention as shown in Figure 5 (simulation conditions: Corner: TT; Temperature: 27 °C; VDD: 1.2V), so as to obtain the timing waveform diagram as shown in Figure 6 . It can be seen from Figure 6 that the HRH-14T radiation-hardened SRAM memory cell circuit provided by Embodiment 1 of the present invention can perform operations of writing '1', reading '1', writing '0' and reading '0' on the normal memory node.

[0037] (2) For the QUATRO 10T circuit in the prior art as shown in Figure 1 , the QUCCE10T circuit in the prior art as shown in Figure 2 ,Figure 3 In the prior art shown, the We-QUATRO 12T circuit, such as Figure 4 In the prior art shown, the RHBD14T circuit and such as Figure 5 The HRH-14T radiation-hardened SRAM memory cell circuit provided in Embodiment 1 of the present invention shown is subjected to circuit area comparison, read / write time and power consumption simulation comparison (simulation conditions: Corner: TT; Temperature: 27 °C; VDD: 1.2V), so as to obtain the circuit area, read / write time and power consumption simulation comparison table shown in Table 1 below:

[0038] Table 1

[0039] SRAM memory cell circuit Circuit area (μm) Read operation time (ps) Write operation time (ps) QUATRO 10T 7.69 112.5 29.15 QUCCE 10T 7.81 88.31 62.67 We-QUATRO 12T 8.76 60.58 20.3 RHBD 14T 9.54 99.52 39.3 HRH-14T 9.51 96.13 32.1

[0040] It can be seen from Table 1 that: compared with the SRAM memory cell circuit in the prior art, the circuit area of HRH-14T in Embodiment 1 of the present invention is smaller than that of the RHBD 14T circuit in the prior art and slightly higher than that of the We-QUATRO12T circuit in the prior art; the read operation time of HRH-14T in Embodiment 1 of the present invention is better than that of the RHBD 14T circuit in the prior art, and the write operation time of HRH-14T in Embodiment 1 of the present invention is much better than that of the RHBD 14T circuit in the prior art and the QUCCE 10T circuit in the prior art. At the same time, the power consumption of HRH-14T in Embodiment 1 of the present invention is also close to that of other existing circuit units.

[0041] (3) Simulate the HRH-14T radiation-hardened SRAM memory cell circuit provided in Embodiment 1 of the present invention shown (simulation condition: VDD: 1.2V), so as to obtain the transient waveform simulation diagram of the HRH-14T radiation-hardened SRAM memory cell circuit provided in Embodiment 1 of the present invention shown when it is injected with a double-exponential current source pulse at different times and different nodes. It can be seen from Figure 5 that: the HRH-14T radiation-hardened SRAM memory cell circuit provided in Embodiment 1 of the present invention can achieve the recovery of all single-node flips and can achieve the self-recovery of the node pair S0-S1, and has good single-node and multi-node flip immunity characteristics. Figure 7 that: the HRH-14T radiation-hardened SRAM memory cell circuit provided in Embodiment 1 of the present invention can achieve the recovery of all single-node flips and can achieve the self-recovery of the node pair S0-S1, and has good single-node and multi-node flip immunity characteristics. Figure 7 It can be seen that: the HRH-14T radiation-hardened SRAM memory cell circuit provided in Embodiment 1 of the present invention can achieve the recovery of all single-node flips and can achieve the self-recovery of the node pair S0-S1, and has good single-node and multi-node flip immunity characteristics.

[0042] (4) For the QUATRO 10T circuit in the prior art shown, the QUCCE10T circuit in the prior art shown, the We-QUATRO 12T circuit in the prior art shown, the RHBD14T circuit in the prior art shown and the Figure 1 For the QUATRO 10T circuit in the prior art shown, the QUCCE10T circuit in the prior art shown, the We-QUATRO 12T circuit in the prior art shown, the RHBD14T circuit in the prior art shown and the Figure 2 For the QUATRO 10T circuit in the prior art shown, the QUCCE10T circuit in the prior art shown, the We-QUATRO 12T circuit in the prior art shown, the RHBD14T circuit in the prior art shown and the Figure 3 For the QUATRO 10T circuit in the prior art shown, the QUCCE10T circuit in the prior art shown, the We-QUATRO 12T circuit in the prior art shown, the RHBD14T circuit in the prior art shown and the Figure 4 For the QUATRO 10T circuit in the prior art shown, the QUCCE10T circuit in the prior art shown, the We-QUATRO 12T circuit in the prior art shown, the RHBD14T circuit in the prior art shown and the Figure 5The critical charge comparison simulation is performed on the HRH-14T radiation-hardened SRAM memory cell circuit provided by Embodiment 1 of the present invention shown in the figure (simulation conditions: Corner: TT; Temperature: 27 °C; VDD: 1.2V), and thus the critical charge comparison table shown in Table 2 below can be obtained:

[0043] Table 2

[0044]

[0045] As can be seen from Table 2: Compared with the SRAM memory cell circuit in the prior art, the critical charge of the HRH-14T radiation-hardened SRAM memory cell circuit provided by Embodiment 1 of the present invention is relatively high, and the cell is more stable.

[0046] In summary, the embodiments of the present invention can improve the SEU resistance of the cell, can improve the single-event upset resistance of the cell circuit while sacrificing a relatively small cell area, can resist all single-node upsets, and can also resist the double-node upsets of the peripheral memory. Moreover, the critical charge of the cell is relatively high, the cell is more stable, and its read operation time and write operation time are better than those of the existing 14-transistor SRAM memory cell circuit.

[0047] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background art part of this article is only intended to deepen the understanding of the overall background art of the present invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art.

Claims

1. A 14T radiation-hardened SRAM memory cell circuit, characterized in that, It includes 8 NMOS transistors and 6 PMOS transistors; these 8 NMOS transistors are respectively defined as N1, N2, N3, N4, N5, N6, N7, N8; these 6 PMOS transistors are respectively defined as P1, P2, P3, P4, P5, P6; PMOS transistor P5 and NMOS transistor N3 form the first inverter, PMOS transistor P6 and NMOS transistor N4 form the second inverter, and these two inverters are cross-coupled; PMOS transistors P3 and P4 serve as pull-up transistors; an internal storage node QB is provided between the drain of PMOS transistor P5 and the drain of NMOS transistor N3, an internal storage node Q is provided between the drain of PMOS transistor P6 and the drain of NMOS transistor N4, NMOS transistors N1 and N2 reinforce the internal storage nodes QB and Q, and the internal storage nodes Q and QB are surrounded by NMOS transistors N1 - N8, which constitutes a polarity reinforcement structure; The peripheral nodes S0 and S1 are cross-coupled by PMOS transistors P1 and P2, and NMOS transistors N5 and N6 serve as pull-down transistors; the internal storage node QB is connected to the second bit line BLB through NMOS transistor N7, the internal storage node Q is connected to the first bit line BL through NMOS transistor N8, and the gates of NMOS transistor N7 and NMOS transistor N8 are both electrically connected to the word line WL; Among them, the drain of PMOS transistor P5 is electrically connected to the drain of NMOS transistor N1, the source of NMOS transistor N1 and the drain of NMOS transistor N3 are electrically connected to the internal storage node QB, and the source of NMOS transistor N3 is grounded; the drain of PMOS transistor P6 is electrically connected to the drain of NMOS transistor N2, the source of MOS transistor N2 and the drain of NMOS transistor N4 are electrically connected to the internal storage node Q, and the source of NMOS transistor N4 is grounded; the internal storage node QB is electrically connected to the gates of PMOS transistor P6 and NMOS transistor N4 together, and the internal storage node Q is electrically connected to the gates of PMOS transistor P5 and NMOS transistor N3 together; The drain of PMOS transistor P3 is electrically connected to the source of PMOS transistor P5, and the source of PMOS transistor P3 is connected to the voltage VDD; the drain of PMOS transistor P4 is electrically connected to the source of PMOS transistor P6, and the source of PMOS transistor P4 is connected to the voltage VDD; The source of the PMOS transistor P1 is connected to the voltage VDD. The drain of the PMOS transistor P1 is electrically connected to the gate of the PMOS transistor P2, the gate of the NMOS transistor N1, and the drain of the NMOS transistor N5 at the peripheral node S0. The gate of the NMOS transistor N5 is electrically connected to the internal storage node Q, and the source of the NMOS transistor N5 is grounded. The source of the PMOS transistor P2 is connected to the voltage VDD. The drain of the PMOS transistor P2 is electrically connected to the gate of the PMOS transistor P1, the gate of the NMOS transistor N2, and the drain of the NMOS transistor N6 at the peripheral node S1. The gate of the NMOS transistor N6 is electrically connected to the internal storage node QB, and the source of the NMOS transistor N6 is grounded. The gate of the PMOS transistor P1 is electrically connected to the gate of the PMOS transistor P3. The gate of the PMOS transistor P2 is electrically connected to the gate of the PMOS transistor P4. The drain of the NMOS transistor N7 is electrically connected to the internal storage node QB. The source of the NMOS transistor N7 is electrically connected to the second bit line BLB. The gate of the NMOS transistor N7 is electrically connected to the word line WL. The drain of the NMOS transistor N8 is electrically connected to the internal storage node Q. The source of the NMOS transistor N8 is electrically connected to the first bit line BL. The gate of the NMOS transistor N8 is electrically connected to the word line WL.

Images