Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a manufacturing method of a semiconductor structure and the semiconductor structure, which comprises the following steps: providing a first wafer, the first wafer has opposite first and second surfaces, and the first wafer has a first conductive structure, one end of the first conductive structure is located in the first wafer; performing a thinning treatment on the first wafer in a direction perpendicular to the first surface of the second surface until the thickness of the remaining first wafer reaches a preset thickness and the one end of the first conductive structure is exposed, the thinning treatment comprises at least one film layer peeling treatment, and the film layer peeling treatment comprises the following steps: performing hydrogen ion implantation on the second surface to form a hydrogen ion containing layer in the first wafer; and performing a heating treatment on the first wafer to make the hydrogen ion containing layer fall off.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Wafer bonding technology refers to the process of tightly joining two homogeneous or heterogeneous wafers through chemical and physical interactions. After bonding, the atoms at the interface react under the influence of external forces to form covalent bonds, achieving a specific bonding strength at the interface. Currently, a significant problem exists: the total thickness variation (TTV) of the resulting semiconductor structure is large, affecting its stability. Summary of the Invention

[0003] The technical problem solved by the embodiments of this disclosure is to provide a method for fabricating a semiconductor structure and a semiconductor structure, which at least helps to improve the stability of wafer bonding.

[0004] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a first wafer, the first wafer having a first surface and a second surface opposite to each other, and the first wafer having a first conductive structure, one end of the first conductive structure being located within the first wafer; performing a thinning process on the first wafer along a direction perpendicular to the first surface from the second surface until the remaining thickness of the first wafer reaches a preset thickness to expose one end of the first conductive structure, the thinning process including at least one film peeling process, the film peeling process including: performing hydrogen ion implantation on the second surface to form a hydrogen ion-containing layer within the first wafer; and performing a heat treatment on the first wafer to cause the hydrogen ion-containing layer to detach.

[0005] In addition, before performing the film peeling process, the process further includes: grinding the second surface of the first wafer in a direction perpendicular to the first surface until the remaining thickness of the first wafer is a first thickness, and the first thickness is greater than the preset thickness.

[0006] In addition, prior to the grinding process, the method further includes: providing a carrier wafer and bonding the first side of the first wafer to the carrier wafer.

[0007] Additionally, a second wafer is provided, the second wafer having a front side and a back side, the front side of the second wafer exposing a second conductive structure, and after the thinning process, the second side of the first wafer is bonded to the front side of the second wafer.

[0008] In addition, before bonding the first wafer and the second wafer, the method further includes: forming a groove on the second surface of the first wafer, the groove exposing the first conductive structure; forming a third conductive structure in the groove, the third conductive structure being electrically connected to the first conductive structure.

[0009] In addition, after bonding the second side of the first wafer to the front side of the second wafer, the process further includes removing the carrier wafer.

[0010] In addition, after the grinding process, the second surface of the ground first wafer is subjected to hydrogen ion implantation.

[0011] In addition, after the grinding process and before the film peeling process, the process further includes: the second surface after the grinding process has a concave structure and a convex structure, and the convex structure is subjected to hydrogen ion implantation, wherein the depth of hydrogen ion implantation is the same as the depth difference between the convex structure and the concave structure.

[0012] In addition, before injecting the hydrogen ions, the procedure further includes: oxidizing the convex structure on the surface of the second surface to form an oxide layer; and removing the oxide layer.

[0013] In addition, the oxidation treatment includes in-situ water vapor generation oxidation process or furnace tube oxidation treatment.

[0014] In addition, after the grinding process, the method further includes measuring the flatness of the second surface.

[0015] In addition, the instruments used to measure the flatness of the second surface include a laser interferometer.

[0016] In addition, the heating temperature used in the heat treatment is 400-600℃.

[0017] In addition, the thinning process includes multiple film peeling processes, and the implantation depth of the hydrogen ion implantation performed in each film peeling process decreases progressively from front to back.

[0018] According to some embodiments of this disclosure, another aspect of this disclosure also provides a semiconductor structure, which is formed using the fabrication method described above.

[0019] The technical solutions provided in this disclosure have at least the following advantages:

[0020] In the above technical solution, a first wafer is provided, which has a first side and a second side, and a first conductive structure is provided inside the first wafer. The first wafer is thinned along the second side of the first wafer in a direction perpendicular to the first side until the thickness of the first wafer reaches the expected thickness. The thinning process includes at least one film stripping process, which includes hydrogen ion implantation on the second side to form a hydrogen ion-containing layer. Heating causes the hydrogen ion-containing layer to fall off, thereby improving the flatness of the second side of the thinned first wafer and facilitating subsequent semiconductor structure processing. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are not to be limited in scale unless otherwise stated.

[0022] Figures 1 to 4 This is a schematic diagram of the semiconductor structure corresponding to each step of a semiconductor structure fabrication method.

[0023] Figures 5 to 12 A schematic diagram of the semiconductor structure corresponding to each step of a method for fabricating a semiconductor structure provided for the implementation of this disclosure;

[0024] Figures 13 to 15 The diagram shows the semiconductor structure corresponding to each step of another method for fabricating a semiconductor structure provided in this embodiment. Detailed Implementation

[0025] As can be seen from the background technology, there is currently a problem that the total thickness variation of the bonded semiconductor structure does not meet the requirements. Figures 1 to 4 This is a schematic diagram of the semiconductor structure corresponding to each step of a semiconductor structure fabrication method. Currently, the semiconductor structure fabrication steps include:

[0026] refer to Figure 1 A carrier wafer 111 and a first wafer 121 are provided in a stacked manner. The first wafer 121 has a first surface 11 and a second surface 12 opposite to each other. The first wafer 121 has a first conductive structure 13. The first surface 11 exposes the top surface of the first conductive structure 13, and the bottom surface of the first conductive structure 13 is located inside the first wafer 121.

[0027] The first side 11 can be the front side of the first wafer 121, and the second side 12 can be the back side of the first wafer 121.

[0028] refer to Figure 2 The second surface 12 of the first wafer 121 is ground until the remaining thickness of the first wafer 121 reaches the expected thickness.

[0029] Generally, a chemical mechanical polishing process is used for polishing. After polishing, a recessed area may appear on the second surface 12 of the first wafer 121.

[0030] refer to Figure 3 Conductive pads 14 are formed in the first wafer 121, and the conductive pads 14 are in contact with the first conductive structure 13, and the second surface 12 exposes the first conductive structure 13.

[0031] refer to Figure 4 The first wafer 121 is bonded to the second wafer 131 through the second surface 12 of the first wafer 121.

[0032] Because the surface of the second side 12 of the first wafer 121 is uneven, the first conductive structure 13 and the second wafer 131 may have poor contact, which may lead to delamination after the first wafer 121 and the second wafer 131 are bonded, or the bonded semiconductor structure may fail to achieve the target function.

[0033] This disclosure provides a method for fabricating a semiconductor structure. A first wafer is subjected to a film peeling process by hydrogen ion implantation, which results in a high degree of flatness on the second side of the first wafer after thinning. This provides a process basis for subsequent bonding of the semiconductor structure and improves the yield of the bonded semiconductor structure.

[0034] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0035] The memory structure provided in this embodiment will be described in more detail below with reference to the accompanying drawings.

[0036] Figures 5 to 13 This is a schematic diagram of the semiconductor structure corresponding to each step of the semiconductor structure fabrication method provided in this embodiment.

[0037] refer to Figure 5 A first wafer 211 is provided, the first wafer 211 has a first surface 21 and a second surface 22 opposite to each other, and a first conductive structure 23 is provided in the first wafer 211, one end of the first conductive structure 23 is located in the first wafer 211.

[0038] In some embodiments, the first conductive structure 23 may be a TSV (Through Silicon Via), which enables vertical interconnection to reduce the area of ​​the semiconductor structure in the horizontal direction, and can also reduce interconnection length and signal delay.

[0039] In some embodiments, the first wafer 211 may be a semiconductor wafer such as a silicon wafer or a germanium wafer; the first wafer 211 may have a memory cell, which may be a DRAM memory cell.

[0040] The material of the first conductive structure 23 can be conductive materials such as copper, tungsten, or polycrystalline silicon.

[0041] The first wafer 211 will then undergo a thinning process to reduce its thickness. In some embodiments, before the thinning process, a carrier wafer 221 may be provided, and the first surface 21 of the first wafer 211 may be bonded to the carrier wafer 221. During the subsequent thinning process, the carrier wafer 221 can provide support for the first wafer 211 to improve its mechanical strength and protect it. This is beneficial for improving the flatness of the second surface 23 of the first wafer 211 during the subsequent thinning process.

[0042] Specifically, in some embodiments, the carrier wafer 221 can be a wafer made of various suitable materials, such as a silicon wafer or a glass wafer. It is understood that the carrier wafer 221 can also be made of other semiconductor materials, such as germanium, silicon germanide, or other semiconductor materials, or it can be a wafer made of other metallic or non-metallic materials.

[0043] In some embodiments, the carrier wafer 221 and the first wafer 211 may be made of different materials, that is, the carrier wafer 221 and the first wafer 211 are heterogeneous wafers. During the bonding process of the carrier wafer 221 and the first wafer 211, the thermal mismatch and lattice mismatch problems between the carrier wafer 221 and the first wafer 211 can be solved by controlling the temperature and pressure, thereby improving the bonding quality between the carrier wafer 221 and the first wafer 211.

[0044] In other embodiments, the carrier wafer 221 and the first wafer 211 can be made of the same material, that is, the carrier wafer 221 and the first wafer 211 are homogeneous wafers, for example, both are silicon substrates. In the process of bonding the carrier wafer 221 and the first wafer 211, the first surface 21 of the carrier wafer 221 and the first wafer 211 can be directly bonded at room temperature, and then annealed to improve the bonding strength, so that the two wafers are combined into a whole. In order to improve the bonding strength between the wafers, the annealing process generally needs to reach 800°C to 1000°C.

[0045] refer to Figures 6 to 9 Along the direction of the second surface 22 perpendicular to the first surface 21, the first wafer 211 is thinned until the remaining thickness of the first wafer 211 reaches a preset thickness to expose one end of the first conductive structure 23. The thinning process includes at least one film stripping process, which includes: hydrogen ion implantation on the second surface 22 to form a hydrogen ion-containing layer 251 in the first wafer 211; and heating the first wafer 211 to remove the hydrogen ion-containing layer 251.

[0046] By forming a hydrogen ion-containing layer 251 and then peeling off the hydrogen ion-containing layer 251, the second surface 22 of the thinned first wafer 211 can have a higher flatness, thus providing a process basis for subsequent bonding of semiconductor structures and improving the yield of the bonded semiconductor structure.

[0047] refer to Figure 6 In some embodiments, before performing the film peeling process, the process may further include: grinding the first wafer 211 in the direction from the second surface 22 to the first surface 21 until the remaining thickness of the first wafer 211 is the initial thickness and the initial thickness is greater than the preset thickness.

[0048] Since the depth of each hydrogen ion implantation is limited, in order to reduce the process time, the first wafer 211 with a portion of its thickness is removed by grinding, which can reduce the number of subsequent film stripping processes and reduce the film stripping process time.

[0049] In some embodiments, a chemical mechanical polishing process may be used for polishing.

[0050] Specifically, during the grinding process of the first wafer 211, the surface of the second side 22 of the first wafer 211 may be uneven after grinding. This can lead to the formation of a defective third conductive structure in the subsequent back-end process, which will affect the stability of the bonded semiconductor structure.

[0051] In some embodiments, after the grinding process, the method may further include measuring the flatness of the second surface 22. By measuring the flatness of the second surface 22, the areas with higher heights on the second surface 22 can be thinned accordingly to facilitate subsequent film peeling.

[0052] In some embodiments, the instrument used to measure the surface flatness of the second surface 22 may include a laser interferometer. A high-precision laser interferometer can accurately measure the height difference of the second surface 22, thereby providing a theoretical basis for the thickness of the first wafer 211 to be removed in subsequent thinning processes, thus facilitating subsequent film stripping.

[0053] After the grinding process and before the film peeling process, the process may further include: the second surface after the grinding process has a concave structure 231 and a convex structure 232, and the convex structure 232 is subjected to hydrogen ion implantation, wherein the depth of hydrogen ion implantation is the same as the depth difference between the convex structure 232 and the concave structure 231.

[0054] It is understandable that the first wafer 211 will vibrate during the grinding process. This vibration will cause the surface of the grinding surface to be uneven. That is, the second surface 22 of the first wafer 211 may have several concave structures 231 and convex structures 232. These concave structures 231 and convex structures 232 will reduce the stability of the semiconductor structure after subsequent bonding and the bonding yield. Therefore, it is necessary to process these concave structures 231 and convex structures 232 to make the second surface 22 of the first wafer 211 relatively flat, thereby improving the stability of the semiconductor structure after subsequent bonding and the bonding yield.

[0055] In some embodiments, hydrogen ions may be implanted and react with ions in the first wafer 211 to break some of the chemical bonds in the first wafer 211. By removing this reacted portion of the first wafer 211, the flatness of the second surface 22 of the first wafer 211 can be improved.

[0056] It is understandable that the depth of hydrogen ion injection is related to the concave structure 231 and the convex structure 232. That is, the greater the height difference between the concave structure 231 and the convex structure 232, the deeper the hydrogen ion injection.

[0057] It should be noted that the specific shapes of the concave structure 231 and the convex structure 232 are related to the grinding method and the corresponding grinding tools, etc. This disclosure does not limit the shapes of the concave structure 231 and the convex structure 232.

[0058] refer to Figure 7 Before injecting hydrogen ions, the process also includes: oxidizing the convex structure 232 on the surface of the second surface 22 to form an oxide layer 241, and removing the oxide layer 241.

[0059] A portion of the thickness of the first wafer 211 is removed by forming an oxide layer 241 to improve the flatness of the second surface 22.

[0060] Local oxidation can be performed based on the flatness of the second surface 22 of the first wafer 211. In the direction perpendicular to the first surface 21, the thicker the first wafer 211, the thicker the oxide layer 241 can be. Since the thickness of the first wafer 211 removed in each film peeling process is limited, the flatness of the second surface 22 can be improved by removing the oxide layer 241, thereby reducing the number of film peeling processes and thus reducing the manufacturing process time of the semiconductor structure.

[0061] In some embodiments, in order to perform local oxidation on the second surface 22, a protective layer is usually formed on the surface of the second surface 22 that does not need to be oxidized, that is, on the surface of the second surface 22 with a thinner thickness in the direction perpendicular to the first surface 21. Then, the surface of the first wafer 211 is oxidized, and the protective layer on the surface of the second surface is removed after the oxidation process is completed.

[0062] In some embodiments, the oxidation process includes an in-situ water vapor generation oxidation process or a furnace tube oxidation process. The oxide layer 241 formed by the in-situ water vapor generation oxidation process or the furnace tube oxidation process has high density, and the second surface 22 of the first wafer 211 after removing the oxide layer 241 has high flatness. In other embodiments, the first wafer 211 can also be oxidized by an oxidizing agent to form the oxide layer 241.

[0063] In some embodiments, the material of the first wafer 211 is silicon, and the corresponding oxide layer 241 is silicon oxide. The method for removing the oxide layer 241 may be to etch the oxide layer 241 with a hydrofluoric acid solution with a molar concentration of 40% to 60%.

[0064] refer to Figure 8 Hydrogen ions are injected from the second surface 22, wherein the convex structure 232 (reference) Figure 6 The greater the depth difference between the concave structure 231 and the concave structure 231, the deeper the hydrogen ion is injected.

[0065] It is understandable that the convex structure 232 (reference) Figure 6 The greater the depth difference between the convex structure 232 and the concave structure 231, that is, in the direction perpendicular to the second surface 22 from the first surface 21, the greater the depth difference between the convex structure 232 (reference) and the concave structure 231. Figure 6 The higher the thickness of the first wafer 211 in the part where it is located, the higher the thickness of the first wafer 211 needs to be removed in order to improve the flatness of the second surface 22 of the first wafer 211.

[0066] Specifically, in some embodiments, hydrogen ion implantation can be performed on the entire second surface 22 of the first wafer 211.

[0067] In the direction perpendicular to the second surface 22 on the first surface 21, the amount of hydrogen ions injected can be adjusted according to the thickness of the first wafer 211 to increase the depth of hydrogen ions on the second surface 22 of the first wafer 211, forming a hydrogen ion-containing layer 251 with different thicknesses on the surface of the second surface 22.

[0068] In some embodiments, an ion implantation machine can be used to implant hydrogen ions, using a fixed high current to inject a large number of hydrogen ions from the second side 22 of the first wafer 211 to form a hydrogen ion-containing layer 251.

[0069] Specifically, an ion implantation machine may include an ion beam assembly and a base assembly. The ion beam assembly is used to provide an ion beam, and the base assembly is used to place the object to be implanted with ions.

[0070] refer to Figure 9 For hydrogen-containing ion layer 251 (reference) Figure 8 ) is heated to make the hydrogen ion layer 251 (reference) Figure 8 In some embodiments, the heat treatment is performed at a temperature of 400–600°C to prevent detachment.

[0071] Temperatures of 400℃ to 600℃ will cause the hydrogen ion layer 251 (reference) to be affected. Figure 8 The surface connected to the first wafer 211 creates a continuous cavity, thereby allowing the hydrogen ion layer 251 (reference) to form a continuous cavity. Figure 8 Automatically peeled off from the surface of the first wafer 211.

[0072] In some embodiments, a single heat treatment can be used to create a hydrogen ion layer 251 (reference layer) with different surface heights on the second side 22 of the first wafer 211. Figure 8 ) shedding, that is, by multiple local hydrogen ion implantations to form hydrogen ion-containing layers 251 of varying thicknesses on the surface of the second side 22 of the first wafer 211 (reference) Figure 8 Then, the hydrogen ion layer 251 is removed by another heat treatment.

[0073] In other embodiments, hydrogen ions may be locally implanted based on the flatness of the second surface after oxide layer removal to form a hydrogen-containing ion layer in a local area of ​​the first wafer. The hydrogen-containing ion layer is then heated to cause it to detach from the local area. The flatness of the remaining second surface of the first wafer is then obtained. Based on the newly obtained flatness, hydrogen ions are locally implanted again to form a new hydrogen-containing ion layer. The newly formed hydrogen-containing ion layer is then heated to cause it to detach. This process is repeated, injecting hydrogen ions into the area on the second surface of the first wafer with the highest height compared to the first surface and heating it to cause the hydrogen-containing ion layer to detach until the total thickness difference of the remaining second surface of the first wafer is less than 0.5 μm.

[0074] Heating causes the hydrogen ion layer 251 (reference) to be affected. Figure 8 The method of shedding can improve the flatness of the second surface 22 of the first wafer 211, and the hydrogen ion layer 251 (reference) Figure 8 The thickness difference of the second surface 22 of the first wafer 211 after detachment in the direction from the second surface 22 to the first surface 21 can be less than or equal to 0.2 μm, thereby improving the yield of the semiconductor structure.

[0075] In some embodiments, the thinning process includes multiple film stripping processes, wherein the hydrogen ion implantation depth of each film stripping process decreases progressively from front to back.

[0076] After multiple film peeling processes until the remaining thickness of the first wafer 211 reaches the preset thickness, i.e., without polishing, a hydrogen ion-containing layer 251 is formed through multiple hydrogen ion implantations (see reference). Figure 8 And heat to make the hydrogen ion layer 251 (reference) Figure 8 Delamination is performed, thereby forming a first wafer 211 with a high degree of flatness on the second surface 22 of the first wafer 211.

[0077] refer to Figure 10 Before bonding the first wafer 211 and the second wafer, the method further includes: forming a groove on the second surface 22 of the first wafer 211, exposing the first conductive structure 23 in the groove, forming a third conductive structure 24 in the groove, and electrically connecting the third conductive structure 24 with the first conductive structure 23.

[0078] In some embodiments, the third conductive structure may not be formed. Compared to not forming the third conductive structure, bonding the third conductive structure 24 with the second wafer can increase the contact area of ​​the conductive structure, thereby reducing the resistance of the contact surface.

[0079] In some embodiments, the third conductive structure 24 can also be formed by back-end process embedding. Using back-end process embedding can reduce contact resistance and improve the connection between the first conductive structure 22 and the third conductive structure 24.

[0080] refer to Figure 11 It also provides a second wafer 261 having a front side 25 and a back side 26, with the front side 25 of the second wafer 261 exposing a second conductive structure 27. After thinning, the second side 22 of the first wafer 211 is bonded to the front side 25 of the second wafer 261.

[0081] In some embodiments, the second wafer 261 may be a silicon wafer or a germanium wafer, and the wafer material of the second wafer 261 may be the same as that of the first wafer 211, and the second conductive structure 27 may be the same as the structure of the first conductive structure 23. The first wafer 211 and the second wafer 261 are bonded to achieve vertical interconnection, thereby reducing the area of ​​the semiconductor structure in the horizontal direction.

[0082] In other embodiments, before bonding the first wafer and the second wafer, the second side of the first wafer and the front side of the second wafer may be oxidized. Before the oxidation treatment, a second protective layer is formed on the exposed surfaces of the second conductive structure and the third conductive structure to prevent the second conductive structure and the third conductive structure from being oxidized. After the oxidation treatment, the second protective layer is removed. During the bonding process of the first wafer and the second wafer, the oxide films formed after the oxidation treatment are bonded to each other, and the conductive structures are bonded to each other, thereby realizing the bonding of the first wafer and the second wafer.

[0083] refer to Figure 12 After bonding the second side 22 of the first wafer 211 to the front side 25 of the second wafer 261, the process further includes: removing the carrier wafer 221 (see reference). Figure 11 ).

[0084] In this embodiment, the carrier wafer 221 (reference) Figure 11 ) is used to improve the mechanical strength of the first wafer 211 during the grinding process, and the carrier wafer 221 (reference) Figure 11 The carrier wafer 221 (reference) itself does not have a function. After bonding the first wafer 211 and the second wafer 261, the carrier wafer 221 is placed. Figure 11 Remove.

[0085] refer to Figure 13 In some other embodiments, the wafer materials of the first wafer 211 and the second wafer 261 are different, that is, the first wafer 211 and the second wafer 261 are heterogeneous wafers, and the first surface 21 of the first wafer 211 and the front surface 25 of the second wafer 261 can be directly bonded.

[0086] refer to Figure 14 and Figure 15 The second surface 22 of the first wafer 211 is thinned by hydrogen ion implantation until the remaining thickness of the first wafer 211 reaches the preset thickness. A groove is formed on the second surface 22 in a direction perpendicular to the first surface 21. The groove exposes the first conductive structure 23. Then, conductive material is filled into the groove to form a third conductive structure 24. The signal of the first conductive structure 23 is extracted through the third conductive structure 24.

[0087] In some embodiments, the thinning process of the second surface 22 of the first wafer 211 can be carried out by first performing a chemical mechanical polishing process, and then improving the flatness of the second surface 22 of the first wafer 211 by film peeling. During the chemical mechanical polishing process, the second wafer 261 improves the mechanical strength of the first wafer 211.

[0088] This embodiment of the present disclosure improves the flatness of the second surface 22 of the first wafer 211 by bonding the first surface 21 of the first wafer 211 to the carrier wafer 221, thinning the second surface 22 of the first wafer 211, and forming a hydrogen ion-containing layer by hydrogen ion implantation and heating to remove the hydrogen ion-containing layer. This improves the bonding strength of the subsequent bonding interface and thus enhances the stability of the semiconductor structure.

[0089] refer to Figure 15 The present disclosure also provides a semiconductor structure, including: a first wafer 211 having a first side 21 and a second side 22 opposite to each other, and the first wafer 211 having a first conductive structure 23 and a third conductive structure 24; and a second wafer 261 having a front side 25 and a back side 26 opposite to each other, and the second wafer 261 having a second conductive structure 27.

[0090] The first conductive structure 23 is electrically connected to the third conductive structure 24, and the second surface 22 exposes the surface of the third conductive structure 24. The front surface 25 of the second wafer 261 exposes the second conductive structure 27. The first wafer 211 and the second wafer 261 are bonded to the front surface 25 through the first surface 21, and the second conductive structure 27 is electrically connected to the third conductive structure 24.

[0091] This disclosure provides a semiconductor structure with a high degree of flatness at the bonding interface, thereby improving the bonding strength of the bonding interface and thus enhancing the stability of the semiconductor structure.

[0092] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A first wafer is provided, the first wafer having opposing first and second surfaces, and the first wafer having a first conductive structure, one end of the first conductive structure being located within the first wafer; The first wafer is thinned along the direction perpendicular to the first surface of the second surface until the remaining thickness of the first wafer reaches a preset thickness to expose one end of the first conductive structure. The thinning process includes at least one film stripping process, which includes: Hydrogen ion implantation is performed on the second surface to form a hydrogen ion-containing layer within the surface layer of the second surface of the first wafer; The first wafer is subjected to heat treatment to remove the hydrogen-containing ion layer; Before performing the film peeling process, the manufacturing method further includes: grinding the second surface of the first wafer in a direction perpendicular to the first surface until the remaining thickness of the first wafer is a first thickness, and the first thickness is greater than the preset thickness. The fabrication method further includes: providing a second wafer having a front side and a back side, the front side of the second wafer exposing a second conductive structure, and bonding the second side of the first wafer to the front side of the second wafer after the thinning process.

2. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, Prior to the grinding process, the method further includes: providing a carrier wafer and bonding the first side of the first wafer to the carrier wafer.

3. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, Before bonding the first wafer and the second wafer, the process further includes: A groove is formed on the second side of the first wafer, the groove exposing the first conductive structure; A third conductive structure is formed within the groove, and the third conductive structure is electrically connected to the first conductive structure.

4. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, After bonding the second side of the first wafer to the front side of the second wafer, the process further includes removing the carrier wafer.

5. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, After the grinding process, hydrogen ion implantation is performed on the entire second surface of the ground first wafer.

6. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, After the grinding process and before the film peeling process, the procedure further includes: The second surface after grinding has a concave structure and a convex structure. The convex structure is subjected to hydrogen ion implantation, wherein the depth of hydrogen ion implantation is the same as the depth difference between the convex structure and the concave structure.

7. The method for fabricating a semiconductor structure as described in claim 6, characterized in that, Before injecting the hydrogen ions, the procedure further includes: oxidizing the convex structure on the surface of the second surface to form an oxide layer; and removing the oxide layer.

8. The method for fabricating a semiconductor structure as described in claim 7, characterized in that, The oxidation treatment includes in-situ water vapor generation oxidation process or furnace tube oxidation treatment.

9. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, After the grinding process, the method further includes measuring the flatness of the second surface.

10. The method for fabricating a semiconductor structure as described in claim 9, characterized in that, The instruments used to measure the flatness of the second surface include: a laser interferometer.

11. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The heating temperature used in the heat treatment is 400~600℃.

12. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The thinning process includes multiple membrane stripping processes, and the implantation depth of the hydrogen ion implantation in each membrane stripping process decreases progressively from front to back.

13. A semiconductor structure, characterized in that, Semiconductor structure formed by the fabrication method according to any one of claims 1 to 12 above.

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