Semiconductor process method, semiconductor device

Abstract

The application provides a semiconductor process method, which comprises the following steps: forming a patterned hard mask layer on the top surface of a semiconductor epitaxial wafer; introducing a first process gas which does not react with the semiconductor epitaxial wafer and the hard mask layer into the upper side of the semiconductor epitaxial wafer, and ionizing the first process gas to form a first plasma, so as to heat the semiconductor epitaxial wafer to a temperature higher than a preset temperature; introducing an etching process gas into the upper side of the semiconductor epitaxial wafer, and ionizing the etching process gas to form a second plasma, so as to etch the semiconductor coating layer by using the second plasma. In the application, the first plasma formed by ionizing the first process gas before the etching process starts is used to heat the surface of the wafer, so that the temperature of the wafer is higher than the preset temperature, and thus the normal volatilization of the etching by-products such as indium chloride can be ensured by using the existing conventional lower electrode and other hardware structures, the hardware requirement is reduced, and the film etching effect is ensured. The application further provides a semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor process method and a semiconductor device manufactured by the semiconductor process method. Background Technology

[0002] With the continuous development of semiconductor materials, III-V compound materials, mainly gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), and gallium nitride (GaN), have larger band gaps and higher electron mobility, which can meet the requirements of modern electronic technology for high temperature and high frequency, and are widely used in semiconductor processes.

[0003] Indium phosphide (InP) materials possess high breakdown electric fields and higher average electron velocities. They exhibit significant conduction band discontinuities and high two-dimensional electron gas density at the InAlAs / InGaAs heterojunction interface, resulting in higher electron mobility. Therefore, InP-based devices are more suitable for high frequencies. Furthermore, the bandgap distribution of InP matches the long-wavelength optical fiber communication range (1.3-1.5µm), thus showing promising prospects in long-wavelength optoelectronic integrated circuits. The excellent properties of InP make it highly effective and important in high-frequency devices, such as InP-based high-electron-mobility transistors (HEMTs) and bipolar junction transistors (HBTs) in satellite military applications, as well as in optical communication applications, such as semiconductor lasers in the 1.31µm and 1.55µm bands.

[0004] With the continuous development of technology, high-performance semiconductor lasers are widely used in various fields such as gas detection, ultra-long-distance relay-free communication, and biomedicine. Obtaining better ridge waveguide morphology is a key process step in the fabrication of indium phosphide lasers.

[0005] In existing semiconductor process solutions, etching byproducts often accumulate in the trenches, affecting the etching effect of the trench structure and resulting in low product yield. To avoid the accumulation of byproducts affecting the etching effect, the chuck needs to be maintained at a high temperature during the semiconductor process, which places higher demands on the temperature resistance and temperature control of existing chucks and other components.

[0006] Therefore, how to provide a semiconductor process method that can reduce hardware requirements while ensuring film etching effect has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The present invention aims to provide a semiconductor process method and a semiconductor device fabricated by the semiconductor process method, which can reduce hardware requirements while ensuring film etching effect.

[0008] To achieve the above objectives, as one aspect of the present invention, a semiconductor process method is provided, the method comprising:

[0009] In the mask formation step, a patterned hard mask layer is formed on the top surface of the semiconductor epitaxial wafer, wherein the top layer of the semiconductor epitaxial wafer is a semiconductor cladding layer;

[0010] In the preheating step, a first process gas that does not chemically react with the semiconductor epitaxial wafer and the hard mask layer is introduced above the semiconductor epitaxial wafer, and the first process gas is ionized to form a first plasma, so as to use the first plasma to heat the semiconductor epitaxial wafer to a temperature higher than a preset temperature.

[0011] In the etching step, an etching process gas is introduced above the semiconductor epitaxial wafer, and the etching process gas is ionized to form a second plasma, so as to use the second plasma to etch the semiconductor cladding layer;

[0012] The preset temperature is not lower than the volatilization temperature of the byproducts generated in the etching step.

[0013] Optionally, the first process gas includes at least one of an inert gas and oxygen.

[0014] Optionally, the first process gas is helium.

[0015] Optionally, the power of the upper electrode in the preheating step is 500W-3000W, and the power of the lower electrode is 0W-50W.

[0016] Optionally, the etching process gas includes a chemical etching gas, a physical etching gas, and a thermally conductive gas. The chemical etching gas is a chlorine-based gas that does not contain hydrogen. The physical etching gas includes at least one of nitrogen and argon. The thermally conductive gas includes at least one of helium and oxygen.

[0017] Optionally, the chemical etching gas is chlorine, the physical etching gas is nitrogen, and the thermally conductive gas is helium.

[0018] Optionally, the flow rate of chlorine in the etching process gas is 10-200 sccm, and the flow rate of nitrogen in the etching process gas is 10-200 sccm; the ratio of the flow rate of nitrogen to the flow rate of chlorine is 1.5-2.5.

[0019] Optionally, the cavity pressure of the etching step is 1-20 mT, the lower electrode power is 100-1000 W, and the lower electrode temperature is 25℃-70℃.

[0020] As a second aspect of the present invention, a semiconductor device is provided, which is fabricated by the semiconductor process described above.

[0021] Optionally, the semiconductor device includes the semiconductor cladding layer, and the semiconductor cladding layer is made of at least one of indium phosphide, indium gallium arsenide phosphide, indium gallium phosphide, and aluminum indium gallium phosphide.

[0022] In the semiconductor process method and semiconductor device provided by the present invention, the surface of the wafer is heated by a first plasma formed by the ionization of a first process gas before the etching process begins, so that the temperature of the wafer is higher than a preset temperature. Thus, the normal volatilization of etching byproducts such as indium chloride can be ensured by using existing conventional lower electrodes (e.g., lower electrodes with an operating temperature of 20℃-70℃). This reduces hardware requirements while ensuring the film etching effect, obtaining a better ridge waveguide morphology, improving the performance of the semiconductor device, and reducing the production cost of the semiconductor device. Attached Figure Description

[0023] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof. In the drawings:

[0024] Figures 1 to 8 This is a schematic diagram of the process for fabricating semiconductor devices using the semiconductor process method provided in the embodiments of the present invention;

[0025] Figure 9 This is a scanning electron microscope characterization image of the trench structure obtained by etching using the semiconductor process method provided in the embodiments of the present invention;

[0026] Figure 10 yes Figure 9 Side view of region A of the central trench structure;

[0027] Figure 11 yes Figure 9 Enlarged schematic diagram of region B of the central trench structure;

[0028] Figure 12 yes Figure 9 Enlarged schematic diagram of region C of the central trench structure;

[0029] Figure 13 This is a comparative schematic diagram of the trenches etched in the semiconductor process method provided in this embodiment of the invention and the trenches etched in the prior art;

[0030] Figure 14 This is a comparative schematic diagram of scanning electron microscope characterization images of trenches obtained by etching in two embodiments of the semiconductor process method provided in this invention.

[0031] Figure 15 This is an atomic force microscope characterization image of a trench obtained by etching in one embodiment of the semiconductor process method provided by the present invention;

[0032] Figure 16 This is an atomic force microscopy characterization image of the trench obtained by etching in another embodiment of the semiconductor process method provided by the present invention;

[0033] Figure 17 This is a comparative schematic diagram of surface roughness statistics of trenches obtained by etching in two embodiments of the semiconductor process method provided by the present invention.

[0034] Figure 18 This is a flowchart of a semiconductor process method provided in an embodiment of the present invention. Detailed Implementation

[0035] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0036] In semiconductor device fabrication, plasma etching is typically used to etch semiconductor films to create patterns. A mixture of methane (CH4) and hydrogen (H2) is generally used as the process gas. The process utilizes the hydrogen ions (H+) in the plasma formed by the ionization of this process gas. + Etching is performed on semiconductor films. However, for group III-V compounds rich in In and P, such as indium phosphide (InP), indium gallium arsenide phosphide (InGaAsP), indium gallium phosphide (InGaP), and aluminum indium gallium phosphide (AlGaInP), hydrogen ions readily diffuse during the etching process and form a thin film deposition at the bottom of the trench, causing irreversible damage to the light-emitting performance of the device. Even with cleaning steps, hydrogen ions cannot be completely removed. Therefore, the introduction of hydrogen ions is strictly prohibited in the high-precision semiconductor processes of group III-V compounds.

[0037] As an alternative, chlorine (Cl)-based gases (such as chlorine gas, boron chloride gas, etc.) can be used to perform plasma etching on III-V materials. However, the temperature required for the volatilization of byproducts generated by etching III-V compounds with chlorine-based gases is relatively high. In order to avoid the accumulation of byproducts affecting the etching effect, the chuck needs to be maintained at a high temperature during the semiconductor process.

[0038] For example, the main product of etching indium phosphide materials with chlorine-based gases is indium chloride (InCl). x) and phosphorus chloride (PCl) x The main components are indium chloride (InCl3) and phosphorus chloride (PCl3), with indium chloride having a higher volatilization temperature than phosphorus chloride. Indium chloride is present in a chamber at a pressure of 10... -2 Under Torr conditions, the volatilization temperature is 150℃, at 10 -8 Under Torr conditions, the volatilization temperature is 100℃, and the chamber pressure during the etching process is greater than 5×10⁻⁶. -3 Under Torr conditions, the volatilization temperature is above 150°C.

[0039] Therefore, to avoid the etching process being affected by the failure to remove high-volatility byproducts, primarily indium chloride, in a timely manner, the conventional lower electrode (operating temperature 20℃-70℃) cannot meet the requirements. It needs to be replaced with a high-temperature lower electrode with an operating temperature of 20℃-200℃. At the same time, the high-temperature cooling source (chiller) for the lower electrode also needs to be replaced. Additionally, the process gas pipeline (gas line) and clean dry air (CDA) pipeline that meet the higher process temperatures also need to be replaced, which increases the cost of the entire semiconductor process chamber and the cost of the etching equipment.

[0040] To address the aforementioned technical problems, as one aspect of the present invention, a semiconductor process method is provided, such as... Figures 1 to 5 , Figure 18 As shown, the method includes:

[0041] Mask formation step S1: A hard mask layer 210 is formed on the top surface of the semiconductor epitaxial wafer 100. The top layer of the semiconductor epitaxial wafer 100 is a semiconductor cladding layer 170 (e.g., Figures 1 to 4 (as shown);

[0042] In the preheating step S2, a first process gas that does not chemically react with the semiconductor epitaxial wafer 100 and the hard mask layer 210 is introduced above the semiconductor epitaxial wafer 100, and the first process gas is ionized to form a first plasma, so as to use the first plasma to heat the semiconductor epitaxial wafer 100 to a temperature higher than the preset temperature.

[0043] In etching step S3, etching process gas is introduced above the semiconductor epitaxial wafer 100, and the etching process gas is ionized to form a second plasma, which is then used to etch the semiconductor cladding layer 170 (e.g., ...). Figures 4 to 5 (as shown);

[0044] The preset temperature is not lower than the volatilization temperature of the byproducts generated in etching step S3.

[0045] In the semiconductor process method provided by the present invention, before the etching process (step S3) begins, the surface of the wafer is heated by the first plasma formed by the ionization of the first process gas, so that the temperature of the wafer is higher than the preset temperature. Thus, the normal volatilization of etching byproducts such as indium chloride can be ensured by using existing conventional lower electrodes (e.g., lower electrodes with an operating temperature of 20℃-70℃). This reduces hardware requirements while ensuring the film etching effect, improving the performance of semiconductor devices, and reducing the production cost of semiconductor devices.

[0046] This invention does not specifically limit the film structure of the semiconductor epitaxial wafer 100. For example, when the semiconductor device to be fabricated is an indium phosphide (InP)-based high electron mobility transistor (HEMT), such as... Figure 1 As shown, the semiconductor epitaxial wafer 100 may include an indium phosphide substrate 110 and an N-type indium phosphide buffer layer 120, an aluminum indium gallium phosphide (AlGaInP) optical waveguide layer 130, an aluminum indium gallium arsenide (AlInGaAs) light absorption layer 140, a P-type aluminum indium gallium arsenide optical waveguide layer 150, and a P-type aluminum indium gallium phosphide optical waveguide layer 160 sequentially formed on the substrate 110.

[0047] As an optional embodiment of the present invention, the semiconductor cladding layer 170 may be made of at least one of indium phosphide, indium gallium arsenide phosphide, indium gallium phosphide, and aluminum indium gallium phosphide. The hard mask layer 210 may be made of at least one of silicon dioxide (SiO2) and silicon nitride (Si3N4).

[0048] like Figure 9 , Figure 13 As shown, the trenches obtained by etching the semiconductor cladding layer 170 using the semiconductor process method provided in this embodiment of the invention are... Figure 9 , Figure 13 (b) and trenches obtained by etching using existing techniques ( Figure 13 Compared to (a)), the cross-sectional view ( Figure 10 It can be seen that the sidewalls of the etched trenches are perpendicular (>88°), without footing (bottom rounded corners) or trench (micro-groove) structures, as shown in the magnified sidewall image. Figure 11 ) and bottom zoom-in image ( Figure 12 It can be clearly seen that the surface roughness of the sidewalls and bottom of the trench is very small, which can meet the etching precision requirements.

[0049] It should be noted that the preset temperature must be set to be greater than or equal to the highest volatilization temperature of all byproducts generated in etching step S3. For example, if the semiconductor cladding layer 170 is made of at least one of indium phosphide, indium gallium arsenide phosphide, indium gallium phosphide, and aluminum indium gallium phosphide, then indium phosphide has the highest volatilization temperature among the byproducts generated from etching the semiconductor cladding layer 170. In this case, as an optional embodiment of the present invention, the preset temperature can be the volatilization temperature of indium phosphide, 150°C (or higher), to ensure that all etching byproducts can volatilize normally. If the wafer surface temperature does not reach the volatilization temperature of the byproducts, the byproducts will deposit on the wafer surface and in the patterned grooves, thereby hindering the continued etching process. This manifests as differences in etching rates at different locations, inability to maintain a perpendicular morphology, and a significant increase in sidewall roughness. The heating time of the preheating step S2 can be determined in advance through experiments, as long as the time is long enough to ensure that the wafer temperature is heated to the preset temperature before the end of the preheating step S2. For example, the heating time can optionally be 180 seconds.

[0050] It should be noted that the semiconductor process method provided by the present invention is implemented through a semiconductor process chamber, which includes an upper electrode, a lower electrode, and devices and components such as a vacuum pump for controlling the chamber pressure. By providing radio frequency power to the upper electrode and the lower electrode respectively through a radio frequency power supply, the process gas between the two is ionized to form plasma, thereby performing semiconductor processing on the wafer on the lower electrode.

[0051] To further reduce the etching effect of the first plasma on the wafer, in a preferred embodiment of the present invention, the power of the lower electrode is controlled to be as low as possible in the preheating step S2. For example, the power of the upper electrode loaded in the preheating step S2 can be 500W-3000W, and the power of the lower electrode can be 0W-50W, thereby minimizing the bombardment effect of the first plasma on the wafer and reducing its influence on the surface morphology of the wafer while using the first plasma to achieve heating. Of course, as a preferred embodiment, radio frequency power may not be provided to the lower electrode.

[0052] In an optional embodiment of the present invention, in etching step S3, the temperature of the lower electrode can be controlled between 25°C and 70°C (e.g., 65°C). The chamber pressure range is controlled between 1 and 20 mTorr (e.g., 5 mTorr), the power of the upper electrode center (i.e., the power of the upper electrode center coil) is 500 to 3000 W (e.g., 800 W), the power of the upper electrode edge (i.e., the power of the upper electrode edge coil) is 500 to 3000 W (e.g., 600 W), and the power of the lower electrode is 100 to 1000 W (e.g., 220 W). The back helium pressure is 1-8 Torr (e.g., 2 Torr).

[0053] It should be noted that the first plasma formed by the ionization of the first process gas is only used for plasma heating and will not significantly etch the wafer surface through physical bombardment or chemically react with the hard mask layer 210 or the semiconductor cladding layer 170. For example, the first process gas may optionally include at least one of an inert gas and oxygen. Preferably, the first process gas is helium (He). Helium is an inert gas, and its plasma after dissociation will not chemically react with the material being etched and has a very small relative atomic mass. In this embodiment of the invention, helium, with the smallest molecular weight, is preferred for plasma heating, thereby minimizing the physical bombardment effect of the first plasma on the wafer surface. That is, after dissociation, it only plays a role in heating and heat conduction, and will not have any negative impact on the etching effect of the subsequent etching step S3.

[0054] To further improve the smoothness of the groove structure generated by etching, in a preferred embodiment of the present invention, the etching process gas includes a gas that serves to heat and conduct heat. For example, the etching process gas may include a heat-conducting gas, which includes at least one of helium and oxygen.

[0055] In this embodiment of the invention, the etching process gas includes a heat-conducting gas, which may include at least one of helium and oxygen, so that the second plasma includes the components of the first plasma. Heat conduction continues in the etching step S3, making the temperature distribution on the wafer surface more uniform. This avoids the low-temperature areas from being affected by the inability of etching byproducts to be removed from the chamber in time, thus affecting the etching morphology. This further improves the flatness of the trench structure and ensures the etching effect.

[0056] As an optional embodiment of the present invention, the etching process gas further includes chemical etching gas and physical etching gas, wherein the chemical etching gas is a chlorine-based gas that does not contain hydrogen; and the physical etching gas includes at least one of nitrogen and argon.

[0057] In the case where oxygen is used for plasma heat conduction in the etching process gas, as an optional embodiment of the present invention, the chemical etching gas is boron chloride (BCl3), the physical etching gas is argon (Ar), and the heat conduction gas is oxygen.

[0058] Argon gas, used for physical etching, is used to physically etch the semiconductor coating layer 170; boron chloride gas, used for chemical etching, is used to ionize and generate chloride ions to chemically etch the semiconductor coating layer 170, with the reaction formula being BCl3 → BCl. x +Cl - +B*,6Cl - +3InP→InCl3+PCl3.

[0059] In a preferred embodiment of the present invention, the chemical etching gas is chlorine (Cl2), the physical etching gas is nitrogen, and the thermally conductive gas is helium. That is, the etching process gas includes helium, chlorine, and nitrogen.

[0060] Its reaction mechanism is as follows:

[0061] 3Cl₂ + 2InP → 2InCl₃ + 2PCl₃;

[0062] N2→2N*+e+photons.

[0063] In addition to serving as a physical etching gas, nitrogen can also protect the trench sidewalls from lateral etching, playing a crucial role in optimizing the etching morphology.

[0064] To ensure a proper ratio between physical etching and chemical etching rates, in a preferred embodiment of the present invention, the flow rate ratio of nitrogen to chlorine in the etching process gas is 1.5-2.5. If the proportion of nitrogen in the etching process gas is too high (i.e., the flow rate ratio is higher than 2.5), the bombardment effect of the second plasma on the bottom of the trench will be too strong, resulting in excessively high roughness at the bottom of the trench. If the proportion of chlorine in the etching process gas is too high (i.e., the flow rate ratio is lower than 1.5), the chemical etching effect of the second plasma on the sidewall of the trench will be too strong, resulting in lateral etching and changing the shape of the sidewall of the trench.

[0065] In one optional embodiment of the present invention, the flow rate of helium in the etching process gas is 10–200 sccm. The flow rate of chlorine in the etching process gas is 10–200 sccm, and the flow rate of nitrogen in the etching process gas is 10–200 sccm. For example, optionally, the flow rate of helium can be 20 sccm, the flow rate of chlorine can be 25 sccm, and the flow rate of nitrogen can be 60 sccm.

[0066] like Figure 14 The diagram shows a comparison of the scanning electron microscope (SEM) characterization images of the trench structures obtained when the etching process gas consists only of physical etching gas and chemical etching gas (a) and when the etching process gas uses a thermally conductive gas (helium) (b). Figure 15 The image shown is an atomic force microscopy (AFM) characterization of the bottom of the trench corresponding to case (a). Figure 16The image shown is an atomic force microscopy (AFM) characterization of the bottom of the trench in case (b). The top left corner of the AFM characterization is a schematic diagram of the height distribution of each point (pixel) in the area detected by the microscope, with the average height of the bottom of the trench as the reference plane. Below is a histogram of the number of pixels (pxl) corresponding to each height interval in each cell (div). On the right is a statistical chart of the number of pixels corresponding to each height interval in the whole region detected by the microscope. Figure 17 The figure shows a comparison of the statistical data of the surface roughness of the groove structure obtained in two cases (including the minimum height min, maximum height max, median mid, mean, average height of a single micro-irregularity Rpv, root mean square roughness Rq, arithmetic mean roughness Ra, and the difference between the maximum and minimum values ​​Rz).

[0067] Depend on Figures 15 to 17 It can be seen that the arithmetic mean roughness Ra of the trench structure surface obtained by the chlorine + nitrogen scheme (case a) is 2.615 nm, while the arithmetic mean roughness Ra of the trench structure surface obtained by the chlorine + nitrogen + helium scheme (case b) is 2.074 nm. It is evident that the addition of helium to the etching process gas significantly reduces the roughness of the etched trench surface, which is beneficial to improving the light extraction performance of semiconductor devices such as lasers.

[0068] As an optional embodiment of the present invention, the hard mask layer 210 can be made of silicon dioxide (SiO2), and the patterned hard mask layer 210 can be obtained by photolithography, for example, as... Figures 1 to 4 As shown, step S2, which involves fabricating a patterned hard mask layer 210 on the top surface of the semiconductor epitaxial wafer 100, may specifically include:

[0069] Step S21: Fabricate a hard mask material layer 200 on the semiconductor cladding layer 170 (e.g., ... Figures 1 to 2 (as shown);

[0070] Step S22: Fabricate a patterned photoresist (PR, also known as photoresist) layer 300 on the hard mask material layer 200 (e.g., ...). Figures 2 to 3 (as shown);

[0071] Step S23: Using the photoresist layer 300 as a mask, perform an opening process on the hard mask material layer 200 (i.e., remove the material of the hard mask material layer 200 located in the area not covered by the photoresist layer 300) to obtain a patterned hard mask layer 210 (e.g., ...). Figures 3 to 4 (As shown).

[0072] In an optional embodiment of the present invention, step S21 specifically involves depositing a silicon dioxide mask to obtain a hard mask material layer 200 using plasma-enhanced chemical vapor deposition (PECVD). Specifically, a deposition gas formulation of nitrous oxide (N₂O) + nitrogen + silicon tetrahydrodeionide (SiH₄) can be used for deposition at 300°C, with a deposition rate controlled at approximately 45 nm / min, resulting in a film thickness of approximately 1 μm. The uniformity of the deposited film is required to be less than 3%, and the number of particles larger than 0.3 μm is required to be less than 30. The hard mask layer 210 obtained after the opening in step S23 is required to have a vertical morphology (i.e., the angle between the sidewall of the opening and the surface of the underlying film layer is greater than 88°), with no residual silicon dioxide material at the bottom of the opening, and a stripe width loss (CD loss) of less than 0.3 μm. In step S3, the hard mask layer 210 is directly used as the hard mask for ridge waveguide etching.

[0073] As an optional embodiment of the present invention, the semiconductor process method further includes the following steps after step S3:

[0074] Step S4, Remove hard mask layer 210 (e.g.) Figures 5 to 6 (as shown);

[0075] Step S6: Fabricate a P-type indium gallium arsenide (InGaAs) contact layer 400 on the semiconductor cladding layer 170;

[0076] Step S7, prepare electrode 500.

[0077] In a preferred embodiment of the present invention, the hard mask layer 210 can be removed in step S4 by cleaning with buffered oxide etch (BOE) (requiring no silicon dioxide mask residue).

[0078] In a preferred embodiment of the present invention, in step S5, a P-type indium gallium arsenide contact layer 400 may be deposited by metal-organic chemical vapor deposition (MOCVD).

[0079] As a second aspect of the present invention, a semiconductor device is provided, which is manufactured by the semiconductor process method provided in the embodiments of the present invention.

[0080] The semiconductor device provided by this invention is fabricated using the semiconductor process method provided in the embodiments of this invention. Before the etching process (step S3) begins, the surface of the wafer is heated by a first plasma formed by the ionization of a first process gas, so that the temperature of the wafer is higher than a preset temperature. This allows the normal volatilization of etching byproducts such as indium chloride to be ensured using existing conventional lower electrodes (e.g., lower electrodes with an operating temperature of 20°C-70°C). This reduces hardware requirements while ensuring the film etching effect, resulting in a better ridge waveguide morphology, improving the performance of the semiconductor device, and reducing the production cost of the semiconductor device.

[0081] The embodiments of the present invention do not specifically limit the structure type of the semiconductor device. For example, the semiconductor device may be a high electron mobility transistor (HEMT) or a heterojunction bipolar transistor (HBT).

[0082] As an optional embodiment of the present invention, the semiconductor device includes a semiconductor cladding layer 170, the material of which may include at least one of indium phosphide, indium gallium arsenide phosphide, indium gallium phosphide, and aluminum indium gallium phosphide.

[0083] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A semiconductor manufacturing process, characterized in that, The method includes: In the mask formation step, a patterned hard mask layer is formed on the top surface of the semiconductor epitaxial wafer, wherein the top layer of the semiconductor epitaxial wafer is a semiconductor cladding layer; In the preheating step, a first process gas that does not chemically react with the semiconductor epitaxial wafer and the hard mask layer is introduced above the semiconductor epitaxial wafer, and the first process gas is ionized to form a first plasma, so as to use the first plasma to heat the semiconductor epitaxial wafer to a temperature higher than a preset temperature. In the etching step, an etching process gas is introduced above the semiconductor epitaxial wafer, and the etching process gas is ionized to form a second plasma, so as to use the second plasma to etch the semiconductor coating layer. The etching process gas includes chemical etching gas, physical etching gas and thermally conductive gas. The preset temperature is not lower than the volatilization temperature of the byproducts generated in the etching step.

2. The semiconductor process method according to claim 1, characterized in that, The first process gas includes at least one of an inert gas and oxygen.

3. The semiconductor process method according to claim 2, characterized in that, The first process gas is helium.

4. The semiconductor process method according to claim 3, characterized in that, The preheating step applies a power of 500W-3000W to the upper electrode and a power of 0W-50W to the lower electrode.

5. The semiconductor process method according to claim 1, characterized in that, The chemical etching gas is a chlorine-based gas that does not contain hydrogen; the physical etching gas includes at least one of nitrogen and argon; the thermally conductive gas includes at least one of helium and oxygen.

6. The semiconductor process method according to claim 5, characterized in that, The chemical etching gas is chlorine, the physical etching gas is nitrogen, and the thermally conductive gas is helium.

7. The semiconductor process method according to claim 6, characterized in that, The flow rate of chlorine in the etching process gas is 10-200 sccm, and the flow rate of nitrogen in the etching process gas is 10-200 sccm; the ratio of the flow rate of nitrogen to the flow rate of chlorine is 1.5-2.

5.

8. The semiconductor process method according to claim 1, characterized in that, The cavity pressure of the etching step is 1-20 mT, the lower electrode power is 100-1000 W, and the lower electrode temperature is 25℃-70℃.

9. A semiconductor device, characterized in that, The semiconductor device is manufactured by the semiconductor process method described in any one of claims 1 to 8.

10. The semiconductor device according to claim 9, characterized in that, The semiconductor device includes the semiconductor cladding layer, and the semiconductor cladding layer is made of at least one of indium phosphide, indium gallium arsenide phosphide, indium gallium phosphide, and aluminum indium gallium phosphide.

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