Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region and a first fin located on the surface of the first region; forming an isolation prefabricated layer on the surface of the substrate, the isolation prefabricated layer also located on the sidewall of the first fin; etching the first fin to form a plurality of openings within the isolation prefabricated layer, the sidewalls of the openings exposing the isolation prefabricated layer; forming a barrier layer on the sidewalls of the openings; and forming a channel layer within the openings. Since the channel layer is formed by growing a channel layer material at the bottom of the openings, it is not necessary to first form a channel material layer and then etch it. Therefore, the stress of the channel layer is determined by the material growth, and there is no stress release due to subsequent etching, thus maintaining the stress of the channel layer and not affecting the improvement of the mobility of channel layer carriers, thereby improving the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] With the further development of semiconductor technology, as transistor feature sizes shrink to the nanoscale, proportional scaling techniques face increasingly severe challenges, such as mobility degradation, source-drain punch-through leakage, and hot carrier effects. Among these, mobility degradation is a major obstacle affecting the speed improvement of integrated circuits. By improving the mobility of carriers within the channel, it is possible to compensate for the mobility degradation caused by factors such as Coulomb interactions due to high channel doping, increased effective electric field strength due to thinner gate dielectric, and enhanced interface scattering.

[0003] Strained silicon technology introduces strain, or stress variation, into the channel layer through device structure and material design. This alters the lattice structure of the channel layer substrate, thereby increasing carrier mobility and improving device performance. Direct epitaxy of stressed channel materials is becoming a development trend. Germanium-silicon materials, due to their high carrier mobility, improved device reliability, and compatibility with existing silicon-based processes, have become a hot research topic for novel channel materials.

[0004] However, the technology of germanium-silicon channel devices still needs continuous improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, a method for forming a semiconductor structure is provided, comprising: providing a substrate, the substrate including a first region and a first fin located on the surface of the first region; forming an isolation prefabricated layer on the surface of the substrate, the isolation prefabricated layer also located on the sidewall of the first fin; etching the first fin to form a plurality of openings within the isolation prefabricated layer, the sidewalls of the openings exposing the isolation prefabricated layer; forming a barrier layer on the sidewalls of the openings; and forming a channel layer within the openings.

[0007] Optionally, the material of the barrier layer includes silicon nitride.

[0008] Optionally, the barrier layer is characterized by having a thickness ranging from 5 angstroms to 20 angstroms.

[0009] Optionally, the method for forming the barrier layer includes: forming a barrier material layer on the sidewall and bottom surface of the opening and on the surface of the isolation prefabricated layer; and etching the barrier material layer back until the first fin at the bottom of the opening is exposed to remove the barrier material layer at the bottom of the opening.

[0010] Optionally, the process for forming the barrier material layer includes atomic layer deposition.

[0011] Optionally, the etching process parameters for etching back the barrier material layer include: the angle between the incident direction of the ions and the normal direction of the substrate is 0 degrees to 2.5 degrees.

[0012] Optionally, after the trench layer is formed, the isolation prefabrication layer is etched to expose the top and part of the sidewalls of the trench layer, forming an initial isolation layer. The top of the initial isolation layer is lower than the top of the trench layer and is higher than or flush with the bottom of the trench layer.

[0013] Optionally, after forming the initial isolation layer, the method further includes annealing the initial isolation layer to form an isolation layer.

[0014] Optionally, the annealing process includes a steam annealing process.

[0015] Optionally, the parameters of the annealing process include: the gases used include oxygen / ozone and gaseous water, and the annealing temperature range is 350°C to 750°C.

[0016] Optionally, the material of the isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.

[0017] Optionally, the substrate further includes a second region and a second fin located on the surface of the second region.

[0018] Optionally, after forming the channel layer and before forming the initial isolation layer, the method further includes: planarizing the isolation prefabricated layer and the channel layer until the channel layer is flush with the top surface of the second fin.

[0019] Optionally, it also includes: the initial isolation layer is also located on the sidewall of the second fin and exposes the top and part of the sidewall of the second fin.

[0020] Optionally, after forming the initial isolation layer but before forming the isolation layer, the method further includes: modifying the channel layer and the second fin exposed by the initial isolation layer so that the channel layer exposed by the initial isolation layer and the second fin exposed by the initial isolation layer have the same size in both the direction parallel to the substrate and the direction perpendicular to the substrate.

[0021] Optionally, the process for modifying the channel layer and the second fin exposed by the initial isolation layer has a selection ratio of 1:3 to 1:8 for the channel layer and the second fin.

[0022] Optionally, after forming the initial isolation layer and before etching the channel layer and the second fin exposed by the initial isolation layer, the method further includes: removing the barrier layer.

[0023] Optionally, a hard mask layer is also provided on the top surfaces of the first fin and the second fin.

[0024] Optionally, before forming the opening, the process further includes removing the hard mask layer on the first region.

[0025] Optionally, the method for removing the hard mask layer on the first region includes: forming a patterned layer on the surface of the isolation prefabricated layer, the patterned layer exposing the isolation prefabricated layer and the top surface of the hard mask layer on the first region; etching the hard mask layer on the first region to expose the top surface of the first fin; and removing the patterned layer after removing the hard mask layer on the first region.

[0026] Optionally, it may also include forming a capping layer on the exposed surface of the channel layer.

[0027] Optionally, the material of the cover layer includes silicon.

[0028] Optionally, the process for forming the channel layer includes an epitaxial growth process.

[0029] Optionally, the method for forming the isolation prefabricated layer includes: forming a dielectric material layer on the surface of the substrate, planarizing the dielectric material layer until the top surface of the first fin is exposed, thereby forming the isolation prefabricated layer.

[0030] Optionally, the process parameters for forming the isolation prefabricated layer include: the gases used include NH3 and (SiH3)3N, the flow rate of NH3 is 1 sccm to 1000 sccm, the flow rate of (SiH3)3N is 3 sccm to 800 sccm, and the temperature is 50°C to 100°C.

[0031] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0032] In the semiconductor structure formation method provided by the present invention, the first fin is etched to form a plurality of openings in the isolation prefabrication layer. The sidewalls of the openings expose the isolation prefabrication layer. A channel layer is formed in the openings. Since the channel layer is formed by growing a channel layer material at the bottom of the opening, it is not necessary to form a channel material layer first and then etch it. Therefore, the stress of the channel layer is determined by the material growth, and there will be no stress release due to subsequent etching. The stress of the channel layer is maintained, and the improvement of the mobility of the channel layer carriers is not affected, thus improving the performance of the device. Attached Figure Description

[0033] Figures 1 to 2 This is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0034] Figures 3 to 10 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention;

[0035] Figures 11 to 20 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0036] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0037] As described in the background section, the performance of semiconductor structures formed using existing germanium-silicon channel device technology urgently needs improvement. This paper will now illustrate and analyze one such semiconductor structure.

[0038] Figures 1 to 2 This is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0039] Please refer to Figure 1 A substrate 101 is provided; a channel material layer 102 is formed on the substrate 101; a patterned layer 103 is formed on the channel material layer 102, the patterned layer 103 exposing a portion of the surface of the channel material layer 102.

[0040] Please refer to Figure 2 Using the patterned layer 103 as a mask, the channel material layer 101 and the substrate 101 are etched to form a fin 104 and a bottom structure 105 located between the fin 104 and the substrate 101.

[0041] In the above method, the fin 104 is used to form the channel of a germanium-silicon channel device. The fin 104 is located on the bottom structural layer 105. The material of the fin 104 is germanium-silicon, and the material of the bottom structural layer 105 is silicon. Due to the lattice mismatch between germanium and silicon, compressive stress is generated on the fin 104. This compressive stress can reduce the effective conductivity mass of holes in the channel direction and improve the speed of the PMOS device. During the formation of the fin 104, the channel material layer 101 is etched, which causes partial release of the stress within the channel material layer 101. This significantly reduces the stress obtained in the final channel, thereby limiting the improvement of the channel carrier mobility and affecting the device performance.

[0042] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. This method involves etching the first fin to form multiple openings within the isolation prefabrication layer. The sidewalls of these openings expose the isolation prefabrication layer. A channel layer is formed within these openings. Since the channel layer is formed by growing a channel layer material at the bottom of the openings, it is not necessary to first form a channel material layer and then etch it. Therefore, the stress in the channel layer is determined by the material growth process, preventing stress release due to subsequent etching. This maintains the stress in the channel layer, does not affect the improvement of the channel layer carrier mobility, and improves the device performance.

[0043] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figures 3 to 10 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0045] Please refer to Figure 3 A substrate is provided, the substrate including a first region I and a first fin 201 located on the surface of the first region I.

[0046] The substrate material can be monocrystalline silicon, polycrystalline silicon, or amorphous silicon, or it can be a semiconductor material such as silicon, germanium, silicon germanide, or gallium arsenide, or it can be a semiconductor-on-insulator structure. In this embodiment, the substrate material is monocrystalline silicon.

[0047] The material of the first fin 201 includes silicon. In this embodiment, the material of the first fin 201 is monocrystalline silicon. In other embodiments, the material of the first fin 201 may also be polycrystalline silicon, amorphous carbon, etc.

[0048] In this embodiment, a hard mask layer 202 is also provided on the top surface of the first fin 201.

[0049] The hard mask layer 202 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the hard mask layer 202 is made of silicon nitride.

[0050] The method for forming the first fin 201 includes: forming a patterned hard mask layer 202 on the surface of the substrate, the hard mask layer 202 exposing a portion of the substrate surface; using the hard mask layer 202 as a mask, etching the substrate to form the first region I and the first fin 201 located on the surface of the first region I.

[0051] Please refer to Figure 4An isolation prefabrication layer 203 is formed on the surface of the substrate, and the isolation prefabrication layer 203 is also located on the sidewall of the first fin 201.

[0052] The method for forming the isolation prefabricated layer 203 includes: forming a dielectric material layer (not shown in the figure) on the surface of the substrate, planarizing the dielectric material layer until the top surface of the first fin 201 is exposed, thereby forming the isolation prefabricated layer 203. In this embodiment, the isolation prefabricated layer 203 is also located on the sidewall of the hard mask layer 202. Specifically, the dielectric material layer is planarized until the top surface of the hard mask layer 202 above the first fin 201 is exposed.

[0053] The process parameters for forming the isolation prefabricated layer 203 include: the gases used include NH3 and (SiH3)3N, the flow rate of NH3 is 1 sccm to 1000 sccm, the flow rate of (SiH3)3N is 3 sccm to 800 sccm, and the temperature is 50°C to 100°C.

[0054] In this embodiment, the process for forming the isolation prefabricated layer 203 employs a fluid chemical vapor deposition process that does not include annealing. The isolation prefabricated layer 203 is used to subsequently form an initial isolation layer, which in turn forms the isolation layer and provides electrical insulation between different devices. To form the isolation layer, the initial isolation layer formed from the isolation prefabricated layer 203 is subsequently annealed. However, no annealing is performed in the process of forming the isolation prefabricated layer 203. This is to reduce the number of annealing processes, reduce ion diffusion within the structure (such as the deep well region) formed before this process step, reduce the adverse effects of ion diffusion on the device, and improve device performance.

[0055] Please refer to Figure 5 The first fin 202 is etched to form a plurality of openings 204 in the isolation prefabrication layer 203, and the sidewalls of the openings 204 expose the isolation prefabrication layer 203.

[0056] The etching process for the first fin 202 includes one or a combination of dry etching and wet etching. In this embodiment, the etching process for the first fin 202 is a dry etching process. The process parameters for etching the first fin 202 include: etching gases including HBr and Cl2, etching machine power of 100W to 1000W, gas pressure in the etching chamber of 2mTorr to 20mTorr, hydrogen bromide flow rate of 10sccm to 500sccm, and chlorine flow rate of 10sccm to 500sccm. The dry etching process is beneficial for forming openings with better shapes.

[0057] Before forming the opening 204, the process further includes: removing the hard mask layer 202 on the first region I.

[0058] The process for removing the hard mask layer 202 on the first region includes either dry etching or wet etching. In this embodiment, the process for removing the hard mask layer 202 on the first region is a wet etching process. The process parameters for removing the hard mask layer 202 on the first region include: the chemical solution is hot phosphoric acid with a concentration (volume fraction) of 60% to 95%, and the temperature range is 155°C to 165°C. Since hot phosphoric acid has a high etching selectivity for silicon nitride, the wet etching process has a high selectivity ratio for the hard mask layer 202 and the isolation prefabricated layer 203, which is beneficial for removing the hard mask layer 202 and causes less damage to the isolation prefabricated layer 203.

[0059] Subsequently, a barrier layer is formed on the sidewall of the opening 204. For the method of forming the barrier layer, please refer to [reference needed]. Figures 6 to 7 .

[0060] Please refer to Figure 6 A barrier material layer 205 is formed on the sidewall and bottom surface of the opening 204 and on the surface of the isolation prefabricated layer 203.

[0061] The formation process of the barrier material layer 205 includes atomic layer deposition (ALD). In this embodiment, the barrier material layer 205 is formed using ALD; in other embodiments, it can be formed using other chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes. ALD has excellent step coverage, which is beneficial for forming a film of uniform thickness.

[0062] The barrier material layer 205 is made of silicon nitride; the thickness of the barrier material layer 205 ranges from 5 angstroms to 20 angstroms. The barrier material layer 205 is used for subsequent formation of the barrier layer. In this embodiment, the barrier material layer 205 is made of silicon nitride.

[0063] Please refer to Figure 7 The barrier material layer 205 is etched back until the first fin 201 at the bottom of the opening 204 is exposed, in order to remove the barrier material layer 205 at the bottom of the opening 204.

[0064] In this embodiment, the method for forming the barrier layer 206 further includes: etching back the barrier material layer 205 until the surface of the isolation prefabricated layer 203 is exposed.

[0065] The barrier layer 206 is made of silicon nitride; the thickness of the barrier layer ranges from 5 angstroms to 20 angstroms. The material and thickness of the barrier layer 206 are determined by the barrier material layer 205. In this embodiment, the material of the barrier layer 206 is silicon nitride.

[0066] The barrier layer 206 is used to block the subsequent growth of the channel layer material on the sidewall, so that the channel layer material grows only from the first fin 201 at the bottom of the opening 204, which inhibits the lateral growth of the channel layer material and facilitates the formation of a channel layer with a smooth surface.

[0067] The etching process parameters for re-etching the barrier material layer 205 include: the angle between the incident direction of the ions and the normal direction of the substrate is 0 degrees to 2.5 degrees. Because the angle between the incident direction of the ions and the normal direction of the substrate is small, it facilitates the removal of the barrier material layer 205 from the bottom of the opening 204 and the surface of the isolation prefabrication layer 203, and reduces damage to the barrier layer 206.

[0068] Please refer to Figure 8 A channel layer 207 is formed within the opening 204.

[0069] The material of the channel layer 207 includes germanium and silicon.

[0070] The process for forming the channel layer 207 includes an epitaxial growth process. In this embodiment, the process for forming the channel layer 207 is an epitaxial growth process. The process parameters of the epitaxial growth process include: the reaction gases include SiH4, GeH4, and H2, the flow rate of SiH4 is in the range of 110 sccm to 130 sccm, the flow rate of GeH4 is in the range of 95 sccm to 115 sccm, the flow rate of H2 is in the range of 25 slm to 35 slm, and the gas pressure is in the range of 95 to 105 Torr.

[0071] The channel layer 207 is used to form the channel of the device in the future. The channel layer 207 is formed by growing a channel layer material at the bottom of the opening, without the need to form a channel material layer first and then etch it. Therefore, the stress of the channel layer is determined by the material growth, and there will be no stress release due to subsequent etching. This maintains the stress of the channel layer, does not affect the improvement of the mobility of the channel layer carriers, and improves the performance of the device.

[0072] The channel layer 207 is made of germanium-silicon, and the substrate is made of silicon. Due to the lattice mismatch between germanium and silicon, compressive stress is generated on the channel layer 207. The compressive stress can reduce the effective conductivity mass of holes in the channel direction and improve the speed of PMOS devices.

[0073] Please refer to Figure 9 After the trench layer 207 is formed, the isolation prefabricated layer 203 is etched to expose the top and part of the sidewalls of the trench layer 207, forming an initial isolation layer 208. The top of the initial isolation layer 208 is lower than the top of the trench layer 207 and is higher than or flush with the bottom of the trench layer 207.

[0074] The etching process for the isolation prefabricated layer 203 includes one or a combination of dry etching and wet etching. In this embodiment, the etching process for the isolation prefabricated layer 203 is a dry etching process. The process parameters for etching the isolation prefabricated layer 203 include: etching gases including HBr and Cl2, etching machine power of 100W to 1000W, gas pressure in the etching chamber of 2mTorr to 20mTorr, hydrogen bromide flow rate of 10sccm to 500sccm, and chlorine flow rate of 10sccm to 500sccm.

[0075] In this embodiment, the method further includes removing the blocking layer 206.

[0076] The process for removing the barrier layer 206 includes one or a combination of dry etching and wet etching. In this embodiment, the process for removing the barrier layer 206 is a wet etching process. The process parameters for removing the barrier layer 206 include: the chemical solution is hot phosphoric acid with a concentration (volume fraction) of 60% to 95%, and the temperature range is 155°C to 165°C. Because hot phosphoric acid has a high etching selectivity for silicon nitride, the process for removing the barrier layer 206 has a high selectivity ratio for both the barrier layer 206 and the initial isolation layer 208, and also has a high selectivity ratio for both the barrier layer 206 and the fin 201, which is beneficial for removing the barrier layer 206 and causes less damage to the initial isolation layer 208 and the fin 201.

[0077] Please refer to Figure 10 A cover layer 209 is formed on the exposed surface of the channel layer 207.

[0078] The material of the capping layer 209 includes silicon. The material of the contact surface between the capping layer 209 and the channel layer 207 is silicon or silicon nitride. The capping layer 209 can be a single-layer structure, and its material can be silicon or SiN; the capping layer 209 can also be a multi-layer structure, such as a three-layer structure of Si / SiO2 / SiN or SiN / SiO2 / SiN.

[0079] The capping layer 209 is used to protect the channel layer 207 and prevent the channel layer 207 from being oxidized. Alternatively, it can be formed into a gate dielectric layer through a subsequent oxidation process during the gate structure formation process.

[0080] After forming the initial isolation layer 209, the method further includes annealing the initial isolation layer 209 to form an isolation layer.

[0081] The material of the isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

[0082] The annealing process includes a water vapor annealing process, and the parameters of the annealing process include: the gases used include oxygen / ozone and gaseous water, and the annealing temperature range is 350℃ to 750℃.

[0083] The annealing process is used to form the initial isolation layer 209 into an insulating dielectric layer, and also to eliminate the stress generated during the formation of the channel layer 207, thereby improving the performance of the device. On the other hand, it also reduces the number of annealing processes. The reasons and purposes are explained in the process description of forming the isolation prefabricated layer 203, and will not be repeated here.

[0084] Figures 11 to 20 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to another embodiment of the present invention.

[0085] Please refer to Figure 11 A substrate is provided, the substrate including a first region I and a first fin 301 located on the surface of the first region I, and also including a second region II and a second fin 302 located on the surface of the second region II.

[0086] The substrate material can be monocrystalline silicon, polycrystalline silicon, or amorphous silicon, or it can be a semiconductor material such as silicon, germanium, silicon germanide, or gallium arsenide, or it can be a semiconductor-on-insulator structure. In this embodiment, the substrate material is monocrystalline silicon.

[0087] The material of the first fin 301 includes silicon; the material of the second fin 302 also includes silicon. In this embodiment, the materials of the first fin 301 and the second fin 302 are monocrystalline silicon. In other embodiments, the materials of the first fin 301 and the second fin 302 may also be polycrystalline silicon, amorphous carbon, etc.

[0088] In this embodiment, a hard mask layer 303 is also provided on the top surface of the first fin 301 and the second fin 302.

[0089] The hard mask layer 303 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the hard mask layer 303 is made of silicon nitride.

[0090] The method for forming the first fin 301 and the second fin 302 includes: forming a patterned hard mask layer 303 on the surface of the substrate, the hard mask layer 303 exposing a portion of the substrate surface; using the hard mask layer 303 as a mask, etching the substrate to form the first fin 301 located in the first region I and the second fin 302 located in the second region II.

[0091] Please refer to Figure 12An isolation prefabrication layer 304 is formed on the surface of the substrate, and the isolation prefabrication layer 304 is also located on the sidewall of the first fin 301 and the sidewall of the second fin 302.

[0092] The method for forming the isolation prefabricated layer 304 includes: forming a dielectric material layer (not shown in the figure) on the surface of the substrate; planarizing the dielectric material layer until the top surfaces of the first fin 301 and the second fin 302 are exposed, thereby forming the isolation prefabricated layer 304. In this embodiment, the isolation prefabricated layer 304 is also located on the sidewall of the hard mask layer 303. Specifically, the dielectric material layer is planarized until the top surface of the hard mask layer 303 is exposed.

[0093] The process parameters for forming the isolation prefabricated layer 304 include: the gases used include NH3 and (SiH3)3N, the flow rate of NH3 is 1 sccm to 1000 sccm, the flow rate of (SiH3)3N is 3 sccm to 800 sccm, and the temperature is 50°C to 100°C.

[0094] In this embodiment, the process for forming the isolation prefabricated layer 304 employs a fluid chemical vapor deposition process that does not include annealing. The isolation prefabricated layer 304 is used to subsequently form an initial isolation layer, which in turn forms the isolation layer and provides electrical insulation between different devices. While the initial isolation layer formed from the isolation prefabricated layer 304 is typically annealed before forming the isolation layer, no annealing is performed in the process of forming the isolation prefabricated layer 304. This is to reduce the number of annealing processes, minimize ion diffusion within the structure already formed before this process step (such as a deep well region), reduce the adverse effects of ion diffusion on the device, and improve device performance.

[0095] The first fin 301 is subsequently etched to form multiple openings within the isolation prefabrication layer 304. Before forming the openings, the process further includes removing the hard mask layer 303 on the first region. For a method of removing the hard mask layer 303 on the first region, please refer to [reference needed]. Figure 13 .

[0096] Please refer to Figure 13 A patterned layer 305 is formed on the surface of the isolation prefabricated layer 304, the patterned layer 305 exposing the top surface of the isolation prefabricated layer 304 and the hard mask layer 303 on the first region I; the hard mask layer 303 on the first region I is etched to expose the top surface of the first fin 301; after removing the hard mask layer 303 on the first region I, the patterned layer 305 is removed.

[0097] The process for removing the hard mask layer 303 on the first region includes either dry etching or wet etching. In this embodiment, the process for removing the hard mask layer 303 on the first region is a wet etching process. The process parameters for removing the hard mask layer 303 on the first region include: the chemical solution is hot phosphoric acid with a concentration (volume fraction) of 60% to 95%, and the temperature range is 155°C to 165°C. Since hot phosphoric acid has a high etching selectivity for silicon nitride, the wet etching process has a high selectivity ratio for the hard mask layer 303 and the isolation prefabricated layer 304, which is beneficial for removing the hard mask layer 303 and causes less damage to the isolation prefabricated layer 304.

[0098] Please refer to Figure 14 The first fin 301 is etched to form a plurality of openings 306 in the isolation prefabrication layer 304.

[0099] In this embodiment, the etching process for the first fin 301 is a dry etching process. The process parameters for etching the first fin 301 include: etching gases comprising HBr and Cl2; etching machine power ranging from 100W to 1000W; gas pressure within the etching chamber ranging from 2mTorr to 20mTorr; hydrogen bromide flow rate ranging from 10sccm to 500sccm; and chlorine flow rate ranging from 10sccm to 500sccm. The dry etching process facilitates the formation of openings with better shapes.

[0100] Subsequently, a barrier layer is formed on the sidewall of the opening 303. For the method of forming the barrier layer, please refer to [reference needed]. Figures 15 to 16 .

[0101] Please refer to Figure 15 A barrier material layer 307 is formed on the sidewall and bottom surface of the opening 306 and on the surface of the isolation prefabricated layer 304.

[0102] The formation process of the barrier material layer 307 includes atomic layer deposition (ALD). In this embodiment, the barrier material layer 307 is formed using ALD; in other embodiments, it can be formed using other chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes. ALD has excellent step coverage, which is beneficial for forming a film of uniform thickness.

[0103] The barrier material layer 307 is made of silicon nitride; the thickness of the barrier material layer 307 ranges from 5 angstroms to 20 angstroms. The barrier material layer 307 is used for subsequent formation of the barrier layer. In this embodiment, the barrier material layer 307 is made of silicon nitride.

[0104] Please refer to Figure 16 The barrier material layer 307 is etched back until the first fin 301 at the bottom of the opening 306 is exposed, in order to remove the barrier material layer 307 at the bottom of the opening 306.

[0105] In this embodiment, the method for forming the barrier layer 308 further includes: etching back the barrier material layer 307 until the surface of the isolation prefabricated layer 304 is exposed.

[0106] The barrier layer 308 is made of silicon nitride; the thickness of the barrier layer ranges from 5 angstroms to 20 angstroms. The material and thickness of the barrier layer 308 are determined by the barrier material layer 307. In this embodiment, the material of the barrier layer 308 is silicon nitride.

[0107] The barrier layer 308 is used to block the subsequent growth of the channel layer material on the sidewall, so that the channel layer material grows only from the first fin 301 at the bottom of the opening 306, which inhibits the lateral growth of the channel layer material and facilitates the formation of a channel layer with a smooth surface.

[0108] The etching process parameters for re-etching the barrier material layer 307 include: the angle between the incident direction of the ions and the normal direction of the substrate is 0 degrees to 2.5 degrees. Because the angle between the incident direction of the ions and the normal direction of the substrate is small, it facilitates the removal of the barrier material layer 307 from the bottom of the opening 306 and the surface of the isolation prefabrication layer 304, and reduces damage to the barrier layer 308.

[0109] Please refer to Figure 17 A channel layer 309 is formed within the opening 306.

[0110] The material of the channel layer 309 includes germanium and silicon.

[0111] The process for forming the channel layer 309 includes an epitaxial growth process. In this embodiment, the process for forming the channel layer 309 is an epitaxial growth process. The process parameters of the epitaxial growth process include: the reaction gases include SiH4, GeH4, and H2, the flow rate of SiH4 is in the range of 110 sccm to 130 sccm, the flow rate of GeH4 is in the range of 95 sccm to 115 sccm, the flow rate of H2 is in the range of 25 slm to 35 slm, and the gas pressure is in the range of 95 to 105 Torr.

[0112] The channel layer 309 is used to form the channel of the device in the future. The channel layer 309 is formed by growing a channel layer material at the bottom of the opening, without the need to form a channel material layer first and then etch it. Therefore, the stress of the channel layer is determined by the material growth, and there will be no stress release due to subsequent etching. This maintains the stress of the channel layer, does not affect the improvement of the mobility of the channel layer carriers, and improves the performance of the device.

[0113] The channel layer 309 is made of germanium-silicon, and the substrate is made of silicon. Due to the lattice mismatch between germanium and silicon, compressive stress is generated on the channel layer 309. The compressive stress can reduce the effective conductivity mass of holes in the channel direction and improve the speed of PMOS devices.

[0114] Subsequently, the isolation prefabricated layer 304 is etched to expose the top and part of the sidewalls of the channel layer 309, forming the initial isolation layer.

[0115] Please refer to Figure 18 After the channel layer 309 is formed, but before the initial isolation layer is formed, the method further includes: planarizing the isolation prefabricated layer 304 and the channel layer 309 until the channel layer 309 is flush with the top surface of the second fin 302.

[0116] The planarization process for the isolation prefabricated layer 304 and the channel layer 309 includes a mechanical chemical polishing process. The planarization process is used to ensure that the channel layer 309 and the second fin 302 have the same height in the direction perpendicular to the substrate.

[0117] Please refer to Figure 19 After the trench layer 309 is formed, the isolation prefabricated layer 304 is etched to expose the top and part of the sidewalls of the trench layer 309, forming an initial isolation layer 310. The top of the initial isolation layer 310 is lower than the top of the trench layer 309 and is higher than or flush with the bottom of the trench layer 309.

[0118] The etching process for the isolation prefabricated layer 304 includes one or a combination of dry etching and wet etching. In this embodiment, the etching process for the isolation prefabricated layer 304 is a dry etching process. The process parameters for etching the isolation prefabricated layer 304 include: etching gases including HBr and Cl2, etching machine power of 100W to 1000W, gas pressure in the etching chamber of 2mTorr to 20mTorr, hydrogen bromide flow rate of 10sccm to 500sccm, and chlorine flow rate of 10sccm to 500sccm.

[0119] In this embodiment, the method further includes removing the barrier layer 308. Specifically, the barrier layer 308 located on the surface of the channel layer 309 on the initial isolation layer 310 is removed.

[0120] The process for removing the barrier layer 308 includes one or a combination of dry etching and wet etching. In this embodiment, the process for removing the barrier layer 308 is a wet etching process. The process parameters for removing the barrier layer 308 include: the chemical solution is hot phosphoric acid with a concentration (volume fraction) of 60% to 95%, and the temperature range is 155°C to 165°C. Because hot phosphoric acid has a high etching selectivity for silicon nitride, the process for removing the barrier layer 308 has a high selectivity ratio for the barrier layer 308 and the initial isolation layer 208, a high selectivity ratio for the barrier layer 308 and the channel layer 309, and a high selectivity ratio for the barrier layer 308 and the second fin 302, which is beneficial for removing the barrier layer 308 and causes less damage to the initial isolation layer 310, the channel layer 309, and the second fin 302.

[0121] The initial isolation layer 310 is then annealed to form an isolation layer.

[0122] In this embodiment, after forming the initial isolation layer 310 and before forming the isolation layer, the method further includes: modifying the channel layer 309 and the second fin 302 exposed by the initial isolation layer 310, so that the channel layer 309 exposed by the initial isolation layer 310 and the second fin 302 exposed by the initial isolation layer 310 have the same size in both the direction parallel to the substrate and the direction perpendicular to the substrate.

[0123] The process for modifying the exposed channel layer 309 and second fin 302 of the initial isolation layer 310 has a selection ratio for the channel layer 309 and the second fin 302 ranging from 1:3 to 1:8. In this embodiment, the process for modifying the exposed channel layer 309 and second fin 302 of the initial isolation layer 310 has a selection ratio for the channel layer 309 and the second fin 302 of 1:3.

[0124] The process for modifying the exposed channel layer 309 and second fin 302 of the initial isolation layer 310 includes one or a combination of dry etching and wet etching. In this embodiment, the process for modifying the exposed channel layer 309 and second fin 302 of the initial isolation layer 310 is a dry etching process. The process parameters of the dry etching process include: etching gases including H2 and Ar2, and the power range of the etching machine from 100W to 500W.

[0125] Please refer to Figure 20 A cover layer 311 is formed on the exposed surface of the channel layer 309.

[0126] The material of the capping layer 311 includes silicon. The material of the contact surface between the capping layer 311 and the channel layer 309 is silicon or silicon nitride. The capping layer 311 can be a single-layer structure, and its material can be silicon or SiN; the capping layer 311 can also be a multi-layer structure, such as a three-layer structure of Si / SiO2 / SiN or SiN / SiO2 / SiN.

[0127] In this embodiment, the covering layer 311 is also located on the surface of the second fin 302, specifically, on the surface of the second fin 302 above the initial isolation layer 310.

[0128] The capping layer 311 is used to protect the channel layer 309 and prevent the channel layer 309 from being oxidized. Alternatively, it can be formed into an oxide layer during the gate structure formation process through a subsequent oxidation process and used as a gate dielectric layer.

[0129] After forming the initial isolation layer 310, the process further includes annealing the initial isolation layer 310 to form an isolation layer.

[0130] The material of the isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

[0131] The annealing process includes a water vapor annealing process, and the parameters of the annealing process include: the gases used include oxygen / ozone and gaseous water, and the annealing temperature range is 350℃ to 750℃.

[0132] The annealing process is used to form the initial isolation layer 310 into an insulating dielectric layer, and also to eliminate the stress generated during the formation of the channel layer 309, thereby improving the performance of the device. On the other hand, it also reduces the number of annealing processes. The reasons and purposes are explained in the process description of forming the isolation prefabricated layer 304, and will not be repeated here.

[0133] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a first fin located on the surface of the first region; An isolation prefabrication layer is formed on the surface of the substrate, and the isolation prefabrication layer is also located on the sidewall of the first fin. The process of forming the isolation prefabrication layer adopts a fluid chemical vapor deposition process that does not include an annealing process. The first fin is etched to form a plurality of openings in the isolation prefabrication layer, the sidewalls of which expose the isolation prefabrication layer; A barrier layer is formed on the sidewall of the opening; A channel layer is formed within the opening, and the barrier layer is used to prevent the growth of the channel layer material on the sidewall. The isolation prefabricated layer is etched to expose the top and part of the sidewalls of the trench layer, forming an initial isolation layer. The top of the initial isolation layer is lower than the top of the trench layer and flush with the bottom of the trench layer. Remove the barrier layer; The initial isolation layer is annealed to form an isolation layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The barrier layer is made of silicon nitride.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the barrier layer ranges from 5 angstroms to 20 angstroms.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the barrier layer includes: forming a barrier material layer on the sidewall and bottom surface of the opening and on the surface of the isolation prefabricated layer; and etching the barrier material layer back until the first fin at the bottom of the opening is exposed to remove the barrier material layer at the bottom of the opening.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The process for forming the barrier material layer includes atomic layer deposition.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The parameters of the etching process for re-etching the barrier material layer include: the angle between the incident direction of the ions and the normal direction of the substrate is 0 degrees to 2.5 degrees.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The annealing process includes a steam annealing process.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The parameters of the annealing process include: the gases used include oxygen / ozone and gaseous water, and the annealing temperature range is 350 ℃ to 750 ℃.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes a second region and a second fin located on the surface of the second region.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, After the channel layer is formed but before the initial isolation layer is formed, the method further includes: planarizing the isolation prefabricated layer and the channel layer until the channel layer is flush with the top surface of the second fin.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, Also includes: The initial isolation layer is also located on the sidewall of the second fin and exposes the top and part of the sidewall of the second fin.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming the initial isolation layer, but before forming the isolation layer, the method further includes: modifying the channel layer and the second fin exposed by the initial isolation layer so that the channel layer exposed by the initial isolation layer and the second fin exposed by the initial isolation layer have the same size in both the direction parallel to the substrate and the direction perpendicular to the substrate.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process for modifying the exposed channel layer and the second fin of the initial isolation layer has a selection ratio of 1:3 to 1:8 for the channel layer and the second fin.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, After forming the initial isolation layer, before etching the channel layer and the second fin exposed by the initial isolation layer, the method further includes: removing the barrier layer.

16. The method for forming a semiconductor structure as described in claim 10, characterized in that, A hard mask layer is also located on the top surface of the first fin and the second fin.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, Before forming the opening, the process further includes removing the hard mask layer on the first region.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The method for removing the hard mask layer on the first region includes: forming a patterned layer on the surface of the isolation prefabricated layer, the patterned layer exposing the isolation prefabricated layer and the top surface of the hard mask layer on the first region; etching the hard mask layer on the first region to expose the top surface of the first fin; and removing the patterned layer after removing the hard mask layer on the first region.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A capping layer is formed on the exposed surface of the channel layer.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The material of the cover layer includes silicon.

21. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the channel layer includes an epitaxial growth process.

22. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the isolation prefabricated layer includes: forming a dielectric material layer on the surface of the substrate, planarizing the dielectric material layer until the top surface of the first fin is exposed, thereby forming the isolation prefabricated layer.

23. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for forming the isolation prefabricated layer include: the gases used include NH3 and (SiH3)3N, the flow rate of NH3 is 1 sccm to 1000 sccm, the flow rate of (SiH3)3N is 3 sccm to 800 sccm, and the temperature is 50 ℃ to 100 ℃.

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