A semiconductor structure and a method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. A substrate structure is provided, which comprises a silicon substrate, a buried oxide layer on the silicon substrate, and a semiconductor layer on the buried oxide layer. An isolation structure is formed in the substrate structure, which at least penetrates the semiconductor layer. A cover layer is formed to cover the semiconductor layer and the isolation structure. Etching is performed on the cover layer, the semiconductor layer and the buried oxide layer to obtain an etching groove. The etching groove exposes the silicon substrate. The sidewall of the etching groove is the sidewall of the isolation structure, or the sidewall of the etching groove comprises the sidewall of the buried oxide layer and the sidewall of the isolation structure. Then, semiconductor material is selectively epitaxially grown in the etching groove to form a semiconductor structure. The cover layer is removed. The sidewall of the isolation structure and the sidewall of the buried oxide layer are not semiconductor material, so that the sidewall of the isolation structure and the sidewall of the buried oxide layer are not easy to grow during the selective epitaxial growth of the semiconductor material. The semiconductor structure is easy to grow upward from the silicon substrate and has good quality, and the process defects are reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] As semiconductor device dimensions shrink, the short-channel effect (SCE) in traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) becomes increasingly severe. The SCE leads to problems such as subthreshold swing (SS) degradation, drain-induced barrier lowing (DIBL), and increased device leakage current.

[0003] To allow MOS device dimensions to continue shrinking according to Moore's Law, there are currently two solutions: one is to form a FinFET (Fin Field-Effect Transistor), and the other is the Fully Depleted Silicon on Insulator (FDSOI) design. The FDSOI process is characterized by a wafer consisting of a silicon substrate, a buried oxide (BOX) layer on the silicon substrate, and an ultrathin top silicon layer (SOI) on the oxide layer. The thickness of the top silicon layer is much smaller than the thickness of the depletion layer under the transistor channel.

[0004] Compared to FinFET technology, FDSOI offers several advantages. Firstly, FDSOI devices remain planar transistors, requiring fewer photomasks and simplifying the manufacturing process. Secondly, FDSOI MOSFETs exhibit lower parasitic capacitance, effectively suppressing short-channel effects, reducing transistor power consumption, and improving circuit operating speed. For RF circuits, smaller capacitance increases the characteristic frequency (ft) and maximum frequency (fmax), two crucial parameters. For digital circuits, FDSOI MOSFETs can modulate their threshold voltage through back-gate bias (forward and reverse bias) to achieve multi-threshold voltage circuits.

[0005] In the FDSOI process, a hybrid region also needs to be formed, which is equivalent to the bulk silicon structure in the FDSOI architecture. There are two reasons for needing a hybrid region: First, in addition to forming CMOS devices, FDSOI also needs to form passive devices that contact the underlying silicon substrate, such as resistors, capacitors, and ESD protection circuits, which require formation on the bulk silicon structure. Second, the hybrid region can be used to bring out the back gate for studying and implementing back gate modulation.

[0006] However, the quality of the bulk silicon structure formed in the current mixed region is poor and cannot meet the actual needs. Summary of the Invention

[0007] In view of this, the purpose of this application is to provide a semiconductor device and a method for manufacturing the same, which forms a semiconductor structure of good quality.

[0008] This application provides a method for manufacturing a semiconductor device, including:

[0009] A substrate structure is provided, the substrate structure comprising a silicon substrate, a buried oxide layer on the silicon substrate, and a semiconductor layer on the buried oxide layer;

[0010] An isolation structure is formed in the substrate structure; the isolation structure penetrates at least through the semiconductor layer.

[0011] A cover layer is formed covering the semiconductor layer and the isolation structure;

[0012] An etching trench is formed by etching the capping layer, the semiconductor layer, and the buried oxide layer; the etching trench exposes the silicon substrate; the sidewall of the etching trench is the sidewall of the isolation structure, or the sidewall of the etching trench includes the sidewall of the buried oxide layer and the sidewall of the isolation structure.

[0013] Semiconductor material is selectively epitaxially grown in the etching trench to form a semiconductor structure; the capping layer is then removed.

[0014] Optionally, the isolation structure is a local silicon oxide isolation, the sidewall of the etching trench includes the sidewall of the buried oxide layer and the sidewall of the isolation structure above the buried oxide layer, and forming the isolation structure in the substrate structure includes:

[0015] A portion of the semiconductor layer is thermally oxidized to form an isolation structure for the isolation semiconductor layer.

[0016] Optionally, the partial thermal oxidation of the semiconductor layer includes:

[0017] A hard mask layer is formed on the substrate, and the hard mask layer is patterned to expose the substrate structure of the isolation region;

[0018] An oxide layer is formed by thermal oxidation growth on the substrate structure using a patterned hard mask layer as a mask.

[0019] Optionally, the isolation structure is a shallow trench isolation, the sidewall of the etching trench includes the sidewall of the isolation structure, and forming the isolation structure in the substrate structure includes:

[0020] The semiconductor layer, the buried oxide layer, and the substrate structure are etched to form an isolation trench that penetrates the semiconductor layer and the buried oxide layer and partially penetrates the substrate structure.

[0021] The isolation trench is filled with a medium material to form an isolation structure.

[0022] Optionally, the etching of the semiconductor layer, the buried oxide layer, and the substrate structure includes:

[0023] A hard mask layer is formed on the substrate, and the hard mask layer is patterned to expose the substrate structure of the isolation region;

[0024] The semiconductor layer, the buried oxide layer, and the substrate structure are etched using a patterned hard mask layer as a mask.

[0025] Optionally, the material of the hard mask layer is silicon nitride, or the hard mask layer is a stack of a pad oxide layer and a silicon nitride layer.

[0026] Optionally, when etching the cover layer, semiconductor layer and buried oxide layer between two adjacent isolation structures to obtain an etching trench, the isolation structure is also partially etched.

[0027] Optionally, the material of the buried oxide layer is silicon oxide, and the material of the isolation structure is silicon oxide.

[0028] This application provides a semiconductor device, including:

[0029] A substrate structure, the substrate structure comprising a silicon substrate, a buried oxide layer on the silicon substrate, and a semiconductor layer on the buried oxide layer;

[0030] An isolation structure in the substrate structure, the isolation structure extending at least through the semiconductor layer;

[0031] A semiconductor structure located between two adjacent isolation structures; the semiconductor structure extends through the semiconductor layer and the buried oxide layer; all sidewalls of the semiconductor structure are in contact with the sidewalls of the isolation structure, or a portion of the sidewalls of the semiconductor structure are in contact with the sidewalls of the isolation structure, and another portion of the sidewalls are in contact with the sidewalls of the buried oxide layer.

[0032] Optionally, the isolation structures on both sides of the semiconductor structure have a smaller horizontal cross-section compared to the isolation structures farther away from the semiconductor structure.

[0033] Optionally, the isolation structure is a local silicon oxide isolation or a shallow trench isolation.

[0034] This application provides a semiconductor device and its manufacturing method. A substrate structure is provided, comprising a silicon substrate, a buried oxide layer on the silicon substrate, and a semiconductor layer on the buried oxide layer. An isolation structure is formed in the substrate structure, penetrating at least through the semiconductor layer, forming a capping layer covering the semiconductor layer and the isolation structure. An etching trench is formed by etching the capping layer, the semiconductor layer, and the buried oxide layer, exposing the silicon substrate. The sidewalls of the etching trench are the sidewalls of the isolation structure, or the sidewalls of the etching trench include the sidewalls of the buried oxide layer and the sidewalls of the isolation structure. Semiconductor material is then selectively epitaxially grown in the etching trench to form a semiconductor structure. The capping layer is then removed. Since the sidewalls of the isolation structure and the buried oxide layer are not semiconductor material, semiconductor material is not easily grown on the sidewalls of the isolation structure and the buried oxide layer during selective epitaxial growth. Therefore, it is easier to grow a high-quality semiconductor structure upwards from the silicon substrate, avoiding the bulging problem caused by the overlap of upward and lateral semiconductor material growth during selective epitaxial growth, reducing process defects, and improving process window and device yield. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a current method for forming a semiconductor structure;

[0037] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device as provided in this application embodiment;

[0038] Figures 3-13 This is a schematic diagram of the structure of a semiconductor device during the manufacturing process. Detailed Implementation

[0039] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0040] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0041] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0042] Currently, integrating MOS devices on FDSOI can effectively solve the short-channel effect present in planar MOS devices, reduce transistor power consumption, and improve circuit operating speed. In the current FDSOI process, a hybrid region is formed, and silicon material is grown on the silicon substrate within the hybrid region to constitute a bulk silicon structure.

[0043] refer to Figure 1 The diagram shown illustrates a current method for forming a bulk silicon structure. First, a substrate structure is provided, comprising a silicon substrate, a buried oxide layer (BOX) on the silicon substrate, and a top silicon insulator (SOI) on the buried oxide layer. (Refer to...) Figure 1 As shown in Figure A; a hard mask layer is formed on the substrate structure, and the hard mask layer is patterned to expose the mixing region beneath it, as referenced. Figure 1 As shown in B; using a patterned hard mask layer as a mask, the top silicon layer and buried oxide layer are etched to obtain the etch trench of the mixed region, as shown in the reference. Figure 1 As shown in Figure C; selective epitaxial growth of silicon material in an etching tank yields a bulk silicon structure, as referenced. Figure 1 As shown in E; remove the hard mask layer to make the top silicon layer and the upper surface of the bulk silicon structure flush, as shown in the reference. Figure 1 As shown in G. However, in this selective epitaxial growth of silicon material, the sidewalls of the etching trench expose the sidewalls of the top silicon layer. Therefore, in addition to growing silicon upwards from the surface of the silicon substrate, silicon is also grown laterally from the sidewalls of the top silicon layer. The overlap of the upwardly grown silicon and the laterally grown silicon can easily form bulges, resulting in defects in the bulk silicon structure.

[0044] Currently, using patterned hard masks as a mask, etching of the top silicon layer and buried oxide layer can be performed in a step-by-step etching process. First, isotropic etching is performed on the top silicon layer in both the horizontal and vertical directions, followed by anisotropic etching on the buried oxide layer in the vertical direction, resulting in etched trenches for the mixed region. (Refer to...) Figure 1 As shown in D; then, semiconductor materials are selectively epitaxially grown in the etching tank to obtain a bulk silicon structure, as referenced. Figure 1 As shown in Figure F; remove the hard mask layer to make the top silicon layer and the upper surface of the bulk silicon structure flush, as shown in Figure F. Figure 1 As shown in H. In this selective epitaxial growth of silicon material, the sidewalls of the etching trench expose the sidewalls of the top silicon layer. Therefore, in addition to growing silicon upwards from the surface of the silicon substrate, silicon is also grown laterally from the sidewalls of the top silicon layer. However, the sidewalls of the top silicon layer are recessed compared to the sidewalls of the buried oxide layer, thus reducing the overlap between the upwardly grown silicon and the laterally grown silicon, and to some extent solving the problem of bulging during silicon epitaxial growth.

[0045] However, in this selective epitaxial growth of silicon material, isotropic etching of the top silicon layer is used. The depth of lateral etching of the top silicon layer is the same as the depth of vertical etching of the silicon substrate. When the thickness of the top silicon layer is thin, the depth of lateral etching is shallow, but the trenches in the entire mixing region are very deep, so the problem of bulging cannot be completely eliminated.

[0046] Therefore, the current process for forming bulk silicon structures in the hybrid region tends to result in poor quality of the bulk silicon structures in the hybrid region, which cannot meet practical needs.

[0047] Based on this, embodiments of this application provide a semiconductor device and a method for manufacturing the same. A substrate structure is provided, comprising a silicon substrate, a buried oxide layer on the silicon substrate, and a semiconductor layer on the buried oxide layer. An isolation structure is formed within the substrate structure, penetrating at least the semiconductor layer to form a capping layer covering the semiconductor layer and the isolation structure. An etching trench is formed between two adjacent isolation structures, including the capping layer, the semiconductor layer, and the buried oxide layer, exposing the silicon substrate. The sidewalls of the etching trench are either the sidewalls of the isolation structure or include both the sidewalls of the buried oxide layer and the sidewalls of the isolation structure. Semiconductor material is then selectively epitaxially grown in the etching trench to form the semiconductor structure. The capping layer is then removed. Since the sidewalls of the isolation structure and the buried oxide layer are not semiconductor material, semiconductor material is not easily grown on the sidewalls of the isolation structure and the buried oxide layer during selective epitaxial growth. Therefore, it is easier to grow a high-quality semiconductor structure upwards from the silicon substrate, avoiding the bulging problem caused by the overlap of upward and lateral semiconductor material growth during selective epitaxial growth, reducing process defects, and improving the process window and device yield.

[0048] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0049] refer to Figure 2 The diagram shown is a flowchart of a semiconductor device manufacturing method provided in an embodiment of this application. Figures 3-13 This is a schematic diagram of the structure of a semiconductor device during the manufacturing process. The method may include:

[0050] S01, providing a substrate structure, the substrate structure including a silicon substrate 101, a buried oxide layer 102 on the silicon substrate 101, and a semiconductor layer 103 on the buried oxide layer 102, reference. Figure 3 As shown.

[0051] In this embodiment of the application, the substrate structure may include a silicon substrate 101, a buried oxide layer 102 and a semiconductor layer 103, wherein the buried oxide layer 102 is located on the silicon substrate 101 and the semiconductor layer 103 is located on the buried oxide layer 102.

[0052] The buried oxide layer 102 serves as an isolation layer between the semiconductor layer 103 and the silicon substrate 101. The semiconductor layer 103 serves as a functional layer in subsequent devices, such as a channel layer. The semiconductor layer 103 can be made of silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-germanium carbide (SiGeC), or other semiconductor materials. For example, when the semiconductor layer 103 is made of silicon, the substrate structure can be called an FDSOI structure; when the semiconductor layer 103 is made of germanium, the substrate structure can be called a GOI structure. The buried oxide layer 102 can be made of silicon oxide, and its thickness can range from 50 to 200 nm. The thickness of the semiconductor layer 103 can range from 10 to 40 nm.

[0053] S02, an isolation structure 104 is formed in the substrate structure, the isolation structure 104 extending at least through the semiconductor layer 103.

[0054] In this embodiment, an isolation structure 104 can be formed in the substrate structure. The isolation structure 104 is used to isolate different devices, and the isolation structure 104 penetrates at least through the semiconductor layer 103. Specifically, the isolation structure 104 can be shallow trench isolation (STI). STI isolation is mostly used for MOS devices below 0.25 micrometers. The formation process of shallow trench isolation can be specifically as follows: a hard mask layer is formed on the substrate structure; the hard mask layer is patterned by photolithography and etching to expose the substrate structure of the isolation region; the substrate structure below is etched using the hard mask layer as a mask to form an isolation trench; a dielectric material is filled in the isolation trench to form the isolation structure 104; and the hard mask layer is removed. After forming the isolation structure 104 and before removing the hard mask layer, a chemical mechanical polishing (CMP) process can be used to planarize the device surface to form an active region and an isolation region that isolates the active region. (Refer to...) Figure 4 As shown.

[0055] The isolation structure 104 can be made of silicon oxide, and the hard mask layer can be silicon nitride, or a stack of pad oxide and silicon nitride. The hard mask layer can be formed using chemical vapor deposition (CVD). After the hard mask layer is formed, the surface of the hard mask layer can be oxidized to prevent nitrogen from diffusing into the photoresist and affecting the photoacid reaction at the bottom of the photoresist, thus preventing photoresist poisoning.

[0056] Patterning a hard mask layer can be achieved by forming photoresist on the hard mask layer, patterning the photoresist using photolithography, then using the patterned photoresist as a mask to etch the hard mask layer to transfer the photoresist pattern to the hard mask layer, and finally removing the photoresist. Etching of the hard mask layer can be performed using anisotropic dry etching.

[0057] Using a hard mask layer as a shield, etching is performed on the underlying substrate structure to form isolation trenches. Specifically, the semiconductor layer 103 and the buried oxide layer 102 can be etched to form isolation trenches that penetrate the semiconductor layer 103 and the buried oxide layer 102; alternatively, the semiconductor layer 103, the buried oxide layer 102, and the silicon substrate 101 can be etched to form isolation trenches that penetrate the semiconductor layer 103 and the buried oxide layer 102, and partially penetrate the substrate structure. In other words, the isolation trenches can extend to the upper surface of the silicon substrate 101, or the silicon substrate 101 can be partially etched.

[0058] The isolation structure 104 is formed by filling the isolation trench with a dielectric material. This can be achieved by chemical vapor deposition, which can include high aspect ratio plasma (HARP), high density plasma (HDP), or flowable chemical vapor deposition (FCVD).

[0059] Specifically, the isolation structure 104 can be Local Oxidation of Silicon (LOCOS). LOCOS isolation is mostly used in MOS devices larger than 0.35 micrometers. The formation of LOCOS can be specifically as follows: a hard mask layer is formed on the substrate structure; the hard mask layer is patterned by photolithography and etching to expose the substrate structure of the isolation region; the underlying semiconductor layer is completely oxidized by thermal oxidation using the hard mask layer as a mask to obtain the corresponding oxide layer, which serves as the isolation structure; the hard mask layer is then removed. (Refer to...) Figure 5 As shown, the oxide layer has a larger thickness than the unoxidized semiconductor layer 103. The oxide layer is located in the isolation region, and the unoxidized semiconductor layer 103 is located in the active region, thus forming the active region and the film layer in the isolation region that isolates the active region. Since the isolation structure 104 is obtained by oxidizing the semiconductor layer 103, the material of the isolation structure 104 is an oxide of the semiconductor layer 103, such as silicon oxide, germanium oxide, or silicon-germanium oxide.

[0060] S03, forming a cover layer 105 covering the semiconductor layer 103 and the isolation structure 104, reference. Figure 6 and Figure 7 As shown.

[0061] After forming the isolation structure 104, a cover layer 105 can be formed covering the semiconductor layer 103 and the isolation structure 104. The cover layer 105 can serve as a protective layer for the semiconductor layer 103 or as a mask layer for subsequent etching. The cover layer 105 can be silicon oxide or a stack of pad oxide and silicon nitride. The cover layer 105 can be formed using a chemical vapor deposition (CVD) process. When the cover layer 105 includes silicon nitride, the surface of the cover layer 105 can be oxidized to prevent nitrogen from diffusing into the photoresist and affecting the photoacid reaction at the bottom of the photoresist, thus preventing photoresist poisoning.

[0062] It is important to note that a pre-cleaning process is usually performed before subsequent selective epitaxial growth. This pre-cleaning typically employs a wet cleaning method. The dilute hydrofluoric acid (HF) used in this process can corrode and damage silicon oxide or silicon nitride. Therefore, the thickness of the deposited capping layer 105 needs to be matched with the time and amount of pre-cleaning used. For example, the thickness of the capping layer 105 can range from 300 to 600 nm.

[0063] When the isolation structure 104 is a shallow trench isolation, the semiconductor structure after forming the capping layer 105 can be referenced. Figure 6 As shown; when the isolation structure 104 is a local silicon oxide isolation, the semiconductor structure after forming the capping layer 105 can be referred to Figure 7 As shown.

[0064] S04, etching is performed on the capping layer 105, the semiconductor layer 103, and the buried oxide layer 102 to obtain the etching trench 106, reference. Figure 8 and Figure 9 As shown.

[0065] In this embodiment, the mixing region can be located between two adjacent isolation structures 104. After the cover layer 105 is formed, the cover layer 105, semiconductor layer 103 and buried oxide layer 102 of the mixing region can be etched to obtain an etching trench 106.

[0066] Specifically, photoresist can be formed on the capping layer 105, and then photolithography can be used to pattern the photoresist to define the mixing region. The patterned photoresist exposes the mixing region, which can be located between two adjacent isolation structures 104. Spin-coating a bottom anti-reflective coating (BARC) before the photoresist can suppress standing waves and reflection effects that occur during photolithography.

[0067] After forming the patterned photoresist, the capping layer 105, semiconductor layer 103, and buried oxide layer 102 can be removed sequentially to form an etching trench 106 in the mixed region. Specifically, the capping layer 105 can be etched using the patterned photoresist as a mask, and then the semiconductor layer 103 and buried oxide layer 102 can be etched using the capping layer 105 as a mask. The etching of the capping layer 105, semiconductor layer 103, and buried oxide layer 102 can be achieved using anisotropic dry etching. To ensure complete etching, a portion of the silicon substrate 101 can be over-etched (OE), with the over-etched silicon substrate 101 accounting for 5%-15% of the total etching thickness.

[0068] An etching trench 106, obtained by etching the capping layer 105, the semiconductor layer 103 and the buried oxide layer 102, exposes the silicon substrate 101, and the sidewalls of the etching trench 106 do not include the sidewalls of the semiconductor layer 103.

[0069] Specifically, when the isolation structure 104 is a shallow trench isolation, the isolation structure 104 extends through the silicon substrate 101, and the sidewalls of the etching trench 106 can be the sidewalls of the isolation structure 104, as shown in the reference. Figure 8 As shown. During the etching process of the capping layer 105, the semiconductor layer 103 and the buried oxide layer 102, the isolation structure 104 can also be partially etched, that is, the mixed region can also contain part of the isolation structure 104, and the etched isolation structure 104 is located in the mixed region.

[0070] Specifically, when the isolation structure 104 is a local silicon oxide isolation, the local silicon oxide isolation is only located on the upper layer of the buried oxide layer 102. Therefore, the sidewall of the etching trench 106 can include the sidewall of the buried oxide layer 102 and the sidewall of the isolation structure 104. In fact, the sidewall of the etching trench 106 includes the sidewall of the buried oxide layer 102 and the sidewall of the isolation structure 104 above the buried oxide layer 102. (Refer to...) Figure 9 As shown. During the etching process of the capping layer 105, the semiconductor layer 103 and the buried oxide layer 102, the isolation structure 104 can also be partially etched, that is, the mixed region can also contain part of the isolation structure 104, and the etched isolation structure 104 is located in the mixed region.

[0071] After forming the etching tank 106, photoresist and etching residue can be removed. Photoresist removal is divided into wet removal and dry removal. Wet removal mainly involves dissolving the photoresist in an organic solvent or using an inorganic solvent to oxidize the carbon elements in the photoresist into carbon dioxide, thereby removing the photoresist. Dry removal uses plasma etching to remove the photoresist. Wet and dry removal methods are often used in combination.

[0072] After removing photoresist and etching residues, selective pre-epitaxy cleaning can be performed. The purpose of pre-cleaning is mainly to remove impurity particles and the natural oxide layer on the surface of the bare silicon substrate 101, so as to provide a good growth environment for subsequent epitaxial growth. Dilute hydrofluoric acid is usually used for cleaning.

[0073] S05, selective epitaxial growth of semiconductor material is performed in etching trench 106 to form semiconductor structure 107, followed by removal of capping layer 105, referenced. Figure 10 , Figure 11 , Figure 12 and Figure 13 As shown.

[0074] In this embodiment, after forming the etching trench 106, semiconductor materials can be selectively epitaxially grown in the etching trench 106 to form a semiconductor structure 107. The formed semiconductor structure 107 can be flush with the semiconductor layer 103. The material of the semiconductor structure 107 can be the same as or different from the material of the semiconductor layer 103. The material of the semiconductor structure 107 can be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide germanium (SiGeC), or other semiconductor materials.

[0075] Selective epitaxy of semiconductor materials utilizes the principle of selective epitaxial growth. Semiconductor materials are easily grown on a silicon substrate 101, but not easily on films made of semiconductor oxides such as silicon dioxide or silicon nitride. The bottom of the etching trench 106 is the silicon substrate 101, and the sidewalls of the etching trench 106 are either sidewalls of an isolation structure or include sidewalls of a buried oxide layer and sidewalls of an isolation structure. Therefore, semiconductor materials grow faster at the bottom of the etching trench 106, but are less likely to grow on the sidewalls, causing the growth direction of the semiconductor material to be upward along the bottom of the etching trench 106. The principle of selective epitaxy is simultaneous growth and etching. Because the growth rate of semiconductor materials is faster on the substrate and slower on films made of semiconductor oxides, the semiconductor material grown on the semiconductor oxide film is etched away simultaneously with the growth of the semiconductor material.

[0076] When the isolation structure 104 is a shallow trench isolation, the isolation structure 104 extends to the silicon substrate 101, and all sidewalls of the semiconductor structure 107 are in contact with the sidewalls of the isolation structure 104. Figure 10 As shown. Since the isolation structures 104 on both sides of the semiconductor structure 107 may be etched, the isolation structures 104 on both sides of the semiconductor structure 107 can be asymmetric structures.

[0077] When the isolation structure 104 is a local silicon oxide isolation, the local silicon oxide isolation is only located on the upper layer of the buried oxide layer 102. A portion of the sidewall of the semiconductor structure 107 contacts the sidewall of the isolation structure 104, and another portion of the sidewall contacts the sidewall of the buried oxide layer 102. (Refer to...) Figure 11 As shown. Since the isolation structures 104 on both sides of the semiconductor structure 107 may be etched, the horizontal cross-section of the isolation structures 104 on both sides of the semiconductor structure 107 is smaller than that of the isolation structures 104 far away from the semiconductor structure 107. Therefore, the isolation structures 104 on both sides of the semiconductor structure 107 can be asymmetric structures.

[0078] When the material of the semiconductor structure 107 is silicon, the steps for selective epitaxy of the semiconductor material are as follows: After the semiconductor structure is pre-cleaned, the semiconductor structure is placed in the reaction chamber, H2 is introduced to bake and remove the natural oxide layer on the surface, and silicon sources (SiCl4, SiH2Cl2, SiHCl3, SiH4) are continuously introduced to react or pyrolyze with H2 to generate silicon atoms that are deposited on the silicon substrate 101 to grow an epitaxial layer.

[0079] After forming the semiconductor structure 107, the capping layer 105 can be removed. The capping layer 105 can be removed by wet etching. Specifically, a buffered oxide etch (BOE) can be used to remove the silicon oxide mask layer, and phosphoric acid (H3PO4) can be used to remove the silicon nitride mask layer.

[0080] The hybrid region is an essential structure in the FDSOI process, equivalent to semiconductor structure 107 in the FDSOI structure. It not only allows for the formation of passive devices in contact with the underlying silicon substrate 101, but also enables the extraction of the back gate for research and implementation of back gate modulation. Therefore, forming a high-quality hybrid region without bulge defects is crucial for the development and application of the FDSOI process. Furthermore, the isolation structure 104 is also indispensable in integrated circuit manufacturing; therefore, forming the isolation region first and then the hybrid region does not increase the manufacturing cost.

[0081] This application provides a method for manufacturing a semiconductor device. A substrate structure is provided, comprising a silicon substrate, a buried oxide layer on the silicon substrate, and a semiconductor layer on the buried oxide layer. An isolation structure is formed within the substrate structure, penetrating at least through the semiconductor layer to form a capping layer covering the semiconductor layer and the isolation structure. An etching trench is formed between two adjacent isolation structures, including the capping layer, the semiconductor layer, and the buried oxide layer, exposing the silicon substrate. The sidewalls of the etching trench are either the sidewalls of the isolation structure or include both the sidewalls of the buried oxide layer and the sidewalls of the isolation structure. Semiconductor material is then selectively epitaxially grown in the etching trench to form a semiconductor structure. The capping layer is then removed. Since the sidewalls of the isolation structure and the buried oxide layer are not semiconductor material, semiconductor material is not easily grown on these sidewalls during selective epitaxial growth. This facilitates the upward growth of a high-quality semiconductor structure from the silicon substrate, avoiding the bulging problem caused by the overlap of upward and lateral semiconductor material growth during selective epitaxial growth, reducing process defects, and improving process window and device yield.

[0082] Based on the semiconductor device manufacturing method provided in the embodiments of this application, the embodiments of this application also provide a semiconductor structure, referencing... Figure 12 and Figure 13 As shown, the semiconductor structure includes:

[0083] A substrate structure, the substrate structure comprising a silicon substrate, a buried oxide layer on the silicon substrate, and a semiconductor layer on the buried oxide layer;

[0084] An isolation structure in the substrate structure, the isolation structure extending at least through the semiconductor layer;

[0085] A semiconductor structure located between two adjacent isolation structures; the semiconductor structure extends through the semiconductor layer and the buried oxide layer; all sidewalls of the semiconductor structure are in contact with the sidewalls of the isolation structure, or a portion of the sidewalls of the semiconductor structure are in contact with the sidewalls of the isolation structure, and another portion of the sidewalls are in contact with the sidewalls of the buried oxide layer.

[0086] Optionally, the isolation structures on both sides of the semiconductor structure have a smaller horizontal cross-section compared to the isolation structures farther away from the semiconductor structure.

[0087] Optionally, the isolation structure is a local silicon oxide isolation or a shallow trench isolation.

[0088] When describing elements of various embodiments of this application, the articles “a,” “an,” “this,” and “described” are all intended to indicate that there are one or more elements. The words “comprising,” “including,” and “having” are inclusive and mean that there may be other elements in addition to those listed.

[0089] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0090] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate structure is provided, the substrate structure comprising a silicon substrate, a buried oxide layer on the silicon substrate, and a semiconductor layer on the buried oxide layer; An isolation structure is formed in the substrate structure; The isolation structure extends at least through the semiconductor layer; A cover layer is formed covering the semiconductor layer and the isolation structure; An etching trench is obtained by etching the capping layer, semiconductor layer and buried oxide layer between two adjacent isolation structures; The etched trench exposes the silicon substrate; The sidewall of the etching tank is the sidewall of the isolation structure, or the sidewall of the etching tank includes the sidewall of the buried oxide layer and the sidewall of the isolation structure; Semiconductor material is selectively epitaxially grown in the etching trench to form a semiconductor structure; the capping layer is then removed.

2. The method according to claim 1, characterized in that, The isolation structure is a local silicon oxide isolation, and the sidewalls of the etching trench include the sidewalls of the buried oxide layer and the sidewalls of the isolation structure above the buried oxide layer. Forming the isolation structure in the substrate structure includes: A portion of the semiconductor layer is thermally oxidized to form an isolation structure for the isolation semiconductor layer.

3. The method according to claim 2, characterized in that, The partial thermal oxidation of the semiconductor layer includes: A hard mask layer is formed on the substrate, and the hard mask layer is patterned to expose the substrate structure of the isolation region; An oxide layer is formed by thermal oxidation growth on the substrate structure using a patterned hard mask layer as a mask.

4. The method according to claim 1, characterized in that, The isolation structure is a shallow trench isolation, and the sidewall of the etching trench includes the sidewall of the isolation structure. The formation of the isolation structure in the substrate structure includes: The semiconductor layer, the buried oxide layer, and the substrate structure are etched to form an isolation trench that penetrates the semiconductor layer and the buried oxide layer and partially penetrates the substrate structure. The isolation trench is filled with a medium material to form an isolation structure.

5. The method according to claim 4, characterized in that, The etching of the semiconductor layer, the buried oxide layer, and the substrate structure between two adjacent isolation structures includes: A hard mask layer is formed on the substrate, and the hard mask layer is patterned to expose the substrate structure of the isolation region; The semiconductor layer, the buried oxide layer, and the substrate structure between two adjacent isolation structures are etched using a patterned hard mask layer as a mask.

6. The method according to claim 3 or 5, characterized in that, The material of the hard mask layer is silicon nitride, or the hard mask layer is a stack of a pad oxide layer and a silicon nitride layer.

7. The method according to any one of claims 1-5, characterized in that, When etching the capping layer, semiconductor layer and buried oxide layer between two adjacent isolation structures to obtain an etching trench, the isolation structure is also partially etched.

8. The method according to claim 4 or 5, characterized in that, The material of the buried oxide layer is silicon oxide, and the material of the isolation structure is silicon oxide.

9. A semiconductor device, characterized in that, include: A substrate structure, the substrate structure comprising a silicon substrate, a buried oxide layer on the silicon substrate, and a semiconductor layer on the buried oxide layer; An isolation structure in the substrate structure, the isolation structure extending at least through the semiconductor layer; A semiconductor structure located between two adjacent isolation structures; The semiconductor structure extends through the semiconductor layer and the buried oxide layer; The isolation structure penetrates the semiconductor layer and the buried oxide layer, and all sidewalls of the semiconductor structure are in contact with the sidewalls of the isolation structure; or, the isolation structure penetrates the semiconductor layer but not the buried oxide layer, and a portion of the sidewalls of the semiconductor structure are in contact with the sidewalls of the isolation structure and another portion of the sidewalls are in contact with the sidewalls of the buried oxide layer.

10. The semiconductor device according to claim 9, characterized in that, The isolation structure is either local silicon oxide isolation or shallow trench isolation.

Images