Method for manufacturing high-k metal gate

Abstract

The application discloses a manufacturing method of a high dielectric constant metal gate, which comprises the following steps: step one, depositing a high dielectric constant layer on a semiconductor substrate; step two, forming a first blocking layer; step three, depositing an amorphous silicon cap layer; step four, pretreatment, controlling the temperature and oxygen flow of the pretreatment to make the surface of the amorphous silicon cap layer oxidized; step five, performing a spike annealing treatment to absorb oxygen elements in the high dielectric constant layer, and the structure of the surface of the amorphous silicon cap layer being oxidized is used to inhibit the appearance of silicon nucleation and silicon crystal growth in the spike annealing treatment, so as to facilitate the removal of the subsequent amorphous silicon cap layer; and step six, removing the amorphous silicon cap layer without silicon residue and avoiding damaging the first blocking layer at the same time. The amorphous silicon cap layer on the top of the first blocking layer of the high dielectric constant layer is removed without silicon residue after absorbing oxygen, the first blocking layer can be avoided from being damaged, and the reliability of the device can be improved finally.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a method for manufacturing a high dielectric constant metal gate (HKMG). Background Technology

[0002] HKMG has a high dielectric (HK) gate dielectric layer and a metal gate (MG), hence it is commonly abbreviated as HKMG in the art. HKMG is typically used in process nodes below 28nm. As the critical dimensions of devices are further scaled down proportionally, fins are also used, and semiconductor devices are formed on the fins; therefore, semiconductor devices formed on fins are also called fin field-effect transistors (FinFETs). In FinFETs, the gate structure also uses HKMG.

[0003] Typically, in FinFET (Fin Field-Effect Transistor) technology, an amorphous silicon (α-Si) capping layer is deposited after the formation of a high-k dielectric layer. Oxygen is then absorbed from the HK layer through annealing. After removing the amorphous silicon capping layer, the metal gate is deposited. Usually, a TiN layer is formed after the high-k dielectric layer as a barrier layer, located at the bottom of the metal work function layer of the metal gate, and is also commonly referred to as the bottom barrier layer (BBM). However, in actual production, wet etching is typically used to remove the amorphous silicon capping layer. Residual silicon defects are easily formed during the removal of the annealed amorphous silicon. These residual defects can be removed by extending the wet etching time, but extending the wet etching time damages the TiN barrier layer, affecting device reliability. Conversely, not extending the wet etching time results in residual silicon defects. Therefore, removing residual amorphous silicon defects has become a key technical challenge in the formation of the HKMG in FinFETs. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing a high dielectric constant metal gate, which can avoid the generation of silicon residue when removing the amorphous silicon capping layer used to absorb oxygen from the high dielectric constant layer, thereby improving the reliability of the device.

[0005] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a high dielectric constant metal gate, comprising the following steps:

[0006] Step 1: Deposit a high dielectric constant layer on a semiconductor substrate.

[0007] Step 2: Form a first barrier layer on the high dielectric constant layer.

[0008] Step 3: Deposit an amorphous silicon capping layer.

[0009] Step four, pre-treating the amorphous silicon cap layer, in which oxygen is introduced, and the temperature of the pre-treatment and the flow rate of the oxygen are controlled to cause oxidation of the surface of the amorphous silicon cap layer.

[0010] Step five, the amorphous silicon cap layer is subjected to a spike annealing process to absorb oxygen elements in the high dielectric constant layer, and the spike annealing process is combined with the oxidized structure of the surface of the amorphous silicon cap layer to inhibit the occurrence of silicon nucleation and silicon crystal growth in the spike annealing process, so as to facilitate the subsequent removal of the amorphous silicon cap layer.

[0011] Step six, the amorphous silicon cap layer is removed without silicon residue while avoiding damaging the first barrier layer.

[0012] Further improvement is that in step one, before depositing the high dielectric constant layer, further comprising: forming an interface layer on the semiconductor substrate.

[0013] Further improvement is that the semiconductor substrate comprises a silicon substrate.

[0014] Further improvement is that the first barrier layer comprises a TiN layer.

[0015] Further improvement is that in step four, the pre-treatment adopts rapid thermal annealing.

[0016] Further improvement is that the temperature of the pre-treatment is 400-550°C, the flow rate of the oxygen is 0.05-0.5slm, and the time is 5-20s.

[0017] Further improvement is that in step five, the stable temperature of the spike annealing is 550-650°C, the peak temperature range is 950-1050°C, and the heating rate is 150-220°C / s.

[0018] Further improvement is that in the spike annealing, the cooling is achieved by placing the semiconductor substrate away from the heat source through Z-axis motion.

[0019] Further improvement is that in step six, a wet etching process is used to remove the amorphous silicon cap layer.

[0020] Further improvement is that after step six, further comprising the step of forming a metal gate.

[0021] Further improvement is that the material of the interface layer comprises silicon oxide.

[0022] Further improvement is that the material of the high dielectric constant layer is hafnium dioxide.

[0023] Further improvement is that the metal gate comprises a metal work function layer and a metal conductive material layer which are stacked in sequence.

[0024] Further improvement is that the material of the metal work function layer of the metal gate of the PMOS comprises TiN.

[0025] The material of the metal work function layer of the metal gate of the NMOS comprises TiAl.

[0026] Further improvement is that the material of the metal conductive material layer comprises aluminum.

[0027] The present application sets the annealing process for realizing oxygen absorption of the amorphous silicon cap layer from the high dielectric constant layer to be a spike annealing process and adds a pretreatment for oxidizing the surface of the amorphous silicon cap layer before the spike annealing process, so that the silicon nucleation and silicon crystal growth in the oxygen absorption process can be well inhibited, and the amorphous silicon cap layer can be removed without silicon residue and the removal process of the amorphous silicon cap layer will not damage the first barrier layer, so the quality of the high dielectric constant layer has a great influence on the reliability of the device in the device with the high dielectric constant metal gate, and the present application can realize oxygen absorption of the high dielectric constant layer, avoid silicon residue and avoid damage to the first barrier layer, which can greatly improve the reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0028] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0029] Figure 1 is a flow chart of the manufacturing method of the high dielectric constant metal gate of the embodiment of the present application;

[0030] Figures 2A-2D is a structural schematic diagram of the device in each step of the manufacturing method of the high dielectric constant metal gate of the embodiment of the present application. DETAILED DESCRIPTION

[0031] As Figure 1 shown, it is a flow chart of the manufacturing method of the high dielectric constant metal gate of the embodiment of the present application; as Figures 2A to 2D shown, it is a structural schematic diagram of the device in each step of the manufacturing method of the high dielectric constant metal gate of the embodiment of the present application; the manufacturing method of the high dielectric constant metal gate of the embodiment of the present application comprises the following steps:

[0032] Step one, as Figure 2A shown, a high dielectric constant layer 103 is deposited on a semiconductor substrate 101.

[0033] In the embodiment of the present application, before the high dielectric constant layer 103 is deposited, an interface layer 102 is formed on the semiconductor substrate 101. The material of the interface layer 102 comprises silicon oxide.

[0034] The material of the high dielectric constant layer 103 is hafnium dioxide.

[0035] The semiconductor substrate 101 comprises a silicon substrate. In some embodiments, when the formed device is a FinFET, a fin body is also formed on the semiconductor substrate 101, which is formed by patterning and etching the semiconductor substrate 101. The high dielectric constant metal gate covers the side surface and the top surface of the fin body. Figure 2A For the cross-sectional structure along the length direction of the fin body, along the length direction of the fin body, the fin body and the semiconductor substrate 101 are integrated; the top surface of the semiconductor substrate 101 outside the fin body is lowered.

[0036] Generally, the high dielectric constant metal gate is formed by a gate last process. Before the high dielectric constant layer 103 is formed, a step of removing a dummy gate structure is further included. The dummy gate structure is generally formed by stacking a dummy gate dielectric layer and a polysilicon dummy gate. The source region and the drain region of the FinFET are self-aligned with the dummy gate structure. Before the dummy gate structure is removed, a zeroth interlayer film is formed, and the top surface of the zeroth interlayer is leveled with the top surface of the dummy gate structure. Then, the dummy gate structure is removed. In the removal area of the dummy gate structure, the surface of the semiconductor substrate 101 is exposed and a gate trench surrounded by the zeroth interlayer film is formed. Figure 2A Only the cross-sectional structure at the gate trench is shown, and the structure of the zeroth interlayer film outside the gate trench is omitted.

[0037] Step two, as shown in the figure, a first barrier layer 104 is formed on the high dielectric constant layer 103. Figure 2A

[0038] In the embodiment of the present application, the first barrier layer 104 comprises a TiN layer.

[0039] Step three, as shown in the figure, an amorphous silicon cap layer 105 is deposited. Figure 2A

[0040] Step four, as shown in the figure, the amorphous silicon cap layer 105 is pretreated. In the pretreatment, oxygen is introduced, and the temperature of the pretreatment and the flow rate of the oxygen are controlled to cause oxidation of the surface of the amorphous silicon cap layer 105 and form a surface oxide layer 106. Figure 2B

[0041] In the embodiment of the present application, the pretreatment adopts rapid thermal annealing.​​​

[0042] The temperature of the pre-treatment is 400-550℃, the flow of the oxygen is 0.05-0.5slm, and the time is 5-20s.

[0043] From the above process conditions, the pre-treatment is a low-temperature small-oxygen annealing treatment. The surface oxide layer 106 formed has a good effect on inhibiting silicon nucleation.

[0044] Step five, as shown in the figure, the amorphous silicon cap layer 105 is subjected to a spike annealing treatment to absorb the oxygen elements in the high dielectric constant layer 103, Figure 2C The arrow line indicates that the oxygen elements are absorbed into the amorphous silicon cap layer 105. By using the spike annealing treatment combined with the structure that the surface of the amorphous silicon cap layer 105 is oxidized, silicon nucleation and silicon growth in the spike annealing treatment are inhibited, so as to facilitate the removal of the amorphous silicon cap layer 105 later. Figure 2C

[0045] In the embodiment of the present application, the stable temperature of the spike annealing is 550-650℃, the peak temperature range is 950-1050℃, and the heating rate is 150-220℃ / s.

[0046] The cooling in the spike annealing is realized by placing the semiconductor substrate 101 far away from the heat source by using the Z-axis motion mode.

[0047] On the basis of the surface oxide layer 106, the spike annealing can further inhibit silicon nucleation. After silicon nucleation and growth, the difficulty of silicon removal is increased, the control of the removal process of the amorphous silicon cap layer 105 becomes complex, and it is still difficult to completely remove silicon when the first barrier layer 104 is damaged. The embodiment of the present application can reduce the difficulty of removing the amorphous silicon cap layer 105 by inhibiting silicon nucleation and growth.

[0048] Step six, as shown in the figure, the amorphous silicon cap layer 105 is removed without silicon residue and while avoiding damaging the first barrier layer 104. Figure 2D

[0049] In the embodiment of the present application, the wet etching process is used to remove the amorphous silicon cap layer 105. Since silicon nucleation and growth are inhibited in step four, the control of the wet etching process for removing the amorphous silicon cap layer 105 is simple, and the amorphous silicon cap layer 105 can be removed without silicon residue before the first barrier layer 104 is damaged.

[0050] After step six, a step of forming a metal gate is further included. ​​

[0051] The metal gate includes a metal work function layer and a metal conductive material layer which are stacked in sequence.

[0052] The material of the metal work function layer of the metal gate of the PMOS includes TiN;

[0053] The material of the metal work function layer of the metal gate of the NMOS includes TiAl.

[0054] The material of the metal conductive material layer includes aluminum.

[0055] Generally, the top of the TiN layer of the first barrier layer 104 also forms a TaN layer, which is stacked together with the TiN layer and the Ta layer to form the bottom barrier layer.

[0056] Generally, a top barrier layer (TBM) is also formed between the metal work function layer and the metal conductive material layer to prevent the metal of the metal conductive material layer, such as Al, from diffusing into the metal work function layer.

[0057] After the metal gate is formed, a high dielectric constant metal gate is formed. Subsequently, a metal interconnection structure is formed, which includes multiple metal layers, multiple interlayer films and vias. The metal layers are separated by the corresponding interlayer films and connected by the vias through the interlayer films.

[0058] The embodiment of the present application sets the annealing process for realizing the oxygen absorption of the amorphous silicon cap layer 105 from the high dielectric constant layer 103 as a spike annealing process and adds a pre-process for oxidizing the surface of the amorphous silicon cap layer 105 before the spike annealing process, which can well inhibit the silicon nucleation and silicon crystal growth during the oxygen absorption process, so as to realize the silicon residue-free removal of the amorphous silicon cap layer 105 and ensure that the removal process of the amorphous silicon cap layer 105 will not damage the first barrier layer 104. Therefore, since the quality of the high dielectric constant layer 103 has a great influence on the reliability of the device in the device using the high dielectric constant metal gate, the embodiment of the present application can realize the oxygen absorption of the high dielectric constant layer 103, avoid the silicon residue and avoid the damage to the first barrier layer 104, which can greatly improve the reliability of the device.

[0059] The present application has been described in detail by specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can make many modifications and improvements without departing from the principle of the present application, which should be considered as the protection scope of the present application.

Claims

1. A method of manufacturing a high-k metal gate, comprising: The method comprises the following steps: Step one, depositing a high dielectric constant layer on a semiconductor substrate; Step two, forming a first barrier layer on the high dielectric constant layer; Step three, depositing an amorphous silicon cap layer; Step four, pre-treating the amorphous silicon cap layer, wherein oxygen is introduced, and the temperature of the pre-treatment and the flow rate of the oxygen are controlled to cause oxidation of the surface of the amorphous silicon cap layer; Step five, performing a spike annealing process on the amorphous silicon cap layer to absorb oxygen in the high dielectric constant layer, and the spike annealing process is combined with the structure of the surface of the amorphous silicon cap layer being oxidized to inhibit silicon nucleation and silicon crystal growth during the spike annealing process, so as to facilitate subsequent removal of the amorphous silicon cap layer; Step six, removing the amorphous silicon cap layer without leaving silicon residues while avoiding damaging the first barrier layer.

2. The method of manufacturing a high dielectric constant metal gate of claim 1, wherein: In step one, before depositing the high dielectric constant layer, an interface layer is formed on the semiconductor substrate.

3. The method of claim 1, wherein: The semiconductor substrate comprises a silicon substrate.

4. The method of claim 1, wherein: The first barrier layer comprises a TiN layer.

5. The method of claim 1, wherein: In step four, the pre-treatment adopts rapid thermal annealing.

6. The method of claim 5, wherein: The temperature of the pre-treatment is 400-550°C, the flow rate of the oxygen is 0.05-0.5 slm, and the time is 5-20 s.

7. The method of claim 5, wherein: In step five, the stable temperature of the spike annealing is 550-650°C, the peak temperature ranges from 950°C to 1050°C, and the heating rate is 150-220°C / s.

8. The method of claim 7, wherein: In the spike annealing, the semiconductor substrate is placed away from the heat source by adopting a Z-axis motion mode to achieve cooling.

9. The method of claim 1, wherein: In step six, a wet etching process is adopted to remove the amorphous silicon cap layer.

10. The method for manufacturing a high dielectric constant metal gate as described in claim 1, characterized in that: After step six, a step of forming a metal gate is further included.

11. The method for manufacturing a high dielectric constant metal gate as described in claim 2, characterized in that: The material of the interface layer comprises silicon oxide.

12. The method of claim 1, wherein: The material of the high dielectric constant layer is hafnium dioxide.

13. The method for manufacturing a high dielectric constant metal gate as described in claim 10, characterized in that: The metal gate comprises a metal work function layer and a metal conductive material layer which are stacked in sequence.

14. The method of claim 13, wherein: The material of the metal work function layer of the metal gate of PMOS comprises TiN; The material of the metal work function layer of the metal gate of NMOS comprises TiAl.

15. The method of claim 13, wherein: The material of the metal conductive material layer comprises aluminum.

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