Panel-based chipset system and method of manufacturing a chipset system

Abstract

This disclosure provides a panel-based chipset system and a method for manufacturing the chipset system. The panel-based chipset system includes a panel, multiple logic cores, multiple memory chips, and multiple input / output chips. The panel has a rectangular first surface. The multiple logic cores are disposed on the first surface of the panel and arranged in an array. The multiple memory chips are disposed on the first surface of the panel and are respectively disposed adjacent to each side of the multiple logic cores. The multiple input / output chips are disposed on the first surface of the panel and are disposed adjacent to the four sides of the first surface and surrounding the multiple logic cores and the multiple memory chips. The panel-based chipset system and the method for manufacturing the chipset system disclosed herein can integrate a high number and high density of chipsets.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to a panel-based chipset system and a method for manufacturing the chipset system. Background Technology

[0002] Since current artificial intelligence (AI) computing and high-performance computing (HPC) require the simultaneous use of more and more logic cores and access to high-bandwidth and high-density memory, how to integrate a large number of logic cores and high-density memory chips while also achieving good heat dissipation is the main research direction in this field. Summary of the Invention

[0003] This disclosure relates to a panel-based chipset system and a method for manufacturing the chipset system, which can integrate a high number and high density of chipsets.

[0004] According to embodiments of this disclosure, the panel-based chipset system includes a panel, a plurality of logic cores, a plurality of memory chips, and a plurality of input / output chips. The panel has a rectangular first surface. The plurality of logic cores are disposed on the first surface of the panel and arranged in an array. The plurality of memory chips are disposed on the first surface of the panel and are respectively disposed adjacent to each side of the plurality of logic cores. The plurality of input / output chips are disposed on the first surface of the panel and are disposed adjacent to the four sides of the first surface and surrounding the plurality of logic cores and the plurality of memory chips.

[0005] According to embodiments of this disclosure, a method for manufacturing a panel-based chipset system includes the following steps: forming a circuit layer on a rectangular substrate; forming a plurality of logic cores, a plurality of memory chips, and a plurality of input / output chips on the circuit layer, wherein the plurality of logic cores are arranged in an array, the plurality of memory chips are respectively disposed adjacent to each side of the plurality of logic cores, and the plurality of data exchange chips are disposed adjacent to the four sides of the rectangular substrate and surrounding the plurality of logic cores and the plurality of memory chips; encapsulating the plurality of logic cores, the plurality of memory chips, and the plurality of data exchange chips to form an encapsulation layer; forming a panel on the encapsulation layer, wherein the panel is rectangular; and removing the rectangular substrate.

[0006] Based on the above, the panel-based chipset system and the manufacturing method of the chipset system disclosed herein can achieve a chipset with a high number of chips and a high chip density by integrating a high-performance computing system on a rectangular first surface of the panel.

[0007] To make the above-described features and advantages of this disclosure more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a side view of a panel-based chipset system according to an embodiment of the present disclosure;

[0009] Figure 2 This is a top view of the encapsulation layer according to an embodiment of the present disclosure;

[0010] Figure 3 This is a flowchart of a method for manufacturing a panel-based chipset system according to an embodiment of the present disclosure;

[0011] Figures 4A to 4F This is a schematic diagram illustrating the manufacturing process of a panel-based chipset system according to an embodiment of this disclosure;

[0012] Figure 5 This is a flowchart of a method for manufacturing a panel-based chipset system according to another embodiment of the present disclosure;

[0013] Figures 6A to 6C This is a schematic diagram illustrating the manufacturing process of a panel-based chipset system according to another embodiment of this disclosure.

[0014] Explanation of reference numerals in the attached figures

[0015] 100: Chipset system;

[0016] 110: Heat dissipation layer;

[0017] 120: Panel;

[0018] 130: Encapsulation layer;

[0019] 131: Logical core;

[0020] 132: Memory chip;

[0021] 133: Input / output chip;

[0022] 134: Data exchange chip;

[0023] 135: Sealing;

[0024] 136: First micro-copper pillar;

[0025] 137: Solder;

[0026] 140: Line layer;

[0027] 141: Second micro-copper pillar;

[0028] 142: Bridge chip;

[0029] 143_1~143_3: Fill layer;

[0030] 144: First solder ball;

[0031] 151, 152: Voltage regulation module;

[0032] 153: Multiple input / output connectors;

[0033] 154: Second solder ball;

[0034] 160: Circuit board;

[0035] 170: Rectangular carrier plate;

[0036] D1: First direction;

[0037] D2: Second direction;

[0038] D3: third direction;

[0039] S1: First surface;

[0040] S2: Second surface;

[0041] S310~S350, S510~S540: Steps. Detailed Implementation

[0042] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0043] Figure 1 This is a side view of a panel-based chipset system according to an embodiment of the present disclosure. Figure 2 This is a top view of the encapsulation layer according to an embodiment of this disclosure. (See reference...) Figure 1 as well as Figure 2The chipset system 100 includes a heat dissipation layer 110, a panel 120, an encapsulation layer 130, a circuit layer 140, multiple voltage regulator modules 151 and 152, multiple input / output connectors 153, and a circuit board 160. In this embodiment, the panel 120 has a rectangular first surface S1. The first surface S1 is parallel to a plane extending along a first direction D1 and a second direction D2, and the first surface S1 faces a third direction D3, wherein the first direction D1, the second direction D2, and the third direction D3 are perpendicular to each other. In this embodiment, the encapsulation layer 130 may include multiple logic cores 131, multiple memory chips 132, multiple input / output chips 133, and multiple data exchange chips 134 disposed on the first surface S1 of the panel 120, and encapsulated as the encapsulation layer 130 by a mold 135. Figure 1 as well as Figure 2 Multiple logic cores 131 and multiple data exchange chips 134 are arranged in an array, with the data exchange chips 134 and the logic cores 131 interleaved. Multiple memory chips 132 are disposed adjacent to each side of the multiple logic cores 131. Multiple input / output chips 133 are disposed adjacent to the four sides of the first surface S1 and surrounding the multiple logic cores 131 and the multiple memory chips 132. In this embodiment, the encapsulation layer 130 also includes multiple first micro copper pillars 136 (or micro copper rods) to connect (electrically connect) the multiple logic cores 131, the multiple memory chips 132, the multiple input / output chips 133, and the multiple data exchange chips 134.

[0044] In this embodiment, the plurality of logic cores 131, the plurality of memory chips 132, the plurality of input / output chips 133, and the plurality of data exchange chips 134 may each include a device layer and a substrate layer. The device layer may include relevant functional circuits, such as logic circuits, memory circuits, input / output circuits, and data exchange circuits. The substrate layer may be made of silicon (Si) substrate, and the device layer may be made of silicon dioxide (SiO2).

[0045] In this embodiment, panel 120 can be a cold plate. Panel 120 can be a metal plate, and the material can be, for example, copper or stainless steel. The second surface S2 of panel 120 has a heat dissipation layer 110. In this way, heat dissipation layer 110 and panel 120 can realize the heat dissipation function of chipset system 100. In one embodiment, panel 120 can be, for example, a rectangular panel with a length and width of 500 mm, or it can be a rectangular panel of any other size.

[0046] In this embodiment, the circuit layer 140 may be disposed on the package layer 130. The circuit layer 140 may be a redistribution layer (RDL) formed using fan-out packaging technology, and may be filled with the same or different filler materials (e.g., organic resin) to form filling layers 143_1 to 143_3. The circuit layer 140 may include a plurality of second micro copper pillars 141 and a plurality of bridge dies 142. At least a portion of the plurality of second micro copper pillars 141 may penetrate the filling layers 143_1 to 143_3, and at least another portion of the plurality of second micro copper pillars 141 may penetrate only one of the filling layers 143_1 to 143_3, and this disclosure is not limiting.

[0047] In this embodiment, the actual configuration of the plurality of second micro-copper pillars 141 can be determined according to the electrical connection requirements between actual circuit elements, and the circuit layer 140 may also include internal circuitry and / or internal (copper) traces to enable interconnection of a portion of the plurality of second micro-copper pillars 141. In this embodiment, a plurality of logic cores 131, a plurality of memory chips 132, a plurality of input / output chips 133, and a plurality of data exchange chips 134 are connected to a plurality of second micro-copper pillars 141 disposed in the circuit layer 140 via a plurality of first micro-copper pillars 136 in the encapsulation layer 130, wherein the plurality of first micro-copper pillars 136 and the plurality of second micro-copper pillars 141 are connected by solder (e.g., solder) 137 to form microbumps (μbump).

[0048] In this embodiment, multiple bridging chips 142 may be disposed, for example, in the fill layer 143_2 and connected to the first portions of multiple second micro copper pillars 141. Each of the multiple bridging chips 142 can bridge at least one of multiple logic cores 131 and at least one of multiple memory chips 132 through the first portions of the multiple second micro copper pillars 141 and the first portions of the multiple first micro copper pillars 136, respectively, to provide data transmission and bridging functions between the logic cores and the memory chips. In this embodiment, each of the multiple bridging chips 142 includes fine internal traces, and the fineness of its traces may be higher than that of the (copper) traces inside the circuit layer 140.

[0049] In this embodiment, multiple data exchange chips 134 can be connected to multiple logic cores 131 and multiple memory chips 132 through lines in the line layer 140 and / or multiple bridge chips 142 to provide data routing functions between multiple logic cores 131 and multiple memory chips 132.

[0050] In this embodiment, multiple voltage regulation modules 151 and 152 and multiple input / output connectors 153 are disposed on the line layer 140. Second portions of multiple second micro-copper pillars 141 are connected to the multiple voltage regulation modules 151 and 152 via portions of multiple first solder balls 144, and third portions of the multiple second micro-copper pillars 141 are connected to the multiple input / output connectors 153 via other portions of the multiple first solder balls 144. The multiple first solder balls 144 can be formed using Ball Grid Array (BGA) packaging technology. In this embodiment, the multiple voltage regulation modules 151 can be electrically connected to multiple logic cores 131 via the first solder balls 144, second micro-copper pillars 141, and first micro-copper pillars 136 to provide power supply voltage to the multiple logic cores 131. The multiple voltage regulation modules 152 can be electrically connected to multiple memory chips 132 via the first solder balls 144, second micro-copper pillars 141, and first micro-copper pillars 136 to provide power supply voltage to the multiple memory chips 132. Multiple input / output connectors 153 can be electrically connected to multiple input / output chips 133 via first solder balls 144, second micro copper pillars 141 and first micro copper pillars 136, for example, to transmit data, voltage or current and other related signals to external circuits.

[0051] In this embodiment, a circuit board 160 is disposed on multiple voltage regulation modules 151 and 152, and is connected to the multiple voltage regulation modules 151 and 152 via multiple second solder balls 154, so that the multiple voltage regulation modules 151 and 152 can be connected to external circuits through the circuit board 160. The multiple second solder balls 154 can be formed using ball grid array packaging process technology. The circuit board 160 may, for example, include power control logic for supplying power (e.g., high-voltage input current) to the multiple voltage regulation modules 151 and 152.

[0052] Figure 3 This is a flowchart of a method for manufacturing a panel-based chipset system according to an embodiment of the present disclosure. Figures 4A to 4F This is a schematic diagram illustrating the manufacturing process of a panel-based chipset system according to an embodiment of this disclosure. (Reference) Figure 3 as well as Figures 4A to 4F The manufacturing method of the chipset system disclosed herein can be implemented by the following steps S310 to S350, and the material of each layer, the connection relationship and the circuit element features of this embodiment can be referred to the above. Figure 1 and Figure 2 Description of the embodiment. In step S310, a circuit layer 140 is formed on the rectangular carrier board 170. (As...) Figure 4A As shown, multiple traces of the redistribution layer and filler material can be formed on the rectangular substrate 170 first, and a filler layer 143_3 is formed. Next, as... Figure 4BAs shown, multiple bridging chips 142 are formed on the fill layer 143_3 to connect multiple traces of the fill layer 143_3, and multiple additional traces and filler material are formed on the multiple bridging chips 142. A fill layer 143_2 is formed, and the surface of the fill layer 143_2 is polished. Next, as... Figure 4C As shown, a second micro copper pillar 141 is formed on the redistribution layer and a filler material is placed on the filler layer 143_2 to connect multiple traces and form the filler layer 143_1.

[0053] In step S320, multiple logic cores 131, multiple memory chips 132, multiple input / output chips 133, and multiple data exchange chips (not shown) are formed (or attached) on the line layer 140. Figure 4D As shown, multiple logic cores 131, multiple memory chips 132, multiple input / output chips 133, and multiple data exchange chips can be pre-prepared, and copper pillars of the first micro copper pillar 136 can be pre-formed on the multiple logic cores 131, multiple memory chips 132, multiple input / output chips 133, and multiple data exchange chips, and the second micro copper pillar 141 and the first micro copper pillar 136 are joined by multiple solders 137.

[0054] In step S330, multiple logic cores 131, multiple memory chips 132, multiple data exchange chips 133, and multiple data exchange chips (not shown) are encapsulated to form an encapsulation layer 130. For example... Figure 4E As shown, encapsulant is filled between multiple logic cores 131, multiple memory chips 132, multiple input / output chips 133, and multiple data exchange chips (not shown) to form an encapsulation layer 130.

[0055] In step S340, panel 120 is formed (or bonded) on encapsulation layer 130. In step S350, rectangular carrier plate 170 is removed. Figure 4F As shown, panel 120 is first bonded to encapsulation layer 130, and then heat dissipation layer 110 is formed on panel 120. In this way, heat dissipation layer 110, encapsulation layer 130 and circuit layer 140 can be fixed on panel 120, so rectangular carrier board 170 can be removed.

[0056] Figure 5 This is a flowchart of a method for manufacturing a panel-based chipset system according to another embodiment of the present disclosure. Figures 6A to 6C This is a schematic diagram illustrating the manufacturing process of a panel-based chipset system according to another embodiment of this disclosure. (See reference) Figure 5 as well as Figures 6A to 6C , Figure 4FAfter removing the rectangular carrier 170 of the chipset system shown, and inverting the chipset system, the chipset system can be further fabricated by the following steps S510 to S540. The materials, connections, and circuit element features of each layer in this embodiment can be referred to the above. Figure 1 and Figure 2 Description of the embodiment. In step S510, a plurality of first solder balls 144 are formed on the second portion of a plurality of second micro-copper pillars 141, and another plurality of first solder balls 144 are formed on the third portion of a plurality of second micro-copper pillars 141. Figure 6A As shown, in Figure 4F After the rectangular carrier board 170 shown is removed, a plurality of first solder balls 144 are formed on the circuit layer 140 and connected to a plurality of corresponding second micro copper pillars 141.

[0057] In step S520, multiple voltage regulation modules 151 and 152 are formed (or bonded) on the circuit layer 140 and connected to the second portions of multiple second micro-copper pillars 141 via multiple first solder balls 144. In step S530, multiple input / output connectors 153 are formed on the circuit layer 140 and connected to the third portions of multiple second micro-copper pillars 141 via another multiple first solder balls 144. Figure 6B As shown, multiple voltage regulation modules 151, 152 and multiple input / output connectors 153 can be pre-prepared and bonded to the line layer 140 by multiple first solder balls 144. Multiple second solder balls 154 can be formed on the multiple voltage regulation modules 151, 152.

[0058] In step S540, a circuit board 160 is formed (or bonded) on multiple voltage regulation modules 151, 152, and connected to the multiple voltage regulation modules 151, 152 via multiple second solder balls 154. Figure 6C As shown, the circuit board 160 connects multiple voltage regulation modules 151 and 152 via multiple second solder balls 154, so that the internal circuitry and components of the circuit board 160 can be electrically connected to the multiple voltage regulation modules 151 and 152. In this way, the manufacturing method of this embodiment can complete the manufacturing of... Figure 1 and Figure 2 The chipset system 100 shown.

[0059] In summary, the panel-based chipset system and its manufacturing method disclosed herein effectively integrate a high number and high density of multiple logic cores and memory chips on a panel to achieve a high-performance computing system. The panel-based chipset system and its manufacturing method directly support multiple logic cores and memory chips on the panel, thus providing excellent heat dissipation; the panel can even utilize an immersion liquid cooling system for heat dissipation. Furthermore, the panel-based chipset system and its manufacturing method can utilize multiple bridging chips to achieve high-density internal interconnect (circuit) density.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A panel-based chipset system, comprising: include: A panel, wherein the panel has a rectangular first surface; An encapsulation layer is disposed on one side of the panel and includes multiple logic cores, multiple memory chips, multiple input / output chips, and multiple data exchange chips that are encapsulated by the same sealant and in contact with the sealant. A circuit layer is disposed on the side of the encapsulation layer away from the panel; as well as A bridging chip, embedded in the circuit layer, bridges at least one of the plurality of logic cores and at least one of the plurality of memory chips. in, The plurality of logic cores are disposed on the first surface of the panel and arranged in an array; The plurality of memory chips are disposed on the first surface of the panel and are respectively disposed adjacent to each side of the plurality of logic cores; The plurality of input / output chips are disposed on the first surface of the panel, and are arranged adjacent to the four sides of the first surface and surrounding the plurality of logic cores and the plurality of memory chips; and The plurality of data exchange chips are disposed on the first surface of the panel and arranged in an array.

2. The chipset system according to claim 1, characterized in that, The multiple data exchange chips and the multiple logic cores are interleaved.

3. The chipset system according to claim 1, characterized in that, A heat dissipation layer is provided on the second surface of the panel, wherein the second surface is opposite to the first surface.

4. The chipset system according to claim 3, characterized in that, The plurality of logic cores, the plurality of memory chips, the plurality of input / output chips, and the plurality of data exchange chips are connected to the plurality of second micro-copper pillars disposed in the circuit layer through the plurality of first micro-copper pillars in the packaging layer. The plurality of first micro copper pillars and the plurality of second micro copper pillars are connected by solder.

5. The chipset system according to claim 4, characterized in that, The first microcopper pillar and the second microcopper pillar, which are electrically connected to at least one of the bridge chip, the plurality of logic cores, and the plurality of memory chips, are respectively the first part of the plurality of first microcopper pillars and the first part of the plurality of second microcopper pillars, and the first part of the plurality of first microcopper pillars and the first part of the plurality of second microcopper pillars are connected to each other.

6. The chipset system according to claim 4, characterized in that, The line layer is a rewiring layer.

7. The chipset system according to claim 4, characterized in that, Also includes: Multiple voltage regulation modules are mounted on the circuit layer. The second micro-copper pillars that electrically connect the multiple voltage regulation modules, the multiple logic cores, and the multiple memory chips are the second part of the multiple second micro-copper pillars, and the second part of the multiple second micro-copper pillars are connected to the multiple voltage regulation modules through the traces of the circuit layer and multiple first solder balls.

8. The chipset system according to claim 7, characterized in that, Also includes: A circuit board is disposed on the plurality of voltage regulation modules and is connected to the plurality of voltage regulation modules through a plurality of second solder balls.

9. The chipset system according to claim 4, characterized in that, Also includes: Multiple input / output connectors are disposed on the line layer. The second micro copper pillar that electrically connects the plurality of input / output connectors and the plurality of input / output chips is the third part of the plurality of second micro copper pillars, and the third part of the plurality of second micro copper pillars is connected to the plurality of input / output connectors through the traces of the circuit layer and the plurality of first solder balls.

10. The chipset system according to claim 1, characterized in that, The panel is a metal plate.

11. A method for manufacturing a panel-based chipset system, characterized in that, include: A circuit layer is formed on a rectangular substrate, and a bridging chip is formed in the circuit layer; Multiple logic cores, multiple memory chips, multiple input / output chips, and multiple data exchange chips are formed on the circuit layer. The multiple logic cores are arranged in an array. The multiple memory chips are respectively disposed adjacent to each side of the multiple logic cores. The multiple input / output chips are disposed adjacent to the four sides of the rectangular carrier board and surround the multiple logic cores and the multiple memory chips. The multiple data exchange chips are arranged in an array. The bridging chip bridges at least one of the multiple logic cores and at least one of the multiple memory chips. The multiple logic cores, multiple memory chips, multiple input / output chips, and multiple data exchange chips are encapsulated using the same encapsulant to form an encapsulation layer; A panel is formed on the encapsulation layer, wherein the panel is rectangular; as well as Remove the rectangular carrier plate.

12. The manufacturing method according to claim 11, characterized in that, The multiple data exchange chips and the multiple logic cores are interleaved.

13. The manufacturing method according to claim 11, characterized in that, Also includes: A heat dissipation layer is formed on the second surface of the panel, wherein the encapsulation layer is located on the first surface of the panel, and the second surface is opposite to the first surface.

14. The manufacturing method according to claim 11, characterized in that, The steps of forming the circuit layer on the rectangular carrier include: Multiple second micro-copper pillars are formed in the circuit layer; The steps for forming the encapsulation layer include: Multiple first micro copper pillars are formed in the encapsulation layer; and The plurality of first micro copper pillars and the plurality of second micro copper pillars are connected by solder.

15. The manufacturing method according to claim 14, characterized in that, The bridging chip is formed in the circuit layer. The first microcopper pillar and the second microcopper pillar, which are electrically connected to at least one of the bridge chip, the plurality of logic cores, and the plurality of memory chips, are respectively the first portion of the plurality of first microcopper pillars and the first portion of the plurality of second microcopper pillars, and the first portion of the plurality of first microcopper pillars and the first portion of the plurality of second microcopper pillars are connected to each other.

16. The manufacturing method according to claim 14, characterized in that, The line layer is a rewiring layer.

17. The manufacturing method according to claim 14, characterized in that, Also includes: Multiple voltage regulation modules are formed on the circuit layer, wherein the second micro copper pillars that electrically connect the multiple voltage regulation modules to the multiple logic cores and the multiple memory chips are the second portions of the multiple second micro copper pillars, and the multiple voltage regulation modules are connected to the second portions of the multiple second micro copper pillars through multiple first solder balls and the traces of the circuit layer.

18. The manufacturing method according to claim 17, characterized in that, Also includes: A circuit board is formed on the plurality of voltage regulation modules and connected to the plurality of voltage regulation modules via a plurality of second solder balls.

19. The manufacturing method according to claim 14, characterized in that, Also includes: Multiple input / output connectors are formed on the circuit layer, wherein the second micro-copper pillars that electrically connect the multiple input / output connectors and the multiple input / output chips are the third part of the multiple second micro-copper pillars, and the multiple input / output connectors are connected to the third part of the multiple second micro-copper pillars through multiple first solder balls and traces of the circuit layer.

20. The manufacturing method according to claim 11, characterized in that, The panel is a metal plate.

Images