A method for improving HDP filling defects through STI etching process

Abstract

The present invention provides a method for improving HDP filling defects through an STI etching process. The method comprises providing a wafer having pixel areas and logic areas evenly distributed thereon, and dividing the surface of the wafer into first to fourth quadrants. The second quadrant of the wafer is placed in an etching chamber facing the cantilever beam of the etching machine. The wafer is etched to form STI regions of equal depth in the pixel areas and logic areas of the first to fourth quadrants. The wafer is removed from the etching machine, and the STI regions of the pixel areas are covered with photoresist. The wafer is then re-placed on an electrostatic chuck of the etching chamber, with any quadrant of the wafer other than the second quadrant facing the cantilever beam. The STI regions of the logic areas of the first to fourth quadrants of the wafer are further etched to form deep STI regions. The present invention improves in-plane depth uniformity by matching the angles of the STI etching and deep STI etching, or by rotating the angles of the STI and deep STI etching, thereby preventing voids in the HDP filling.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving HDP filling defects through an STI etching process. Background Art

[0002] Due to process requirements, the shallow trench isolation (STI) depths of the pixel and logic areas in Huali's current CIS product process flow are different. Etching is done in two steps: the first step is to simultaneously etch the STI in the pixel and logical areas. The second step is to block the pixel area with photoresist before continuing to etch the STI in the logical area. Because the STI in the logical area is deeper and the filling process uses high-density plasma (HDP), void defects will appear at certain locations along the edge. This is mainly because the STI depth in these locations is deeper than at other locations. The deeper STI depth in these locations is mainly due to the cantilever beam position of the Kiyo-type mechanical design of the etching machine. Currently, both the STI and HDP processes in the process select machines with better process capabilities to pass through, thereby reducing void defects. However, with the increase in product input and the need for machine maintenance, this control method can no longer meet the needs of running products.

[0003] Therefore, it is necessary to propose a new method to solve the above problems. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for improving HDP filling defects through an STI etching process, which is used to solve the problem in the prior art that the STI etching of the logic area at the edge of the wafer is deeper due to the cantilever position of the etching machine, thereby causing voids in the HDP filling.

[0005] To achieve the above-mentioned and other related objectives, the present invention provides a method for improving HDP filling defects through an STI etching process, the method comprising at least:

[0006] Step 1: providing a wafer, wherein the wafer has pixel areas and logic areas evenly distributed thereon;

[0007] Step 2: Dividing the surface of the wafer into first to fourth quadrants with the center of the wafer as the origin of a rectangular coordinate system;

[0008] Step 3: placing the wafer on an electrostatic chuck of an etching chamber of an etching machine, and aligning the second quadrant of the wafer with the cantilever beam of the etching machine;

[0009] Step 4: performing STI etching on the pixel regions and logic regions in the first to fourth quadrants of the wafer simultaneously, forming STI regions of the same depth in the pixel regions and logic regions in the first to fourth quadrants, respectively, wherein the depth of the STI regions is H;

[0010] Step 5: moving the wafer out of the etching machine, and covering the STI regions of the pixel regions in the first to fourth quadrants of the wafer with photoresist;

[0011] Step 6: Re-place the wafer on the electrostatic chuck of the etching chamber of the etching machine, and place any one of the other three quadrants of the wafer except the second quadrant facing the cantilever beam of the etching machine;

[0012] Step 7: Continue etching the STI regions of the logic areas in the first to fourth quadrants of the wafer to form deep STI regions, where the depth of the deep STI regions is H+h.

[0013] Preferably, in step six, the fourth quadrant of the wafer is placed facing the cantilever beam of the etching machine.

[0014] The present invention also provides a method for improving HDP filling defects through an STI etching process, the method at least comprising:

[0015] Step 1: providing a wafer, wherein the wafer has pixel areas and logic areas evenly distributed thereon;

[0016] Step 2: Dividing the surface of the wafer into first to fourth quadrants with the center of the wafer as the origin of a rectangular coordinate system;

[0017] Step 3: placing the wafer on the electrostatic chuck of the etching chamber of the etching machine, and aligning the second quadrant of the wafer with the cantilever beam of the etching machine; then, performing STI etching on the pixel areas and logic areas of the first to fourth quadrants of the wafer simultaneously, forming STI regions with a depth of 1 / 4H in the pixel areas and logic areas of the first to fourth quadrants respectively;

[0018] Step 4: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the first quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the pixel regions and logic regions in the first to fourth quadrants of the wafer are then simultaneously etched to a depth of 2 / 4H.

[0019] Step 5: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the fourth quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the pixel regions and logic regions in the first to fourth quadrants of the wafer are then simultaneously etched to a depth of 3 / 4H.

[0020] Step 6: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the third quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the pixel and logic regions of the first to fourth quadrants of the wafer are then simultaneously etched to a depth of H.

[0021] Step 7: moving the wafer out of the etching machine, and covering the STI regions of the pixel regions in the first to fourth quadrants of the wafer with photoresist;

[0022] Step 8: Place the wafer on the electrostatic chuck of the etching chamber of the etching machine, and align the second quadrant of the wafer with the cantilever beam of the etching machine; then continue etching the STI regions of the logic regions of the first to fourth quadrants of the wafer to a depth of H+1 / 4h;

[0023] Step 9: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the first quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the logic regions in the first to fourth quadrants of the wafer are then continuously etched to a depth of H+2 / 4h.

[0024] Step 10: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the fourth quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the logic regions in the first to fourth quadrants of the wafer are then continuously etched to a depth of H+3 / 4h.

[0025] Step 11: Move the wafer out of the etching chamber and rotate it 90 degrees. Then, re-enter the etching chamber and place it on the electrostatic chuck, with the third quadrant of the wafer facing the cantilever beam of the etching machine. Then, continue etching the STI area of ​​the logic area in the first to fourth quadrants of the wafer until the etching depth reaches H+h.

[0026] As described above, the method of the present invention for improving HDP filling defects through the STI etching process has the following beneficial effects: the present invention performs etching in two steps, the first step is to etch the pixel area and the logic area at the same time; the second step is to block the pixel area with a photoresist, and then continue to etch the logic area; the present invention will use the angle matching during STI etching and deep STI etching or the rotation angle during STI and deep STI etching to improve the in-plane depth uniformity, thereby avoiding the occurrence of voids in HDP filling. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shown is a schematic cross-sectional structure diagram of a pixel region and a logic region in the first embodiment of the present invention;

[0028] Figure 2 It is a schematic diagram of the cross-sectional structure after the STI region of the wafer pixel region is covered with photoresist in the first embodiment of the present invention;

[0029] Figure 3 It is a schematic diagram of the cross-sectional structure of a deep STI region formed after continuing to etch the STI region of the logic region in the first embodiment of the present invention;

[0030] Figure 4a It is a top view schematic diagram showing the second quadrant of the wafer facing the cantilever beam of the etching machine in the first embodiment of the present invention;

[0031] Figure 4b It is a top view schematic diagram showing the fourth quadrant of the wafer facing the cantilever beam of the etching machine in the first embodiment of the present invention;

[0032] Figure 5a It is a top view schematic diagram showing the second quadrant of the wafer facing the cantilever beam of the etching machine in the second embodiment of the present invention;

[0033] Figure 5b It is a top view schematic diagram showing the first quadrant of the wafer facing the cantilever beam of the etching machine in the second embodiment of the present invention;

[0034] Figure 5c It is a top view schematic diagram showing the fourth quadrant of the wafer facing the cantilever beam of the etching machine in the second embodiment of the present invention;

[0035] Figure 5d It is a top view schematic diagram showing the third quadrant of the wafer facing the cantilever beam of the etching machine in the second embodiment of the present invention;

[0036] Figure 6 Shown is a flow chart of a method for improving HDP filling defects through an STI etching process according to a first embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] See also Figures 1 to 6 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0039] Example 1

[0040] The present invention provides a method for improving HDP filling defects through STI etching process, such as Figure 6 As shown, Figure 6 The flowchart of the method for improving HDP filling defects by STI etching process according to the first embodiment of the present invention is shown. The method at least includes:

[0041] Step 1: providing a wafer, wherein the wafer has pixel areas and logic areas evenly distributed thereon;

[0042] Step 2: Taking the center of the wafer as the origin of the rectangular coordinate system, the surface of the wafer is divided into the first to fourth quadrants; Figure 4a As shown, the marks 1, 2, 3, and 4 on the wafer surface correspond to the first, second, third, and fourth quadrants respectively; since the pixel areas and logic areas are evenly distributed on the wafer, the first to fourth quadrants of the wafer are all distributed with pixel areas and logic areas.

[0043] Step 3: Place the wafer on the electrostatic chuck of the etching chamber of the etching machine, and make the second quadrant of the wafer face the cantilever beam of the etching machine; Figure 4a As shown, Figure 4a It is a top view schematic diagram showing the second quadrant of the wafer facing the cantilever beam of the etching machine in the first embodiment of the present invention. Figure 4a The symbol A represents the cantilever beam.

[0044] Step 4: Perform STI etching on the pixel regions and logic regions of the first to fourth quadrants of the wafer simultaneously, forming STI regions of the same depth in the pixel regions and logic regions of the first to fourth quadrants, respectively, wherein the depth of the STI regions is H; Figure 1 As shown, Figure 1The schematic diagram of the cross-sectional structure of the pixel area and the logic area in the first embodiment of the present invention is shown. The first to fourth quadrants all contain the pixel area and the logic area. Synchronous etching is simultaneous etching, forming the STI region 05 in the pixel area and the STI region 06 in the logic area. Due to the synchronous etching, the two have the same depth H. After etching, the bottom of the STI region is located on the substrate 01 on the wafer. Before etching, the substrate is also provided with a first layer structure 02 and a second layer structure 03.

[0045] Step 5: moving the wafer out of the etching machine and covering the STI regions of the pixel regions in the first to fourth quadrants of the wafer with photoresist; Figure 2 As shown, Figure 2 The schematic diagram of the cross-sectional structure after the STI area of ​​the wafer pixel area is covered with photoresist in the first embodiment of the present invention is shown. In step five, after the wafer is removed from the etching chamber, it is removed from the etching machine to spin-coat a layer of photoresist. The spun-on layer of photoresist covers the STI areas of the pixel area and the logic area at the same time. After that, the STI areas of the logic area of ​​the first to fourth quadrants are exposed through development. Only the STI area of ​​the pixel area is covered with photoresist 04, forming a structure as shown in FIG. Figure 2 The structure shown.

[0046] Step 6: Place the wafer back on the electrostatic chuck of the etching chamber of the etching machine, and make any one of the other three quadrants of the wafer except the second quadrant face the cantilever beam of the etching machine; the present invention further, in step 6 of this embodiment, make the fourth quadrant of the wafer face the cantilever beam of the etching machine. Figure 4b As shown, Figure 4b The diagram shows a top view of the fourth quadrant of the wafer facing the cantilever beam of the etching machine in the first embodiment of the present invention. In other words, in step six, the wafer is rotated 180 degrees and then placed on the electrostatic chuck. Figure 4b The symbol A represents the cantilever beam.

[0047] Step 7: Continue etching the STI regions of the logic regions in the first to fourth quadrants of the wafer to form deep STI regions, where the depth of the deep STI regions is H+h. Figure 3 As stated, Figure 3 It is a schematic cross-sectional structural diagram of forming a deep STI region 07 after continuing to etch the STI region of the logic area in the first embodiment of the present invention.

[0048] Example 2

[0049] The present invention also provides a method for improving HDP filling defects through an STI etching process, the method at least comprising:

[0050] Step 1: providing a wafer, wherein the wafer has pixel areas and logic areas evenly distributed thereon;

[0051] Step 2: Taking the center of the wafer as the origin of the rectangular coordinate system, divide the surface of the wafer into first to fourth quadrants; the operating principles of steps 1 and 2 of this embodiment are the same as those of steps 1 and 2 of the embodiment of the present invention.

[0052] Step 3: Place the wafer on the electrostatic chuck of the etching chamber of the etching machine, and make the second quadrant of the wafer face the cantilever beam of the etching machine; Figure 5a As shown, Figure 5a It shows a top view schematic diagram of the second quadrant of the wafer facing the cantilever beam A of the etching machine in the second embodiment of the present invention; then STI etching is performed synchronously on the pixel area and logic area of ​​the first to fourth quadrants of the wafer, and STI areas with a depth of 1 / 4H are formed in the pixel area and logic area of ​​the first to fourth quadrants respectively; the synchronous etching in this step three is also etching at the same time, forming an STI area with a depth of 1 / 4H in the pixel area and an STI area with a depth of 1 / 4H in the logic area.

[0053] Step 4: Move the wafer out of the etching chamber and rotate it 90 degrees, then re-enter the etching chamber and place it on the electrostatic chuck, with the first quadrant of the wafer facing the cantilever beam of the etching machine; Figure 5b As shown, Figure 5b It shows a top view schematic diagram of the first quadrant of the wafer facing the cantilever beam A of the etching machine in the second embodiment of the present invention; then the STI areas of the pixel areas and logic areas of the first to fourth quadrants of the wafer are continuously etched synchronously until the depth reaches 2 / 4H.

[0054] Step 5: Move the wafer out of the etching chamber and rotate it 90 degrees, then re-enter the etching chamber and place it on the electrostatic chuck, with the fourth quadrant of the wafer facing the cantilever beam of the etching machine; Figure 5c As shown, Figure 5c Schematic diagram of a top view of the fourth quadrant of the wafer facing the cantilever beam A of the etching machine in the second embodiment of the present invention; then, the STI regions of the pixel regions and logic regions of the first to fourth quadrants of the wafer are simultaneously etched until the depth reaches 3 / 4H;

[0055] Step 6: Move the wafer out of the etching chamber and rotate it 90 degrees, then re-enter the etching chamber and place it on the electrostatic chuck, with the third quadrant of the wafer facing the cantilever beam of the etching machine; Figure 5d As shown, Figure 5dIt shows a top view schematic diagram of the third quadrant of the wafer facing the cantilever beam A of the etching machine in the second embodiment of the present invention; then the STI areas of the pixel areas and logic areas of the first to fourth quadrants of the wafer are continuously etched synchronously until the etching depth reaches H.

[0056] Step 7: Move the wafer out of the etching machine and cover the STI areas of the pixel areas in the first to fourth quadrants of the wafer with photoresist; in step 7, the depth of the STI areas of the pixel areas covered by the photoresist is H, and the depth of the STI areas of the logic areas not covered by the photoresist is also H.

[0057] Step 8: Place the wafer on the electrostatic chuck of the etching chamber of the etching machine, and align the second quadrant of the wafer with the cantilever beam of the etching machine; then continue etching the STI regions of the logic regions of the first to fourth quadrants of the wafer to a depth of H+1 / 4h;

[0058] Step 9: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the first quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the logic regions in the first to fourth quadrants of the wafer are then continuously etched to a depth of H+2 / 4h.

[0059] Step 10: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the fourth quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the logic regions in the first to fourth quadrants of the wafer are then continuously etched to a depth of H+3 / 4h.

[0060] Step 11: Move the wafer out of the etching chamber and rotate it 90 degrees. Then, re-enter the etching chamber and place it on the electrostatic chuck, with the third quadrant of the wafer facing the cantilever beam of the etching machine. Then, continue etching the STI area of ​​the logic area in the first to fourth quadrants of the wafer until the etching depth reaches H+h.

[0061] In summary, the present invention employs a two-step etching process. The first step involves simultaneously etching the pixel and logic regions. In the second step, the pixel regions are shielded with photoresist before etching the logic region. Furthermore, the present invention utilizes angle matching during STI and deep STI etching, or by rotating the STI and deep STI etching angles, to improve in-plane depth uniformity, thereby preventing voids in HDP fill. Therefore, the present invention effectively overcomes the shortcomings of existing technologies and possesses high industrial applicability.

[0062] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for improving HDP filling defects through STI etching process, characterized in that: The method comprises at least: Step 1: providing a wafer, wherein the wafer has pixel areas and logic areas evenly distributed thereon; Step 2: Dividing the surface of the wafer into first to fourth quadrants with the center of the wafer as the origin of a rectangular coordinate system; Step 3: placing the wafer on an electrostatic chuck of an etching chamber of an etching machine, and aligning the second quadrant of the wafer with the cantilever beam of the etching machine; Step 4: performing STI etching on the pixel regions and logic regions in the first to fourth quadrants of the wafer simultaneously, forming STI regions of the same depth in the pixel regions and logic regions in the first to fourth quadrants, respectively, wherein the depth of the STI regions is H; Step 5: moving the wafer out of the etching machine, and covering the STI regions of the pixel regions in the first to fourth quadrants of the wafer with photoresist; Step 6: Re-place the wafer on the electrostatic chuck of the etching chamber of the etching machine, and place any one of the other three quadrants of the wafer except the second quadrant facing the cantilever beam of the etching machine; Step 7: Continue etching the STI regions of the logic areas in the first to fourth quadrants of the wafer to form deep STI regions, where the depth of the deep STI regions is H+h.

2. The method for improving HDP filling defects through an STI etching process according to claim 1, wherein: In step six, the fourth quadrant of the wafer is placed facing the cantilever beam of the etching machine.

3. A method for improving HDP filling defects through STI etching process, characterized in that: The method comprises at least: Step 1: providing a wafer, wherein the wafer has pixel areas and logic areas evenly distributed thereon; Step 2: Dividing the surface of the wafer into first to fourth quadrants with the center of the wafer as the origin of a rectangular coordinate system; Step 3: placing the wafer on the electrostatic chuck of the etching chamber of the etching machine, and aligning the second quadrant of the wafer with the cantilever beam of the etching machine; then, performing STI etching on the pixel areas and logic areas of the first to fourth quadrants of the wafer simultaneously, forming STI regions with a depth of 1 / 4H in the pixel areas and logic areas of the first to fourth quadrants respectively; Step 4: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the first quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the pixel regions and logic regions in the first to fourth quadrants of the wafer are then simultaneously etched to a depth of 2 / 4H. Step 5: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the fourth quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the pixel regions and logic regions in the first to fourth quadrants of the wafer are then simultaneously etched to a depth of 3 / 4H. Step 6: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the third quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the pixel and logic regions of the first to fourth quadrants of the wafer are then simultaneously etched to a depth of H. Step 7: moving the wafer out of the etching machine, and covering the STI regions of the pixel regions in the first to fourth quadrants of the wafer with photoresist; Step 8: Place the wafer on the electrostatic chuck of the etching chamber of the etching machine, and align the second quadrant of the wafer with the cantilever beam of the etching machine; then continue etching the STI regions of the logic regions of the first to fourth quadrants of the wafer to a depth of H+1 / 4h; Step 9: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the first quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the logic regions in the first to fourth quadrants of the wafer are then continuously etched to a depth of H+2 / 4h. Step 10: The wafer is removed from the etching chamber and rotated 90 degrees. The wafer is then re-entered the etching chamber and placed on the electrostatic chuck, with the fourth quadrant of the wafer facing the cantilever beam of the etching machine. The STI regions of the logic regions in the first to fourth quadrants of the wafer are then continuously etched to a depth of H+3 / 4h. Step 11: Move the wafer out of the etching chamber and rotate it 90 degrees. Then, re-enter the etching chamber and place it on the electrostatic chuck, with the third quadrant of the wafer facing the cantilever beam of the etching machine. Then, continue etching the STI area of ​​the logic area in the first to fourth quadrants of the wafer until the etching depth reaches H+h.

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