A thin film substrate structure and acoustic filter

Abstract

The application relates to the fields of material preparation technology and radio frequency devices, in particular to a thin film substrate structure and an acoustic filter. The thin film substrate structure comprises a supporting substrate, an interface layer, an insulating layer and a functional layer; the supporting substrate has opposite first and second surfaces, and the interface layer is located on the second surface; the insulating layer is located on the side surface of the interface layer away from the supporting substrate; the functional layer is located on the side surface of the insulating layer away from the supporting substrate; and the interface layer has at least one of a deep energy level defect and a preset band gap width. The application plays a pinning effect on the Fermi level of the device by the interface layer having at least one of a deep energy level defect and a preset band gap width. The surface local conductance effect of the supporting substrate when working at a high frequency is effectively inhibited, the generation of high-order harmonics is inhibited, and the linearity of the device is optimized.

Description

Technical Field

[0001] This application relates to the fields of materials preparation technology and radio frequency devices, and in particular to a thin film substrate structure and an acoustic filter. Background Technology

[0002] As people increasingly demand higher data transmission speeds, performance, and power consumption from telecommunications equipment, there is a need for new chip integration solutions to achieve faster data transmission at high frequencies.

[0003] Currently, piezoelectric materials are typically integrated with silicon to provide a material-level integrated wafer substrate, offering a material platform for fabricating monolithically integrated modules. Filters fabricated using heterogeneous substrate wafers can effectively improve the center frequency and bandwidth of related filters while reducing power consumption and heat dissipation. However, in filters operating in the radio frequency (RF) band, the RF signal causes inherent defects in the insulating layer to attract majority or minority carriers from the surface of the supporting substrate, leading to an increase in local conductivity on the supporting substrate surface. This results in additional losses and the generation of higher harmonics. Therefore, an improved thin-film substrate structure and filter are needed to address these issues. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this application provides a thin-film substrate structure and a filter to solve technical problems such as interface acoustic wave energy reflection in existing device structures. The specific technical solution is as follows:

[0005] On the one hand, this application provides a thin film substrate structure, including: a supporting substrate, an interface layer, an insulating layer, and a functional layer;

[0006] The supporting substrate has opposing first and second surfaces, and the interface layer is located on the second surface;

[0007] The insulating layer is located on the surface of the interface layer away from the supporting substrate;

[0008] The functional layer is located on the side surface of the insulating layer away from the supporting substrate, and the functional layer is bonded to the insulating layer;

[0009] The interface layer has at least one of deep energy level defects and a preset bandgap width.

[0010] Furthermore, the preset bandgap width is 3-15 eV.

[0011] Furthermore, the material of the interface layer includes at least one of single-crystal materials and polycrystalline materials, and the thickness of the interface layer is 0.1-10 μm.

[0012] Furthermore, the insulating layer is made of at least one of silicon oxide and germanium oxide, and the thickness of the insulating layer is 0.1-10 μm.

[0013] Furthermore, the interface layer can be formed by at least one of ion implantation, impurity doping, and grain refinement.

[0014] Furthermore, the second surface of the supporting substrate is either rough or smooth.

[0015] Furthermore, if the second surface is rough, the roughness is 100-1000 nm.

[0016] Furthermore, the material of the functional layer includes one or more of lithium niobate, lithium tantalate, lithium borate, lead magnesium niobate-lead titanate, lanthanum gallium silicate, quartz, and potassium sodium tartrate, and the thickness of the functional layer is 0.1-10 μm.

[0017] Furthermore, the material of the supporting substrate includes at least one of silicon, silicon oxide, sapphire, diamond, aluminum nitride, gallium nitride, silicon carbide, and silicon-on-insulator.

[0018] On the other hand, this application also provides a filter, including the heterogeneous thin film substrate structure as described above.

[0019] Due to the above technical solution, a thin film substrate structure and a filter have the following beneficial effects:

[0020] This application introduces an interface layer between the insulating layer and the supporting substrate. This interface layer has deep-level defects and at least one pair of Fermi levels within a predetermined bandgap, which act as pinning agents for the devices. This effectively suppresses the localized surface conductivity effect of the supporting substrate when operating at high frequencies, suppresses the generation of higher harmonics, and optimizes the linearity of the device. Attached Figure Description

[0021] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the thin film substrate structure provided in the embodiments of this application;

[0023] Figure 2 This is a schematic diagram of the structure of the supporting substrate provided in an embodiment of this application;

[0024] Figure 3This is a schematic diagram of the structure after an interface layer is formed on the supporting substrate, provided in an embodiment of this application;

[0025] Figure 4 This is a schematic diagram of the structure after an insulating layer is formed on the interface layer, provided in an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of the structure of the piezoelectric substrate provided in the embodiments of this application;

[0027] Figure 6 This is a schematic diagram of the structure of the piezoelectric substrate after ion implantation provided in the embodiments of this application;

[0028] Figure 7 This is a schematic diagram of the structure of the bonding wafer provided in the embodiments of this application;

[0029] Figure 8 A schematic diagram of a filter provided in an embodiment of this application;

[0030] Figure 9 The loss characterization diagram of the coplanar waveguide with and without an interface layer provided in the embodiments of this application.

[0031] In the figure, the corresponding reference numerals are: 100 - support substrate; 200 - interface layer; 300 - insulating layer; 400 - functional layer; 500 - metal patterned electrode; 600 - implanted damage layer; 700 - piezoelectric substrate. Detailed Implementation

[0032] The technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0033] For the terms defined below, unless a different definition is given elsewhere in the claims or this specification, these definitions shall apply. All numerical values, whether explicitly indicated or not, are defined herein as being modified by the term "about." The term "about" generally refers to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated values ​​to produce substantially the same properties, functions, results, etc. A range of numerical values ​​indicated by a low value and a high value is defined as including all numerical values ​​included within that range and all subranges included within that range.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0035] The following describes a thin film substrate structure provided in an embodiment of this application. Please refer to [the relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of a thin film substrate structure. It includes: a supporting substrate 100, an interface layer 200, an insulating layer 300, and a functional layer 400; the supporting substrate 100 has opposing first and second surfaces, with the interface layer 200 located on the second surface; the insulating layer 300 is located on the surface of the interface layer 200 away from the supporting substrate 100; the functional layer 400 is located on the surface of the insulating layer 300 away from the supporting substrate 100, and the functional layer 400 is bonded to the insulating layer 300; the interface layer 200 has at least one of a deep-level defect and a predetermined bandgap width.

[0036] This application introduces an interface layer 200 between the insulating layer 300 and the supporting substrate 100. The interface layer 200 has at least one of deep-level defects and a predetermined bandgap. By limiting the bandgap of the interface layer 200, this application suppresses the increase in local conductivity on the surface of the supporting substrate 100. Simultaneously, the interface layer 200 with deep-level defects pins the Fermi level of the device, reduces the local conductivity effect of the supporting substrate 100, suppresses the generation of higher harmonics, and optimizes the linearity of the device.

[0037] In some embodiments, the material of the support substrate 100 includes at least one selected from silicon, silicon oxide, sapphire, diamond, aluminum nitride, gallium nitride, silicon carbide, and silicon-on-insulator. Please refer to... Figure 2 , Figure 2 This is a schematic diagram of the structure of the support substrate provided in the embodiments of this application.

[0038] In some embodiments, the second surface of the support substrate 100 is either rough or smooth. When the second surface of the support substrate 100 is rough, the roughness can be 100-1000 nm, 300-1000 nm, 300-600 nm, or 100-800 nm.

[0039] In some embodiments, the material of the interface layer 200 includes at least one of single-crystal and polycrystalline materials, and the thickness of the interface layer 200 can be 0.1-10 μm, 5-10 μm, or 5-8 μm. Please refer to [reference needed]. Figure 3 , Figure 3 This is a schematic diagram of the structure after an interface layer is formed on the supporting substrate, as provided in an embodiment of this application.

[0040] In some embodiments, the interface layer 200 has a preset bandgap width of 3-15 eV;

[0041] In other embodiments, the interface layer 200 has a preset bandgap width of 5-15 eV;

[0042] In other embodiments, the interface layer 200 has a preset bandgap width of 3-10 eV;

[0043] In other embodiments, the interface layer 200 has a preset bandgap width of 6-10 eV.

[0044] In some embodiments, the interface layer 200 is formed by at least one of ion implantation, impurity doping, and grain refinement. Specifically, an interface layer 200 of a certain thickness is formed in the support substrate 100 by ion implantation under different energy conditions. This interface layer 200 has a Fermi level pinning effect due to the presence of many deep-level defects introduced by ion implantation, which can significantly alleviate the local conductivity effect of the device operating at high frequencies, reduce the electrical losses and high-order harmonic levels of the device, and improve linearity. Similarly, the defects introduced by impurity doping and ion implantation are beneficial to achieving the above effects in this functional layer. The large number of grain boundaries introduced by grain refinement can also achieve the above effects.

[0045] In some embodiments, the material of the insulating layer 300 includes at least one of silicon oxide and germanium oxide, and the thickness of the insulating layer 300 is 0.1-10 μm, 5-10 μm, or 5-8 μm. Please refer to [reference needed]. Figure 4 , Figure 3 This is a schematic diagram of the structure after an insulating layer is formed on the interface layer, as provided in an embodiment of this application.

[0046] In some embodiments, the material of the functional layer 400 includes one or more of lithium niobate, lithium tantalate, lithium borate, lead magnesium niobate-lead titanate, lanthanum gallium silicate, quartz, and potassium sodium tartrate. The thickness of the functional layer 400 is 0.1-10 μm, or it can be 5-10 μm or 5-8 μm.

[0047] In some embodiments, the formation of the functional layer 400 on the insulating layer 300 includes:

[0048] S100: Provides a piezoelectric substrate 700, which has opposing third and fourth surfaces. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of the structure of the piezoelectric substrate provided in the embodiments of this application.

[0049] In some embodiments, the material of the piezoelectric substrate 700 includes at least one of lithium niobate, lithium tantalate, potassium niobate, and barium titanate.

[0050] S200: Ion implantation is performed on the piezoelectric substrate 700 to form an implantation damage layer 600 within the piezoelectric substrate 700; the ion implantation direction is from the third surface to the fourth surface. The ion implantation depth is not limited here, and the implantation damage layer 600 is formed inside the piezoelectric substrate 700 on the side near the third surface. Please refer to [reference needed]. Figure 6 , Figure 6 This is a schematic diagram of the structure of the piezoelectric substrate after ion implantation provided in the embodiments of this application.

[0051] S300: The third surface of the piezoelectric substrate 700 is bonded to the surface of the insulating layer 300 away from the supporting substrate 100 to obtain a bonded wafer. Please refer to [reference needed]. Figure 7 , Figure 7 This is a schematic diagram of the structure of the bonding wafer provided in an embodiment of this application.

[0052] In practical applications, the methods and conditions for bonding the insulating layer 300 and the piezoelectric substrate 700 can be the same as those in the prior art, and this application does not impose any restrictions.

[0053] S400: The bonding substrate is heat-treated to allow it to peel off along the implantation damage layer 600, yielding a thin film substrate. Please refer to [reference needed]. Figure 1 , Figure 1 This is a schematic diagram of the structure of the thin film substrate provided in the embodiments of this application.

[0054] In some embodiments, ion implantation is performed on the piezoelectric substrate 700 in S200 to form an implantation damage layer 600 within the piezoelectric substrate 700, wherein the ions used for ion implantation include at least one selected from hydrogen ions, helium ions, and neon ions; wherein the ion implantation temperature is -25 to 300°C; the ion implantation energy is 1-2000 keV; and the ion implantation dose is 1 × 10⁻⁶. 16 -1×10 18 cm -2 .

[0055] On the other hand, this application also provides an acoustic filter, including the thin film substrate structure as described above. The filter includes: depositing a metal patterned electrode 500 (e.g., ...) on the surface of the functional layer 400 on the side away from the supporting substrate 100. Figure 8 As shown in the figure, the filter is obtained. Specifically, the patterned electrodes can be interdigitated electrodes.

[0056] The following are some specific embodiments of the above technical solutions listed in this specification.

[0057] Example 1:

[0058] The following describes a thin film substrate structure provided in an embodiment of this application. Please refer to [the relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of a thin film substrate structure. It includes: a supporting substrate 100, an interface layer 200, an insulating layer 300, and a functional layer 400; the supporting substrate 100 has opposing first and second surfaces, with the interface layer 200 located on the second surface; the insulating layer 300 is located on the surface of the interface layer 200 away from the supporting substrate 100; the functional layer 400 is located on the surface of the insulating layer 300 away from the supporting substrate 100; the interface layer 200 has at least one of a deep-level defect and a predetermined bandgap width.

[0059] The support substrate 100 is a single-crystal silicon wafer with a resistivity of 3000 Ω·cm. Please refer to [reference needed]. Figure 2 , Figure 2 This is a schematic diagram of the structure of the support substrate provided in the embodiments of this application.

[0060] In some embodiments, the second surface of the support substrate 100 is either rough or smooth. When the second surface of the support substrate 100 is rough, the roughness can be 100-1000 nm, 300-1000 nm, 300-600 nm, or 100-800 nm.

[0061] In some embodiments, the interface layer 200 is formed by chemical vapor deposition. The material of the interface layer 200 is polycrystalline silicon, and the thickness of the interface layer 200 is 0.5-1.5 μm. Please refer to [reference needed]. Figure 3 , Figure 3 This is a schematic diagram of the structure after an interface layer is formed on the supporting substrate, as provided in an embodiment of this application.

[0062] In some embodiments, an insulating layer 300 is formed on the interface layer 200 by thermal oxidation. The insulating layer 300 is made of silicon dioxide and has a thickness of 700 nm. Please refer to [reference needed]. Figure 4 , Figure 3 This is a schematic diagram of the structure after an insulating layer is formed on the interface layer, as provided in an embodiment of this application.

[0063] In some embodiments, the material of the functional layer 400 includes one or more of lithium niobate, lithium tantalate, lithium borate, lead magnesium niobate-lead titanate, lanthanum gallium silicate, quartz, and potassium sodium tartrate. The thickness of the functional layer 400 is 0.1-10 μm, or it can be 5-10 μm or 5-8 μm.

[0064] In some embodiments, the formation of the functional layer 400 on the insulating layer 300 includes the following methods:

[0065] S100: Provides a piezoelectric substrate 700, which has opposing third and fourth surfaces. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of the structure of the piezoelectric substrate provided in the embodiments of this application.

[0066] In some embodiments, the material of the piezoelectric substrate 700 includes at least one of lithium niobate, lithium tantalate, potassium niobate, and barium titanate.

[0067] S200: Ion implantation is performed on the piezoelectric substrate 700 to form an implantation damage layer 600 within the piezoelectric substrate 700; the ion implantation direction is from the third surface to the fourth surface. The ion implantation depth is not limited here, and the implantation damage layer 600 is formed inside the piezoelectric substrate 700 on the side near the third surface. Please refer to [reference needed]. Figure 6 , Figure 6 This is a schematic diagram of the structure of the piezoelectric substrate after ion implantation provided in the embodiments of this application.

[0068] S300: The third surface of the piezoelectric substrate 700 is bonded to the surface of the insulating layer 300 away from the supporting substrate 100 to obtain a bonded wafer. Please refer to [reference needed]. Figure 7 , Figure 7 This is a schematic diagram of the structure of the bonding wafer provided in an embodiment of this application.

[0069] In practical applications, the methods and conditions for bonding the insulating layer 300 and the piezoelectric substrate 700 can be the same as those in the prior art, and this application does not impose any restrictions.

[0070] S400: The bonding substrate is heat-treated to allow it to peel off along the implantation damage layer 600, yielding a thin film substrate. Please refer to [reference needed]. Figure 1 , Figure 1 This is a schematic diagram of the structure of the thin film substrate provided in the embodiments of this application.

[0071] In some embodiments, ion implantation is performed on the piezoelectric substrate 700 in S200 to form an implantation damage layer 600 within the piezoelectric substrate 700, wherein the ions used for ion implantation include at least one of hydrogen ions, helium ions, and neon ions.

[0072] The temperature range for ion implantation is -25 to 300°C;

[0073] The implantation energy for ion implantation is 1-2000 keV;

[0074] The ion implantation dose is 1×10 16 -1×10 18 cm -2 .

[0075] Electrical passive devices were fabricated on the aforementioned thin-film substrate, and their transmission performance was tested. Simultaneously, another thin-film substrate without a polycrystalline silicon interface layer was fabricated, and electrical passive devices were fabricated on the same substrate, with their transmission performance also tested. Please refer to [reference needed]. Figure 9 , Figure 9 The figure shows the loss characterization of coplanar waveguides with and without interface layers. As can be seen from the figure, the loss of the thin film substrate with interface layer is significantly lower than that of the substrate without interface layer in the range of 0.5-8 GHz. At the same time, as the frequency increases, the local conductivity effect of the substrate without interface layer becomes more and more serious, and the overall loss gradually increases. In contrast, the local conductivity effect of the substrate with interface layer is basically completely suppressed, and its overall loss remains basically stable.

[0076] Example 2:

[0077] The following describes a thin film substrate structure provided in an embodiment of this application. Please refer to [the relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of a thin film substrate structure. It includes: a supporting substrate 100, an interface layer 200, an insulating layer 300, and a functional layer 400; the supporting substrate 100 has opposing first and second surfaces, with the interface layer 200 located on the second surface; the insulating layer 300 is located on the surface of the interface layer 200 away from the supporting substrate 100; the functional layer 400 is located on the surface of the insulating layer 300 away from the supporting substrate 100; the interface layer 200 has at least one of a deep-level defect and a predetermined bandgap width.

[0078] The support substrate 100 is a single-crystal silicon wafer with a resistivity of 3000 Ω·cm. Please refer to [reference needed]. Figure 2 , Figure 2 This is a schematic diagram of the structure of the support substrate provided in the embodiments of this application.

[0079] In some embodiments, the second surface of the support substrate 100 is either rough or smooth. When the second surface of the support substrate 100 is rough, the roughness can be 100-1000 nm, 300-1000 nm, 300-600 nm, or 100-800 nm.

[0080] In some embodiments, H ions at concentrations of 85 keV, 105 keV, 130 keV, and 145 keV are implanted via ion implantation to form an interface layer 200, the thickness of which is 300-500 nm. Please refer to [reference needed]. Figure 3 , Figure 3 This is a schematic diagram of the structure after an interface layer is formed on the supporting substrate, as provided in an embodiment of this application.

[0081] In some embodiments, an insulating layer 300 is formed on the interface layer 200 by thermal oxidation. The insulating layer 300 is made of silicon dioxide and has a thickness of 700 nm. Please refer to [reference needed]. Figure 4 , Figure 3 This is a schematic diagram of the structure after an insulating layer is formed on the interface layer, as provided in an embodiment of this application.

[0082] In some embodiments, the material of the functional layer 400 includes one or more of lithium niobate, lithium tantalate, lithium borate, lead magnesium niobate-lead titanate, lanthanum gallium silicate, quartz, and potassium sodium tartrate. The thickness of the functional layer 400 is 0.1-10 μm, or it can be 5-10 μm or 5-8 μm.

[0083] In some embodiments, the formation of the functional layer 400 on the insulating layer 300 includes the following methods:

[0084] S100: Provides a piezoelectric substrate 700, which has opposing third and fourth surfaces. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of the structure of the piezoelectric substrate provided in the embodiments of this application.

[0085] In some embodiments, the material of the piezoelectric substrate 700 includes at least one of lithium niobate, lithium tantalate, potassium niobate, and barium titanate.

[0086] S200: Ion implantation is performed on the piezoelectric substrate 700 to form an implantation damage layer 600 within the piezoelectric substrate 700; the ion implantation direction is from the third surface to the fourth surface. The ion implantation depth is not limited here, and the implantation damage layer 600 is formed inside the piezoelectric substrate 700 on the side near the third surface. Please refer to [reference needed]. Figure 6 , Figure 6This is a schematic diagram of the structure of the piezoelectric substrate after ion implantation provided in the embodiments of this application.

[0087] S300: The third surface of the piezoelectric substrate 700 is bonded to the surface of the insulating layer 300 away from the supporting substrate 100 to obtain a bonded wafer. Please refer to [reference needed]. Figure 7 , Figure 7 This is a schematic diagram of the structure of the bonding wafer provided in an embodiment of this application.

[0088] In practical applications, the methods and conditions for bonding the insulating layer 300 and the piezoelectric substrate 700 can be the same as those in the prior art, and this application does not impose any restrictions.

[0089] S400: The bonding substrate is heat-treated to allow it to peel off along the implantation damage layer 600, yielding a thin film substrate. Please refer to [reference needed]. Figure 1 , Figure 1 This is a schematic diagram of the structure of the thin film substrate provided in the embodiments of this application.

[0090] In some embodiments, ion implantation is performed on the piezoelectric substrate 700 in S200 to form an implantation damage layer 600 within the piezoelectric substrate 700, wherein the ions used for ion implantation include at least one of hydrogen ions, helium ions, and neon ions.

[0091] The temperature range for ion implantation is -25 to 300°C;

[0092] The implantation energy for ion implantation is 1-2000 keV;

[0093] The ion implantation dose was 1×10¹⁶-1×10¹⁸ cm⁻².

[0094] Embodiment 2 of this application alleviates the local conductivity effect of the thin film substrate by preparing an interface layer with many defects.

[0095] Example 3:

[0096] The following describes a thin film substrate structure provided in an embodiment of this application. Please refer to [the relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of a thin film substrate structure. It includes: a supporting substrate 100, an interface layer 200, an insulating layer 300, and a functional layer 400; the supporting substrate 100 has opposing first and second surfaces, with the interface layer 200 located on the second surface; the insulating layer 300 is located on the surface of the interface layer 200 away from the supporting substrate 100; the functional layer 400 is located on the surface of the insulating layer 300 away from the supporting substrate 100; the interface layer 200 has at least one of a deep-level defect and a predetermined bandgap width.

[0097] The support substrate 100 is a single-crystal silicon wafer with a resistivity of 3000 Ω·cm. Please refer to [reference needed]. Figure 2 , Figure 2 This is a schematic diagram of the structure of the support substrate provided in the embodiments of this application.

[0098] In some embodiments, the second surface of the support substrate 100 is either rough or smooth. When the second surface of the support substrate 100 is rough, the roughness can be 100-1000 nm, 300-1000 nm, 300-600 nm, or 100-800 nm.

[0099] In some embodiments, the interface layer 200 is formed epitaxially. The interface layer 200 is silicon carbide, and its thickness is 200-400 nm. Please refer to [reference needed]. Figure 3 , Figure 3 This is a schematic diagram of the structure after an interface layer is formed on the supporting substrate, as provided in an embodiment of this application.

[0100] In some embodiments, an insulating layer 300 is formed on the interface layer 200 by thermal oxidation. The insulating layer 300 is made of silicon dioxide and has a thickness of 700 nm. Please refer to [reference needed]. Figure 4 , Figure 3 This is a schematic diagram of the structure after an insulating layer is formed on the interface layer, as provided in an embodiment of this application.

[0101] In some embodiments, the material of the functional layer 400 includes one or more of lithium niobate, lithium tantalate, lithium borate, lead magnesium niobate-lead titanate, lanthanum gallium silicate, quartz, and potassium sodium tartrate. The thickness of the functional layer 400 is 0.1-10 μm, or it can be 5-10 μm or 5-8 μm.

[0102] In some embodiments, the formation of the functional layer 400 on the insulating layer 300 includes the following methods:

[0103] S100: Provides a piezoelectric substrate 700, which has opposing third and fourth surfaces. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of the structure of the piezoelectric substrate provided in the embodiments of this application.

[0104] In some embodiments, the material of the piezoelectric substrate 700 includes at least one of lithium niobate, lithium tantalate, potassium niobate, and barium titanate.

[0105] S200: Ion implantation is performed on the piezoelectric substrate 700 to form an implantation damage layer 600 within the piezoelectric substrate 700; the ion implantation direction is from the third surface to the fourth surface. The ion implantation depth is not limited here, and the implantation damage layer 600 is formed inside the piezoelectric substrate 700 on the side near the third surface. Please refer to [reference needed]. Figure 6 , Figure 6 This is a schematic diagram of the structure of the piezoelectric substrate after ion implantation provided in the embodiments of this application.

[0106] S300: The third surface of the piezoelectric substrate 700 is bonded to the surface of the insulating layer 300 away from the supporting substrate 100 to obtain a bonded wafer. Please refer to [reference needed]. Figure 7 , Figure 7 This is a schematic diagram of the structure of the bonding wafer provided in an embodiment of this application.

[0107] In practical applications, the methods and conditions for bonding the insulating layer 300 and the piezoelectric substrate 700 can be the same as those in the prior art, and this application does not impose any restrictions.

[0108] S400: The bonding substrate is heat-treated to allow it to peel off along the implantation damage layer 600, yielding a thin film substrate. Please refer to [reference needed]. Figure 1 , Figure 1 This is a schematic diagram of the structure of the thin film substrate provided in the embodiments of this application.

[0109] In some embodiments, ion implantation is performed on the piezoelectric substrate 700 in S200 to form an implantation damage layer 600 within the piezoelectric substrate 700, wherein the ions used for ion implantation include at least one of hydrogen ions, helium ions, and neon ions.

[0110] The temperature range for ion implantation is -25 to 300°C;

[0111] The implantation energy for ion implantation is 1-2000 keV;

[0112] The ion implantation dose was 1×10¹⁶-1×10¹⁸ cm⁻².

[0113] In Embodiment 3 of this application, the local conductivity effect of the thin film substrate operating at high frequencies is suppressed by preparing an interface layer with a large bandgap.

[0114] Due to the above technical solution, a thin film substrate structure and a filter have the following beneficial effects:

[0115] This application introduces an interface layer between an insulating layer and a supporting substrate. This interface layer has at least one of deep-level defects and a predetermined bandgap. By limiting the bandgap of the interface layer and / or having an interface layer with deep-level defects, this application pins the Fermi level of the device. This effectively suppresses the surface local conductivity effect of the supporting substrate when operating at high frequencies, suppresses the generation of higher harmonics, and optimizes the linearity of the device.

[0116] The foregoing description has fully disclosed the specific embodiments of this application. It should be noted that any modifications made by those skilled in the art to the specific embodiments of this application do not depart from the scope of the claims. Accordingly, the scope of the claims of this application is not limited to the foregoing specific embodiments.

Claims

1. A thin film substrate structure, characterized by, It includes: a support substrate (100), an interface layer (200), an insulating layer (300), and a functional layer (400); The supporting substrate (100) has a first surface and a second surface opposite to each other, and the interface layer (200) is located on the second surface. When the second surface is rough, the roughness of the second surface is 100-1000 nm. The insulating layer (300) is located on the side surface of the interface layer (200) away from the supporting substrate (100); The functional layer (400) is located on the side surface of the insulating layer (300) away from the supporting substrate (100), and the functional layer (400) is bonded to the insulating layer (300); The interface layer (200) has deep energy level defects and a preset band gap. The material of the interface layer (200) includes a single crystal material. The thickness of the interface layer (200) is 0.1-10 μm. The interface layer (200) is formed by at least one of ion implantation, impurity doping and grain refinement.

2. The thin film substrate structure of claim 1, wherein The preset band gap width is 3-15eV.

3. The thin film substrate structure of claim 1, wherein The material of the interface layer (200) also includes polycrystalline materials.

4. The thin film substrate structure of claim 1, wherein The insulating layer (300) is made of at least one of silicon oxide and germanium oxide, and the thickness of the insulating layer (300) is 0.1-10 μm.

5. The thin film substrate structure of claim 1, wherein The second surface of the support substrate (100) is smooth.

6. The thin film substrate structure of claim 1, wherein The material of the functional layer (400) includes one or more of lithium niobate, lithium tantalate, lithium borate, lead magnesium niobate-lead titanate, lanthanum monazite silicate, quartz and sodium potassium tartrate, and the thickness of the functional layer (400) is 0.1-10 μm.

7. The thin film substrate structure of claim 1, wherein The material of the support substrate (100) includes at least one of silicon, silicon oxide, sapphire, diamond, aluminum nitride, tungsten nitride, silicon carbide, and silicon-on-insulator.

8. An acoustic filter characterized by, Includes the thin film substrate structure according to any one of claims 1-7.

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