Improving the Efficiency of Excess Loop Delay Compensation in Δ-Σ Modulators

Abstract

Systems and methods are provided for improving the efficiency of excess loop delay compensation in a Δ-Σ analog-to-digital converter. In some examples, systems and methods are provided for reducing the total capacitance in an embedded excess loop delay compensation digital-to-analog converter (DAC) in a quantizer for a continuous-time Δ-Σ ADC. In other examples, the excess loop delay compensation DAC can be a current-domain DAC, a charge-domain DAC, or a voltage-domain DAC. Additionally, methods are provided for digitally controlling the gain of an excess loop delay DAC. Further, methods are provided for calibrating the gain mismatch between a main successive approximation register DAC and an excess loop delay DAC. The systems and methods provided herein improve the performance of a continuous-time Δ-Σ ADC. Continuous-time Δ-Σ ADCs are high-precision and energy-efficient ADCs that are commonly used in audio playback devices and medical devices.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 905,348, filed on September 24, 2019, entitled "Improving the Efficiency of Excess Loop Delay Compensation in Delta - Sigma Analog - to - Digital Converters", which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present invention relates to analog - to - digital converters and, more particularly, to sigma - delta analog - to - digital converters. Background Art

[0004] An analog - to - digital converter converts an analog signal to the digital domain by sampling the analog signal and quantizing the sampled analog signal to generate a digital signal. A delta - sigma ADC (also known as a sigma - delta ADC) uses high - frequency delta - sigma modulation to encode an analog input signal into a digital output signal. Oversampling is used to improve noise filtering. A delta - sigma ADC typically includes a digital filter to subsequently reduce the sampling rate and filter out noise. Since a delta - sigma ADC uses oversampling to reduce noise, generally, a delta - sigma ADC has high resolution.

[0005] Since circuit modules in a delta - sigma ADC introduce time delays, for example, during quantization, an excess loop delay is introduced. The excess loop delay can have an adverse effect on the performance of the delta - sigma ADC.

[0006] This summary is intended to provide an overview of the subject matter of this patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. By comparing these systems with some aspects of the invention set forth in the remainder of this application with reference to the drawings, further limitations and disadvantages of conventional and traditional methods will become apparent to those of ordinary skill in the art. Summary of the Invention

[0007] Systems and methods are provided for improving the efficiency of excess loop delay compensation in a delta - sigma analog - to - digital converter (also known as a sigma - delta ADC). In some examples, systems and methods are provided for reducing the total capacitance in an embedded excess loop delay compensation digital - to - analog converter (DAC) in a quantizer for a continuous - time delta - sigma ADC. In other examples, the excess loop delay compensation DAC can be a current - domain DAC, a charge - domain DAC, or a voltage - domain DAC. Additionally, a method is provided for digitally controlling the gain of the excess loop delay DAC. Moreover, a method is provided for calibrating the gain mismatch between a master successive - approximation register DAC and the excess loop delay DAC. The systems and methods provided herein improve the performance of a continuous - time delta - sigma ADC. A continuous - time delta - sigma ADC is a high - precision and high - energy - efficiency ADC and is typically used in audio playback devices and medical devices.

[0008] According to one aspect, a method of operating a delta-sigma analog-to-digital converter includes: sampling a first input analog signal on a first set of capacitors and a first excess loop delay (ELD) signal on a second set of capacitors; placing a second excess loop delay (ELD) signal on the second set of capacitors to generate a controlled gain ELD signal; subtracting the controlled gain ELD signal from the sampled first input analog signal to generate a delta signal; generating a reference level based on a SAR control signal; comparing the delta signal with the reference level to generate an updated SAR control signal; and generating a SAR output code based on the updated SAR control signal.

[0009] According to another aspect, a delta-sigma analog-to-digital converter includes: a sampling switch connected to an input; a first DAC coupled to the sampling switch, having a first set of capacitors configured to store successive approximation register (SAR) capacitance; a second set of capacitors coupled to the first set of capacitors, configured to store excess loop delay (ELD) capacitance; a quantizer configured to receive outputs from the first and second sets of capacitors; and at least one feedback line connecting the quantizer output to the first and second sets of capacitors, wherein at least one feedback line includes an ELD feedback line to the second set of capacitors.

[0010] According to another aspect, a delta-sigma analog-to-digital converter includes: a sampling switch connected to an input; a first DAC coupled to the sampling switch, having a first set of capacitors (SAR) configured to store a first input signal; a second set of capacitors coupled to the first set of capacitors, configured to store an excess loop delay (ELD) signal; a third capacitor coupled to the sampling switch; wherein the sampling switch is closed during a sampling phase to connect the input to the first DAC, and wherein during the sampling phase the input is sampled into at least one of: at least a portion of the first set of capacitors; and the third capacitor. In some embodiments, at least one of the first set of capacitors, the second set of capacitors, and the third capacitor is configured to be calibrated and constructed at each clock cycle from the entire capacitor bank.

[0011] The drawings show example analog-to-digital circuits and configurations. Variations of these circuits, e.g., changing the location of the circuit, adding or removing certain elements in the circuit, are not beyond the scope of the present invention. The illustrated converters, configurations, and supplementary devices are intended to supplement the support in the detailed description. Description of the Drawings

[0012] When associated with the attached Figure 1When starting to read, the present disclosure can be best understood from the following detailed description. It should be emphasized that according to the standard practices of the industry, various features are not necessarily drawn to scale and are for illustrative purposes only. In cases where the scale is explicitly or implicitly shown, it only provides an illustrative example. In other embodiments, for the sake of clarity in discussion, the sizes of various features can be arbitrarily increased or decreased.

[0013] To more fully understand the nature and advantages of the present invention, please refer to the following detailed description of the preferred embodiments in conjunction with the accompanying drawings, wherein:

[0014] Figure 1 depicts an analog-to-digital converter architecture;

[0015] Figure 2 is a diagram showing a delta-sigma analog-to-digital converter according to various embodiments of the present disclosure;

[0016] Figure 3 is a flowchart showing a method for operating a delta-sigma ADC according to various embodiments of the present disclosure;

[0017] Figures 4A - 4C shows a timing diagram of a delta-sigma analog-to-digital converter according to various embodiments of the present disclosure;

[0018] Figures 5A - 5C is a diagram showing a table of capacitors and proposed capacitor control signals during different operation stages according to various embodiments of the present disclosure;

[0019] Figure 6 is a diagram showing two sets of capacitors for gain calibration according to various embodiments of the present disclosure;

[0020] Figure 7 is a diagram showing capacitor swapping for gain calibration according to various embodiments of the present disclosure;

[0021] Figure 8 is a diagram showing capacitors for gain calibration and fine-tuning gain according to various embodiments of the present disclosure;

[0022] Figure 9 is a graph showing gain mismatch before and after calibration according to various embodiments of the present disclosure;

[0023] Figure 10 is a flowchart showing a method for gain calibration using a trimming capacitor according to various embodiments of the present disclosure;

[0024] Figure 11 is a graph showing gain mismatch before and after calibration using a trimming capacitor according to various embodiments of the present disclosure;

[0025] Figure 12 A diagram showing the fast Fourier transform of a Δ-Σ ADC using the systems and methods discussed herein, in accordance with various embodiments of the present disclosure;

[0026] Figure 13 A block diagram of an example electrical device that may include one or more Δ-Σ ADCs, in accordance with various embodiments of the present disclosure. Detailed Description

[0027] Systems and methods are provided for improving the efficiency of excess loop delay compensation in a Δ-Σ analog-to-digital converter. In particular, systems and methods are provided for reducing the total capacitance in a quantizer for a continuous-time Δ-Σ ADC's embedded excess loop delay compensation digital-to-analog converter. Additionally, a method for digitally controlling the gain of an excess loop delay (ELD) DAC is provided. Moreover, a method for calibrating the gain mismatch between a master successive approximation register (SAR) DAC and an excess loop delay DAC is provided. The systems and methods provided herein improve the performance of a continuous-time Δ-Σ ADC. Continuous-time Δ-Σ ADCs are high-precision and energy-efficient ADCs, commonly used in audio playback devices and medical devices.

[0028] Excess loop delay (ELD) compensation is typically accomplished by a current-steering DAC. As disclosed herein, systems and methods are provided for moving ELD compensation into the capacitive domain and integrating ELD compensation with SAR operation. The present invention includes a switched sampling technique that is embedded in the converter, thereby achieving smaller area and higher power efficiency. The gain control method improves the performance of a continuous-time Δ-Σ ADC by reducing power consumption while maintaining stability. Continuous-time Δ-Σ ADCs are high-precision and energy-efficient ADCs, which are key components in many signal processing circuits.

[0029] The following description and the drawings set forth in detail certain illustrative embodiments of the present disclosure, which indicate several exemplary ways in which the various principles of the present disclosure may be implemented. However, the illustrative examples do not exhaust the many possible embodiments of the present disclosure. Other objects, advantages, and novel features of the present disclosure are set forth in the program in the applicable drawings.

[0030] Figure 1FIG. 0 shows an analog-to-digital converter (ADC) 100, including a loop filter 102, a feedback excess loop delay (ELD) digital-to-analog converter (DAC) 104, an adder 106, and a quantizer 108. For example, ADC 100 is a continuous-time ADC. The quantizer may be a successive approximation register ADC with a conversion delay. An ELD DAC is added to fix the conversion delay in the SAR quantizer. However, the ELD DAC takes up chip area and consumes power. Therefore, it is necessary to embed the ELD DAC into the SAR ADC. Several methods and systems for embedding the ELD DAC into the SAR ADC have been proposed. However, previous systems have a problem of increased gain in the feedback path. Some solutions include a second set of reference voltages for ELD DAC gain control, but the additional set of reference voltages requires additional area and power to generate the reference voltages.

[0031] Figure 2 FIG. 200 is a diagram showing a delta-sigma analog-to-digital converter according to various embodiments of the present disclosure. The SAR quantizer 202 is connected to the loop filter 204, and the output of the loop filter 204 is input to the SAR quantizer 202. The SAR quantizer 202 includes a switch 206 connected to the input of the SAR quantizer 202, a first DAC 208, an adder 210, a comparator 212, a successive approximation register and an excess loop delay logic 214, an ELD DAC 216, and an output 230. The input of the loop filter 204 is a voltage input. The switch 206 connects the input (output from the loop filter 204) and the first DAC 208 when closed. According to various embodiments, the switch 206 is closed during the sampling phase of the SAR quantizer 202 and the switch 206 is open during the conversion phase of the SAR quantizer 202. In some examples, the input is sampled onto an additional sampling capacitor.

[0032] There is also a reference voltage 218 input to the first DAC 208, and a feedback signal 224 from the successive approximation register 214. The output from the first DAC 218 is input to the adder 210, where it is added to the output from the ELD DAC 216. In some embodiments, the first DAC 208 and the ELD DAC 216 are combined or partially combined to reduce the overhead of the ELD DAC 216 in the SAR quantizer 202. According to various embodiments, the ELD feedback operation occurs during two sampling phases and the conversion phase, allowing an increase in ELD functionality. Additionally, in some examples, in the SAR quantizer 202, the ELD gain is programmable. In some examples, the ELD gain can be controlled by changing the gain factors of ELD1 and ELD2. In some examples, in the SAR quantizer 202, the ELD gain is fixed.

[0033] The output of adder 210 is input to comparator 212. The comparison signal of comparator 212 is input to the SAR and ELD logic module 214. The SAR and ELD logic module 214 outputs the output d of the Δ-Σ ADC 200 out 230.

[0034] The SAR and ELD logic module 214 also outputs several feedback signals. The first ELD signal ELD1 220 and the second ELD signal ELD2 222 are output to the ELD DAC 216. The ELD2 signal is used to control the gain of the ELD feedback operation. In some embodiments, the ELD2 is the inverted ELD1 signal. In some embodiments, the ELD2 is the shifted ELD1 signal. In some embodiments, the ELD1 and ELD2 can have different values. In some examples, the first ELD signal ELD1 220 and the second ELD signal ELD2 222 share a single feedback bus. In addition, the SAR and ELD logic module 214 outputs the SAR feedback signal 224 to the first DAC 208. The output 226 from the SAR and ELD logic module 214 is also fed back to the loop filter 204. According to various embodiments, the Δ-Σ ADC 200 includes a modified switching scheme that allows the ELD function to be embedded in the SAR quantizer 202, thereby reducing the power consumption and area of the ADC 200 compared to previous systems.

[0035] Figure 3 is a flowchart showing a method 300 for operating a Δ-Σ ADC according to various embodiments of the present disclosure. The method begins at step 302 when a first input analog signal is sampled into C samp and a first excess loop delay signal is sampled into C ELD to generate a first Δ. According to various examples, C samp is the sum of the capacitors used to sample the input signal, while C ELD is the sum of the ELD DAC capacitors. In some examples, the input analog signal is sampled using additional capacitors. In some examples, the input analog signal is sampled using a portion of the first or second set of capacitors or additional sampling capacitors. At step 304, the ELD DAC is set to the second ELD signal to control the overall ELD signal gain. At step 306, the gain-controlled ELD signal is subtracted from the sampled signal to generate a first Δ signal. In some examples, the second ELD signal is the ELD feedback signal. In one example, the second ELD signal is Figure 2 the feedback signal ELD2 on the second feedback line 222 in the SAR quantizer 202 of

[0036] At step 308, a reference level is generated based on the SAR control signal. In some embodiments, the reference level is generated at a main DAC of a first DAC 208 in an SAR quantizer 202 such as Figure 2 . In some examples, the SAR control signal is an SAR feedback signal. In one example, the SAR control signal is a feedback signal SAR on an SAR feedback line 224 in an SAR quantizer 202 such as Figure 2 , and the feedback signal SAR is converted at the first DAC 208.

[0037] At step 310, the Δ signal generated at step 306 is compared with the reference level (generated at step 308). At step 312, the SAR control signal is updated based on the comparison result of step 310. At step 314, method 300 determines whether there are more bits. If there are more bits, the method returns to step 308. When there are no more bits, the method proceeds to step 316. In some examples, method 300 includes multiple conversion cycles (steps 308 - 314). In one example, method 300 includes six conversion cycles. When the conversion cycle is completed, method 300 proceeds to step 316 and an SAR output code is generated. At step 318, it is determined whether there are more samples. If there are more samples, method 300 repeats, returning to step 302. If there are no more samples at step 318, method 300 ends.

[0038] Figures 4A - 4C A timing diagram of an SAR quantizer according to various embodiments of the present disclosure is shown. Figure 4A A timing diagram 400 of an SAR quantizer is shown, including a sampling phase and a bit trial phase that together constitute a conversion phase. In the sampling phase, both the SAR and the ELD DAC are reset while sampling the signal. In the bit trial phase, the ELD DAC is set to the ELD2 signal and the SAR DAC starts the bit trial operation. The timing diagram 400 shows a 3 - bit operation, so there are three bit trials (BT0, BT1, BT2) for the SAR. Figure 4A The ELD gain (G ELD ) in the example shown is equal to the capacitance ratio factor of the ELD and the SAR, which is calculated by dividing the sum of the ELD capacitances (C ELD ) by the sum of the SAR capacitances (C SAR ) (G ELD = C ELD / C SAR ).

[0039] Figure 4BShows the timing diagram 420 of the SAR quantizer, which also includes a sampling phase and a bit trial phase, which together constitute the conversion phase. In the timing diagram 420, the ELD DAC is set to the ELD signal during the sampling phase, and the ELD is reset during the bit trial phase. In particular, in the timing diagram 420, the ELD is subtracted from the sample. Figure 4B The ELD gain (G ELD ) in the example shown is equal to the sum of the ELD capacitors (C ELD ) divided by the sum of the SAR capacitors (C SAR ) (G ELD = C ELD / C SAR ).

[0040] Figure 4C Shows the timing diagram 450 of the SAR quantizer according to various embodiments of the present disclosure, again including a sampling phase and a bit trial phase, which together constitute the conversion phase. In the timing diagram 450, the ELD DAC is not reset. Specifically, the ELD DAC is set to the first ELD signal value ELD1 during the sampling phase, while the ELD DAC is set to the second ELD signal value ELD2 during the bit trial phase. This allows for maximum utilization of the DAC, saving area and power. Additionally, the method using the timing diagram 450 allows for a gain higher than 1 - in particular, a gain of 2 can be obtained. Figure 4C The ELD gain (G ELD ) in the example shown is equal to the difference between the amount (a ELD1 ) of the first ELD signal ELD1 in the sampling phase and the amount (a ELD2 ) of the second ELD signal ELD2 in the bit trial phase, which is normalized by a ELD1 and multiplied by the sum of the ELD capacitors (C ELD ) divided by the sum of the SAR capacitors (C SAR ) (G ELD = (a ELD1 – a ELD2 ) / a ELD1 * C ELD / C SAR ). The system using the timing diagram 450 can have a gain factor of two.

[0041] In some examples, there are two sets of capacitors: the first set of capacitors is for the SAR main feedback DAC, and the second set of capacitors is for the ELD feedback. The second set of capacitors for the ELD feedback is alternately used for the ELD1 feedback value (on Figure 2 ) and the ELD2 feedback value (on Figure 2on the feedback line 222). The amount of capacitance difference between the ELD feedback and the main SAR DAC is a factor of the gain. According to various characteristics, the capacitance ratio is combined with the signal gain difference to improve the efficiency of the system.

[0042] In a traditional system, the gain of the ELD DAC is set by the capacitance ratio of the SAR main DAC. For example, both the SAR main DAC and the ELD DAC are 3-bit DACs. The sum of the SAR main DAC capacitances is 7C (4C + 2C + C), and the sum of the ELD DAC capacitances is 14C (8C + 4C + 2C). In this example, the gain of the ELD is equal to 14C divided by 7C, which is equal to 2. In other systems, the gain of the ELD DAC is set by changing the reference voltage between the SAR main DAC and the ELD DAC. For example, both the SAR main DAC and the ELD DAC are 3-bit DACs. The sum of the SAR main DAC capacitances is 7C (4C + 2C + 1C), and the sum of the ELD DAC capacitances is also 7C (4C + 2C + 1C). In this example, the ELD reference voltage is twice the SAR reference voltage. Therefore, the gain of the ELD is equal to 2 times Vref divided by Vref, which is equal to 2.

[0043] The systems and methods described herein use the sampling phase and the bit trial phase of the SAR ADC to subtract or add ELD feedback gain control. In contrast, traditional methods use only one of the phases (the sampling phase or the bit trial phase) for ELD feedback and reset the signal applied to the ELD in the other phase. The described systems and methods have several advantages. According to some embodiments, the systems and methods improve the efficiency of capacitor use. According to some embodiments, the systems and methods digitally control the gain instead of changing analog values (such as capacitance ratio or reference voltage), which saves circuit overhead and power. In one example, the SAR main DAC and the ELD DAC are 3-bit DACs, and the sum of the SAR DAC and ELD DAC capacitances and reference voltages is the same. In this example, an ELD feedback signal is applied to the ELD DAC (e.g., '010') during the sampling phase, and an inverted ELD feedback signal (e.g., '101') is applied to the ELD DAC during the bit trial phase. The reset value is 3.5 in decimal ('111' and '000' midpoint), and the ELD1 and ELD2 signal amounts are -1.5 (a ELD1 = 2 - 3.5 = -1.5) and 1.5 (a ELD2 = 5 – 3.5 = 1.5). This results in a gain of the ELD equal to 2 (G ELD = (a ELD1 – a ELD2 ) / a ELD1 * C ELD / C SAR= (-1.5 - 1.5) / (-1.5) * 7C / 7C = 2).

[0044] According to other aspects, the systems and methods described herein allow for digital control of the ELD gain. In one example, the SAR master DAC is 7C (4C + 2C + C) in total, with 3 bits, and the ELD DAC is 7.5C (4C + 2C + C + 0.5C), with 4 bits (i.e., 3 bits + one sub-bit). Even though the sub-bit increases the total capacitance of the ELD DAC, the sub-bit shifts the reset value from 3.5 (= 7 / 2) to 3.75 (= 7.5 / 2), and the ELD DAC still uses 3 bits for each ELD signal (the first 3 bits (7C in total) or the last 3 bits (3.5C in total, but the shift includes a 0.5x factor). This results in an effective total ELD capacitance C ELD remaining at 7C and a capacitance ratio factor of 1 (= 7C / 7C). A combination of subtraction and addition is used to provide additional gain settings. For example, during the sampling phase, an ELD feedback signal is applied to the ELD DAC (assuming '010R', a ELD1 = 2.25 - 3.75 = -1.5), and then during the bit trial phase, a shifted ELD feedback signal ('R010', a ELD2 = 3 - 3.75 = -0.75) is applied to the ELD DAC. In this example, the gain of the ELD is equal to 0.5 (G ELD = (-1.5 - (-0.75)) / (-1.5) * 1 = 0.5). In particular, R is used to represent 0.5 (half of 1) to simplify the single-ended manner of the shift operation. Similarly, if an inverted shifted ELD feedback signal ('R101', a ELD2 = 0.75) is applied during the bit trial phase, then the gain of the ELD is equal to 1.5 (G ELD = (-1.5 - 0.75) / (-1.5) * 1 = 1.5).

[0045] According to some aspects, the ELD gain can be changed on a per-cycle basis. The coefficients in the loop filter of a continuous-time Δ-Σ ADC can be changed to account for process-voltage-temperature (PVT) variations. In some embodiments, to keep the loop stable, the ELD gain tracks these variations over cycles. As described herein, with digital gain control of the ELD, any changes in the loop filter can be easily followed by the ELD gain. In some examples, the gain is adjusted by an external reference voltage, and it takes some time for the reference voltage to stabilize.

[0046] According to some aspects, systems and methods are provided for gain calibration between the ELD gain and the SAR gain. Since the actual capacitance on the capacitors may change (e.g., due to mismatches), the gain may go out of the target range. Gain calibration can be used to minimize the mismatch between the total SAR capacitance and the total ELD capacitance.

[0047] Figure 5A FIG. 500 shows the SAR capacitor 504 and the ELD capacitor 506 according to various embodiments of the present disclosure, and Table 510 with proposed capacitor values. As shown in FIG. 500, the circuit includes a switch 502 at the input, followed by a first SAR capacitor with the SAR signal SAR[2], a second SAR capacitor with the SAR signal SAR[1], and a third SAR capacitor with the SAR signal SAR[0], a first ELD capacitor with the ELD signal ELD[2], a second ELD capacitor with the ELD signal ELD[1], and a third ELD capacitor with the ELD signal ELD[0].

[0048] As shown in FIG. 500, the capacitance value of the first SAR capacitor is 4C, the capacitance value of the second SAR capacitor is 2C, and the capacitance value of the third SAR capacitor is C. Similarly, the capacitance value of the first ELD capacitor is 4C, the capacitance value of the second ELD capacitor is 2C, and the capacitance value of the third ELD capacitor is C. Therefore, the total capacitance of the system is 14C, which is 33% lower than the previous system. The lower capacitance allows the use of smaller capacitors, thus saving space and reducing power consumption. The total capacitance of the system is lower, in part because the ELD capacitor is used in the sampling and bit trial phases. In particular, the previous system required the ELD capacitor (8C, 4C, 2C) to have a higher capacitance value, in part because the ELD capacitor was not used in both the sampling and bit trial phases of the previous system. Using the ELD capacitor 506 during the sampling and bit trial phases allows the capacitance of the ELD capacitor 506 to be reduced, as described in detail below.

[0049] As Figure 5A shown, during the sampling phases 520, 524, the bottom plates of each SAR capacitor 504 are reset. According to various examples, the sampling switch 502 is closed during the sampling phase and open during the bit trial phase. During Figure 5A the shown sampling phases 520, 524, the input signal is charged to all the capacitors 504, 506. Specifically, during the sampling phase, the top plates of each capacitor sample the input signal. According to various examples, the top plates are used for the DAC output, and the feedback is applied to the bottom plates of the capacitors. In addition, during the sampling phase, the ELD capacitor 506 is charged using the ELD signal. In one example, during the sampling phase, the ELD capacitor 506 is charged using Figure 2 the first ELD signal ELD1 on the first ELD feedback line 220 as shown.

[0050] During Figure 5AIn the bit trial phase, there are three bit trials 522a, 522b, 522c. In various examples, each bit trial phase 522a, 522b, 522c corresponds to steps 308 - 314 of method 300 described above with respect to Figure 3 In the first bit trial, all SAR capacitors SAR[2:0] are held at a reset to produce a first reference level for comparison to obtain a first comparison result C k [2]. In the second bit trial, the capacitance of the first SAR capacitor SAR[2] is set to the first comparison result C k [2] to produce a second reference level. In the second bit trial, the SAR feedback signal from the first bit trial is incorporated into the result. In the third bit trial, the capacitance of the second SAR capacitor SAR[1] is set to the second comparison result C k [1]. The capacitance values of the ELD capacitors 506 are all set to the second ELD signal ELD2, which is the previous SAR quantizer digital output (bit trial phase k - 1). During the second sampling phase 524, the capacitance of the ELD capacitors 506 is set to the inverted comparison results obtained in the first 522a, second 522b, and third bit trials 522c. Additionally, during the second sampling phase 524, the bottom plates of the SAR capacitors 504 are reset.

[0051] Figure 5B FIG. 520 is a diagram showing a set of ELD capacitors 522 and a table 524 that shows the capacitance values of each capacitor 522 during three different states: a reset state 526a (used in a previous system), an ELD1 state 526b (during a sampling phase, as Figure 4C shown), and an ELD2 state 526c (during a bit trial phase, as Figure 4C shown). Figure 5B FIG. shows an example where the gain is set to 0.5 instead of Figure 5A a gain of 2. As Figure 5B shown, compared to the ELD capacitor bank 506 of Figure 5A , an additional 0.5C capacitor is added to the ELD capacitor bank 522. According to various examples, the additional 0.5C capacitor increases the gain flexibility. As shown in the last column of table 524, in some examples, the total capacitance of the ELD capacitor bank 522 varies from 7C to 7.5C. In particular, during the reset state, each capacitor in the ELD capacitor bank 522 is set to 0.5, resulting in a total value of 3.75, and the amount of the ELD signal a ELD , which is the total value minus the reset value, is 0 (3.75 - 3.75).

[0052] In the ELD1 state 526b, the capacitance of the first three capacitors is set as shown inFigure 4A As shown, the additional 0.5C capacitor is set to 0.5. In Figure 5B the example shown, these values total 5.25, and the amount of the signal a ELD1 is 1.5, as shown in Table 528. In the ELD2 state 526c, the ELD signal is shifted to the right to control the gain by 1 bit, and the first capacitor (4C capacitor) is set to 0.5 (so the value is 2 (4 x 0.5)). This results in a total value of 4.5, as shown in the total column 528 of Table 524. In various embodiments, the second ELD feedback signal ELD2 is modified to achieve Figure 5B the change in ELD2 shown in

[0053] The gain can be expressed by the following equation:

[0054] G ELD = (a ELD1 - a ELD2 ) / a ELD1 = (a ELD1 - 0.5a ELD1 ) / a ELD1 = 0.5a ELD1 / a ELD1 = 0.5

[0055] where G ELD is the ELD gain, a ELD1 is the amount of the ELD control signal in the sampling phase (ELD1), and a ELD2 is the amount of the ELD control signal in the bit trial phase (ELD2).

[0056] Figure 5C FIG. 530 is a diagram showing the ELD capacitor bank 522 and Table 534, and Table 534 shows the capacitance values of each capacitor 522 during three different states: the reset state 536a, the ELD1 state 536b (during the sampling phase, as Figure 4C shown), and the ELD2 state 536c (during the bit trial phase, as Figure 4C shown). According to various examples, C kb is equal to the inverted value of C k . Figure 5C FIG. shows an example of setting the gain to 2 using an additional 0.5C capacitor. As shown in the last column of Table 534, in some examples, the total value of the ELD capacitor bank 522 changes from 5.25 to 2.25.

[0057] The gain can be expressed by the following equation:

[0058] G ELD=(a ELD1 -a ELD2 ) / a ELD1 =(a ELD1 –(-a ELD1 )) / a ELD1 =2a ELD1 / a ELD1 =2

[0059] where G ELD is the ELD gain, a ELD1 is the amount of the ELD control signal in the sampling phase (ELD1), and a ELD2 is the amount of the ELD control signal in the bit trial phase (ELD2).

[0060] Figure 6 FIG. 600 is a diagram showing a set of SAR capacitors 602 and a set of ELD capacitors 604 for gain calibration according to various embodiments of the present disclosure. The SAR capacitors 602 include a first and a second capacitor having an SAR signal SAR[2], a capacitor having an SAR signal SAR[1], and a capacitor having an SAR signal SAR[0]. In some examples, the first and second SAR[2] capacitors are the most significant bit (MSB) capacitors or split MSB capacitors. The ELD capacitors 604 include a first and a second ELD[2] capacitors, an ELD[1] capacitor, and an ELD[0] capacitor. In some embodiments, the SAR capacitors 602 are on a first DAC, and the ELD capacitors 604 are on an ELD DAC. As Figure 6 shown, the first, second SAR[2] capacitances, and the SAR[1] capacitance are all 2C capacitances, and the SAR[0] capacitance is 1C capacitance. Similarly, the first and second ELD[2] capacitances and the ELD[1] capacitance are all 2C capacitances, and the ELD[0] capacitance is 1C capacitance. However, in actual implementation, the capacitance values on each capacitor may vary. According to various examples, if there is a total capacitance mismatch between the SAR capacitors 602 and the ELD capacitors 604, the mismatch affects the gains of the SAR and ELD feedbacks.

[0061] According to some embodiments, the gain mismatch between the SAR feedback path and the ELD feedback path can be minimized by exchanging equivalent capacitors between the first DAC and the ELD DAC, as described below with respect to Figure 7More detailed descriptions are provided. According to various examples, the 2C capacitor 620 is equivalent. Similarly, the 1C capacitor 622 is equivalent. Note that for the first and second SAR[2] capacitors 612, the most significant bit (MSB) can be split for swapping. Similarly, for the first and second ELD[2] capacitors 614, the most significant bit (MSB) can be separated for swapping. In various examples, the ELD gain variation is minimized. According to some examples, various possible combinations of swapping capacitors between the SAR capacitor bank 602 and the ELD capacitor bank 604 are attempted, and the setting with the minimum gain error is selected.

[0062] Figure 7 FIG. 700 is a diagram illustrating capacitor swapping for gain calibration according to various embodiments of the present disclosure. The top of FIG. 700 shows the first 702a, second 702b, third 702c, and fourth 702d SAR capacitors and the first 704a, second 704b, third 704c, and fourth 704d capacitors. Although the first 702a, second 702b, and third 702c SAR capacitors and the first 704a, second 704b, and third 704c ELD capacitors are 2C capacitors, the actual value of each capacitor can vary. In Figure 7 the example shown, the value of the first SAR capacitor 702a is 1.8C, the value of the second SAR capacitor 702b is 2C, and the value of the third SAR capacitor 702c is 1.9C. Additionally, in Figure 7 the example shown, the value of the first ELD capacitor 704a is 2C, the value of the second ELD capacitor 704b is 2.1C, and the value of the third ELD capacitor 704c is 2.2C. Similarly, although the fourth SAR capacitor 702d and the fourth ELD capacitor 704d are 1C capacitors, the actual values can be different. In Figure 7 the example shown, the value of the fourth SAR capacitor 702d is 0.9C, and the value of the fourth ELD capacitor 704d is 1.1C.

[0063] Adding the values of each of the SAR capacitors 702a, 702b, 702c, and 702d, the total SAR capacitance is 6.6. Adding the values of each of the ELD capacitors 704a, 704b, 704c, and 704d, the total ELD capacitance is 7.4. The capacitance mismatch between the SAR capacitors and the ELD capacitors can cause a gain gap. To minimize the gain gap, the mapping of each capacitor can be changed such that one or more of the SAR capacitors 702a - 702d are used as ELD capacitors, and one or more of the ELD capacitors 704a - 704d are used as SAR capacitors. Although each capacitor remains in place, the usage of each capacitor changes. In Figure 7In the example shown, the third SAR capacitor 702cis is used for the second ELD capacitor, and the fourth SAR capacitor 702d is used for another ELD capacitor. Thus, the second ELD capacitor 704b is used for the third capacitor, and the fourth ELD capacitor 704d is used for the fourth capacitor. As Figure 7 shown, by remapping the capacitors used for SAR capacitance and the capacitors used for ELD capacitance, the total SAR capacitance adds up to 7 and the total ELD capacitance adds up to 7, thereby minimizing capacitance variations. In some examples, the capacitors are calibrated and configured from the entire capacitor bank every clock cycle

[0064] In some embodiments, as described above, one or both of the SAR capacitance bank and the ELD capacitance bank include additional capacitance that can be used to compensate for the difference between the SAR capacitance and the ELD capacitance.

[0065] Figure 8 FIG. 800 is a diagram showing a set of SAR capacitors 802 and a set of ELD capacitors 804 for gain calibration and a set of additional capacitors 806 for fine gain tuning according to various embodiments of the present disclosure. The SAR capacitors 802 include first and second SAR[2] capacitors, a SAR[1] capacitor, and a SAR[0] capacitor. The ELD capacitors 804 include first and second ELD[2] capacitors, an ELD[1] capacitor, and an ELD[0] capacitor. The additional capacitor bank 806 includes four small capacitors. In one example, each capacitor in the bank 806 is a 0.1C capacitor. According to various embodiments, one or more capacitors in the bank 806 can be added to the SAR capacitor bank 802 or the ELD capacitor bank 804 to compensate for the capacitance mismatch between the SAR capacitor bank 802 and the ELD capacitor bank 804.

[0066] According to some examples, various possible combinations of exchanging capacitors between the SAR capacitor bank 802 and the ELD capacitor bank 804 are attempted, and the setting with the minimum gain error is selected. According to some examples, several possible combinations of exchanging capacitors between the SAR capacitor bank 802 and the ELD capacitor bank 804 are attempted until the error is within a selected range, and then the trim capacitor 806 is used to minimize the gain error. According to further examples, the gain calibration is completed only with the trim capacitor 806, and the capacitors are not exchanged between the SAR capacitor bank 802 and the ELD capacitor bank 804.

[0067] Figure 9 FIG. 900 is a graph showing the SAR / ELD gain mismatch before and after calibration according to various embodiments of the present disclosure. In particular, the graph 900 shows the SAR / ELD gain values for more than 100 trials. Before calibration, the SAR / ELD values are shown in line 902. As described above regardingFigures 6 - 8 After the calibration described above, the SAR / ELD gain value is significantly reduced, as shown in line 904.

[0068] Figure 10 FIG. 1000 is a flow chart showing a method 1000 for gain calibration using a trimming capacitor in accordance with various embodiments of the present disclosure. Method 1000 includes gain calibration using only the trimming capacitor, rather than swapping capacitors between a set of SAR capacitors and a set of ELD capacitors. At step 1002, the input switches of capacitor banks 802, 804, and 806 are closed to sample the common mode voltage (V cm ) with SAR equal to 1 and ELD equal to 0. At step 1004, the input switches are opened, and at step 1006, SAR is set to 0 and ELD is set to 1. At step 1008, the DAC output is compared with the common mode voltage. If there is a mismatch, the trimming capacitor is used to minimize the mismatch. In particular, if the DAC output is greater than the common mode voltage (i.e., if the SAR capacitance is less than the ELD capacitance), method 1000 proceeds to step 1010 and a trimming capacitor (sub-capacitor) is added to the SAR capacitor bank. At step 1008, if the DAC output is less than the common mode voltage (i.e., if the SAR capacitance is greater than the ELD capacitance), method 1000 proceeds to step 1012 and a trimming capacitor is added to the ELD capacitor bank.

[0069] At step 1014, it is determined whether the comparison at step 1008 is the first comparison. If it is the first comparison, the process returns to step 1002. If it is not the first comparison, the process proceeds to step 1016 to determine whether the comparison at step 1008 is the last comparison. If it is the last comparison, method 1000 ends. If it is not the last comparison, method 1000 proceeds to step 1018, where it is determined whether the comparison at step 1008 is different from the previous result. If the comparison at step 1008 is different from the previous result, method 1000 ends. If the comparison at step 1008 is not different from the previous result, method 1000 returns to step 1002 and repeats.

[0070] Figure 11 FIG. 1100 is a graph showing the SAR / ELD gain mismatch before and after calibration using a trimming capacitor in accordance with various embodiments of the present disclosure. In particular, graph 1100 shows the SAR / ELD gain values over 100 trials. Before calibration, the SAR / ELD values are shown in line 1102. After the calibration described above with respect to Figure 8 and 9 the SAR / ELD gain value is significantly reduced, as shown in line 1104.

[0071] Figure 12FIG. 1200 is a graph showing a fast Fourier transform of a Δ-Σ ADC using the systems and methods discussed herein in accordance with various embodiments of the present disclosure.

[0072] Figure 13 FIG. 700 is a block diagram of an example electrical device that may include one or more analog-to-digital converters in accordance with any of the embodiments disclosed herein. Many components are shown as being included in electrical device 1300, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in electrical device 1300 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-chip (SoC) die. Figure 13 Further, in various embodiments, electrical device 1300 may not include one or more of the components shown, but electrical device 1300 may include interface circuitry for coupling to one or more components. For example, electrical device 1300 may not include display device 1306, but may include display device interface circuitry (e.g., connectors and drive circuitry) to which display device 1306 may be coupled. In another set of examples, electrical device 1300 may not include audio input device 1324 or audio output device 1308, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 1324 or audio output device 1308 may be coupled.

[0073] In addition, in various embodiments, electrical device 1300 may not include Figure 13 one or more of the components shown, but electrical device 1300 may include interface circuitry for coupling to one or more components. For example, electrical device 1300 may not include display device 1306, but may include display device interface circuitry (e.g., connectors and drive circuitry) to which display device 1306 may be coupled. In another set of examples, electrical device 1300 may not include audio input device 1324 or audio output device 1308, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 1324 or audio output device 1308 may be coupled.

[0074] The electrical device 1300 may include a processing device 1302 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory. The processing device 1302 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device. The electrical device 1300 may include a memory 1304, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or a hard disk drive. In some embodiments, the memory 1304 may include a memory that shares a die with the processing device 1302. The memory may be used as a cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0075] In some embodiments, the electrical device 1300 may include a communication chip 1312 (e.g., one or more communication chips). For example, the communication chip 1312 may be configured to manage wireless communications to transmit data to and from the electrical device 1300. The term "wireless" and its derivatives may be used to describe a circuit, device, system, method, technique, communication channel, etc., that may transmit data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0076] The communication chip 1312 can implement any one of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) project, and any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). A broadband wireless access (BWA) network compatible with IEEE 802.16 is commonly referred to as a WiMAX network, which is an abbreviation for Worldwide Interoperability for Microwave Access and is a certification mark for products that pass the IEEE 802.16 standard's compliance and interoperability tests. The communication chip 1312 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 1312 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1312 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and higher. In other embodiments, the communication chip 1312 can operate according to other wireless protocols. The electrical device 1300 can include an antenna 1322 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0077] In some embodiments, the communication chip 1312 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1312 can include multiple communication chips. For example, a first communication chip 1312 can be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, while a second communication chip 1312 can be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 1312 can be dedicated to wireless communication, while the second communication chip 1312 can be dedicated to wired communication.

[0078] The electrical device 1300 may include a battery / power circuit 1314. The battery / power circuit 1314 may include one or more energy storage devices (e.g., a battery or a capacitor) and / or circuitry for coupling components of the electrical device 1300 to a separate energy source external to the electrical device 1300 (e.g., an AC line power source).

[0079] The electrical device 1300 may include a display device 1306 (or corresponding interface circuitry, as described above). The display device 1306 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0080] The electrical device 1300 may include an audio output device 1308 (or corresponding interface circuitry, as described above). The audio output device 1308 may include any device that produces an audible indicator, such as a speaker, headphones, or earbuds.

[0081] The electrical device 1300 may include an audio input device 1324 (or corresponding interface circuitry, as described above). The audio input device 1324 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output).

[0082] The electrical device 1300 may include a GPS device 1318 (or corresponding interface circuitry, as described above). The GPS device 1318 may communicate with a satellite-based system and may receive the location of the electrical device 1300, as is known in the art.

[0083] The electrical device 1300 may include additional output devices 1310 (or corresponding interface circuitry, as described above). Examples of other output devices 1310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0084] The electrical device 1300 may include additional input devices 1320 (or corresponding interface circuitry, as described above). Examples of other input devices 1320 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0085] The electrical device 1300 can have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, smartphone, mobile Internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing components, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1300 can be any other electrical device that processes data.

[0086] Selected Examples

[0087] Example 1 provides a method of operating a Δ-Σ analog-to-digital converter, including: sampling a first input analog signal for a first set of capacitors and a first excess loop delay (ELD) signal for a second set of capacitors; placing a second excess loop delay (ELD) signal on the second set of capacitors to generate a controlled gain ELD signal; subtracting the controlled gain ELD signal from the sampled first input analog signal to generate a Δ signal; generating a reference level based on a SAR control signal; comparing the Δ signal with the reference level to generate an updated SAR control signal; and generating a SAR output code based on the updated SAR control signal.

[0088] Example 2 provides a method according to one or more of the preceding and / or following examples, wherein placing the second ELD signal on the second set of capacitors includes placing an inverted first ELD signal on the second set of capacitors.

[0089] Example 3 provides a method according to one or more of the preceding and / or following examples, wherein the first and second ELD signals are feedback signals, and further includes feeding back the first and second ELD signals on a shared bus.

[0090] Example 4 provides a method according to one or more of the preceding and / or following examples, further including setting an ELD digital-to-analog converter to the second ELD signal, wherein the second ELD signal is an ELD feedback signal.

[0091] Example 5 provides a method according to one or more of the preceding and / or following examples, wherein the second ELD signal is an inverted version of the first ELD signal.

[0092] Example 6 provides a method according to one or more of the preceding and / or following examples, wherein the second ELD signal is equal to the first ELD signal.

[0093] Example 7 provides a method according to one or more of the preceding and / or following examples, wherein the first and second ELD signals are equal to the most recently sampled phase plus the SAR output of the bit phase period.

[0094] Example 8 provides a method according to one or more of the preceding and / or following examples, wherein the first ELD signal and the second ELD signal are respectively related to the SAR output of the most recent sampled phase plus the bit phase period, and the first ELD signal is different from the second ELD signal.

[0095] Example 9 provides a method according to one or more of the preceding and / or following examples, wherein the SAR control signal is a SAR feedback signal.

[0096] Example 10 provides a method according to one or more of the preceding and / or following examples, wherein generating the SAR output code during the first phase further includes: for each of a plurality of bits, repeatedly generating a reference level; comparing the Δ signal with the reference level to generate an updated SAR control signal; and holding the second ELD signal as the input to the second set of capacitors.

[0097] Example 11 provides a method according to one or more of the preceding and / or following examples, wherein sampling the first input analog signal into the first set of capacitors includes sampling the first input analog signal into one of the top plates of each capacitor in the first set of capacitors and the bottom plates of each capacitor in the first set of capacitors.

[0098] Example 12 provides a method according to one or more of the preceding and / or following examples, wherein the sampling and subtraction occur in one of the current domain, the charge domain, and the voltage domain.

[0099] Example 13 provides a method according to one or more of the preceding and / or following examples, further including sampling the first input analog signal into an additional sampling capacitor.

[0100] Example 14 provides a method according to one or more of the preceding and / or following examples, further including sampling the first input analog signal into a portion of the first and second sets of capacitors.

[0101] Example 15 provides a method according to one or more of the preceding and / or following examples, further including a loop filter configured to provide the first input analog signal.

[0102] Example 16 provides a Δ-Σ analog-to-digital converter, including: a sampling switch connected to an input; a first DAC coupled to the sampling switch, having a first set of capacitors (SAR) capacitors configured to store a first input signal; a second set of capacitors coupled to the first set of capacitors, configured to store an excess loop delay (ELD) signal, wherein the second set of capacitors is configured to generate a controlled gain ELD signal; a comparator and logic circuitry configured to receive outputs from the first and second sets of capacitors and generate a SAR control signal; and a plurality of feedback lines, including an ELD feedback line connecting the logic circuitry output and the second set of capacitors.

[0103] Example 17 provides an ADC according to one or more of the previous and / or following examples, further including a loop filter configured to provide an input.

[0104] Example 18 provides an ADC according to one or more of the previous and / or following examples, wherein the plurality of feedback lines includes a loop filter feedback line connecting the logic circuitry output and the loop filter.

[0105] Example 19 provides an ADC according to one or more of the previous and / or following examples, wherein the plurality of feedback lines includes a SAR feedback line connecting the logic circuitry output and the first set of capacitors.

[0106] Example 20 provides an ADC according to one or more of the previous and / or following examples, wherein the sampling switch is closed during a sampling phase to connect the input to the first DAC and wherein the sampling switch is open during a bit trial phase to disconnect the first DAC from the input.

[0107] Example 21 provides an ADC according to one or more of the previous and / or following examples, wherein the second set of capacitors stores a first ELD signal during the sampling phase, wherein the second set of capacitors stores a second ELD signal during the bit trial phase.

[0108] Example 22 provides an ADC according to one or more of the previous and / or following examples, wherein the second ELD signal is a reversed first ELD signal.

[0109] Example 23 provides an ADC according to one or more of the previous and / or following examples, wherein the first and second ELD signals are related to a SAR control signal from a previous phase.

[0110] Example 24 provides an ADC according to one or more of the previous and / or following examples, wherein sampling and subtraction occur in one of a current domain, a charge domain, and a voltage domain.

[0111] Example 25 provides an ADC according to one or more of the preceding and / or following examples, wherein the ELD feedback line is configured to feedback the ELD signal during the sampling phase, and the feedback line is configured to feedback a second ELD signal during the bit trial phase.

[0112] Example 26 provides an ADC according to one or more of the preceding and / or following examples, wherein the first cycle includes a first sampling phase and a first bit trial phase, wherein the second cycle includes a second sampling phase and a second bit trial phase, wherein the ELD gain of the controlled gain ELD signal is a programmable gain, and wherein the ELD gain varies between the first cycle and the second cycle.

[0113] Example 27 provides an ADC according to one or more of the preceding and / or following examples, wherein a second set of capacitors is integrated into one of the first DAC and the second DAC.

[0114] Example 28 provides an ADC according to one or more of the preceding and / or following examples, wherein each of the first set of capacitors includes a top plate configured to store the SAR capacitance, and each capacitor in the first set of capacitors includes a bottom plate configured to store a feedback signal.

[0115] Example 29 provides an ADC according to one or more of the preceding and / or following examples, wherein sampling the input to the first set of capacitors and sampling the first excess loop delay (ELD) signal of the second set of capacitors includes sampling an analog signal into one of the top plate of each in each set of capacitors and the bottom plate of each in each set of capacitors.

[0116] Example 30 provides a Δ-Σ analog-to-digital converter, comprising: a sampling switch connected to an input; a first DAC coupled to the sampling switch, having a first set of capacitors (SAR) configured to store a first input signal; a second set of capacitors coupled to the first set of capacitors, configured to store an excess loop delay (ELD) signal; a third capacitor coupled to the sampling switch; wherein the sampling switch is closed during the sampling phase, thereby connecting the input to the first DAC, and wherein during the sampling phase the input is sampled into at least one of: at least a portion of the first set of capacitors; and the third capacitor.

[0117] Example 31 provides an ADC according to one or more of the preceding and / or following examples, wherein at least one of the first set of capacitors, the second set of capacitors, and the third capacitor is configured to be calibrated and configured at each clock cycle from the entire capacitor bank.

[0118] Example 32 provides a delta-sigma analog-to-digital capacitor according to one or more of the foregoing and / or following examples, wherein each of the first set of capacitors includes a top plate configured to store a SAR capacitance, and wherein each of the first set of capacitors includes a bottom plate configured to store a feedback signal.

[0119] Example 33 includes an apparatus of an analog-to-digital digital gateway as discussed or depicted in any of the foregoing and / or following examples, some other examples, or otherwise discussed or depicted herein.

[0120] Example 34 includes an apparatus for implementing an analog-to-digital cryptocurrency as discussed or depicted in any of the foregoing and / or following examples, some other examples, or otherwise discussed or depicted herein.

[0121] Example 35 includes a method for implementing or manufacturing an analog-to-digital converter as discussed or depicted in any of the foregoing and / or following examples, some other examples, or otherwise discussed or depicted herein.

[0122] Example 36 includes one or more non-transitory computer-readable media that include instructions that, when executed by an electronic device, will cause the electronic device to implement or manufacture an analog-to-digital converter as discussed or depicted in any of the foregoing and / or following examples, some other examples, or otherwise discussed or depicted herein.

[0123] In the foregoing discussion, reference may be made to the accompanying drawings, which form a part hereof, in which like numerals throughout indicate like parts, and in which embodiments of the subject matter of the present disclosure may be shown by way of illustration. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the foregoing detailed description should not be construed as limiting.

[0124] Having thus described several aspects and embodiments of the technology of the present application, it should be understood that various changes, modifications, and improvements will readily occur to those of ordinary skill in the art. Such changes, modifications, and improvements are intended to fall within the spirit and scope of the technology described in the present application. For example, those of ordinary skill in the art will readily envision various other devices and / or structures for performing the functions and / or obtaining the results and / or one or more of the advantages described herein, and each of these variations and / or modifications is considered to be within the scope of the embodiments described herein.

[0125] Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. Accordingly, it should be understood that the foregoing embodiments are presented by way of example only, and that embodiments of the invention may be practiced otherwise than as specifically described within the scope of the appended claims and their equivalents. In addition, any combination of two or more of the features, systems, articles, materials, kits, and / or methods described herein, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the scope of the present disclosure.

[0126] The foregoing outlines features of one or more embodiments of the subject matter disclosed herein. These embodiments are provided to enable those of ordinary skill in the art (PHOSITA) to better understand various aspects of the present disclosure. Certain readily understood terms as well as underlying technologies and / or standards may be cited without detailed description. It is expected that the PHOSITA will have or have access to background knowledge or information of those technologies and standards sufficient to practice the teachings of the present disclosure.

[0127] The PHOSITA will understand that they can readily use the present disclosure as a basis for designing or modifying other processes, structures, or variations to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. The PHOSITA will also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0128] The above embodiments can be implemented in any of a variety of ways. One or more aspects and embodiments of the present application related to the performance of a process or method can utilize program instructions executable by a device (e.g., a computer, a processor, or other device) to perform or control the performance of the process or method.

[0129] In this regard, various inventive concepts can be embodied as a computer-readable storage medium (or multiple computer-readable storage media) encoded with one or more programs (e.g., computer memory, one or more floppy disks, optical disks, CD-ROMs, magnetic tapes, flash memories, circuit configurations in a field-programmable gate array or other semiconductor device, or other tangible computer storage media), which, when executed on one or more computers or other processors, perform methods implementing one or more of the various embodiments described above.

[0130] One or more computer-readable media can be transmittable such that the one or more programs stored thereon can be loaded onto one or more different computers or other processors to implement the various aspects described above. In some embodiments, the computer-readable medium can be a non-transitory medium.

[0131] Note that the activities discussed above with reference to the accompanying drawings apply to any integrated circuit that involves signal processing (e.g., gesture signal processing, video signal processing, audio signal processing, analog-to-digital conversion, digital-to-analog conversion), particularly those integrated circuits that can execute specialized software programs or algorithms, some of which may be associated with processing digitized real-time data.

[0132] In some cases, the teachings of the present disclosure can be encoded in one or more tangible, non-transitory computer-readable media that store executable instructions that, when executed, direct a programmable device (e.g., a processor or DSP) to perform the methods or functions disclosed herein. In cases where the teachings herein are embodied at least in part in a hardware device (e.g., an ASIC, IP block, or SoC), the non-transitory medium can include the hardware device that is hardware-programmed with logic to perform the methods or functions disclosed herein. These teachings can also be practiced in the form of register transfer level (RTL) or other hardware description languages (e.g., VHDL or Verilog) that can be used to program a manufacturing process to produce the disclosed hardware elements.

[0133] In example embodiments, at least some portions of the processing activities outlined herein can also be implemented in software. In some implementations, one or more of these features can be implemented in hardware provided outside of the elements of the disclosed drawings or combined in any suitable manner to achieve the desired functionality. The various components can include software (or reciprocating software) that can coordinate to achieve the operations outlined herein. In still other embodiments, these elements can include any suitable algorithms, hardware, software, components, modules, interfaces, or objects that facilitate their operation.

[0134] Any appropriately configured processor component can execute any type of instruction associated with data to achieve the operations detailed herein. Any processor disclosed herein can transform an element or article (e.g., data) from one state or thing to another. In additional examples, some of the activities outlined herein can be implemented with fixed logic or programmable logic (e.g., software and / or computer instructions executed by a processor), and the elements identified herein can be some type of programmable processor, programmable digital logic (e.g., FPGA, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), ASIC, which includes digital logic, software, code, electronic instructions, flash memory, optical disk, CD-ROM, DVD ROM, magnetic card, or optical card, other types of machine-readable media suitable for storing electronic instructions, or any suitable combination thereof.

[0135] In operation, the processor can store information in any suitable type of non-transitory storage medium (e.g., random access memory (RAM), read-only memory (ROM), FPGA, EPROM, electrically erasable programmable read-only memory (EEPROM), etc.), software, hardware, or, where appropriate and based on specific needs, in any other suitable component, device, element, or object. Additionally, based on specific needs and implementations, the information tracked, sent, received, or stored in the processor can be provided in any database, register, table, cache, queue, control list, or storage structure, all of which can be referenced within any suitable time frame.

[0136] Any memory item discussed herein should be construed as being included within the broad term "memory." Similarly, any potential processing elements, modules, and machines described herein should be construed as being included within the broad terms "microprocessor" or "processor." Additionally, in various embodiments, the processors, memories, network cards, buses, storage devices, associated peripheral devices, and other hardware elements described herein can be implemented by processors, memories, and other associated devices configured by software or firmware to emulate or virtualize the functions of these hardware elements.

[0137] Furthermore, it should be understood that, by way of non-limiting example, a computer can be embodied in any of a variety of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer can be embedded in a device that is not typically considered a computer but has appropriate processing capabilities, including a personal digital assistant (PDA), a smartphone, a mobile phone, an iPad, or any other suitable portable or fixed electronic device.

[0138] Moreover, a computer may have one or more input and output devices. Among other things, these devices can be used to present a user interface. Examples of output devices that can be used to provide a user interface include a printer or a display screen for visual presentation of output and a speaker or other sound-generating device for audible presentation of output. Examples of input devices that can be used for a user interface include a keyboard and a pointing device, such as a mouse, a touchpad, and a digitizing tablet. As another example, a computer can receive input information via speech recognition or other audible formats.

[0139] Such computers can be interconnected in any suitable form via one or more networks, including a local area network or a wide area network, such as a corporate network, as well as a smart network (IN) or the Internet. Such networks can be based on any suitable technology and can operate according to any suitable protocol and can include a wireless network or a wired network.

[0140] Computer-executable instructions can be in many forms that are executed by one or more computers or other devices, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Generally, the functions of program modules can be combined or distributed as needed in various embodiments.

[0141] The term "program" or "software" is used herein in a general sense to refer to any type of computer code or set of computer-executable instructions that can be used to program a computer or other processor to implement the various aspects described above. Additionally, it should be understood that, according to one aspect, one or more computer programs that execute the methods of the present application when executed need not reside on a single computer or processor, but can be distributed in a modular fashion among multiple different computers or processors to implement the various aspects of the present application.

[0142] Furthermore, data structures can be stored in a computer-readable medium in any suitable form. For simplicity of illustration, a data structure can be shown as having fields that are related by their positions in the data structure. Such a relationship can equally be achieved by allocating storage for the fields that has positions in the computer-readable medium that convey the relationship between the fields. However, any suitable mechanism can be used to establish the relationship between the information in the fields of a data structure, including by using pointers, tags, or other mechanisms that establish relationships between data elements.

[0143] When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.

[0144] The computer program logic for implementing all or part of the functions described herein is embodied in various forms, including but not limited to source code form, computer-executable form, hardware description form, and various intermediate forms (e.g., masked works, or tables generated by an assembler, compiler, linker, or locator). In one example, the source code includes a series of computer program instructions implemented in various programming languages, such as object code, assembly language, or high-level languages such as OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, JAVA, or HTML for various operating systems or operating environments. The source code can define and use various data structures and communication messages. The source code can be in computer-executable form (e.g., via an interpreter), or the source code can be converted (e.g., via a translator, assembler, or compiler) into computer-executable form.

[0145] In some embodiments, any number of the circuits in the figures may be implemented on a board of a related electronic device. The board may be a general-purpose circuit board that can accommodate various components of the electronic system inside the electronic device and can also provide connectors for other peripheral devices. More specifically, the board may provide electrical connections through which other components of the system can communicate electrically. Any suitable processor (including digital signal processors, microprocessors, companion chip sets, etc.), storage elements, etc. may be appropriately coupled to the circuit board based on specific configuration requirements, processing requirements, computer design, etc.

[0146] Other components, such as external storage, additional sensors, controllers and peripherals for audio / video display, may be connected to the board as plug-in cards, through cables, or integrated into the board itself. In additional example embodiments, the circuits of the figures may be implemented as stand-alone modules (e.g., devices having related components and circuits configured to perform specific applications or functions) or as plug-in modules in the dedicated hardware of an electronic device.

[0147] Note that through the numerous examples provided herein, interactions may be described in terms of two, three, four, or more electronic components. However, this is done for clarity and solely as an example. It should be understood that the system may be combined in any suitable manner. Along similar design alternatives, any of the components, modules, and elements shown in the figures may be combined in various possible configurations, all of which are clearly within the broad scope of the present disclosure.

[0148] In some cases, it may be easier to describe one or more functions of a given set of processes by referring to only a limited number of electrical components. It should be understood that the circuits of the figures and their teachings are readily extensible and can accommodate a large number of components as well as more complex / precise arrangements and configurations. Thus, the examples provided should not limit the scope or inhibit the broad teachings of the circuits that may be applied to countless other architectures.

[0149] Furthermore, as described, some aspects may be embodied as one or more methods. The actions performed as part of the method may be sequenced in any suitable manner. Accordingly, embodiments may be constructed in which the actions are performed in a different order than shown in the figures, which may include performing some actions simultaneously, even though shown as sequential actions in the illustrative embodiments.

[0150] Glossary

[0151] All definitions as defined and used herein shall be understood to control dictionary definitions, definitions in documents incorporated by reference, and / or the ordinary meaning of the defined terms. Unless the context clearly requires otherwise, throughout the specification and claims:

[0152] Terms such as "comprising" and "including" shall be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

[0153] "Connected", "coupled", or any variant thereof, means any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements can be physical, logical, or a combination thereof.

[0154] Words such as "here", "above", "below", and words of similar import, when used to describe this specification, shall refer to this specification as a whole and not to any particular part of this specification.

[0155] "Or" refers to a list of two or more items and encompasses all of the following interpretations of that term: any item in the list, all items in the list, and any combination of items in the list.

[0156] The singular forms "a", "an", and "the" also include the meaning of any appropriate plural forms.

[0157] Words indicating directions, such as "vertical", "lateral", "horizontal", "upward", "downward", "forward", "backward", "inward", "outward", "perpendicular", "transverse", "left", "right", "front", "rear", "upper", "lower", "beneath", "above", "below", etc., when used in this specification and any appended claims (where such words exist) depend on the particular orientation of the device being described and illustrated. The subject matter described herein can assume various alternative orientations. Accordingly, these directional terms are not rigidly defined and should not be construed narrowly.

[0158] The indefinite articles "a" and "an" used in the specification and claims shall be understood to mean "at least one" unless explicitly stated to the contrary.

[0159] The phrase "and / or" as used herein in the specification and claims shall be understood to mean "one or both" of the elements so combined, i.e., elements that are present together in some cases and separate in other cases. Multiple elements listed with "and / or" shall be construed in the same manner, i.e., "one or more" of such combined elements.

[0160] Elements other than those specifically identified by the "and / or" clauses may optionally be present, whether related or unrelated to those specifically identified elements. Thus, as a non-limiting example, when used in conjunction with open language such as "comprising", a reference to "A and / or B" may in one embodiment refer only to A (optionally including elements other than B); in another embodiment, only to B (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); and so on.

[0161] As used herein in the specification and claims, the phrase "at least one" when referring to a list of one or more elements should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each element specifically listed in the list of elements, and not excluding any combinations of elements in the list of elements. This definition also allows elements other than those specifically identified in the list of elements to which the phrase "at least one" refers to be optionally present, whether related or unrelated to those specifically identified elements.

[0162] Thus, as a non-limiting example, "at least one of A and B" (or equivalently, "at least one of A or B", or equivalently "at least one of A and / or B") may in one embodiment refer to at least one, optionally including more than one of A, with no B present (and optionally including elements other than B); in another embodiment, refer to at least one, optionally including more than one of B, with no A present (and optionally including elements other than A); in yet another embodiment, refer to at least one, optionally including more than one of A, and at least one, optionally including more than one of B (and optionally including other elements); and so on.

[0163] As used herein, unless otherwise specified, the term "between" is inclusive. For example, "between A and B" includes A and B, unless otherwise specified.

[0164] Furthermore, the language and terminology used herein are for descriptive purposes and should not be regarded as limiting. The use of "comprising", "including" or "having", "containing", "involving" and their variants herein is intended to cover the items listed thereafter and their equivalents as well as additional items.

[0165] In the claims as well as in the above specification, all transitional phrases such as "comprising", "including", "carrying", "having", "containing", "involving", "holding", "consisting of", etc. should be understood to be open-ended, i.e., meaning including but not limited to. Only the transitional phrases "consisting of" and "consisting essentially of" are closed or semi-closed transitional phrases, respectively.

[0166] Those skilled in the art can determine many other variations, substitutions, alternatives, changes, and modifications, and this disclosure is intended to cover all such variations, substitutions, alternatives, changes, and modifications that fall within the scope of the appended claims.

[0167] To assist the United States Patent and Trademark Office) and (additionally, readers of any patent issued under this application in interpreting the appended claims, the applicant wishes to note that the applicant: (a) does not intend to rely on any additional claim on 35 U.S.C. § 112(f) as it existed on the filing date, unless the terms "means" or "step" are specifically used in a particular claim; (b) does not intend to limit this disclosure in any way not otherwise reflected in the appended claims by any statement in this disclosure.

[0168] Therefore, the present invention should not be considered limited to the above specific embodiments. Various modifications, equivalent processes, and many structures applicable to the present invention will be apparent to those skilled in the art to which the present invention pertains upon reading this disclosure.

Claims

1. A method of operating a Δ-Σ analog-to-digital converter, comprising: Sampling a first input analog signal into a first set of capacitors and sampling a first excess loop delay (ELD) signal into a second set of capacitors; Placing a second excess loop delay (ELD) signal on the second set of capacitors to generate a controlled gain ELD signal; Subtracting the controlled gain ELD signal from the sampled first input analog signal to generate a first Δ signal; Generating a reference level based on a SAR control signal; Comparing the first Δ signal with the reference level to produce an updated SAR control signal; And Generating a SAR output code based on the updated SAR control signal.

2. The method according to claim 1, further comprising a loop filter configured to provide the first input analog signal.

3. The method according to claim 1, wherein placing the second ELD signal on the second set of capacitors comprises placing an inverted first ELD signal on the second set of capacitors.

4. The method according to claim 1, wherein the first ELD signal and the second ELD signal are feedback signals, and further comprising feeding back the first ELD signal and the second ELD signal on a shared bus.

5. The method according to claim 1, wherein the first ELD signal value is different from the second ELD signal value, and wherein the first ELD signal and the second ELD signal are functions of SAR output codes of a previous stage.

6. The method according to claim 1, wherein generating the SAR output code further comprises, during a first stage: For each of a plurality of bits, repeatedly generating a reference level and comparing the Δ signal with the reference level to produce an updated SAR control signal; and Holding the second ELD signal as an input to the second set of capacitors.

7. The method according to claim 1, wherein sampling the first input analog signal into the first set of capacitors and sampling the first excess loop delay (ELD) signal into the second set of capacitors comprises sampling the analog signal into one of a top plate of each capacitor in the set and a bottom plate of each capacitor in the set.

8. The method according to claim 1, wherein the sampling and subtraction occur in one of a current domain, a charge domain, and a voltage domain.

9. The method according to claim 1, further comprising sampling the first input analog signal into at least one additional sampling capacitor.

10. The method according to claim 9, further comprising sampling the first input analog signal into at least one of the following: a portion of the first set of capacitors, a portion of the second set of capacitors, and at least one additional sampling capacitor.

11. A Δ-Σ analog-to-digital converter, comprising: A sampling switch connected to an input; A first DAC coupled to the sampling switch, having a first set of capacitors configured to store a first input signal; A second set of capacitors coupled to the first set of capacitors, configured to store an excess loop delay (ELD) signal, wherein the second set of capacitors is configured to generate a controlled gain ELD signal; A comparator and logic circuitry configured to receive outputs from the first and second sets of capacitors and generate a SAR control signal; and A plurality of feedback lines including an ELD feedback line connecting the output of the logic circuitry and the second set of capacitors, wherein the sampling switch is closed during a sampling phase to connect the input to the first DAC and is open during a bit trial phase to disconnect the first DAC from the input; and wherein the second set of capacitors stores a first ELD signal during the sampling phase and stores a second ELD signal during the bit trial phase.

12. The Δ-Σ analog-to-digital converter according to claim 11, further comprising a loop filter configured to provide the input, wherein the plurality of feedback lines includes a loop filter feedback line connecting the output of the logic circuitry and the loop filter, and wherein the plurality of feedback lines includes a SAR feedback line connecting the output of the logic circuitry to the first set of capacitors.

13. The Δ-Σ analog-to-digital converter according to claim 11, wherein the second ELD signal is an inverted first ELD signal.

14. The Δ-Σ analog-to-digital converter according to claim 11, wherein the first and second ELD signals are related to a SAR output signal from a previous stage.

15. The Δ-Σ analog-to-digital converter according to claim 11, wherein sampling and subtraction occur in one of a current domain, a charge domain, and a voltage domain.

16. The Δ-Σ analog-to-digital converter according to claim 11, wherein a first cycle includes a first sampling phase and a first bit trial phase, wherein a second cycle includes a second sampling phase and a second bit trial phase, wherein the ELD gain of the controlled gain ELD signal is a programmable gain, and wherein the ELD gain varies between the first cycle and the second cycle.

17. The Δ-Σ analog-to-digital converter according to claim 11, wherein sampling the input to the first set of capacitors and sampling the ELD signal to the second set of capacitors includes sampling an analog signal to one of a top plate of each of the capacitors in the set and a bottom plate of each of the capacitors in the set.

18. A Δ-Σ analog-to-digital converter, comprising: A sampling switch connected to an input; A first DAC coupled to the sampling switch, having a first set of capacitors configured to store a first input signal; A second set of capacitors coupled to the first set of capacitors, configured to store an excess loop delay (ELD) signal; and A third capacitor coupled to the sampling switch; wherein the sampling switch is closed during a sampling phase to connect the input to the first DAC and is open during a bit trial phase; wherein during the sampling phase, the input is sampled into at least one of: at least a portion of the first set of capacitors and the third capacitor, and the second set of capacitors stores a first ELD signal; wherein, during the bit trial phase, the second set of capacitors stores a second ELD signal; and At least one of the first set of capacitors, the second set of capacitors, and the third capacitor is configured to be calibrated and configured at each clock cycle from the entire capacitor bank.

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