A central processing unit system and power management device thereof

Abstract

The present invention provides a central manager system and a power management device thereof, comprising: a power module for providing working power to the device; an output module connected to the power module for converting the working power into different types of power voltage signals and providing them to various types of working modules of the central processor respectively; a communication module connected to at least some of the submodules in the output module for receiving instructions from the central processor and controlling the output voltage signals of at least some of the submodules based on the instructions. According to the present invention, based on the communication between a single power management device and the central processor, the power requirements of each working module in the central processor can be met, the power supply structure of the central processor is simplified, the power supply efficiency thereof is improved, the cost is greatly reduced, and the reliability and safety of the entire system are ensured.

Description

Technical Field

[0001] The present invention relates to the field of power management, and more particularly to power management of a central processing unit. Background Art

[0002] At present, the central processing unit has become the most widely used hardware system architecture in the computer field. Due to its absolute position in market share, the central processing unit developed based on it can adapt to almost all software and hardware in the field of personal hosts and servers. However, due to the lack of unified standards in various fields and insufficient development investment in such a highly versatile hardware system, the power management system that powers the central processing unit has a low degree of integration in its current hardware system. For example, for each specific design, a scattered combination of various power supplies must be carried out, and even each voltage must be separately connected to the previous and next stages to meet the timing requirements. To meet the needs of the system, many devices need to be stacked. This not only consumes costs and reduces the power supply efficiency of the power management system, but also poses a great risk to the integrity and security of the entire central processing unit system.

[0003] Therefore, the integration level of the power management system for supplying power to the central processing unit in the prior art is very low, resulting in a complex power supply structure and low power supply efficiency, which is not conducive to cost reduction and also reduces the reliability and safety of the entire system. Summary of the invention

[0004] The embodiment of the present invention provides a central processing unit system and a power management device thereof, so as to at least solve one of the problems of low power management and low power supply efficiency of the central processing unit.

[0005] According to a first aspect of the present invention, there is provided a power management device based on a central processing unit, the device comprising:

[0006] A power module, used to provide working power for the device;

[0007] An output module, connected to the power module, for converting the working power into different types of power supply voltage signals, and providing them to various types of working modules of the central processor respectively;

[0008] The communication module is connected to at least some of the submodules in the output module, and is used to receive instructions from the central processing unit and control the output voltage signals of at least some of the submodules based on the instructions.

[0009] Optionally, the output module includes:

[0010] The analog submodule is connected to the power module and is used to convert the working power into at least one analog voltage signal and provide the analog voltage signal to the analog signal module of the central processing unit.

[0011] Optionally, the output module includes:

[0012] The digital submodule is connected to the analog submodule and is used to convert the at least one analog voltage signal into at least one digital voltage signal and provide the digital voltage signal to the digital signal module of the central processing unit.

[0013] Optionally, at least some of the sub-modules include:

[0014] The non-business submodule is connected to the digital submodule and is used to output at least one non-business voltage signal based on the first instruction of the central processor and provide the non-business voltage signal to the non-business module of the central processor.

[0015] Optionally, at least some of the sub-modules include:

[0016] The core submodule is connected to the power module and is used for converting the working power into a core voltage signal based on the second instruction of the central processing unit, and providing the core voltage signal to the core module of the central processing unit.

[0017] Optionally, at least some of the sub-modules include:

[0018] The memory submodule is connected to the power module and is used to output at least one memory voltage signal based on the third instruction of the central processing unit and provide the memory voltage signal to the memory module of the central processing unit.

[0019] Optionally, the communication module includes:

[0020] The status submodule is used to send the working status of the output module of the device to the central processor.

[0021] Optionally, the communication module includes: a configuration submodule, which performs configuration communication with the central processor and receives a configuration communication signal;

[0022] The device further comprises: a control module connected to the configuration submodule, and configured to control the device and the central processor to configure based on the configuration communication signal.

[0023] According to a second aspect of the present invention, there is provided a central processing unit system, the system comprising:

[0024] Central processing unit, used for data processing;

[0025] The power management device according to the first aspect is connected to the central processing unit and is used to provide different types of power supply voltage signals to various types of working modules of the central processing unit.

[0026] Optionally, the power management device is further used for:

[0027] providing a power supply voltage signal to at least some modules of the central processor not based on an instruction of the central processor; and

[0028] Based on the instruction of the central processing unit, at least part of the output power supply voltage signal is controlled.

[0029] According to the central processing unit system and its power management device of the embodiment of the present invention, the power supply required by the central processing unit is integrated in the power management device. Based on the communication between the single power management device and the central processing unit, the power supply requirements of each working module in the central processing unit can be met, which simplifies the power supply structure of the central processing unit, improves its power supply efficiency, greatly reduces costs, and ensures the reliability and safety of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other purposes, features and advantages of the present invention will become more apparent by describing the embodiments of the present invention in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0031] Figure 1 is a schematic principle diagram of a power management device based on a central processing unit according to an embodiment of the present invention;

[0032] Figure 2 is a timing diagram of a power management device according to an embodiment of the present invention;

[0033] Figure 3 is an example of a central processing unit system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical scheme and advantages of the present invention more obvious, the exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments of the present invention, and it should be understood that the present invention is not limited to the exemplary embodiments described herein. Based on the embodiments of the present invention described in the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the protection scope of the present invention.

[0035] At present, the central processing unit has become the most widely used hardware system architecture in the computer field. x86 refers to a series of central processing unit instruction set architectures based on Intel 8086 and backward compatible. It has become the most widely used hardware system architecture in the field of personal hosts and servers. Due to its absolute position in market share, the central processing unit developed based on it can adapt to almost all software and hardware in the field of personal hosts and servers. However, such a highly versatile architecture is not perfect. Due to the lack of uniformity in standards in various fields and insufficient development investment, in its current hardware system, the power management system for its power supply still has not achieved a good degree of integration. For each specific design, a scattered combination of various power supplies must be carried out. Even each voltage must be separately connected to the previous and next stages in order to meet the timing. To meet the needs of the system, many devices need to be stacked, which not only consumes costs and reduces power supply efficiency, but also poses a great risk to the integrity and security of the system.

[0036] Based on the above considerations, a power management device based on a central processing unit according to an embodiment of the present invention is proposed. Figure 1 , Figure 1 FIG. 2 shows a schematic diagram of a power management device based on a central processing unit according to an embodiment of the present invention. Figure 1 As shown, the power management device 100 based on a central processing unit may include:

[0037] A power module 110, used to provide working power for the device 100;

[0038] An output module 120, connected to the power module 110, for converting the working power into different types of power supply voltage signals, and providing them to various types of working modules of the central processor respectively;

[0039] The communication module 130 is connected to at least some of the sub-modules in the output module 120, and is used to receive instructions from the central processor and control the output voltage signals of at least some of the sub-modules based on the instructions.

[0040] Among them, the power management device based on the central processing unit converts the working power into different types of power supply voltage signals, which are respectively provided to various types of working modules of the central processing unit, so that a single power management device can meet various types of power requirements of the central processing unit. The power management technology of the traditional central manager requires the power management function to be built through multiple power chips / peripheral devices, and requires a CPU and a separate embedded controller to perform a large amount of control, and the power supply efficiency is low. In contrast, according to the power management device of the embodiment of the present invention, all power supply modules are integrated into one device, or even packaged into one chip. The power management device can start to supply power to the central processing unit immediately after connecting to the working power supply (i.e., powering on), which greatly improves the power supply efficiency. The central manager only needs to communicate with a single power management device, that is, it can control the power supply voltage signal output by it through instructions, which simplifies the power supply structure of the central processing unit, greatly reduces the cost, and ensures the reliability and safety of the entire system. It is suitable for wide application in any power supply occasion for the central processing unit.

[0041] In some embodiments, the power management device 100 may include a chip.

[0042] In some embodiments, see Figure 1 , the power module 110 may include:

[0043] Pin 1, pin 27, pin 28: VIN12, all 12V voltage input pins, for connecting the power management device 100 to the working power supply;

[0044] Alternatively, see Figure 1 , the output module 120 includes:

[0045] The analog submodule 121 is connected to the power module 110 and is used for converting the working power into at least one analog voltage signal and providing the analog voltage signal to the analog signal module of the central processing unit.

[0046] In some embodiments, the analog submodule 121 may include: outputting one or more analog voltage signals of different voltage levels.

[0047] In some embodiments, see Figure 1 , the simulation submodule 121 may include:

[0048] Pin 4, Pin 5, Pin 6, Pin 7: corresponding to signals V1P0A, V1P8A, V1P2A, V3P3A, which are 1.0V, 1.8V, 1.2V, 3.3V voltage output pins of the power management device 100 respectively, and can be used as analog power supplies for different modules of the CPU.

[0049] Specifically, see Figure 1 , pins 1, 27, and 28 are all connected to the input end of the voltage clamp and buck module 121-0, and the output end of the voltage clamp and buck module 121-0 is respectively connected to the first buck circuit 121-1, the second buck circuit 121-2, the third buck circuit 121-3, and the fourth buck circuit 121-4; and the output end of the first buck circuit 121-1 is connected to pin 4 and the input end of the second buck circuit 121-2, the output end of the second buck circuit 121-2 is connected to pin 5 and the input end of the third buck circuit 121-3, the output end of the third buck circuit 121-3 is connected to pin 6 and the input end of the fourth buck circuit 121-4, and the output end of the fourth buck circuit 121-4 is connected to pin 7.

[0050] Alternatively, see Figure 1 , the output module 120 includes:

[0051] The digital submodule 122 is connected to the analog submodule 121 and is used to convert the at least one analog voltage signal into at least one digital voltage signal and provide the digital voltage signal to the digital signal module of the central processing unit.

[0052] In some embodiments, the digital submodule 122 may include: outputting a digital voltage signal of one or more voltage levels.

[0053] In some embodiments, see Figure 1 , the digital submodule 122 may include:

[0054] Pin 8, pin 9, pin 10, pin 11, pin 12: corresponding signals V1P0S, V1P05S, V1P35S, V1P8S, V3P3S: respectively 1.0V, 1.05V, 1.35V, 1.8V, 3.3V voltage output pins of the power management device 100, which can be used as digital power supplies for different modules of the central processing unit.

[0055] Specifically, see Figure 1, the output end of the first buck circuit 122-1 is connected to the first switch 122-5, the first switch 122-5 also receives a signal from pin 25, and the output end of the first switch 122-5 is connected to pin 8; the output end of the first switch 122-5 and the output end of the second buck circuit 121-2 are both connected to the input end of the first low-voltage dropout linear regulator LDO1, and the output end of the first low-voltage dropout linear regulator LDO1 is connected to pin 9; the output end of the second buck circuit 121-2 and the output end of the first low-voltage dropout linear regulator LDO1 are both connected to The input end of the second low-dropout linear regulator LDO2 and the output end of the second low-dropout linear regulator LDO2 are connected to pin 10; the output end of the second step-down circuit 121-2 and the output end of the second low-dropout linear regulator LDO2 are both connected to the input end of the second switch 122-6, and the output end of the second switch 122-2 is connected to pin 11; the output end of the fourth step-down circuit 121-5 and the output end of the second switch 122-6 are both connected to the input end of the third switch 122-7, and the output end of the third switch 122-7 is connected to pin 12.

[0056] Alternatively, see Figure 1 , at least some of the sub-modules include:

[0057] The non-business submodule 123 is connected to the digital submodule 122 and is used to output at least one non-business voltage signal based on the first instruction of the central processor and provide the non-business voltage signal to the non-business module of the central processor.

[0058] In some embodiments, the non-business module may include a multimedia module and / or a non-core module.

[0059] In some embodiments, see Figure 1 , the non-business submodule 123 may include:

[0060] Pin 16: corresponds to signal V1P0SX, is a 1.0V voltage output pin of the power management device 100, and can be used as a power source for the multimedia module of the CPU;

[0061] Pin 17: corresponds to the signal VSFR pin, is a 1.35V voltage output pin of the power management device 100, and can be used as a power source for a non-core module of the CPU.

[0062] Specifically, see Figure 1The output end of the first low-dropout linear regulator LDO1 is connected to the input end of the fourth switch 122-8, the output end of the second low-dropout linear regulator LDO2 is connected to the input end of the fifth switch 122-9, the input end of the fourth switch 122-8 and the input end of the fifth switch 122-9 both receive the first instruction from the central processor through pin 24, and the output end of the fourth switch 122-8 and the output end of the fifth switch 122-9 are connected to pins 16 and 17 respectively, and the fourth switch 122-8 and the fifth switch 122-9 determine whether to output the corresponding voltage signal based on the first instruction.

[0063] Alternatively, see Figure 1 , at least some of the sub-modules include:

[0064] The memory submodule 124 is connected to the power module 110 and is used to output at least one memory voltage signal based on the third instruction of the central processing unit, and provide the memory voltage signal to the memory module of the central processing unit.

[0065] In some embodiments, see Figure 1 , the memory submodule 124 may include:

[0066] Pin 18: corresponds to the signal VDDQ_VTT, and is a 0.75V voltage output pin of the power management device 100, which can provide a reference voltage power supply for the memory (ie, DDR module) of the CPU;

[0067] Pin 19: corresponds to the signal VDDQ, and is a 1.5V voltage output pin of the power management device 100, and can be used as a voltage power supply for the memory (ie, DDR module) of the CPU.

[0068] Specifically, see Figure 1 The output end of the voltage clamp and step-down module 121-0 is connected to the input end of the fifth step-down circuit 122-10. The input end of the fifth step-down circuit 122-10 also receives the opposite instruction of the instruction of pin 24 (that is, the instruction of pin 24 is logically "opposite" and input into the input end of the fifth step-down circuit 122-10). The output end of the fifth step-down circuit 122-10 is connected to pin 19. The output end of the fifth step-down circuit 122-10 is also grounded through two voltage-dividing resistors R1 and R2. The connection point of the voltage-dividing resistors R1 and R2 is connected to pin 18.

[0069] Alternatively, see Figure 1 , at least some of the sub-modules include:

[0070] The core submodule 125 is connected to the power module 110 and is used to convert the working power into a core voltage signal based on the second instruction of the central processing unit, and provide the core voltage signal to the core module of the central processing unit.

[0071] In some embodiments, see Figure 1 , the core submodule 125 may include:

[0072] Pin 20: corresponds to the signal VCC, which can provide VCORE core voltage for the central processing unit;

[0073] Pin 21: corresponds to the signal VNN, and can provide the VGFX core voltage for the central processing unit.

[0074] Specifically, see Figure 1 The output end of the voltage clamp and step-down module 121-0 is connected to the input end of the sixth step-down circuit 122-11, and the input end of the sixth step-down circuit 122-11 also receives the instruction of pin 25; the first output end of the sixth step-down circuit 122-11 is connected to pin 20, and the second output end of the sixth step-down circuit 122-11 is connected to pin 21.

[0075] Alternatively, see Figure 1 , the communication module 130 includes:

[0076] The status submodule 131 is used to send the working status of the output module of the device to the central processor.

[0077] In some embodiments, see Figure 1 , the state submodule 131 may include:

[0078] Pin 23: corresponds to the signal CORE_PWROK, which is used to communicate with the central processing unit and can be used to notify the central processing unit that all pins have output voltage signals normally.

[0079] Alternatively, see Figure 1 , the communication module 130 includes: a configuration submodule 132, which performs configuration communication with the central processor and receives a configuration communication signal;

[0080] The device 100 further includes: a control module 140 connected to the configuration submodule 132, and configured to control the device and the central processor to configure based on the configuration communication signal.

[0081] In some embodiments, see Figure 1 , the configuration submodule 132 may include:

[0082] Pin 14 and Pin 15 are the communication interfaces of the power management device 100 for configuration communication with the central processing unit.

[0083] In some embodiments, the control module 140 may include: an embedded core processor.

[0084] In some embodiments, the configuration communication may be based on a serial communication protocol. 2 C protocol.

[0085] Specifically, see Figure 1 Pin 14 receives a signal SDA based on a serial communication protocol, and pin 15 receives a signal SCL based on a serial communication protocol, and then sends the signal SDA and the signal SCL to the control module 140 to complete the configuration of the power management device 100 .

[0086] Alternatively, see Figure 1 , the communication module 130 may further include:

[0087] Pin 24: corresponds to signal PMC_SLP_S0#, communicates with the CPU, and can be used to notify the power management device 100 that the CPU enters the S0 state and adjusts the voltage configuration to enter the S0 Mode.

[0088] Among them, the S0 state of the CPU is actually the normal working state, and all devices are working.

[0089] Alternatively, see Figure 1 , the communication module 130 may further include:

[0090] Pin 25: corresponds to signal PMC_SLP_S3#, communicates with the CPU, and can be used to notify the power management device 100 that the CPU enters the S3 state and adjusts the voltage configuration to enter the S3 Mode.

[0091] The CPU's S3 state is Suspend to RAM, which means that all data in the CPU's operation is saved and the system enters a pseudo shutdown state. At this time, except for the memory, all other devices are powered off.

[0092] Alternatively, see Figure 1 , the communication module 130 may further include:

[0093] Pin 26: corresponds to signal PMC_SLP_S4, communicates with the CPU, and can be used to notify the power management device 100 that the CPU enters the S4 state and adjusts the voltage configuration to enter the S4 Mode.

[0094] Among them, the S4 state of the CPU is Suspend to Disk, which means that the data in the memory is completely saved in the Disk, and when the computer is restarted, it is directly read from the Disk to the RAM. To use this mode, a complete and continuous space must be reserved on the Disk.

[0095] In some embodiments, see Figure 1 , the power management device 100 may further include at least one of the following:

[0096] Pin 2: corresponds to signal REG3P3, is the internal 3.3V voltage output pin, and is filtered by an external capacitor;

[0097] Pin 3: corresponds to signal VRTC, powered by an external battery, and is the input voltage of the real-time clock;

[0098] Pin 13: GND pin of the chip, used for grounding;

[0099] Pin 22: corresponds to PMC_PLTRST#, a pin for communicating with the CPU, and can be used as a central processor to reset the power management device 100 (TOTAL RESET).

[0100] Among them, see Figure 1 , pins 1, 27, 28VIN12 and pin 3VRTC in the power management device 100 are powered on, and then pins 4V1P0A, 5V1P8A, 6V1P2A, 7V3P3A and the like output analog voltage signals, and the central processor notifies the power management device 100 that it has entered S4 mode through pin 26PMC_SLP_S4 (the actions of the power management device 100 before the pin 26PMC_SLP_S4 signal can all be operated autonomously without the need for central processor control, so that after pins 1, 27, 28VIN12 are powered on, part of the voltage can be immediately supplied to the central processor, so that some of its functions can work, so as to perform the work in the subsequent state); then pin 19VDDQ of the power management device 100 is output, and the central processor notifies the power management device 100 that it has entered S3 through pin 25PMC_SLP_S3# mode; the chip continues to output voltages such as pin 21VNN, pin 20VCC, pin 8V1P0S, pin 9V1P05S, pin 10V1P35S, pin 11V1P8S, and pin 12V3P3S, and the central processing unit notifies the power management device 100 that it has entered S0 mode through pin 24PMC_SLP_S0#; then the power management device 100 provides the central processing unit with VDDQ_VTT at pin 18, V1P0SX at pin 16, and VSFR at pin 17, and notifies the CPU through pin 23CORE_PWROK that the voltage configuration has been completed.

[0101] It can be seen that the power management device according to the embodiment of the present invention integrates the power supply chip of the central processing unit, which originally required multiple chips and peripheral devices, into one chip. The output state can be controlled by several control pins connected to the central processing unit. At the same time, the power management device core settings can be controlled through the I2C standard communication interface to improve the use effect of the power management device. And the power management device according to the embodiment of the present invention can strictly meet the voltage performance and timing requirements of various central processing units (such as X86 architecture), see Figure 2 , Figure 2 The timing diagram of the power management device according to the embodiment of the present invention is shown. The power management device according to the embodiment of the present invention has a simple structure, high safety and reliability, and the power management chip can start part of the work immediately after power-on, and can meet the power supply demand of the central processor before the control of the central processor, greatly improving the power supply efficiency.

[0102] According to an embodiment of the present invention, a central processing unit system is further provided, the system comprising:

[0103] Central processing unit CPU, used for data processing;

[0104] The power management device according to the embodiment of the present invention is connected to the central processing unit CPU and is used to provide different types of power supply voltage signals to various types of working modules of the central processing unit CPU.

[0105] Optionally, the power management device is further used for:

[0106] providing a power supply voltage signal to at least some modules of the central processor not based on an instruction of the central processor; and

[0107] Based on the instruction of the central processing unit, at least part of the output power supply voltage signal is controlled.

[0108] In some embodiments, see Figure 3 , Figure 3 An example of a central processing unit system according to an embodiment of the present invention is shown. Figure 3 As shown, the central processing unit system 300 includes: a central processing unit CPU; a power management device 310, wherein pin 13GND / pins 1, 27, 28VIN12 of the power management device 310 are respectively connected to the system ground and the working power supply (such as 12V POWER);

[0109] Pins 14 and 15 are connected through I 2C protocol to communicate with the central processing unit CPU, and pins 22-26 are used to communicate with the central processing unit CPU. These pins can be configured with external pull-up or pull-down resistors for the default level configuration;

[0110] Pins 4-12 and 16-21 are output pins for the central processing unit CPU to provide corresponding voltages. The power management device 310 performs timing control for generation and output, supplies power to the central processing unit CPU in turn and enables corresponding modules to work. Appropriate grounded parallel capacitors can be placed at these voltage output pins for filtering.

[0111] In summary, according to the central processing unit system and its power management device in the embodiment of the present invention, the power supply required by the central processing unit is integrated in the power management device. Based on the communication between a single power management device and the central processing unit, the power supply requirements of each working module in the central processing unit can be met, which simplifies the power supply structure of the central processing unit, improves its power supply efficiency, greatly reduces costs, and ensures the reliability and safety of the entire system.

[0112] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0113] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0114] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0115] Similarly, it should be understood that in order to streamline the present invention and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of the present invention should not be interpreted as reflecting the following intention: the claimed invention requires more features than the features explicitly stated in each claim. More specifically, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with less than all the features of a single disclosed embodiment. Therefore, the claims following the specific embodiment are hereby expressly incorporated into the specific embodiment, wherein each claim itself serves as a separate embodiment of the present invention.

[0116] It will be understood by those skilled in the art that, except for mutually exclusive features, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this specification may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.

[0117] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.

[0118] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0119] The above is only a specific embodiment of the present invention or an explanation of a specific embodiment. The protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A power management device based on a central processing unit, characterized in that: The device comprises: A power module, used to provide working power for the device; An output module, connected to the power module, for converting the working power into different types of power supply voltage signals, and providing them to various types of working modules of the central processor respectively; a communication module connected to at least some of the submodules in the output module, configured to receive instructions from the central processor and control output voltage signals of at least some of the submodules based on the instructions; Wherein, the output module includes: an analog submodule, connected to the power module, for converting the working power into at least one analog voltage signal, and providing the analog voltage signal to the analog signal module of the central processing unit; the analog submodule comprises: a fourth pin, a fifth pin, a sixth pin, and a seventh pin; the fourth pin, the fifth pin, the sixth pin, and the seventh pin are respectively different voltage output pins of the power management device, and are configured to serve as analog power supplies for different modules of the central processing unit; A voltage clamp and step-down module, wherein the input end of the voltage clamp and step-down module is connected to the power module; the output end of the voltage clamp and step-down module is respectively connected to the first step-down circuit, the second step-down circuit, and the fourth step-down circuit; the output end of the first step-down circuit is connected to the fourth pin and the input end of the second step-down circuit, the output end of the second step-down circuit is connected to the fifth pin and the input end of the third step-down circuit, the output end of the third step-down circuit is connected to the sixth pin and the input end of the fourth step-down circuit, and the output end of the fourth step-down circuit is connected to the seventh pin.

2. The device according to claim 1, characterized in that The output module comprises: The digital submodule is connected to the analog submodule and is used to convert the at least one analog voltage signal into at least one digital voltage signal and provide the digital voltage signal to the digital signal module of the central processing unit.

3. The device according to claim 2, characterized in that At least some of the submodules include: The non-business submodule is connected to the digital submodule and is used to output at least one non-business voltage signal based on the first instruction of the central processor and provide the non-business voltage signal to the non-business module of the central processor.

4. The device according to claim 1, characterized in that At least some of the submodules include: The core submodule is connected to the power module and is used for converting the working power into a core voltage signal based on the second instruction of the central processing unit, and providing the core voltage signal to the core module of the central processing unit.

5. The device according to claim 1, characterized in that At least some of the submodules include: The memory submodule is connected to the power module and is used to output at least one memory voltage signal based on the third instruction of the central processing unit and provide the memory voltage signal to the memory module of the central processing unit.

6. The device according to claim 1, characterized in that The communication module comprises: The status submodule is used to send the working status of the output module of the device to the central processor.

7. The device according to claim 1, characterized in that The communication module includes: a configuration submodule, which performs configuration communication with the central processor and receives a configuration communication signal; The device further comprises: a control module connected to the configuration submodule, and configured to control the device and the central processor to configure based on the configuration communication signal.

8. A central processing unit system, characterized in that: The system comprises: Central processing unit, used for data processing; The power management device according to any one of claims 1 to 7 is connected to the central processing unit and is used to provide different types of power supply voltage signals to various types of working modules of the central processing unit.

9. The system according to claim 8, characterized in that The power management device is also used for: providing a power supply voltage signal to at least some modules of the central processor not based on an instruction of the central processor; and Based on the instruction of the central processing unit, at least part of the output power supply voltage signal is controlled.

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