Test structure and method of manufacturing the same, semiconductor structure test method using the test structure

Abstract

Embodiments of the present invention relate to test structures, methods of fabricating test structures, and methods of testing semiconductor structures using test structures. A method of testing a semiconductor structure is provided that includes forming a test structure, forming an electrostatic force on a polysilicon structure of the test structure, and measuring a capacitance of the polysilicon structure. In forming the test structure, a first substrate having a first surface is provided, a first trench is formed in the first surface of the first substrate, a polysilicon structure is formed in the first trench, and a second trench is formed in the first surface of the first substrate, leaving the polysilicon structure suspended in the second trench in a side view. The test structure and methods of fabricating the test structure are also provided.

Description

Technical Field

[0001] This invention relates to a test structure and its manufacturing method, a test method using the test structure, and particularly to a semiconductor structure test method using the test structure, the test structure, and the manufacturing method of the test structure. Background Technology

[0002] Polycrystalline silicon is a semiconductor material used to fabricate semiconductor devices, integrated circuits, and solar cells. Structurally, it consists of many single crystals with different crystal orientations and boundaries. In practical applications, using polycrystalline silicon as the gate electrode for metal-oxide-semiconductor (MOS) devices represents a significant advancement in this field due to its superior reliability compared to aluminum electrodes. For instance, it exhibits a longer capacitance breakdown time compared to aluminum electrodes. Furthermore, polycrystalline silicon can serve as a diffusion source to form shallow junctions and ensure ohmic contact with single-crystal silicon. It can also be used to fabricate conductors and high-resistance resistors. Summary of the Invention

[0003] An embodiment of the present invention relates to a semiconductor structure testing method, comprising: forming a test structure, comprising: providing a first substrate having a first surface; forming a first trench on the first surface of the first substrate; forming a polysilicon structure in the first trench; forming a second trench on the first surface of the first substrate, such that the polysilicon structure is suspended in the second trench from a side view angle; forming an electrostatic force on the polysilicon structure of the test structure; and measuring the capacitance value of the polysilicon structure.

[0004] An embodiment of the present invention relates to a method for manufacturing a test structure, comprising: providing a first substrate having a first surface and a second surface relative to the first surface; bonding a second substrate to the second surface of the first substrate; forming a first trench on the first surface of the first substrate; depositing polysilicon in the first trench to form a polysilicon structure; and forming a second trench on the first surface such that one end of the polysilicon structure is connected to the first substrate and the other end is suspended in the second trench.

[0005] One embodiment of the present invention relates to a test structure located within a test block of a wafer, comprising: a polysilicon structure including: a connection portion whose bottom is connected to the wafer; a central portion whose one end is connected to the top of the connection portion; and at least one suspended portion connected to the central portion, which is substantially perpendicular to the central portion in a top view and symmetrical to the central portion. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, the following detailed description is the best way to understand aspects of this disclosure. It should be noted that, in accordance with standard industry practice, the various structures are not drawn to scale. In fact, the dimensions of the various structures can be arbitrarily increased or decreased for clarity of illustration.

[0007] Figure 1A This is a top view of some embodiments of the test structure disclosed herein.

[0008] Figure 1B These are cross-sectional views of some embodiments of the test structure disclosed herein.

[0009] Figures 2A to 2H These are cross-sectional and top views showing structural variations of some embodiments of the manufacturing method of the test structure disclosed herein.

[0010] Figure 3A and Figure 3B These are cross-sectional views of some embodiments of the test structure disclosed herein.

[0011] Figures 4A to 4C These are cross-sectional views of some embodiments of the test structure disclosed herein.

[0012] Figures 5A to 5C These are cross-sectional and top views of some embodiments of the test structure disclosed herein.

[0013] Figures 6A to 6C These are cross-sectional and top views of some embodiments of the test structure disclosed herein.

[0014] Figure 7 This is a top view of some embodiments of the test structure disclosed herein. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples of various components for implementing the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, embodiments in which a first component is formed above or on a second component may include those where the first and second components are formed in direct contact, and embodiments in which additional components may be formed between the first and second components such that the first and second components are not in direct contact. Additionally, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “on,” and similar terms may be used herein to describe the relationship of one element or component to another element or component(s), as illustrated in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise) and therefore the spatial relative descriptors used herein may be interpreted in the same way.

[0017] As used herein, terms such as “first,” “second,” and “third” describe various elements, components, areas, layers, and / or segments, which should not be limited by these terms. These terms may be used only to distinguish one element, component, area, layer, or segment from another. Unless clearly indicated by the context, the use of terms such as “first,” “second,” and “third” herein does not imply sequence or order.

[0018] In some semiconductor processes, polysilicon can be deposited to fill trenches, serving as the primary structure of semiconductor devices. However, with the shrinking of semiconductor dimensions, some deposition techniques, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), may result in rapid polysilicon deposition at the trench opening due to excessively small openings or high aspect ratios. Consequently, the trench may be closed before it is fully filled with polysilicon. This poor step coverage, resulting in suboptimal polysilicon filling, can affect the electrical or mechanical properties of the semiconductor device, and even cause it to fail. However, such structural defects cannot be detected in real-time during semiconductor device manufacturing.

[0019] In view of this, this disclosure provides a method for testing semiconductor structures, a test structure thereof, and a method for manufacturing the test structure thereof, so that the presence of seams inside polysilicon deposited in trenches can be quickly and accurately tested, thereby enabling the control of the production quality of semiconductor structures.

[0020] refer to Figure 1A This is a top view of the deposited polycrystalline silicon structure. As shown, the polycrystalline silicon structure 40 is deposited on the first surface 101 of the first substrate 10. In some embodiments, such as Figure 1B As shown, it is Figure 1AThe cross-sectional view of line segment AA' shows that the polysilicon structure 40 is deposited in at least a first trench 31 on the first surface 101 of the first substrate 10. In some embodiments, the polysilicon structure 40 includes an oxide layer 600 between itself and the first substrate 10 within the first trench 31.

[0021] As previously mentioned, in some cases, the polysilicon structure 40 may form seams or voids within the first trench 31 due to the abnormal morphology of the first trench 31; these will be referred to as seams in this disclosure. The formation of these seams may be caused by various factors. For example, the first trench 31 itself may exhibit a tapered structure with a narrow opening but a wide bottom, making it easy for the opening of the first trench 31 to be closed before the polysilicon structure 40 is deposited, resulting in the polysilicon material failing to fill the first trench 31. Alternatively, in some cases, the side and / or bottom surface contours of the first trench 31 may have uneven features, such as containing a porous surface. This can cause the polysilicon material to fail to form a tight seal at the center of the first trench 31 during deposition, thus failing to fill the first trench 31.

[0022] Given that the polysilicon structure 40 manufactured using conventional techniques cannot be visually inspected for the aforementioned seams immediately after its formation, leading to a decrease in the overall device yield rate after subsequent processes, this disclosure uses an electrostatic force to form on the polysilicon structure 40. By measuring the capacitance change of the polysilicon structure 40 in a timely manner, for example during the Wafer Acceptance Test (WAT) stage or other wafer electrical measurement stages, the presence of seams within the polysilicon structure 40 can be determined, thereby improving the overall device yield rate.

[0023] In some embodiments, this disclosure describes the formation of a test structure first. (See reference...) Figure 2A The first substrate 10 is provided, which has a first surface 101 and a second surface 102 opposite to the first surface 101. In some embodiments, the first substrate 10 comprises silicon.

[0024] refer to Figure 2B In some embodiments, the first trench 31 is formed on the first surface 101 of the first substrate 10 by methods such as dry etching or wet etching. In some embodiments, such as Figure 2C As shown in the top view, the first groove 31 is a single groove structure containing a grid. In some embodiments, the grid-like first groove 31 is symmetrical about both sides along the central axis CC' in the top view.

[0025] refer to Figure 2DAfter the first trench 31 is formed, in some embodiments, an oxide layer 602 is then deposited on the surface of the first trench 31; in some embodiments, the oxide layer 602 also covers the first surface 101. The oxide layer 602 contains an oxide, such as silicon dioxide, which acts as an etch stop layer to protect the subsequently formed polysilicon structure from being damaged by other etching processes.

[0026] refer to Figure 2E After forming the oxide layer 602 in the first trench 31, in some embodiments, polysilicon material is then deposited in the first trench 31 to form a polysilicon structure 40. In this step, the polysilicon material is not only deposited within the first trench 31, but it also further partially covers the first surface 101 of the first substrate 10. However, this polysilicon material protruding above the first surface 101 will be removed in subsequent processes, such as... Figure 2F As shown, in some embodiments, a portion of the polysilicon material is removed via a patterning step to expose the first surface 101 of the first substrate 10. In some embodiments, the polysilicon material above the first surface 101 can be removed via a planarization step, such as chemical mechanical polishing (CMP). In some embodiments, a portion of the polysilicon structure 40, a portion of the oxide layer 602, and a portion of the first surface 101 of the first substrate 10 are removed in the planarization step, such that the first surface 101' of the first substrate 10 after planarization is different from the first surface 101 before planarization.

[0027] refer to Figure 2G In some embodiments, this disclosure further discloses that the polysilicon structure 40 is fabricated as a suspended structure. As shown, after removing a portion of the polysilicon structure 40 to expose the first surface 101' of the first substrate 10, in some embodiments, a second trench 32 is then formed on the first surface 101' of the first substrate 10, such that the polysilicon structure 40 is suspended. Figure 1A The cross-sectional view of line segment AA' shown shows that, except for one end of the polysilicon structure 40 which is supported by the first substrate 10, the other part is suspended within the second trench 32. For example... Figure 2H As shown, the polycrystalline silicon structure 40 is in such a state as Figure 1A The cross-sectional view of line segment BB' shows that, except for one end of the polysilicon structure 40 being supported by the first substrate 10, the other end is suspended within the second trench 32. The cross-section shown by line segment BB' is the center of the polysilicon structure 40. For a detailed explanation, please refer to the following sections. Figure 5B .

[0028] In some embodiments, the second trench 32 is formed by wet etching to remove the first substrate 10 structure located beneath the polysilicon structure 40. In some embodiments, the oxide layer 602 covering the sides and bottom of the polysilicon structure 40 protects the polysilicon structure 40 from the effects of wet etching forming the second trench 32. In some embodiments, the aspect ratio of the second trench 32 is approximately 30:1.

[0029] refer to Figure 3A In some embodiments, the first substrate 10 may further include an oxide layer 601 below the polysilicon structure 40 to control the depth of the second trench 32 formed during the etching step. In some embodiments, such as Figure 3B As shown, the oxide layer 601 may have patterned structural features and be interspersed in the vertical direction with the polysilicon structure 40. That is, the oxide layer 601 may not be included below the projection of the polysilicon structure 40, so that the second trench 32 may have different depths in different regions.

[0030] refer to Figure 4A In some embodiments, the oxide layer 601 may be provided by the second substrate 20. For example, the second substrate 20 has a third surface 203 and a fourth surface 204 opposite to the third surface 203. The second substrate 20 is bonded to the second surface 102 of the first substrate 10 with the third surface 203, and the oxide layer 601 is formed on the third surface 203 of the second substrate 20 before the first substrate 10 and the second substrate 20 are bonded. (See reference...) Figure 4B In some embodiments, the third surface 203 has a plurality of patterned holes 203A that are not covered by the oxide layer 601. In some embodiments, the patterned holes 203A are vertically aligned with portions of the polysilicon structure 40 to allow the polysilicon structure 40 to be suspended within the second trench. (See reference...) Figure 4C In some embodiments, the patterned holes 203A are integrated into the second trench 32 during the etching process to form the second trench 32, as a portion of the first substrate 10 is etched away. In other words, the etching process to form the second trench 32 involves etching through the first substrate 10, exposing the patterned holes 203A located on the third surface 203 of the second substrate 20. In some embodiments, the oxide layer 601 and the oxide layer 602 are made of the same material.

[0031] Through the above steps, the second trench 32 is used to make the polysilicon structure 40, except for the connecting portion 401 (as described later), […]. Figure 5B (As shown), all other structures are suspended within the second groove 32. In some embodiments, refer to Figure 5A as well as Figure 5B ,in Figure 5B It is Figure 5AThe polysilicon structure 40 is shown separately. As shown, the polysilicon structure 40 includes a connecting portion 401 supported by a first substrate 10; a central portion 402, one end of which is connected to the connecting portion 401 and the other end of which is suspended in a second trench 32; and at least one suspended portion 403 connected to the central portion 402, which is substantially perpendicular to the central portion 402 in a top view and is symmetrical on both sides of the central portion 402.

[0032] refer to Figure 5B as well as Figure 5C ,in Figure 5C It is a local magnification of itself Figure 4C In region 5C, in some embodiments, the bottom surface 401A and the three side surfaces 401B of the connection portion 401 are in contact with the first substrate 10 via the oxide layer 602 covering the surface. Therefore, the weight of the polysilicon structure 40 is not only supported by the first substrate 10 through the connection portion 401, but the first substrate 10 also restricts the deformation direction of the polysilicon structure 40. That is, when the polysilicon structure 40 deforms, for example, when its structure expands, it will shift in the opposite direction D to the connection portion 401. In other words, the connection portion 401 of the polysilicon structure 40 is a fixed end, while the direction opposite to the connection portion 401 is a free end.

[0033] As previously mentioned, in some embodiments, the first trench 31 for forming the polysilicon structure 40 includes a gate-like structure. Therefore, the polysilicon structure 40 deposited in the first trench 31 also includes a gate-like structure, which is symmetrical about the central portion 402. In some embodiments, both the central portion 402 and the suspended portion 403 are suspended in the second trench 32, thus allowing displacement relative to the connecting portion 401 when subjected to force.

[0034] In this disclosure, the test structure containing the polysilicon structure 40 can be fabricated simultaneously with semiconductor devices in other regions (e.g., device regions) on the first substrate 10, or fabricated under the same conditions and parameters. In other words, the deposition steps in the formation process of the test structure containing the polysilicon structure 40 are substantially equivalent to the polysilicon material deposition steps, deposition conditions, and geometry of semiconductor devices in other regions. Thus, by testing whether there are seams inside the test structure containing the polysilicon structure 40, it can be inferred whether there are seams inside the polysilicon deposition structure of semiconductor devices in other regions on the first substrate 10, serving as a reference for whether to proceed with subsequent processes.

[0035] Regarding the method for testing whether the polysilicon structure 40 has seams, in some embodiments of this disclosure, an electrostatic force is generated by applying a voltage to the silicon plate surrounding the polysilicon structure 40, and the structure of the polysilicon structure 40 is measured under the influence of the electrostatic force to determine whether the polysilicon structure 40 has structural deformation due to the presence of internal seams, resulting in an increase in the capacitance of the polysilicon structure 40. This allows for the determination of whether the polysilicon deposition structure containing the test structure of the polysilicon structure 40 and the semiconductor elements in other areas on the first substrate 10 have seams.

[0036] In some embodiments disclosed herein, reference is made to Figure 6A The process includes etching the first surface 101 of the first substrate 10 to form a plurality of first fins 501 and a plurality of second fins 502, wherein the first fins 501 and the second fins 502 are parallel in plan view. In some embodiments, the formation of the first fins 501 and the second fins 502 is performed in the same step as the formation of the second trench 32, that is, through a patterning step, a portion of the first substrate 10 is etched away, and the remaining portion of the first substrate 10 can be used to form a plurality of first fins 501 and a plurality of second fins 502 standing upright within the second trench 32.

[0037] In some embodiments, at least one first fin 501 and one second fin 502 are included between any two adjacent suspended portions 403 of the polysilicon structure 40. In some embodiments, the first fin 501, the second fin 502, and the suspended portions 403 of the polysilicon structure 40 are parallel to each other from a top-view perspective. In some embodiments, the spacing between any suspended portion 403 of the polysilicon structure 40 and its adjacent first fins 501 and second fins 502 on both sides is the same. In some embodiments, reference... Figure 6B , it is Figure 6A The cross-sectional view of line segment EE' shows that the height H1 of the first fin 501 and the second fin 502 is approximately 150-200 micrometers (μm), and the width W1 of each is approximately 5 micrometers.

[0038] In addition to the first fin 501 and the second fin 502, in some embodiments, a third fin 503 may be formed simultaneously on the etched portion of the first substrate 10. This third fin 503 is adjacent to the suspended portion 403 of the polysilicon structure 40 and away from the connection portion 401 of the polysilicon structure 40. In some embodiments, the third fin 503 has a length L1 that is greater than the length L2 of any suspended portion 403 of the polysilicon structure 40.

[0039] The semiconductor structure testing method disclosed herein generates electrostatic force on the polysilicon structure by applying voltage to the first fin 501 and the second fin 502 after forming a test structure including a suspended portion. In some embodiments, the electrostatic force is generated by providing a voltage to the first fin 501 or the second fin 502, and causing the first fin 501 and the second fin 502 to have different potentials. For example, a DC voltage of about 50 volts (V) is applied to the first fin 501 and the second fin 502 is grounded; or the first fin 501 is grounded and a voltage is applied to the second fin 502. In some embodiments, the third fin 503 is subjected to the same voltage as the first fin 501; in other embodiments, the third fin 503 is subjected to the same voltage as the second fin 502.

[0040] By applying a voltage to either the first fin 501 or the second fin 502 and grounding the other, any suspended portion 403 of the polysilicon structure 40 will be adjacent to the fins with different potentials. The electric field generated by the fins can then produce an electrostatic force on the suspended portion 403 between the fins. If the polysilicon structure 40 has a seam inside, the suspended portion 403 will be displaced by the electrostatic force. In some embodiments, to achieve force balance, the polysilicon structure 40 with seams will deform; that is, to balance the tensile forces from both sides of the suspended portion 403, the seam within the suspended portion 403 will widen, increasing the width W2 of the suspended portion 403. As mentioned earlier, the polysilicon structure 40 includes a connecting portion 401 as a fixed end and a free end in the opposite direction to the connecting portion 401. Therefore, when the width of the suspended portion 403 increases, the polysilicon structure 40 will exhibit displacement towards the free end. In some embodiments, the polysilicon structure 40 includes a plurality of suspended portions 403. When there is a seam inside the suspended portion 403, any suspended portion 403 will be affected by the electric field generated by the fins on both sides, causing deformation to be generated in order to balance the electrostatic force, and accumulating a total displacement in the direction of the free end.

[0041] For example, when any suspended part experiences a deformation of approximately 0.04 to 0.06 micrometers due to the widening of the internal seams, such as... Figure 6CAs shown, when seams exist inside the first suspended portion 403A, the second suspended portion 403B, and the third suspended portion 403C, when a voltage is applied to the first fin 501 or the second fin 502 (the same voltage is applied to the third fin 503), the first suspended portion 403A will have a displacement of about 0.05 micrometers at its center point during the step of providing electrostatic force to the polycrystalline silicon structure of the test structure disclosed in this paper, with the displacement direction opposite to that of the connecting portion 401; the second suspended portion 403B itself will also generate a displacement of about 0.05 micrometers, and there will actually be a cumulative displacement of about 0.10 micrometers at its center point; the third suspended portion 403C itself will also generate a displacement of about 0.05 micrometers, and there will actually be a cumulative displacement of about 0.15 micrometers at its center point, and so on. In other words, in the step of providing electrostatic force, the suspended portion farther away from the connection portion 401 can exhibit a greater displacement due to its own deformation and the pushing from the suspended portion closer to the connection portion 401.

[0042] However, in order to quickly and conveniently determine whether there are seams inside a polycrystalline silicon structure, in addition to detecting the displacement of the polycrystalline silicon structure below the micrometer level as a test indicator, this disclosure further proposes to measure the capacitance value of the polycrystalline silicon structure after being subjected to electrostatic force as a basis for determining whether seams exist. In some embodiments of this disclosure, a reference capacitance value C0 of the polycrystalline silicon structure 40 is obtained before the step of applying electrostatic force, and then the reference capacitance value C0 is compared with the capacitance value C1 of the polycrystalline silicon structure after being subjected to electrostatic force, thereby obtaining the capacitance change value C. v Since the increase in the width of the suspended portion 403 will simultaneously lead to an increase in the capacitance of the polysilicon structure 40, when the capacitance changes by value C... v The value is not zero, or in some embodiments, the capacitance change value C v When the value is positive, it indicates that there are seams inside the polycrystalline silicon structure 40. Therefore, when subjected to electrostatic forces, deformation occurs, leading to a change in capacitance. Conversely, if the capacitance change value C... v If the value is zero, it means that there are no seams inside the polysilicon structure 40. Therefore, its suspended part 403 will not deform in order to achieve force balance. Thus, the capacitance of the polysilicon structure 40 will not change before and after being provided with electrostatic force, or it will only change within the range of measurement error value.

[0043] The semiconductor structure testing method disclosed herein can quickly, conveniently, and directly determine the deposition quality of polysilicon material when filling trenches by measuring capacitance changes using conventional capacitance measurement techniques. In some embodiments, this testing method can determine whether seams have formed in the polysilicon material of other semiconductor elements on the wafer during deposition in the trenches by fabricating a test structure on the wafer. Due to cost considerations, the semiconductor industry is committed to increasing the density and number of semiconductor elements that can be placed on a wafer; therefore, in some embodiments of this disclosure, the test structure containing the polysilicon structure used for testing seams is disposed in a non-element region. Reference Figure 7 In some embodiments, the test structure is disposed within the test block 701. In some embodiments, the test block is located on the scribe line 702 of the wafer 70, and the scribe line 702 is located between adjacent component regions 703. In some embodiments, the test structure is integrated into the process control monitor (PCM) structure, that is, integrated with the test units required for other testing processes within the test block 701, effectively testing the electrical parameters of the semiconductor components on the wafer, such as resistance and voltage, related to whether the semiconductor components can operate normally, during stages such as wafer acceptability testing (WAT), thereby determining the quality of the process.

[0044] In some embodiments, this disclosure is completed simultaneously with the trench filling step of the polysilicon material of the semiconductor device, or the actual filling quality of the semiconductor device is replicated using the same parameters. This allows for the inference of whether seams exist in the corresponding polysilicon structure of the semiconductor device by analyzing the capacitance change of the test structure. Therefore, the testing method disclosed herein can be performed after the test structure is manufactured, without waiting for the semiconductor device on the wafer to complete all its structures. This allows for early, rapid, and accurate determination of process quality in the early stages of the process, providing greater flexibility in controlling the yield rate.

[0045] In one exemplary aspect, a method for testing a semiconductor structure is provided. It includes the steps of: forming a test structure, comprising: providing a first substrate having a first surface; forming a first trench on the first surface of the first substrate; forming a polysilicon structure in the first trench; and forming a second trench on the first surface of the first substrate, such that the polysilicon structure is suspended within the second trench in a side view; forming an electrostatic force on the polysilicon structure of the test structure; and measuring the capacitance value of the polysilicon structure.

[0046] In another exemplary aspect, a method for manufacturing a test structure of a semiconductor structure is provided. It includes the steps of: providing a first substrate having a first surface and a second surface opposite to the first surface; bonding a second substrate to the second surface of the first substrate; forming a first trench on the first surface of the first substrate; depositing polysilicon in the first trench to form a polysilicon structure; and forming a second trench on the first surface such that one end of the polysilicon structure is connected to the first substrate and the other end is suspended in the second trench.

[0047] In another exemplary aspect, a test structure for a semiconductor structure is provided, located within a test block of a wafer, comprising: a polysilicon structure including: a connection portion whose bottom is connected to the wafer; a central portion whose one end is connected to the top of the connection portion; and at least one suspended portion connected to the central portion, which is substantially perpendicular to the central portion in a top view and symmetrical to the central portion.

[0048] The foregoing outlines the structures of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits as the embodiments described herein. Those skilled in the art will also understand that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0049] Symbol Explanation

[0050] 5C: Region

[0051] 10: First substrate

[0052] 20: Second substrate

[0053] 31: First trench

[0054] 32: Second trench

[0055] 40: Polycrystalline silicon structure

[0056] 70: Chip

[0057] 101: First Surface

[0058] 102: Second Surface

[0059] 203: Third Surface

[0060] 203A: Patterned Holes

[0061] 204: Fourth Surface

[0062] 401: Connecting part

[0063] 401A: Bottom surface

[0064] 401B: Side View

[0065] 402: Central Section

[0066] 403: Suspended section

[0067] 403A: First Suspended Section

[0068] 403B: Second Suspended Section

[0069] 403C: Third Suspended Section

[0070] 501: First fin

[0071] 502: Second fin

[0072] 503: Third fin

[0073] 600: Oxide layer

[0074] 601: Oxide layer

[0075] 602: Oxide layer

[0076] 701: Test Block

[0077] 702: Cutting Track

[0078] 703: Component Area

[0079] AA': line segment

[0080] BB': line segment

[0081] CC': Central axis

[0082] D: Direction

[0083] EE': line segment

[0084] L1: Length

[0085] L2: Length

[0086] W1: Width.

Claims

1. A semiconductor structure testing method, comprising: The test structure comprises: A first substrate is provided, having a first surface; The first trench is formed on the first surface of the first substrate; A polycrystalline silicon structure is formed in the first trench; as well as A second trench is formed on the first surface of the first substrate, and the polysilicon structure is suspended in the second trench from a side view angle, wherein both the first trench and the second trench are formed downward from the first surface of the first substrate within the first substrate. Electrostatic forces are formed on the polycrystalline silicon structure of the test structure; and Measure the capacitance value of the polycrystalline silicon structure.

2. The test method according to claim 1, further comprising: Before the electrostatic force is formed, a reference capacitance value for the polycrystalline silicon structure is obtained; and The capacitance value is compared with the reference capacitance value to obtain the capacitance change value.

3. The test method according to claim 2, further comprising: Based on the capacitance change value, it is determined whether the polycrystalline silicon structure contains seams.

4. The test method according to claim 1, further comprising: The first substrate is etched from the first surface to form a plurality of first fins and a plurality of second fins; and A voltage is applied to the first fin or the second fin to generate the electrostatic force; in, The first fin and the second fin are parallel when viewed from above.

5. A method for manufacturing a test structure, comprising: A first substrate is provided, having a first surface and a second surface relative to the first surface; The second substrate is bonded to the second surface of the first substrate; The first trench is formed on the first surface of the first substrate; Polycrystalline silicon is deposited in the first trench to form a polycrystalline silicon structure; as well as A second trench is formed on the first surface, such that one end of the polysilicon structure is connected to the first substrate and the other end is suspended in the second trench, wherein both the first trench and the second trench are formed downward from the first surface of the first substrate within the first substrate.

6. The manufacturing method of claim 5, wherein the second substrate has a third surface and a fourth surface relative to the third surface, the second substrate being bonded to the second surface of the first substrate with the third surface, wherein prior to the step of forming the second trench, a portion of the polysilicon is removed to expose the first surface.

7. A test structure located within a test block of a wafer, wherein the test block is located on a dicing track of the wafer, the test structure comprising: A substrate comprising at least one first fin and at least one second fin connected to the wafer within the test block; A polycrystalline silicon structure comprising: The connecting part, the bottom of which is connected to the chip; The central portion, one end of which is connected to the top of the connecting portion; and Multiple suspended portions are connected to the central portion, are generally perpendicular to the central portion in a top view, and are symmetrical to the central portion, wherein at least one first fin and one second fin are included between any two adjacent suspended portions.

8. The test structure according to claim 7, wherein the side surfaces and bottom surfaces of the polycrystalline silicon structure have an oxide layer.

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