Photodetector array with diffraction gratings of varying spacing

Abstract

The present disclosure relates to a photodetector array having diffraction gratings with different spacings. A photodetector array includes: a substrate; and a pixel array located above the substrate. Each pixel includes a set of diffraction gratings located directly on a semiconductor photodetector. The set of diffraction gratings associated with each pixel in the pixel array has a different spacing, so that each pixel can detect light of a specific wavelength different from other pixels in the pixel array. An air cavity can be provided in the substrate below the germanium photodetector to improve light absorption. A method of forming the photodetector array is also disclosed.

Description

Technical Field

[0001] The present disclosure relates to photodetector arrays, and more particularly, to photodetector arrays comprising an array of pixels positioned above a substrate, wherein each pixel comprises a set of diffraction gratings positioned on a semiconductor photodetector. Background Art

[0002] Photodetector arrays are used in photonic integrated circuits to convert light into electrical signals. One challenge with current photodetector arrays is their inability to selectively absorb and convert incident optical signals (light) with different wavelengths. Current photodetector arrays also use silicon diffraction gratings inline with the optical signal, which produces back reflections. Summary of the Invention

[0003] One aspect of the present disclosure relates to a structure comprising: a substrate; and a pixel array located above the substrate, each pixel comprising a set of diffraction gratings located directly on a semiconductor photodetector, wherein a spacing of the set of diffraction gratings associated with each pixel in the pixel array is different so that each pixel can detect light of a specific wavelength different from other pixels in the pixel array.

[0004] Another aspect of the present disclosure includes a structure comprising: a substrate; a pixel array located above the substrate, each pixel comprising a set of diffraction gratings located directly on a semiconductor photodetector, wherein each set of diffraction gratings comprises one of polysilicon and silicon; trench isolation located around each semiconductor photodetector; and an air cavity in the substrate below at least one semiconductor photodetector, wherein a spacing of the set of diffraction gratings associated with each pixel in the pixel array is different so that each pixel can detect light of a specific wavelength different from other pixels in the pixel array so that the pixel array absorbs more than one wavelength of light.

[0005] One aspect of the present disclosure relates to a method comprising forming a pixel array on a substrate by forming an array of semiconductor photodetectors on the substrate, the array of semiconductor photodetectors being surrounded by trench isolation; and forming a set of diffraction gratings directly on each semiconductor photodetector to create the pixel array, wherein a spacing of the set of diffraction gratings associated with each semiconductor photodetector is different so that each pixel can detect light of a specific wavelength that is different from other pixels in the pixel array.

[0006] The foregoing and other features of the present disclosure will become apparent from the following more particular description of embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like reference numerals represent like elements, and wherein:

[0008] Figure 1 A perspective view of a photodetector array including multiple sets of diffraction gratings having different pitches is shown according to an embodiment of the present disclosure.

[0009] Figure 2 The embodiment according to the present disclosure is shown Figure 1 A plan view of a similar photodetector array but including semiconductor photodetectors with doped regions.

[0010] Figure 3 A perspective view of a photodetector array including multiple sets of diffraction gratings with different pitches and air cavities thereunder is shown according to other embodiments of the present disclosure.

[0011] Figure 4 A perspective view of a photodetector array including multiple groups of diffraction gratings with different pitches and air cavities thereunder according to further embodiments of the present disclosure is shown.

[0012] Figure 5 A cross-sectional view of a pixel of a photodetector array according to an embodiment of the present disclosure is shown.

[0013] Figure 6 A cross-sectional view of a pixel including a PIN semiconductor photodetector according to an alternative embodiment of the present disclosure is shown.

[0014] Figure 7 A cross-sectional view of an avalanche photodetector pixel including a PIPN semiconductor photodetector according to an alternative embodiment of the present disclosure is shown.

[0015] Figure 8 A cross-sectional view of a pixel having a set of diffraction gratings above a base layer is shown according to an alternative embodiment of the present disclosure.

[0016] Figure 9 A cross-sectional view of a pixel including a set of diffraction gratings having non-uniform spacing is shown according to an alternative embodiment of the present disclosure.

[0017] Figure 10 A cross-sectional view illustrating a preliminary structure of a method for forming a photodetector array according to an embodiment of the present disclosure.

[0018] Figure 11 A cross-sectional view illustrating forming an air cavity in a preliminary structure according to an embodiment of the present disclosure.

[0019] Figure 12 A cross-sectional view illustrating forming an air cavity having a plurality of connected air cavities according to an embodiment of the present disclosure is shown.

[0020] Figure 13 A cross-sectional view of forming a semiconductor photodetector layer according to an embodiment of the present disclosure is shown.

[0021] Figure 14 A cross-sectional view of a sealed air cavity is shown according to an embodiment of the present disclosure.

[0022] Figure 15 A perspective view of a patterned semiconductor photodetector layer for a pixel array according to an embodiment of the present disclosure is shown.

[0023] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, similar reference numerals represent similar elements between the drawings. DETAILED DESCRIPTION

[0024] In the following description, reference is made to the accompanying drawings, which form a part of the specification, and in which are shown by way of illustration specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is understood that other embodiments may be used and changes may be made without departing from the scope of the present teachings. Therefore, the following description is illustrative only.

[0025] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0026] References in the specification to "one embodiment" or "an embodiment" of the present disclosure and other variations thereof mean that the particular features, structures, characteristics, etc. described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment" and any other variations appearing throughout the specification do not necessarily refer to the same embodiment. It should be understood that the use of any of " / ", "and / or", and "at least one" in the contexts of, for example, "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As another example, in the case of "A, B, and / or C" and "at least one of A, B, and C," these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to one of ordinary skill in the art, this scenario can be extended to many of the listed options.

[0027] Embodiments of the present disclosure provide a photodetector array comprising a substrate and a pixel array located above the substrate. Each pixel includes a set of diffraction gratings located directly on a semiconductor photodetector. Thus, the diffraction gratings are integrated with the semiconductor photodetector. The spacing of the diffraction grating sets associated with each pixel in the pixel array is different, so that each pixel can detect light of a specific wavelength that is different from other pixels of the pixel array. Thus, the semiconductor photodetector can be used as an optical signal separator. An air cavity can be provided in the substrate below the semiconductor photodetector to improve light absorption. A method of forming a photodetector array is also disclosed. The semiconductor photodetector can be used as part of a photonic integrated circuit (PIC) on a complementary metal oxide semiconductor (CMOS) compatible semiconductor photonic chip that may include integrated electronics.

[0028] Figure 1 shows a perspective view of a photodetector array 100 according to an embodiment of the present disclosure, Figure 2 1 shows a plan view of the photodetector array 100. The photodetector array 100 may include a substrate 102. The substrate 102 may include a semiconductor substrate 104, which may include but is not limited to silicon, germanium, silicon germanium, silicon carbide, and a semiconductor material having a chemical formula of Al X1 Ga X2 In X3 As Y1 P Y2 NY3 Sb Y4 Those composed of one or more III-V compound semiconductors of a defined composition, wherein X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions, which are respectively greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 is the total relative molar amount). Other suitable substrates include those with a composition of Zn A1 Cd A2 Se B1 Te B2 II-VI compound semiconductors, wherein A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1+A2+B1+B2=1 (1 is the total molar amount). In addition, part or all of the semiconductor substrate may be strained. Although not shown, other regions of the substrate 102 may include any type of integrated electronic devices located thereon, such as transistors, resistors, capacitors, inductors, etc., as well as any type of interconnects.

[0029] The photodetector array 100 may also include a pixel array 108 located above the substrate 102. For descriptive purposes, four pixels 110A-D are shown in the array. It is emphasized that according to embodiments of the present disclosure, any number of pixels 110 may be provided in the array. The pixels 110 may be arranged in any desired manner. Each pixel 110 includes a set of diffraction gratings 112 located directly on a semiconductor photodetector 114. A diffraction grating is an optical device having periodic grating elements 116 that split and diffract an optical signal (e.g., light) into several separate beams based on wavelength. The pitch P1-P4 of the diffraction grating set 112 is the spacing between the individual grating elements 116. The pitch of the diffraction grating determines the wavelength of the optical signal that can pass therethrough to be absorbed by the semiconductor photodetector 114 and converted into an electrical signal. The semiconductor photodetector 114 may include, but is not limited to, germanium (Ge), silicon (Si), or silicon germanium (SiGe). According to an embodiment of the present disclosure, the pitches P1-P4 of the diffraction grating group 112 associated with each pixel 110A-D in the pixel array 108 are different, so that each pixel 110 can detect light of a specific wavelength different from the other pixels 110 of the pixel array 108. For example, pixel 110D can have a pitch of 390 nanometers (nm), pixel 110C can have a pitch of 400 nm, and pixel 110B can have a pitch of 410 nm. The pixel array 108 can thus absorb light of more than one wavelength. In this way, the photodetector array 100 can act as an optical signal separator, thereby isolating any number of desired specific wavelengths of light.

[0030] Each set of diffraction gratings 112 may include grating elements 116 comprising silicon or polysilicon. The diffraction grating set 112 may be formed along with other layers of selected materials as part of the formation of integrated electronic devices in other areas of the substrate 102. Each pixel 110 may be optically and electrically separated from adjacent pixels 110 by trench isolation 120. The trench isolation 120 may be formed of any now known or later developed material for providing electrical and / or optical insulation, and may include, for example, silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon oxycarbon (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicates) comprising silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H) atoms, thermosetting polyarylene ether, spin-on silicon-carbon polymer materials, near frictionless carbon (NFC), or layers thereof.

[0031] Figure 3-4 A perspective view of an embodiment of a photodetector array 100 is shown, wherein the photodetector array 100 includes an optional air cavity 130 in the substrate 102 underlying at least one semiconductor photodetector 114 . Figure 3 The air cavity 130 is shown as a single integral air cavity 132 in the substrate 102, while Figure 4 The air cavity 130 is shown as a plurality of connected air cavities 134. The air cavity 130 receives light that passes through the semiconductor photodetector 114 and reflects the light back to the semiconductor photodetector 114 for additional absorption by the underside 136 of the semiconductor photodetector 114. The wavelength of the reflected light has been selected by a set of diffraction gratings 112. Figure 1-4 As shown, semiconductor photodetector 114 is planar. Figure 5 Pixel 110 (eg Figure 3 ), which shows that the incident light is directed through the planar semiconductor photodetector 114 in a planar manner. In this way, as shown Figure 5 As shown by the arrows in , light incident on pixel 110 need not be perpendicular thereto and travels parallel to substrate 102. That is, incident light of a target wavelength originating from outside the page (i.e., not from a laser or waveguide co-linear with the photodetector array) is redirected to travel in-plane with semiconductor photodetector 114. The incident light can (and preferably does) be perpendicular to the surface of the photodetector array, but this is not required.

[0032] Although Figure 5 Pixel 110 is shown with air cavity 130, but it is emphasized that Figure 5 The teachings of the present invention can be applied to any embodiment, such as one without air cavity 130. Figure 1 An embodiment of, or as Figure 4 As shown, the air cavity 130 includes a plurality of connected air cavities 134 .

[0033] Figure 6-9 An enlarged cross-sectional view of a pixel 110 is shown according to various alternative embodiments. Figure 2 and 6 Pixel 110 is shown having a semiconductor photodetector 114 that includes a p-type doped region 140 separated from an n-type doped region 142 by an intrinsic region 144 (which is undoped). P-type doped region 140, intrinsic region 144, and n-type doped region 142 (forming a PIN junction) are desirable for at least one pixel 110 in pixel array 108 to form a photodetector, i.e., to allow detection of an electric current generated by absorption of incident photons of the appropriate wavelength. Figure 7 Pixel 110 is shown having a semiconductor photodetector 114 including a first p-type doped region 146 separated from a second p-type doped region 148 by an intrinsic region 150, and an n-type doped region 152 adjacent to one of the first and second p-type doped regions 146, 148 (shown as 148). The p-type doped region 146, the intrinsic region 150, the p-type doped region 148, and the n-type doped region 152 (forming a PIPN avalanche photodetector) are desirable for at least one pixel 110 in the pixel array 108 to form an avalanche photodiode, i.e., to allow detection of a current generated by absorption of incident photons of the appropriate wavelength (amplified by the PN junction). Figure 8 A pixel 110 is shown including a set of diffraction gratings 112 comprising a base layer 160 positioned on a semiconductor photodetector 114 and a plurality of diffraction grating elements 162 extending from the base layer 160. Here, the grating elements 162 may be partially etched, leaving the base layer 160.

[0034] Figure 9 A pixel 110 is shown in which the spacing of a set of diffraction gratings 112 is non-uniform. In the non-limiting example shown, all pitches P5-P9 are of different sizes and are not equal; however, any non-uniform spacing may be employed. The non-uniform spacing is desirable for at least one pixel 110 in the pixel array 108 in order to diffract a wider bandwidth of light for the selected pixel 110. In this manner, the photodetector array 100 can isolate light of any desired specific bandwidth (wavelength range), such as 390-400 nm, 420-440 nm, etc., as an alternative to or in addition to light of a specific wavelength.

[0035] Any number of pixels 110 in pixel array 108 may include information about Figure 6-9 The alternative embodiments described, for example, at least one of the alternative embodiments. Figure 6-9Pixel 110 is shown with air cavity 130, but it is emphasized that Figure 6-9 The teachings of the present invention can be applied to any embodiment, such as one without air cavity 130. Figure 1 An embodiment of, or as Figure 4 As shown, the air cavity 130 includes a plurality of connected air cavities 134 .

[0036] Figure 1-4 and Figure 10-15 A method of forming a photodetector array 100 according to an embodiment of the present disclosure is shown. More specifically, Figure 1-4 and Figure 10-15 A pixel array 108 is shown formed on a substrate 102 , including an array of corresponding semiconductor photodetectors 114 .

[0037] Figure 10-14 A cross-sectional view is shown of an array of air cavities 130 optionally formed in the substrate 102 prior to forming the array of semiconductor photodetectors 114 . Figure 10 A preliminary structure is shown including a substrate 102 having a patterned hard mask 170 thereon, and the formation of a preliminary air cavity opening 172. Hard mask 170 may comprise any now known or later developed hard mask material, such as silicon nitride, and may be patterned using any technique, such as masked exposure and etching. Opening 172 may be formed by additional etching into substrate 102.

[0038] Etching generally refers to the removal of material from a substrate (or structures formed on it) and is typically performed using a mask in place to selectively remove material from specific areas of the substrate while leaving material in other areas unaffected. There are two common types of etching: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (e.g., an acid) that is chosen for its ability to selectively dissolve a given material (e.g., an oxide) while leaving another material (e.g., polysilicon) relatively intact. This ability to selectively etch a given material is fundamental to many semiconductor manufacturing processes. Wet etching typically etches homogeneous materials (e.g., oxides) isotropically, but wet etching can also anisotropically etch single-crystalline materials (e.g., silicon wafers). Dry etching can be performed using plasma. Plasma systems can operate in several modes by adjusting plasma parameters. Conventional plasma etching generates neutrally charged, high-energy radicals that react on the wafer surface. Because the neutral particles attack the wafer from all angles, the process is isotropic. Ion milling or sputter etching bombards the wafer with high-energy ions of a noble gas. These ions approach the wafer from roughly one direction, making the process highly anisotropic. Reactive ion etching (RIE), operating under conditions between sputtering and plasma etching, can be used to create deep, narrow features, such as STI trenches. RIE can be used in this process.

[0039] Figure 10 Also shown is the formation of a liner oxide 174 in the preliminary cavity opening 172. The liner oxide 174 can be formed, for example, by thermal growth or deposition of an oxide, followed by a directional etch that removes the lower portion of the liner oxide. The latter etch leaves the oxide liner 174 only on the sidewalls 176 of the preliminary cavity opening 172. "Deposition" can include any now known or later developed technique suitable for the material to be deposited, including, but not limited to, chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), sub-atmospheric pressure CVD (SACVD), high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction process CVD (LRPCVD), metal organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin coating, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), electroplating, and evaporation. Here, ALD may be used for the oxide liner 174 .

[0040] In such Figure 11Following the bottom clean shown to partially enlarge the opening 172 below the oxide liner 174, additional etching creates the air cavity 130. Here, the etching may include a non-directional wet etch.

[0041] Figure 12 An alternative embodiment is shown, wherein forming the air cavity 130 includes forming a plurality of connected air cavities 134. Here, the connected air cavities 134 are formed by repeating the air cavity 130 relative to the air cavity 134 at multiple locations simultaneously. Figure 10 and Figure 11 The above process described above is created to form a plurality of adjacent, connected air cavities 134 .

[0042] Figure 1 、 13 -15 shows an array forming the semiconductor photodetector 114. Figure 13 The hard mask 170 ( Figure 11 ) and removal of oxide lining 174 ( Figure 11 ) followed by forming a germanium layer 178. The hard mask 170 and the oxide liner 174 may be removed using any suitable stripping process (eg, ashing). The germanium layer 178 may be formed, for example, by deposition or epitaxial growth. Figure 14 The germanium layer 178 is shown to be thermally annealed, which causes it to plug or seal the opening 172 of the air cavity 130 in the substrate 102 ( Figure 10 ). In this manner, each semiconductor photodetector 114 can be formed over a corresponding air cavity 130. It will be appreciated that without providing the air cavity 130, only the germanium layer 178 is formed over the substrate 102 as described herein.

[0043] Figure 15 A perspective view of forming a hard mask 180 over the germanium layer 178 and etching to pattern the semiconductor photodetector 114 is shown. The etching may also include a process for trench isolation 120 ( Figure 1 ) is etched into a groove (not shown). Figure 1 As shown, trench isolations 120 can be formed around semiconductor photodetectors 114. Trench isolations 120 can be etched into the germanium layer 178 and substrate 102 and filled with an insulating material, such as an oxide, to isolate semiconductor photodetectors 114 from the final pixel 110 and from each other. Planarization can remove any excess insulating material on the germanium layer 178. As understood in the art, trench isolations 120 can also isolate other areas of substrate 102 from adjacent areas of the substrate, for example, to isolate different transistors. Each trench isolation 120 can be formed of any now known or later developed material for providing electrical insulation, as previously listed herein.

[0044] Figure 1A set of diffraction gratings 112 is shown formed directly on each semiconductor photodetector 114 to create pixel array 108, i.e., there are no intervening structures between the set of diffraction gratings 112 and the semiconductor photodetectors 114. The diffraction gratings 112 can be formed as part of a process, such as a process for transistor gates in other areas of the substrate 102. Here, for example, a layer of material for the diffraction gratings 112 can be deposited by ALD as part of the formation of the transistor gate layer, and then patterned and etched to create grating elements 116 having a desired pitch P1-P4. In one embodiment, the diffraction gratings 112 can comprise a single material, such as, but not limited to, polysilicon, silicon, or a metal gate conductor (e.g., copper). In other embodiments, the diffraction gratings 112 can comprise: multiple layers, such as polysilicon or silicon, each with a gate dielectric such as silicon oxide; or a metal gate material including one or more layers of a work function metal and a gate conductor, with a gate dielectric layer such as silicon oxide. In some embodiments, the diffraction grating 112 may include any layer(s) used in gates (not shown) (active or dummy) of transistors in other areas of the wafer.

[0045] As described above, the pitch of the set of diffraction gratings 112 associated with each semiconductor photodetector 114 can be different, so that each pixel 110 can detect light of a specific wavelength different from the other pixels 110 of the pixel array 108. The multiple sets of diffraction gratings 112 can include, for example, silicon or polysilicon. The ends of each diffraction grating element 116 can be aligned with the edge of the corresponding semiconductor photodetector 114, or one or more elements can extend onto the trench isolation 120 adjacent to the corresponding semiconductor photodetector 114. The resulting pitch can be, for example, as described with respect to the embodiments described herein. Figure 1 、 2 , any of the spacings shown in 8 and 9.

[0046] In an alternative embodiment, if Figure 6 As shown, prior to forming the multiple sets of diffraction gratings 112 and as part of forming the array of semiconductor photodetectors 114, at least one semiconductor photodetector 114 can be formed to have a p-type doped region 140 separated from an n-type doped region 142 by an intrinsic region 144. Here, any suitable mask can be formed and the desired region can be doped with the desired dopant, for example using ion implantation. Exemplary n-type dopants can include, but are not limited to, phosphorus (P), arsenic (As), antimony (Sb); and exemplary p-type dopants can include, but are not limited to, boron (B), indium (In), and gallium (Ga). Similarly, in another alternative embodiment, as Figure 7As shown, forming an array of semiconductor photodetectors 114 can include forming at least one semiconductor photodetector 114 in which a first p-type doped region 146 is separated from a second p-type doped region 148 by an intrinsic region 150, and an n-type doped region 152 is adjacent to one of the first and second p-type doped regions. This structure forms a PIPN avalanche photodetector.

[0047] The method may further include forming at least one set of diffraction gratings 112 having non-uniform spacing, such as Figure 9 As shown, patterning is used to generate different spacings. Similarly, Figure 8 As shown, the method can include forming at least one set of diffraction gratings 112 having a base layer 160 on a semiconductor photodetector 114 and a plurality of diffraction grating elements 162 extending from the base layer 160. Here, the grating elements 162 are only partially etched from the diffraction grating layer.

[0048] The above-described method is used for the fabrication of photonic integrated circuit chips (PICs). The resulting PICs can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes PICs and / or integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0049] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or the groups they constitute. "Optional" or "optionally" means that the event or situation described subsequently may or may not occur, and that the description includes situations where the event occurs and situations where the event does not occur.

[0050] Approximate language, as used throughout the specification and claims, may be used to modify any quantitative representation that is permissible to vary without resulting in a change in the basic function to which it relates. Accordingly, a value modified by one or more terms such as "about," "approximately," and "substantially" is not limited to the precise value specified. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. Herein and throughout the specification and claims, range limitations may be combined and / or interchanged, such ranges are identified and include all subranges contained therein unless the context or language indicates otherwise. "Approximately" applied to a particular value of a range applies to both values and may indicate + / - 10% of the stated value unless otherwise dependent upon the precision of the instrument used to measure the value.

[0051] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been given for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular use contemplated.

Claims

1. A photodetector array structure, comprising: substrate; a pixel array positioned above the substrate, each pixel comprising a set of diffraction gratings positioned directly on a semiconductor photodetector; as well as an air cavity in the substrate beneath at least one semiconductor photodetector, The pitch of the set of diffraction gratings associated with each pixel in the pixel array is different, so that each pixel can detect light of a specific wavelength different from other pixels in the pixel array.

2. The photodetector array structure according to claim 1, wherein: The air cavity includes a plurality of connected air cavities.

3. The photodetector array structure according to claim 1, wherein: Each set of diffraction gratings includes one of polysilicon and silicon.

4. The photodetector array structure according to claim 1, wherein: The semiconductor photodetector includes germanium (Ge), silicon (Si), or silicon germanium (SiGe).

5. The photodetector array structure according to claim 1, wherein: At least one semiconductor photodetector includes a p-type doped region separated from an n-type doped region by an intrinsic region.

6. The photodetector array structure according to claim 1, wherein: At least one semiconductor photodetector includes a first p-type doped region separated from a second p-type doped region by an intrinsic region, and an n-type doped region adjacent to one of the first p-type doped region and the second p-type doped region.

7. The photodetector array structure according to claim 1, wherein: The pitch of the set of diffraction gratings for at least one pixel in the pixel array is non-uniform.

8. The photodetector array structure according to claim 1, wherein: The set of diffraction gratings includes a substrate positioned on the semiconductor photodetector and a plurality of diffraction grating elements extending from the substrate.

9. The photodetector array structure according to claim 1, wherein: The pixel array absorbs light of more than one wavelength.

10. A photodetector array structure comprising: substrate; a pixel array over the substrate, each pixel comprising a set of diffraction gratings directly over a semiconductor photodetector, wherein each set of diffraction gratings comprises one of polysilicon and silicon; Trench isolation located around each semiconductor photodetector; as well as an air cavity in the substrate beneath at least one semiconductor photodetector, The set of diffraction gratings associated with each pixel in the pixel array has a different pitch, such that each pixel is capable of detecting light of a specific wavelength different from other pixels in the pixel array, so that the pixel array absorbs light of more than one wavelength.

11. The photodetector array structure according to claim 10, wherein: Each air cavity includes a plurality of connected air cavities.

12. The photodetector array structure according to claim 10, wherein: At least one semiconductor photodetector includes a p-type doped region separated from an n-type doped region by an intrinsic region.

13. The photodetector array structure according to claim 10, wherein: At least one semiconductor photodetector includes a first p-type doped region separated from a second p-type doped region by an intrinsic region, and an n-type doped region adjacent to one of the first p-type doped region and the second p-type doped region.

14. The photodetector array structure according to claim 10, wherein: The pitch of the set of diffraction gratings for at least one pixel in the pixel array is non-uniform.

15. The photodetector array structure according to claim 10, wherein: The set of diffraction gratings includes a substrate positioned on the semiconductor photodetector and a plurality of diffraction grating elements extending from the substrate.

16. A method of forming a photodetector array, comprising: A pixel array is formed on a substrate by: forming a semiconductor photodetector array on a substrate, the semiconductor photodetector array being surrounded by trench isolation; forming a set of diffraction gratings directly on each semiconductor photodetector to create the pixel array, wherein a pitch of the set of diffraction gratings associated with each semiconductor photodetector is different such that each pixel is capable of detecting light of a specific wavelength different from other pixels in the pixel array; as well as An array of air cavities is formed in the substrate before forming the semiconductor photodetector array, wherein forming the semiconductor photodetector array includes forming each semiconductor photodetector over a corresponding air cavity.

17. The method according to claim 16, wherein: The semiconductor photodetector seals the corresponding air cavity.

18. The method according to claim 16, wherein Forming the semiconductor photodetector array includes forming at least one semiconductor photodetector to have a p-type doped region separated from an n-type doped region by an intrinsic region.

19. The method according to claim 16, wherein Forming the semiconductor photodetector array includes forming at least one semiconductor photodetector to have a first p-type doped region separated from a second p-type doped region by an intrinsic region, and an n-type doped region adjacent to one of the first p-type doped region and the second p-type doped region.

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