A three-dimensional memory and a method for forming the same

Abstract

An embodiment of the present application provides a three-dimensional memory and a method for forming the same. The method includes: providing a semiconductor front-end device formed by using a preset front-end process; the semiconductor front-end device includes a peripheral region and an array region; using a back-end process, forming a peripheral region device in the peripheral region of the semiconductor front-end device respectively, and forming an embedded phase change memory cell array in the array region.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductors, including but not limited to a three-dimensional memory and a method for forming the same. Background Art

[0002] Flash is a new type of storage device with fast read / write speed, low power consumption, high temperature resistance and no noise, and has become the current mainstream non-volatile memory (NVM) technology, which is widely used in various fields such as data centers, personal computers, mobile phones, intelligent terminals, and consumer electronics. Embedded Flash (eFlash) is a storage module used to store information in system semiconductors, such as information in microelectronic units (MCUs) and system-on-chips (SoCs) for small electronic products (such as IoT devices). With the continuous evolution of process nodes, the 28nm / 22nm silicon lithography node will be the last cost-effective technology node for eFlash. After that, the effect of size reduction cannot cover the increasing cost brought by the growing number of photomasks. Taking the TSMC process as an example, eFlash requires an additional 12 photomasks. In addition, due to the continuous improvement of storage density, the storage performance of flash memory cells is getting worse and worse, which cannot meet the requirements of high-performance storage systems.

[0003] Phase change memory (PCM) is an emerging non-volatile memory technology, which realizes data storage by rapidly converting phase change materials between an ordered crystalline state and a disordered amorphous state through electrical pulses. Phase change memory has the characteristics of non-volatility, fast speed, easier to be scaled down to a smaller size, and high reliability. Compared with eFlash as a front-end technology, ePCM (embedded phase change memory) can be fabricated in the back-end metal layer without affecting the front-end transistors, and the manufacturing difficulty for foundries is relatively small, making it a replacement for flash memory technology. However, the current embedded phase change memory technology is based on a two-dimensional process, with large cell sizes, high programming currents required, difficult to achieve a high embedded PCM capacity, and occupying a large silicon area, resulting in a large chip size and cost. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a three-dimensional memory and a method for forming the same, which can form a three-dimensional memory with a large storage capacity, strong scalability, and a minimum increase in silicon area, reduce the process steps for manufacturing the three-dimensional memory, and lower the manufacturing cost.

[0005] An embodiment of the present application provides a method for forming a three-dimensional memory, the method including: providing a semiconductor front-end device formed by a preset front-end process; the semiconductor front-end device including a peripheral region and an array region; using a back-end process to form a peripheral region device in the peripheral region of the semiconductor front-end device and form an embedded phase change memory cell array in the array region respectively.

[0006] In some embodiments, forming the embedded phase change memory cell array in the array region includes:

[0007] Using a double-patterning process to form the embedded phase change memory cell array composed of at least two columnar three-dimensional phase change memory cells on the surface of the array region; or using a single-patterning process to form the embedded phase change memory cell array composed of at least two columnar three-dimensional phase change memory cells on the surface of the array region.

[0008] In some embodiments, using the double-patterning process to form the embedded phase change memory cell array composed of at least two columnar three-dimensional phase change memory cells on the surface of the array region includes: forming a phase change memory cell stack and a first mask layer stacked in sequence on the surface of the array region; using the double-patterning process to form a mask pattern with a grid pattern; etching the first mask layer based on the mask pattern to form a first etched mask layer; using the first etched mask layer as a mask to etch the phase change memory cell stack to form at least two columnar three-dimensional phase change memory cells arranged in a grid pattern; wherein the at least two three-dimensional phase change memory cells arranged in a grid pattern constitute the embedded phase change memory cell array.

[0009] In some embodiments, the phase change memory cell stack includes a bottom stack and a top stack stacked in sequence from bottom to top; etching the phase change memory cell stack using the first etched mask layer as a mask includes: performing a first etching on the top stack using the first etched mask layer as a mask to form top stack units; depositing and forming a first encapsulation layer on the surface of the top stack units; performing a second etching on the bottom stack using the top stack units with the first encapsulation layer as a mask to form bottom stack units; depositing and forming a second encapsulation layer on the surface of the bottom stack units to form at least two columnar three-dimensional phase change memory cells arranged in a grid pattern.

[0010] In some embodiments, the top stack includes, formed successively from bottom to top: a PCM element layer, a first electrode layer, and a hard mask layer; using the first etching mask layer as a mask, performing a first etching on the top stack to form top stack units, including: using the first etching mask layer as a mask, successively performing a first etching on the hard mask layer, the first electrode layer, and the PCM element layer to form a hard etching mask layer, a first etched electrode layer, and a PCM etched element layer, and forming a first via hole penetrating through the hard etching mask layer, the first etched electrode layer, and the PCM etched element layer, and a top stack unit around the first via hole.

[0011] In some embodiments, depositing and forming a first encapsulation layer on the surface of the top stack unit includes: depositing a first encapsulation material on the sidewall of the first via hole and the surface of the hard etching mask layer to form the first encapsulation layer.

[0012] In some embodiments, the bottom stack includes, formed successively from bottom to top: a third electrode layer, a selector layer, and a second electrode layer; using the top stack unit having the first encapsulation layer as a mask, performing a second etching on the bottom stack to form bottom stack units, including: using the top stack unit having the first encapsulation layer as a mask, successively performing a second etching on the second electrode layer, the selector layer, and the third electrode layer to form a second etched electrode layer, an etched selector layer, and a third etched electrode layer, and forming a second via hole penetrating through the second etched electrode layer, the etched selector layer, and the third etched electrode layer, and a bottom stack unit around the second via hole.

[0013] In some embodiments, depositing and forming a second encapsulation layer on the surface of the bottom stack unit includes: depositing a second encapsulation material on the sidewall of the second via hole and the surface of the bottom stack unit to form the second encapsulation layer.

[0014] In some embodiments, the method further includes: filling a gap material on the surface of the second encapsulation layer to form a gap material layer; starting from the upper surface of the gap material layer, successively etching the gap material layer, the second encapsulation layer, the first encapsulation layer, and the hard etching mask layer to expose the first etched electrode layer; forming word line contacts on the exposed first etched electrode layers; and forming a word line on each of the word line contacts.

[0015] In some embodiments, before forming the phase change memory cell stack, the method further includes: depositing and forming a plurality of bit lines extending in a first direction on the surface of the array region; depositing and forming a dielectric layer on the surface of the plurality of bit lines; etching the dielectric layer based on the positions of the plurality of bit lines to form a bit line contact hole corresponding to each position; depositing a first contact material in the bit line contact hole to form a bit line contact on each of the bit lines; the bit line contacts are used to connect the bit lines to the phase change memory cell stack.

[0016] In some embodiments, the embedded phase change memory cell array is a stack structure, and the stack structure includes at least one layer of sub-structure, and each sub-structure is composed of at least two columnar three-dimensional phase change memory cells.

[0017] In some embodiments, the following back-end processes are adopted to form peripheral devices in the peripheral region of the semiconductor front-end device, including: sequentially forming an I / O circuit, an MCU logic circuit, an analog circuit, and a PCM control circuit on the surface of the peripheral region; wherein, the I / O circuit, the MCU logic circuit, the analog circuit, and the PCM control circuit constitute the peripheral devices.

[0018] In some embodiments, the method further includes: depositing and forming a first dielectric layer and a first interconnect layer on the surface of the semiconductor front-end device; forming the embedded phase change memory cell array on the surface of the first interconnect layer located in the array region; depositing and forming a second dielectric layer and a second interconnect layer stacked in sequence around the embedded phase change memory cell array to form the three-dimensional memory.

[0019] In some embodiments, the first dielectric layer is formed by the following steps: depositing and forming the first dielectric layer on the surface of the semiconductor front-end device; etching the first dielectric layer to form a plurality of first contact holes extending in a direction perpendicular to the surface of the semiconductor front-end device; depositing a second contact material in the plurality of first contact holes to correspondingly form a plurality of first contact lines; wherein, the upper surfaces of the plurality of first contact lines are flush with the surface of the first dielectric layer.

[0020] In some embodiments, the first interconnect layer is formed by the following steps: forming a metal stack on the surfaces of the first contact lines and the first dielectric layer; the metal stack includes a plurality of metal layers stacked in sequence; etching the metal stack to form a plurality of first metal parts; depositing dielectric materials around each of the first metal parts to form the first interconnect layer.

[0021] An embodiment of the present application provides a three-dimensional memory, which is formed by using any one of the above-mentioned methods for forming a three-dimensional memory. The three-dimensional memory includes: a semiconductor front-end device; the semiconductor front-end device includes a peripheral region and an array region; a peripheral region device located on the surface of the peripheral region; an embedded phase change memory cell array located on the surface of the array region, wherein the embedded phase change memory cell array is composed of at least two columnar three-dimensional phase change memory cells.

[0022] In some embodiments, the embedded phase change memory cell array is a stack structure, and the stack structure includes at least one layer of sub-structure, and each sub-structure is composed of the at least two columnar three-dimensional phase change memory cells.

[0023] The three-dimensional memory and its forming method provided by the embodiment of the present application first form a semiconductor front-end device through a front-end process, and then, during a back-end process, a peripheral region device and an embedded phase change memory cell array are respectively formed on the surface of the semiconductor front-end device to form a three-dimensional memory. Since an embedded phase change memory cell array is also formed on the semiconductor front-end device in the embodiment of the present application, the formed three-dimensional memory has a large storage capacity, scalability, and a small increase in silicon area, reducing the manufacturing cost. Description of the Drawings

[0024] Figure 1 It is a schematic flow chart of the method for forming a three-dimensional memory provided by the embodiment of the present application Figure 1 ;

[0025] Figures 2a - 2c It is a schematic diagram of the forming process of the three-dimensional memory provided by the embodiment of the present application;

[0026] Figures 3a - 3o It is a schematic diagram of the forming process of the embedded phase change memory cell array provided by the embodiment of the present application;

[0027] Figure 4a It is a second schematic flow chart of the method for forming a three-dimensional memory provided by the embodiment of the present application;

[0028] Figures 4b - 4k It is a schematic diagram of the forming process of the three-dimensional memory provided by the embodiment of the present application;

[0029] Figure 5 It is a circuit diagram of the three-dimensional memory provided by the embodiment of the present application. Detailed Embodiments

[0030] Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully communicated to those skilled in the art.

[0031] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these details. In other instances, some well-known technical features are not described in order to avoid confusion with the present application; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0032] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Like reference numerals throughout the drawings denote like elements.

[0033] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion. And when discussing the second element, component, region, layer, or portion, it does not necessarily imply that there is a first element, component, region, layer, or portion in the present application.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0035] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. A layer can extend over the entirety of a structure below or above, or can have a scope less than the scope of the structure below or above. In addition, a layer can be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along an inclined surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above, and / or below it, and a layer can include multiple layers.

[0036] With the development of fully depleted silicon-on-insulator (FD-SOI) as a substrate technology, ePCM produced using the FD-SOI process has excellent performance. In the related art, existing ePCM uses traditional 2D PCM, such as the E-PCM launched by STM (with a storage capacity of 16 Mb and an applicable temperature range of -40 to 165 °C), which meets the AEC-Q100 Grade0 standard. This E-PCM has a larger storage capacity than eFlash, can meet the development needs of automotive intelligence, has a high compatibility with the 28nm FD-SOI process, low processing difficulty, is suitable for applications in the drive system or under the engine hood, and is widely used in fields with extremely high requirements for performance and reliability, such as engine control, transmission electronics, steering, braking, and airbags. However, traditional 2D PCM has problems such as large cell size, high programming current requirements, difficulty in achieving a high embedded PCM capacity, and occupying a large silicon area, resulting in a large chip size and cost.

[0037] Based on this, an embodiment of the present application provides a method for forming a three-dimensional memory. Figure 1 This is a flowchart of the formation process of the three-dimensional memory provided by the embodiment of the present application. Refer to Figure 1 , the method includes:

[0038] Step S100: Provide a semiconductor front-end device, which is formed by a preset front-end process; the semiconductor front-end device includes a peripheral region and an array region.

[0039] Figures 2a - 2b is a schematic diagram of the formation process of the semiconductor front-end device 110. Refer to Figure 2a , a thin silicon dioxide layer 102 with a thickness of 20 nm is formed on the surface of the substrate 101 through a thermal oxidation process. Subsequently, a silicon nitride layer 103 is deposited on the surface of the thin silicon dioxide layer 102. Refer to Figure 2b , etch through the silicon nitride layer and the thin silicon dioxide layer to form an etched silicon nitride layer, an etched thin silicon dioxide layer, and a first substrate 101'. Deposit a filling material on the surface of the etched silicon nitride layer, and remove the etched silicon nitride layer and the etched thin silicon dioxide layer through a chemical mechanical planarization process to form a first isolation groove 111 and a second isolation trench 112 on the surface of the etched first substrate 101', so that the first substrate 101' is divided into a first region and a second region by the first isolation groove 111. Then, a first P well is formed in the first region 120 through ion implantation, and an N well 131 and a second P well 132 are sequentially formed in the second region 130, and the N well and the second P well are separated by the second isolation groove 112. Here, the first substrate 101', the first region 120, the first isolation groove 111, the N well 131, the second isolation groove 112, and the second P well 132 together constitute the semiconductor front-end device 110.

[0040] Here, the substrate may be a silicon substrate, or the substrate may also include other semiconductor elements, such as: germanium (Ge), or include semiconductor compounds, such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as: silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.

[0041] In the embodiments of the present application, the substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; when ignoring the flatness of the top surface and the bottom surface, the direction perpendicular to the top surface and the bottom surface of the substrate is defined as the third direction. In the direction of the top surface and the bottom surface of the substrate (i.e., the plane where the substrate is located), two mutually perpendicular first directions and second directions are defined, where the extending direction along a plurality of bit line structures is the first direction, and the arranging direction of the bit line structures is defined as the second direction. Based on the first direction and the second direction, the plane direction of the substrate can be determined. Here, the first direction, the second direction, and the third direction are perpendicular to each other pairwise. In the embodiments of the present application, the first direction is defined as the X direction, the second direction is defined as the Y direction, and the third direction is defined as the Z direction. In the subsequent embodiments, unless otherwise specified, the first direction, the second direction, and the third direction are understood according to this definition.

[0042] Step S200: Use a back-end process to form peripheral devices in the peripheral area of the semiconductor front-end device and form an embedded phase change memory cell array in the array area, respectively.

[0043] Figure 2c It is a schematic structural diagram of a three-dimensional memory provided by the embodiments of the present application. Refer to Figure 2c , and form a peripheral device 140 on the surface of the peripheral area 120 of the semiconductor front-end device.

[0044] Continue to refer to Figure 2c , first, form a PCM array circuit 150 on the surface of the array area 130, and then form an embedded phase change memory cell array 300 on the PCM array circuit 150 formed on the surface of the array area 130, thereby forming a three-dimensional memory 100.

[0045] In the embodiments of the present application, a double-patterning process or a single-patterning process can be used to form the embedded phase change memory cell array. Here, the embedded phase change memory cell array 300 is composed of at least two columnar three-dimensional phase change memory cells 200.

[0046] When using the double-patterning process to form the embedded phase change memory cell array 300 on the surface of the array area, it can be formed through the following steps:

[0047] Step S301: Deposit and form a plurality of bit lines extending in the first direction on the surface of the array area; correspondingly form bit line contacts located on each of the bit lines; and form a phase change memory cell stack layer and a first mask layer stacked in sequence on the surface of the bit line contacts.

[0048] See Figure 3a, on top of the PCM array circuit (not shown in the figure) formed on the surface of the array region, a plurality of bit lines 301 extending in the first direction are deposited, and a dielectric layer is deposited on the surfaces of the plurality of bit lines; based on the positions of the plurality of bit lines, the dielectric layer is etched to form a bit line contact hole corresponding to each of the positions; a first contact material is deposited in the bit line contact hole to form a bit line contact 302 on each of the bit lines; the bit line contact 302 is used to connect the bit line to the phase change memory cell stack. Then, a phase change memory cell stack 320 and a first mask layer 330 are sequentially stacked on the surface of the bit line contact 302. Here, the first mask layer 330 is used as a mask when etching the phase change memory cell stack 320 after the subsequent double-patterning process is formed.

[0049] In the embodiments of the present application, the bit line 301 may be formed of metallic copper (Cu), or may be formed of other metals, such as tungsten (W), cobalt (Co), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

[0050] Step S302: Form a mask pattern with a grid-like pattern by using the double-patterning process; etch the first mask layer based on the mask pattern to form a first etched mask layer.

[0051] In the embodiments of the present application, step S302 is completed through the following steps:

[0052] Step S3021: Deposit a primary mask stack on the surface of the first mask layer, and the primary mask stack at least includes: a second mask layer, a third mask layer, a first mandrel layer, a first dielectric layer, and a first barrier layer stacked in sequence from bottom to top.

[0053] See Figure 3b , the primary mask stack 340 deposited on the surface of the first mask layer 330 includes: a second mask layer 3401, a third mask layer 3402, a first mandrel layer 3403, a first dielectric layer 3404, and a first barrier layer 3405 stacked in sequence along the third direction.

[0054] Step S3022: Pattern the first barrier layer to form a first etched barrier layer.

[0055] First, see Figure 3c , using an etching pattern, etch the first barrier layer 3045 at the top of the primary mask stack 340 to form a first etched barrier layer 3405'. The first etched barrier layer 3405' has a plurality of groove patterns parallel to each other in the first direction. Here, the first barrier layer may be formed by depositing a SiN material.

[0056] Step S3023: Using the first etching stop layer as a mask, etch the first dielectric layer and the first mandrel layer in sequence, and remove the remaining first etching stop layer to form a first etched mandrel layer.

[0057] Refer to Figure 3d , using the first etching stop layer 3405’ as a mask, etch the first dielectric layer 3404 and the first mandrel layer 3403 in sequence along the Z direction, and remove the remaining first etching stop layer 3405’ to form a first etched dielectric layer 3404’ and a first etched mandrel layer 3403’. The first etched dielectric layer 3404’ and the first etched mandrel layer 3403’ correspondingly form a plurality of first mandrel bodies M1, and there is a groove pattern between every two adjacent first mandrel bodies M1. Here, the first dielectric layer may be formed by depositing SiON material; the material of the first mandrel layer may be polysilicon.

[0058] Step S3024: Based on the mandrel pattern of the first etched mandrel layer, deposit first spacers on both sides of each first mandrel body in the first etched mandrel layer; wherein, the first spacers have the initial etching pattern.

[0059] Here, the mandrel pattern of the first etched mandrel layer is the plurality of parallel groove patterns extending in the X direction formed in Step S3023. In the embodiments of the present application, refer to Figure 3e , the first spacers can be formed in the following two ways:

[0060] Method 1: First, based on the plurality of first mandrel bodies M1 formed after etching, deposit a thin film with a uniform thickness on the surface of the entire semiconductor device to cover the mandrel pattern of the first etched mandrel layer; then, perform oxide / nitride chemical mechanical planarization (CMP) treatment on the surface of the entire semiconductor device to remove the thin film deposited on the surface of the first etched dielectric layer 3404’ and expose the first etched dielectric layer 3404’; then, form a mask pattern on the surface of the planarized thin film and the first etched dielectric layer 3404’, and then, based on the mask pattern, use an etching process to etch a part of the thin film to obtain first spacers S11, S12, S13, and etching holes between two adjacent first spacers.

[0061] Method 2: First, based on the plurality of first mandrel bodies M1 formed after etching, deposit a thin film material between adjacent first mandrel bodies M1 to form a thin film with a uniform thickness; then, form a mask pattern on the surface of the thin film and the first etched dielectric layer 3404’; then, based on the mask pattern, use an etching process to etch a part of the thin film to obtain first spacers S11, S12, S13, etc., and etching holes between two adjacent first spacers.

[0062] Step S3025: Remove the first etching mandrel layer to form a plurality of initial etching patterns extending in the first direction.

[0063] A highly selective etching solution (such as a hydrogen peroxide-based or inorganic acid-based etching solution) can be used to remove the top first etching dielectric layer 3404', retain the first spacers S11, S12, and S13, and form a plurality of initial etching patterns extending in the X direction. Subsequently, a CMP process is used to process the top surface to remove the first etching mandrel layer 3403' and a part of the top surfaces of the first spacers S11, S12, and S13 to form a first spacer with a flat surface and having an initial etching pattern.

[0064] Step S3026: Based on the plurality of initial etching patterns extending in the first direction, etch the third mask layer to form a third etching mask layer having the initial etching patterns.

[0065] Step S3027: Using the third etching mask layer as a mask, etch the second mask layer and remove the remaining third etching mask layer to form a second etching mask layer having the initial etching patterns.

[0066] See Figure 3f , using the first spacer as a mask, etch the third mask layer and the second mask layer 3401 along the Z direction, so that the second etching mask layer 3401' has an initial etching pattern, and the etching stops at the first mask layer 330. In the embodiments of the present application, the first mask layer, the second mask layer, and the third mask layer may be an amorphous carbon layer (ACL), a spin-on hard mask layer (SOH), a polysilicon layer, or a silicon oxynitride layer.

[0067] Step S3028: Form a second mask stack on the surface of the second etching mask layer.

[0068] As Figure 3g shown, a second mask stack 350 is formed on the surface of the second etching mask layer. Here, the second mask stack 350 includes, stacked in sequence along the Z direction: a second mandrel layer 3501, a second dielectric layer 3502, and a second barrier layer 3503. The second mask stack 350 is used to form a grid-shaped mask pattern.

[0069] Step S3029: Use the plurality of secondary etching patterns extending in the second direction to etch the second barrier layer to form a second etching barrier layer.

[0070] See Figure 3h, a plurality of secondary etching patterns extending along the Y direction are used to etch the second barrier layer 3503 in the second mask stack to obtain a second etched barrier layer 3503'. A plurality of parallel secondary etching patterns extending along the Y direction are formed on the second etched barrier layer 3503'.

[0071] Step S3030: Using the second etched barrier layer as a mask, the second dielectric layer and the second mandrel layer are etched in sequence, and the remaining second etched barrier layer is removed to form a second etched mandrel layer.

[0072] See Figure 3i , using the second etched barrier layer 3503' as a mask, the second dielectric layer 3502 and the second mandrel layer 3501 are etched in sequence, and the second etched barrier layer 3503' is removed to form a second etched dielectric layer 3502' and a second etched mandrel layer 3501'. The second etched dielectric layer 3502' and the second etched mandrel layer 3501' correspondingly form a plurality of second mandrel bodies M2, and there is a groove pattern between every two adjacent second mandrel bodies M2.

[0073] Step S3031: Based on the mandrel pattern of the second etched mandrel layer, second spacers S21, S22, S23 are deposited on both sides of each second mandrel body in the second etched mandrel layer.

[0074] Here, the mandrel pattern of the second etched mandrel layer is the plurality of parallel secondary etching patterns extending along the Y direction formed in step S3030. In the embodiment of the present application, based on the mandrel pattern, second spacers S21, S22, S23 and etching holes located between two adjacent second spacers are deposited. Among them, the second spacers S21, S22, S23 have a second characteristic pattern, and the second spacers are used to form a second etched mask layer. The second characteristic pattern is a plurality of parallel line features extending along the Y direction and arranged along the X direction corresponding to the secondary etching pattern. Here, the two methods of forming the second spacer are the same as the two methods of forming the first spacer. For the specific process, please refer to step S3024, which will not be elaborated here.

[0075] Step S3032: Remove the second etched mandrel layer; using the second spacer as a mask, the second etched mask layer is secondarily etched to form a second secondary etched mask layer with a grid-like pattern mask pattern. Based on the second secondary etched mask layer with the grid-like pattern mask pattern, the first mask layer is etched to form the first etched mask layer.

[0076] In the embodiments of the present application, an etchant with strong selectivity (such as hydrogen peroxide-based or inorganic acid-based etchants) can be used to remove the top second etch dielectric layer 3502', leaving only the second spacers S21, S22, and S23, to form a plurality of second feature patterns extending in the Y direction. Subsequently, a CMP process is used to process the top surface, removing the remaining top second etch mandrel layer 3501' and a part of the top surfaces of the second spacers S21, S22, and S23, to form a second spacer with a flat surface and having a second feature pattern.

[0077] See Figure 3j , using the second spacers S21, S22, and S23 with the second feature pattern as a mask, the second etch mask layer is etched twice to form a second etch mask layer 3401" with a mask pattern having a grid-like pattern. Using the second etch mask layer 3401" to continue etching the first mask layer 330 and removing the second etch mask layer 3401", a first etch mask layer 330' is formed. As Figure 3k shown, at this time, the first etch mask layer 330' has a grid-like pattern in the X-Y plane.

[0078] Step S303: Using the first etch mask layer as a mask, etching the phase change memory cell stack to form at least two columnar three-dimensional phase change memory cells arranged in a grid-like pattern; wherein, the at least two three-dimensional phase change memory cells arranged in a grid-like pattern constitute the embedded phase change memory cell array.

[0079] In the embodiments of the present application, the phase change memory cell stack includes a bottom stack and a top stack stacked in sequence from bottom to top. As Figure 3l shown, the phase change memory cell stack 320 includes: a top stack 321 and a bottom stack 322. The top stack 321 includes, in the Z direction in sequence: a hard mask layer 3213, a first electrode layer 3212, and a PCM element layer 3211; the bottom stack 322 includes, in the Z direction in sequence: a second electrode layer 3223, a selector layer 3222, and a third electrode layer 3221. Correspondingly, step S303 can be implemented through the following steps:

[0080] Step S303A: Using the first etch mask layer as a mask, performing a first etch on the top stack to form top stack units; depositing and forming a first encapsulation layer on the surface of the top stack units.

[0081] In the embodiments of the present application, see Figure 3m, step S3031 includes: using the first etching mask layer 330' as a mask, sequentially performing first etching on the hard mask layer 3213, the first electrode layer 3212, and the PCM element layer 3211 to form a hard etched mask layer 3213', a first etched electrode layer 3212', and a PCM etched element layer 3211', and forming a first through hole 1 that penetrates the hard etched mask layer, the first etched electrode layer, and the PCM etched element layer, and top stacked units 10, 20, 30 located around the first through hole; depositing a first encapsulation material on the sidewall of the first through hole 1 and the surface of the hard etched mask layer 3213' to form the first encapsulation layer Y1.

[0082] In the embodiment of the present application, the PCM element layer includes PCM elements. The PCM elements are generally chalcogenide compound materials. For example, they can be GST (germanium antimony tellurium); the first electrode layer can be a carbon electrode layer; the hard mask layer can be a silicon nitride layer.

[0083] Step S303B: Using the top stacked unit with the first encapsulation layer as a mask, performing second etching on the bottom stack to form bottom stacked units; depositing and forming a second encapsulation layer on the surface of the bottom stacked units to form at least two columnar three-dimensional phase change memory units arranged in a grid pattern.

[0084] In the embodiment of the present application, refer to Figure 3n , step S303B includes: using the top stacked unit with the first encapsulation layer as a mask, sequentially performing second etching on the second electrode layer 3223, the selector layer 3222, and the third electrode layer 3221 to form a second etched electrode layer 3223', an etched selector layer 3222', and a third etched electrode layer 3221', and forming a second through hole 2 that penetrates the second etched electrode layer 3223', the etched selector layer 3222', and the third etched electrode layer 3221', and the bottom stacked units 101, 201, 301 located around the second through hole. Depositing a second encapsulation material on the sidewall of the second through hole 2 and the surface of the bottom stacked units 101, 201, 301 to form the second encapsulation layer Y2. In the embodiment of the present application, a bidirectional threshold switch (OTS) is arranged in the selector layer, and the material of the OTS can include Zn x Te y 、Ge x Te y 、Nb x O y 、Si x As y Te zAny one of the above. The second electrode layer and the third electrode layer can be carbon electrode layers. The materials of the first encapsulation layer and the second encapsulation layer can be encapsulation protection materials with insulating effects such as ceramic-based encapsulation materials and plastic-based encapsulation materials.

[0085] Step S303C: Fill the gap material on the surface of the second encapsulation layer to form a gap material layer; starting from the upper surface of the gap material layer, etch the gap material layer, the second encapsulation layer, the first encapsulation layer, and the hard etching mask layer in sequence to expose the first etched electrode layer; form word line contacts on the surfaces of the exposed first etched electrode layers; form a word line on each of the word line contacts.

[0086] See Figure 3o , fill the gap material in the surface of the second encapsulation layer Y2 and the gap of the second via 2 to form a gap material layer G. In the embodiments of the present application, ALD-ox, SOD, or flowing CVD-ox with a low thermal conductivity can be used to fill the gap. In other embodiments, low-conformality TEO can also be used to fill the gap to form an air gap.

[0087] Continue to see Figure 3o , adopt the CMP process to etch the gap material layer G, the second encapsulation layer Y2, the first encapsulation layer Y1, and the hard etching mask layer in sequence to expose the first etched electrode layer 3213'. Subsequently, form word line contacts 303 on the surfaces of the exposed first etched electrode layers 3213', and form a plurality of word lines 304 extending along the second direction and arranged along the first direction on the word line contacts 303, thereby forming the phase change memory array 300. Among them, the phase change memory array 300 is composed of bottom bit lines, top word lines, and at least two columnar three-dimensional phase change memory cells 200 located between the bit lines and the word lines. Among them, the bidirectional threshold switch is located in the cross-point array system formed by the word lines and the bit lines.

[0088] In the embodiments of the present application, through the double-patterning process, first etch the primary mask stack, and then etch the second mask stack, so that after two etches, the mask pattern with a grid shape is copied to the first mask layer. When etching the phase change memory cell stack subsequently, perform one etch with the first mask layer with a grid pattern to obtain columnar phase change memory cells, simplifying the etching process, reducing the etching steps, and lowering the etching cost.

[0089] When adopting the single-patterning process to form an embedded phase change memory cell array on the surface of the array region, it can be formed through the following steps:

[0090] Step S311: Deposit and form a phase change memory cell stack on the surface of the array region.

[0091] In the embodiment of the present application, the phase change memory cell stack includes, from bottom to top: a bottom stack and a top stack. The bottom stack sequentially includes: a third electrode layer, a selector layer, and a second electrode layer. The top stack sequentially includes: a PCM element layer, a first electrode layer, and a hard mask layer.

[0092] In some embodiments, before forming the phase change memory cell stack, a plurality of bit lines extending in a first direction are formed on the surface of the array region, and bit line contacts are formed on each bit line; the bit line contacts are used to connect the bit lines and the phase change memory cell stack.

[0093] Step S312: Form a first preset pattern by using a single-pattern forming process, and perform a first etching on the phase change memory cell stack based on the first preset pattern, where the first preset pattern is a gap pattern extending in the first direction and arranged in the second direction.

[0094] In the embodiment of the present application, when performing a first etching on the phase change memory cell stack based on the first preset pattern, first perform a first etching on the top stack. The etching sequentially passes through the hard mask layer, the first electrode layer, and the PCM element layer to form a hard etching mask layer, a first etched electrode layer, and a PCM etched element layer. A filling material is deposited on the surface and around the hard etching mask layer to form a first encapsulation layer.

[0095] Subsequently, perform a first etching on the bottom stack. The etching sequentially passes through the first encapsulation layer, the second electrode layer, the selector layer, and the third electrode layer on the surface of the second electrode layer to form a second etched electrode layer, an etched selector layer, and a third etched electrode layer, and to form a first gap corresponding to the first preset pattern. A filling material is deposited on the surface of the first encapsulation layer and in the first gap to form a second encapsulation layer.

[0096] Step S313: Form a second preset pattern by using a single-pattern forming process, and perform a second etching on the phase change memory cell stack based on the second preset pattern to form an embedded phase change memory array composed of at least two columnar three-dimensional phase change memory cells arranged in a grid pattern; where the second preset pattern is a gap pattern extending in the second direction and arranged in the first direction.

[0097] In the embodiment of the present application, when performing a second etching on the phase change memory cell stack based on the second preset pattern, first perform a second etching on the top stack unit after the first etching. The etching sequentially passes through the hard etching mask layer, the first etched electrode layer, and the PCM etched element layer to form a hard re-etching mask layer, a first re-etched electrode layer, and a PCM re-etched element layer. A filling material is deposited on the surface and around the hard re-etching mask layer to form a third encapsulation layer.

[0098] Subsequently, the bottom stack unit after the first etching is subjected to a second etching, and the etching sequentially passes through the third encapsulation layer, the second etching electrode layer, the etching selector layer, and the third etching electrode layer located on the surface of the second etching electrode layer to form a second replicated electrode layer, a replicated selector layer, and a third replicated electrode layer, and a second gap corresponding to the second preset pattern is formed. A filling material is deposited on the surface of the third encapsulation layer and in the second gap to form a fourth encapsulation layer. At this time, after the first etching and the second etching, the phase change memory cell stack forms columnar phase change memory cells.

[0099] After forming the fourth encapsulation layer, chemical mechanical polishing (CMP) is performed on the hard replicated mask layer and the first encapsulation layer, the second encapsulation layer, the third encapsulation layer, and the fourth encapsulation layer located above the hard replicated mask layer to expose the first replicated electrode layer. Subsequently, a plurality of word lines extending in the second direction are formed on the exposed first replicated electrode layer.

[0100] In some embodiments, before forming the plurality of word lines extending in the second direction, word line contacts may be formed on the first etching electrode layer, and the word line contacts are used to connect the first etching electrode layer and the word lines.

[0101] In the embodiments of the present application, through a single-pattern forming process, first, the phase change memory cell stack is subjected to a first etching based on the first preset pattern, and then the phase change memory cell stack is subjected to a second etching based on the second preset pattern. That is, two etchings are required in the first direction and the second direction respectively to form columnar phase change memory cells. Compared with the double-pattern forming process, in which the double-pattern forming process can form phase change memory cells with only one etching based on a grid-like pattern, the single-pattern forming process requires two etchings to form phase change memory cells.

[0102] In some embodiments, the embedded phase change memory cell array may be a stack structure, and the stack structure includes at least one sub-structure. Each sub-structure is composed of at least two columnar three-dimensional phase change memory cells. That is, each sub-structure constitutes an embedded phase change memory cell array, and in the Z direction, there may be multiple embedded phase change memory cell arrays. In some embodiments, the minimum unit size of the formed embedded phase change memory cell array or stack may be 4F 2 。

[0103] The method for forming a three-dimensional memory provided by the embodiments of the present application forms semiconductor front-end devices on a substrate through front-end processes. Subsequently, in the back-end process, a dual-pattern or single-pattern forming process is used to form an embedded phase change memory cell array on the surface of the array region of the semiconductor front-end devices to form a three-dimensional memory. In this way, the formed three-dimensional memory has scalability that can be scaled in the XY plane and stacked in the Z direction, providing a large storage capacity and a minimal increase in silicon area, thereby reducing the overall cost.

[0104] The embodiments of the present application provide a method for forming a three-dimensional memory, Figure 4a which is a schematic flow chart of the method for forming a three-dimensional memory provided by the embodiments of the present application. Refer to Figure 4a , and the forming method includes:

[0105] Step S401: Provide semiconductor front-end devices, which are formed by using a preset front-end process; the semiconductor front-end devices include a peripheral region and an array region.

[0106] In the embodiments of the present application, the forming process of step S401 is the same as that of step S100, and will not be described in detail here.

[0107] Step S402: Use a back-end process to form peripheral region devices in the peripheral region of the semiconductor front-end devices.

[0108] In the embodiments of the present application, refer to Figure 4b , forming peripheral region devices 440 on the surface of the peripheral region 420 of the semiconductor front-end devices includes: sequentially forming an I / O circuit 441, an MCU logic circuit 442, an analog circuit 443, and a PCM control circuit 444 on the surface of the peripheral region 420; wherein, the I / O circuit 441, the MCU logic circuit 442, the analog circuit 443, and the PCM control circuit 444 constitute the peripheral region devices 440.

[0109] In some embodiments, while forming peripheral region devices on the surface of the semiconductor front-end devices, peripheral wiring (not shown in the figure) can also be formed on the surface of the semiconductor front-end devices, and the peripheral wiring is used to connect the peripheral region devices. In some embodiments, the peripheral region devices may also include one or more of a bias / regulator, a decoder (for example, a word line decoder and a bit line decoder), a sense amplifier, and a driver.

[0110] Here, taking the formation process of the PCM control circuit 444 as an example, the formation process of the peripheral area device 440 will be described. The formation process of the PCM control circuit 444 is as follows: First, a gate oxide layer with a thickness of 2 - 10 nm is deposited on the surface of the P-well formed in the peripheral area, and a layer of polysilicon with a thickness of 200 - 300 nm is deposited on the surface of the gate oxide layer for photolithography to form a gate. Subsequently, silicon nitride is deposited on the gate and spacers are formed on both sides of the gate through a photolithography process. Then, source and drain are respectively formed on both sides of the gate through ion implantation to obtain the PCM control circuit. In the embodiments of the present application, the formation processes of the remaining devices in the peripheral area device 440 are the same as those of the PCM control circuit 444, and will not be elaborated here.

[0111] Step S403: Deposit and form a first dielectric layer and a first interconnect layer on the surface of the semiconductor front-end device.

[0112] In the embodiments of the present application, step S403 is completed through the following steps:

[0113] Step S4031: Deposit and form the first dielectric layer on the surface of the semiconductor front-end device.

[0114] Refer to Figure 4c , deposit an insulating material on the surface of the semiconductor front-end device 410 to form a first dielectric layer 460. Here, the material of the first dielectric layer 460 can be doped silicon dioxide.

[0115] Step S4032: Etch the first dielectric layer to form a plurality of first contact holes extending in a direction perpendicular to the surface of the semiconductor front-end device.

[0116] Refer to Figure 4d , use a photolithography process to etch the first dielectric layer 460 to form a plurality of first contact holes 461. Here, the plurality of first contact holes 461 are all perpendicular to the surface of the semiconductor front-end device 410, and each contact hole 461 is aligned with the peripheral devices on the surface of the semiconductor front-end device 410 and the source / drain on both sides of the PCM array circuit.

[0117] Step S4033: Deposit a second contact material in the plurality of first contact holes to correspondingly form a plurality of first contact lines; wherein, the upper surfaces of the plurality of first contact lines are flush with the surface of the first dielectric layer.

[0118] Continue to refer to Figure 4e , deposit a second contact material in the plurality of first contact holes 461 to form a plurality of first contact lines 462. Here, the second contact material can be a metal, such as metal copper, metal tungsten, etc. In the embodiments of the present application, the plurality of first contact lines 462 are used to realize the electrical connection between the peripheral area device, the PCM array circuit and the interconnect layer formed by the subsequent process.

[0119] Step S4034: Form a metal stack on the surfaces of the first contact line and the first dielectric layer; the metal stack includes a plurality of metal layers stacked in sequence.

[0120] See Figure 4f , on the surfaces of the first contact line 462 and the first dielectric layer 460, deposit to form a metal stack 470. Here, the metal stack 470 is formed by a plurality of metal layers stacked in sequence, and the metal layer material can be copper, tungsten, etc.

[0121] Step S4035: Etch the metal stack to form a plurality of first metal parts; deposit dielectric materials around each of the first metal parts to form the first interconnect layer.

[0122] See Figure 4g , etch the metal stack 470 to form a plurality of first metal parts 471, and each first metal part 471 is connected to two adjacent first contact lines 462. Deposit electrically insulating dielectric materials around each first metal part 471 to form the first interconnect layer 472. Here, the first interconnect layer includes a plurality of first metal parts and dielectric materials for isolating each first metal part. The dielectric material can be the same as the material of the first dielectric layer, for example, it can be doped silicon dioxide. In the embodiments of the present application, electrical connection between the peripheral area devices, the PCM array circuit and the first metal parts in the first interconnect layer is achieved through the first contact line 462, thereby constituting local interconnection.

[0123] Step S404: Form the embedded phase change memory cell array on the surface of the first interconnect layer located in the array area.

[0124] See Figure 4h , adopt a double-pattern or single-pattern forming process to form an embedded phase change memory cell array 300 composed of at least two columnar three-dimensional phase change memory cells on the surface of the first interconnect layer located in the array area.

[0125] In the embodiments of the present application, the process of forming the embedded phase change memory cell array by using the double-pattern forming process is the same as steps S301 - S303, and the process of forming the embedded phase change memory cell array by using the single-pattern forming process is the same as steps S311 - S313, which will not be elaborated here.

[0126] Step S405: Deposit and form a second dielectric layer and a second interconnect layer stacked in sequence around the embedded phase change memory cell array to form the three-dimensional memory.

[0127] See Figure 4i, a dielectric material is deposited on the surface of the first interconnect layer 472 to form a second dielectric layer 480. Subsequently, the second dielectric layer 480 is etched to form a plurality of second contact holes extending in a direction perpendicular to the surface of the semiconductor front-end device. Then, a contact material is deposited in the plurality of second contact holes to correspondingly form a plurality of second contact lines 481. Here, the upper surface of each second contact line 481 is flush with the second dielectric layer 480. Here, the material of the second dielectric layer may be silicon dioxide, and the material of the second contact line may be a metal material such as copper or tungsten. The second contact line is used to connect the first interconnect layer and the second interconnect layer.

[0128] Continue to refer to Figure 4i , a metal stack composed of a plurality of metal layers stacked in sequence is deposited on the surface of the second dielectric layer 480. The metal stack is etched to form a plurality of second metal parts 491, and an insulating material is deposited around each second metal part 491 to form a second interconnect layer 490. Finally, a passivation layer 492 is deposited on the surface of the second interconnect layer 490 to form the three-dimensional memory 400. Here, the insulating material in the second interconnect layer may be silicon dioxide; the material of the passivation layer may be a material such as silicon nitride, which is used to protect the three-dimensional memory.

[0129] An embodiment of the present application provides a method for forming a three-dimensional memory. The semiconductor front-end device, the peripheral area circuit, and the PCM array circuit are formed through the front-end process. Subsequently, in the back-end process, metal interconnections are formed, and a dual-pattern or single-pattern forming process is used to form an embedded three-dimensional phase change memory cell array to form the three-dimensional memory, which can provide a large storage capacity, flexible scalability, and a small increase in silicon area to reduce the overall cost.

[0130] An embodiment of the present application provides a three-dimensional memory formed by using any one of the above methods for forming a three-dimensional memory. Refer to Figure 4j , the three-dimensional memory 400 includes: a semiconductor front-end device 410; the semiconductor front-end device 410 includes a peripheral area 420 and an array area 430;

[0131] Peripheral area devices 440 located on the surface of the peripheral area;

[0132] An embedded phase change memory cell array 300 located on the surface of the array area, where the embedded phase change memory cell array 300 is composed of at least two columnar three-dimensional phase change memory cells 200.

[0133] In some embodiments, refer to Figure 4k , the embedded phase change memory cell array may be a stack structure. The stack structure 500 includes at least one sub-structure, and each sub-structure is composed of the at least two columnar three-dimensional phase change memory cells 200.

[0134] The 3D memory provided by the embodiments of the present application has scalability that can be scaled in the XY plane and stacked in the Z direction, providing a large storage capacity. In addition, since the 3D memory has a minimal increase in silicon area, the overall cost is reduced.

[0135] Figure 5 For the circuit diagram of the 3D memory provided by the embodiments of the present application, see Figure 5 , the circuit of the 3D memory includes: an MCU logic unit 501, a PCM array unit 502, a built-in self-test technology (BIST) 503, a PCM control unit 504, a bias / regulator 505, a WL decoder 506, and a BL decoder / sense amplifier 507. Each device in the circuit of the 3D memory is connected through peripheral wiring, enabling normal data transmission in the 3D memory. Among them, an electrical connection is formed through wiring between the MCU logic unit 501, the PCM array unit 502, and the PCM control unit 504. The bias / regulator 505 is located between the MCU logic unit 502 and the PCM array unit 502 and is electrically connected to the MCU logic unit 502 and the PCM array unit 502 respectively. The bias / regulator 505 is used to provide a bias voltage for the PCM array unit 502. The WL decoder 506 and the BL decoder / sense amplifier 507 are respectively connected to the WL and BL in the PCM array unit 502 for data decoding and read / write operations.

[0136] Continue to refer to Figure 5 , first, data is transmitted between the MCU logic unit 501 and the PCM array unit 502 in the 3D memory; second, the functions of each device in the circuit are self-tested through the BIST 503; finally, the MCU logic unit 501 reads / writes data from / to the PCM array unit 502 through the PCM control unit 504, the bias / regulator 505, the WL decoder 506, and the BL decoder / sense amplifier 507.

[0137] The embodiments of the present application provide a 3D memory and a method for forming the same. In the method, semiconductor front-end devices are formed through front-end processes, and then an embedded phase change memory cell array is added in the back-end processes to form a 3D memory having one or more phase change memory cell stacks. The size of the smallest unit in the stack or array in the 3D memory is 4F 2 , and the threshold switching selector in the 3D phase change memory cell formed by the embodiments of the present application is located in the cross-point array architecture formed by the word line and the bit line. The formed 3D memory has the performance of being scalable in the XY plane and stackable in the Z direction, has a large storage capacity and a small increase in silicon area, so as to reduce the overall manufacturing cost.

[0138] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the magnitudes of the serial numbers of the above processes do not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The serial numbers of the embodiments of the present application above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0139] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0140] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling or communication connection between the components shown or discussed with each other can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0141] The units described as separate components above may or may not be physically separated, and the components shown as units may or may not be physical units; they may be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, each functional unit in the embodiments of the present application can be all integrated in a processing unit, or each unit can be separately used as a unit, or two or more units can be integrated in one unit; the above integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.

[0142] The methods disclosed in several method embodiments provided by this application can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by this application can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0143] As described above, it is only the implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the said claims.

Claims

1. A method for forming a three-dimensional memory, characterized in that, the method comprises: providing a semiconductor front-end device formed by a preset front-end process; the semiconductor front-end device includes a peripheral region and an array region; adopting a back-end process to sequentially form an I / O circuit, an MCU logic circuit, an analog circuit, and a PCM control circuit on the surface of the peripheral region of the semiconductor front-end device, wherein the I / O circuit, the MCU logic circuit, the analog circuit, and the PCM control circuit constitute the peripheral region device; and, adopting a back-end process to form an embedded phase change memory cell array in the array region.

2. The method according to claim 1, characterized in that, forming the embedded phase change memory cell array in the array region includes: adopting a double-patterning process to form the embedded phase change memory cell array composed of at least two columnar three-dimensional phase change memory cells on the surface of the array region; or, adopting a single-patterning process to form the embedded phase change memory cell array composed of at least two columnar three-dimensional phase change memory cells on the surface of the array region.

3. The method according to claim 2, characterized in that, the adopting the double-patterning process to form the embedded phase change memory cell array composed of at least two columnar three-dimensional phase change memory cells on the surface of the array region includes: forming a phase change memory cell stack and a first mask layer stacked in sequence on the surface of the array region; adopting the double-patterning process to form a mask pattern with a grid-like pattern; etching the first mask layer based on the mask pattern to form a first etched mask layer; using the first etched mask layer as a mask to etch the phase change memory cell stack to form at least two columnar three-dimensional phase change memory cells arranged in a grid-like pattern; wherein the at least two three-dimensional phase change memory cells arranged in a grid-like pattern constitute the embedded phase change memory cell array.

4. The method according to claim 3, characterized in that, the phase change memory cell stack includes a bottom stack and a top stack stacked in sequence from bottom to top; the using the first etched mask layer as a mask to etch the phase change memory cell stack includes: using the first etched mask layer as a mask to perform a first etching on the top stack to form top stack units; depositing and forming a first encapsulation layer on the surface of the top stack units; using the top stack units with the first encapsulation layer as a mask to perform a second etching on the bottom stack to form bottom stack units; depositing and forming a second encapsulation layer on the surface of the bottom stack units to form at least two columnar three-dimensional phase change memory cells arranged in a grid-like pattern.

5. The method according to claim 4, characterized in that, the top stack includes, formed in sequence from bottom to top: a PCM element layer, a first electrode layer, and a hard mask layer; the using the first etched mask layer as a mask to perform a first etching on the top stack to form top stack units includes: Using the first etching mask layer as a mask, sequentially perform first etching on the hard mask layer, the first electrode layer, and the PCM element layer to form a hard etched mask layer, a first etched electrode layer, and a PCM etched element layer, and to form a first through hole penetrating the hard etched mask layer, the first etched electrode layer, and the PCM etched element layer, and a top stack unit located around the first through hole.

6. The method according to claim 5, wherein, the depositing and forming a first encapsulation layer on the surface of the top stack unit includes: depositing a first encapsulation material on the sidewall of the first through hole and the surface of the hard etched mask layer to form the first encapsulation layer.

7. The method according to claim 6, wherein, the bottom stack includes, formed successively from bottom to top: a third electrode layer, a selector layer, and a second electrode layer; the performing second etching on the bottom stack using the top stack unit having the first encapsulation layer as a mask to form a bottom stack unit includes: using the top stack unit having the first encapsulation layer as a mask, sequentially performing second etching on the second electrode layer, the selector layer, and the third electrode layer to form a second etched electrode layer, an etched selector layer, and a third etched electrode layer, and to form a second through hole penetrating the second etched electrode layer, the etched selector layer, and the third etched electrode layer, and the bottom stack unit located around the second through hole.

8. The method according to claim 7, wherein, the depositing and forming a second encapsulation layer on the surface of the bottom stack unit includes: depositing a second encapsulation material on the sidewall of the second through hole and the surface of the bottom stack unit to form the second encapsulation layer.

9. The method according to claim 8, wherein, the method further includes: filling a gap material on the surface of the second encapsulation layer to form a gap material layer; starting from the upper surface of the gap material layer, sequentially etching the gap material layer, the second encapsulation layer, the first encapsulation layer, and the hard etched mask layer to expose the first etched electrode layer; forming word line contacts on the exposed surfaces of the plurality of first etched electrode layers; forming a word line on each of the word line contacts.

10. The method according to claim 3, wherein, before forming the phase change memory cell stack, the method further includes: depositing and forming a plurality of bit lines extending in a first direction on the surface of the array region; depositing and forming a dielectric layer on the plurality of bit lines; etching the dielectric layer based on the positions of the plurality of bit lines to form a bit line contact hole corresponding to each position; depositing a first contact material in the bit line contact hole to form a bit line contact on each of the bit lines; the bit line contact is used to connect the bit line to the phase change memory cell stack.

11. The method according to claim 2, wherein, The embedded phase change memory cell array has a stack structure, and the stack structure includes at least one layer of sub-structure, and each of the sub-structures is composed of at least two columnar three-dimensional phase change memory cells.

12. According to the method described in claim 1, wherein, the method further includes: depositing and forming a first dielectric layer and a first interconnect layer on the surface of the semiconductor front-end device; forming the embedded phase change memory cell array on the surface of the first interconnect layer located in the array region; depositing and forming a second dielectric layer and a second interconnect layer stacked in sequence around the embedded phase change memory cell array to form the three-dimensional memory.

13. According to the method described in claim 12, wherein, the first dielectric layer is formed through the following steps: depositing and forming the first dielectric layer on the surface of the semiconductor front-end device; etching the first dielectric layer to form a plurality of first contact holes extending in a direction perpendicular to the surface of the semiconductor front-end device; depositing a second contact material in the plurality of first contact holes to correspondingly form a plurality of first contact lines; wherein, the upper surfaces of the plurality of first contact lines are flush with the surface of the first dielectric layer.

14. According to the method described in claim 13, wherein, the first interconnect layer is formed through the following steps: forming a metal stack on the surfaces of the first contact lines and the first dielectric layer; the metal stack includes a plurality of metal layers stacked in sequence; etching the metal stack to form a plurality of first metal components; depositing a dielectric material around each of the first metal components to form the first interconnect layer.

15. A three-dimensional memory is formed by using the method for forming a three-dimensional memory according to any one of claims 1 to 14, wherein, the three-dimensional memory includes: a semiconductor front-end device; the semiconductor front-end device includes a peripheral region and an array region; peripheral region devices located on the surface of the peripheral region; an embedded phase change memory cell array located on the surface of the array region, wherein the embedded phase change memory cell array is composed of at least two columnar three-dimensional phase change memory cells.

16. According to the three-dimensional memory described in claim 15, wherein, the embedded phase change memory cell array has a stack structure, and the stack structure includes at least one layer of sub-structure, and each of the sub-structures is composed of at least two columnar three-dimensional phase change memory cells.

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