Memory components

Abstract

The present invention discloses a memory component, which includes a memory structure. The memory structure includes a substrate, a channel region, a first doped region, a second doped region, a floating gate and a dielectric layer. The channel region is arranged on the substrate. The first doped region and the second doped region are arranged on the substrate and are respectively located on both sides of the channel region. The floating gate is arranged on the channel region. The dielectric layer is arranged between the floating gate and the channel region, between the floating gate and the first doped region, and between the floating gate and the second doped region. The floating gate and the first doped region partially overlap, and / or the floating gate and the second doped region do not overlap, and in the length direction of the channel region, the side wall of the floating gate adjacent to the second doped region and the boundary between the second doped region and the channel region are separated by a distance.

Description

Technical Field

[0001] The present invention relates to a memory device, and more particularly to a memory device capable of improving a weak-program or stuck bit (also called over-erase) phenomenon. Background Art

[0002] Non-volatile memory (NVM) has the advantages of multiple operations such as programming operation, reading operation, erasing operation, and the stored data will not disappear after power failure. Therefore, non-volatile memory has been widely used in personal computers and electronic devices.

[0003] Generally speaking, the efficiency of a programming operation of a non-volatile memory may depend on the coupling effect between the gate and the source and the coupling effect between the gate and the drain. Depending on the effect of the process on the memory component including the non-volatile memory, in one case, the initial electron injection point of the non-volatile memory may be too high to inject enough electrons, so weak programming may occur during the programming operation of the non-volatile memory. In another case, the electrons may not be effectively injected, so a fixed bit may occur during the programming operation of the non-volatile memory. As a result, the efficiency of the programming operation is affected by the weak programming or the fixed bit. Therefore, how to effectively improve the weak programming and the fixed bit becomes one of the important topics. Summary of the invention

[0004] The present invention is directed to a memory device that can improve weakly programmed or stuck bits.

[0005] According to an embodiment of the present invention, a memory component includes a memory structure. The memory structure includes a substrate, a channel region, a first doped region, a second doped region, a floating gate and a dielectric layer. The channel region is arranged on the substrate. The first doped region and the second doped region are arranged on the substrate and are respectively located on both sides of the channel region. The floating gate is arranged on the channel region. The dielectric layer is arranged between the floating gate and the channel region, between the floating gate and the first doped region, and between the floating gate and the second doped region. The floating gate and the second doped region do not overlap, and in the length direction of the channel region, the side wall of the floating gate adjacent to the second doped region and the boundary between the second doped region and the channel region are separated by a distance; and / or the floating gate and the first doped region partially overlap.

[0006] In summary, in the memory component of the present invention, since the overlap area between the floating gate and the source increases and / or the distance between the floating gate and the drain increases, weak programming during the programming operation of the nonvolatile memory can be improved. In addition, since the overlap area between the floating gate and the drain increases and / or the distance between the floating gate and the source increases, the stuck bit during the programming operation of the nonvolatile memory can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a cross-sectional schematic diagram of a memory component according to a first embodiment of the present invention;

[0008] Figure 2 is a cross-sectional schematic diagram of a memory component according to a second embodiment of the present invention;

[0009] Figure 3 is a cross-sectional schematic diagram of a memory component according to a third embodiment of the present invention;

[0010] Figure 4 is a cross-sectional schematic diagram of a memory component according to a fourth embodiment of the present invention;

[0011] Figure 5A is a cross-sectional schematic diagram of a memory component according to a fifth embodiment of the present invention;

[0012] Figure 5B yes Figure 5A A top view schematic diagram of a memory component;

[0013] Figure 6 is a cross-sectional schematic diagram of a memory component according to a sixth embodiment of the present invention;

[0014] Figure 7 is a cross-sectional schematic diagram of a memory component according to a seventh embodiment of the present invention;

[0015] Figure 8 is a cross-sectional schematic diagram of a memory component according to an eighth embodiment of the present invention;

[0016] Fig. 9 is a cross-sectional schematic diagram of a memory component according to a ninth embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn to their original size. For ease of understanding, the same components will be described with the same symbols in the following description.

[0018] The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".

[0019] In addition, in this article, the range expressed by "a value to another value" is a summary expression method to avoid listing all the values ​​in the range one by one in the specification. Therefore, the description of a specific numerical range covers any value in the numerical range, and covers a smaller numerical range defined by any value in the numerical range.

[0020] In addition, directional terms mentioned herein, such as “upper”, “lower”, etc., are only used to refer to the directions of the drawings and are not used to limit the present invention.

[0021] When the terms "first", "second", etc. are used to describe components, they are only used to distinguish these components from each other, and do not limit the order or importance of these components. Therefore, in some cases, the first component may also be referred to as the second component, and the second component may also be referred to as the first component, and this does not deviate from the scope of the present invention.

[0022] In one embodiment of the present invention, by increasing the overlap area between the floating gate and the source and / or increasing the distance between the floating gate and the drain, weak programming can be effectively improved. In addition, in other embodiments of the present invention, by increasing the overlap area between the floating gate and the drain and / or increasing the distance between the floating gate and the source, the fixed bit can be effectively improved. The memory components of the embodiments of the present invention will be described in detail below.

[0023] Figure 1 FIG. 1 is a cross-sectional schematic diagram of a memory component according to a first embodiment of the present invention. Figure 1 , the memory component 10 includes a memory structure 103. The memory structure 103 includes a substrate 100, a channel region 102, a first doped region 104, a second doped region 106, a dielectric layer 108, and a floating gate 110. In addition, the memory component 10 includes a conductive line 112 connected to the first doped region 104 and a conductive line 114 connected to the second doped region 106.

[0024] In the memory component 10, the substrate 100 may include a glass substrate 100a and a buffer layer 100b disposed on the glass substrate 100a. The buffer layer 100b may be an oxide layer, but the present invention is not limited thereto. In other embodiments, a silicon substrate may be used instead of the glass substrate 100a. The channel region 102 is disposed on the substrate 100 (buffer layer 100b). The channel region 102 may be an undoped polysilicon layer, but the present invention is not limited thereto. The first doping region 104 and the second doping region 106 are disposed on the substrate 100 (buffer layer 100b), and are respectively located on both sides of the channel region 102 and serve as the source and drain of the memory structure 103. The first doping region 104 and the second doping region 106 have the same doping concentration and the same conductivity type. For example, the first doping region 104 and the second doping region 106 may be P-type doping regions with the same doping concentration, or the first doping region 104 and the second doping region 106 may be N-type doping regions with the same doping concentration.

[0025] The dielectric layer 108 is disposed on the channel region 102, the first doping region 104, and the second doping region 106. In the present embodiment, the dielectric layer 108 covers the channel region 102, the first doping region 104, and the second doping region 106. That is, the dielectric layer 108 covers the top surface of the channel region 102, the top surface and sidewalls of the first doping region 104, and the top surface and sidewalls of the second doping region 106, but the present invention is not limited thereto. The dielectric layer 108 may be an oxide layer, but the present invention is not limited thereto.

[0026] The floating gate 110 is disposed on the channel region 102. In other words, in the present embodiment, the dielectric layer 108 is disposed between the floating gate 110 and the channel region 102, between the floating gate 110 and the first doping region 104, and between the floating gate 110 and the second doping region 106 to isolate the floating gate 110 from the channel region 102, the first doping region 104, and the second doping region 106.

[0027] In addition, in this embodiment, the wire 112 and the wire 114 can be respectively located on both sides of the floating gate 110, and penetrate the dielectric layer 108 to be respectively connected to the first doped region 104 and the second doped region 106. When the first doped region 104 serves as a source, the wire 112 can serve as a source line, and when the second doped region 106 serves as a drain, the wire 114 can serve as a bit line. Alternatively, when the first doped region 104 serves as a drain, the wire 112 can serve as a bit line, and when the second doped region 106 serves as a source, the wire 114 can serve as a source line.

[0028] In the present embodiment, the floating gate 110 does not overlap with the first doping region 104, and the floating gate 110 does not overlap with the second doping region 106. In other words, from a top view, the sidewall SW1 of the floating gate 110 adjacent to the first doping region 104 is aligned with the boundary BD1 between the first doping region 104 and the channel region 102, and the sidewall SW2 of the floating gate 110 adjacent to the second doping region 106 is aligned with the boundary BD2 between the second doping region 106 and the channel region 102. Therefore, in the present embodiment, the width Wg of the floating gate 110 is equal to the channel length Lc of the channel region 102, as shown in FIG. Figure 1 Herein, “channel length” refers to the length of the channel region 102 in the length direction from the first doping region 104 to the second doping region 106 or from the second doping region 106 to the first doping region 104 .

[0029] Figure 2 is a cross-sectional schematic diagram of a memory component according to a second embodiment of the present invention. Figure 2 The difference between this embodiment and the first embodiment is that in this embodiment, in addition to the memory structure 103, the wire 112 and the wire 114, the memory component 20 further includes a selection transistor ST connected in series with the memory structure 103. The selection transistor ST can be arranged between the source of the memory structure and the source line. In this embodiment, when the first doped region 104 serves as the source of the memory structure 103, the selection transistor ST is arranged between the first doped region 104 and the wire 112 serving as the source line.

[0030] Specifically, in the present embodiment, the selection transistor ST may include a channel region 116, a third doped region 118, a first doped region 104 shared with the memory structure 103, a dielectric layer 108, and a selection gate 120. The third doped region 118 is the same as the first doped region 104, and the third doped region 118 and the first doped region 104 may serve as a source and a drain of the selection transistor ST, respectively. The dielectric layer 108 is disposed between the selection gate 120 and the channel region 116 and serves as a gate dielectric layer.

[0031] In another embodiment, when the first doped region 104 serves as the drain of the memory structure 103 , the selection transistor ST is disposed between the second doped region 106 serving as the source of the memory structure 103 and a conductive line (not shown) serving as a source line.

[0032] Figure 3 FIG. 4 is a cross-sectional schematic diagram of a memory component according to a third embodiment of the present invention. Figure 3 The difference between this embodiment and the first embodiment is that the memory element 30 of this embodiment includes a memory structure 103 a , and the memory structure 103 a includes a floating gate 110 a having a larger width Wg1 .

[0033] In the present embodiment, the floating gate 110a extends to the top of the first doping region 104, so that the floating gate 110a and the first doping region 104 partially overlap, so as to increase the overlapping area between the floating gate 110a and the first doping region 104. That is, from a top view, the side wall SW2 of the floating gate 110a adjacent to the second doping region 106 is aligned with the boundary BD2 between the second doping region 106 and the channel region 102, while the side wall SW1 of the floating gate 110a adjacent to the first doping region 104 is not aligned with the boundary BD1 between the first doping region 104 and the channel region 102.

[0034] In the present embodiment, the floating gate 110a extends over the first doping region 104 by a width W1. Therefore, the floating gate 110a has a larger width than the floating gate 110 in the memory structure 103. Therefore, the width Wg1 of the floating gate 110a is the sum of the width W1 and the width Wg (or the channel length Lc) of the floating gate 110. In this way, without changing the design of the first doping region 104 and the second doping region 106 (the width of the first doping region 104 is substantially equal to the width of the second doping region 106), by controlling the overlap area between the floating gate 110a and the first doping region 104, the coupling effect between the floating gate 110a and the first doping region 104 can be effectively improved due to the increase in the coupling ratio.

[0035] When the overlapping area between the floating gate 110 and the first doping region 104 is too small, the coupling effect between the floating gate 110 and the first doping region 104 cannot be effectively improved. When the overlapping area between the floating gate 110 and the first doping region 104 is too large, in addition to being unable to further improve the coupling effect between the floating gate 110 and the first doping region 104, the layout design of the memory device will be affected due to the excessive size of the floating gate 110a. In the present embodiment, the overlapping width W1 of the floating gate 110a and the first doping region 104 is between 0.2 times and 2 times the channel length Lc of the channel region 102, preferably between 0.25 times and 1.5 times. Within this range, the coupling effect between the floating gate 110a and the first doping region 104 can be effectively improved, and the size of the floating gate 110a will not be too large to affect the layout design of the memory device. For example, when the channel length Lc of the channel region 102 is about 4.5 μm, the width W1 may be between 0.9 μm and 9 μm, and preferably between 1.125 μm and 6.75 μm.

[0036] The memory component 30 can effectively improve weakly programmed or stuck bits during a programming operation, as will be described below.

[0037] During the programming operation, when the memory component 30 is subjected to weak programming, since the floating gate 110a and the first doped region 104 partially overlap, the first doped region 104 can be used as a source, and thus the coupling ratio at the source can be increased. Therefore, weak programming can be improved. For example, in order to improve weak programming, the first doped region 104 is used as a source and receives a first voltage through the wire 112 (source line), and the second doped region 106 is used as a drain and receives a second voltage lower than the first voltage through the wire 114 (bit line) to reduce the initial electron injection point and inject more electrons. In this way, weak programming can be effectively improved. For example, the first voltage can be at a VPP level, and the second voltage can be 0V, where VPP is a positive value. Alternatively, the first voltage can be 0V, and the second voltage can be at a -VPP level.

[0038] During a programming operation of the memory element 30, a memory element in which the sidewall of the floating gate is substantially aligned with the boundary between the doped region and the channel region (the drain current (Ioff) is 1×10 -10 A, discharge current (Ion) is 18×10 -6 A) compared to the memory element 30, the memory element 30 may have a lower leakage current (3×10 -11 A) and higher discharge current (24×10 -6 A), achieving nearly 33% improvement in operating performance.

[0039] In addition, during a programming operation, when the memory element 30 is subjected to a fixed bit, since the floating gate 110a and the first doped region 104 partially overlap, the first doped region 104 can serve as a drain, and thus the coupling ratio at the drain can be increased. Therefore, the fixed bit can be improved. For example, in order to improve the fixed bit, the first doped region 104 is used as a drain and receives a first voltage through the wire 112 (bit line), and the second doped region 106 is used as a source and receives a second voltage higher than the first voltage through the wire 114 (source line) to appropriately adjust the higher initial electron injection point. In this way, the fixed bit can be effectively improved.

[0040] Figure 4 FIG. 4 is a cross-sectional schematic diagram of a memory component according to a fourth embodiment of the present invention. Figure 4 The difference between this embodiment and the first embodiment is that the memory component 40 of this embodiment includes a memory structure 103b, and the memory structure 103b includes a channel region 102a with a smaller channel length Lc1 and a first doping region 104a with a larger width.

[0041] In the present embodiment, the first doping region 104a extends into the region below the floating gate 110, so that the floating gate 110 and the first doping region 104a partially overlap to increase the overlapping area between the floating gate 110 and the first doping region 104a. That is, from a top view, the side wall SW2 of the floating gate 110 adjacent to the second doping region 106 is aligned with the boundary BD2 between the second doping region 106 and the channel region 102a, while the side wall SW1 of the floating gate 110 adjacent to the first doping region 104a is not aligned with the boundary BD1 between the first doping region 104a and the channel region 102a.

[0042] In the present embodiment, the first doping region 104a extends under the floating gate 110 by a width W2, so that the width of the first doping region 104a is greater than the width of the second doping region 106. Therefore, compared with the channel region 102 in the memory structure 103, the channel region 102a has a smaller channel length. Therefore, the channel length Lc1 of the channel region 102a is the width Wg (or channel length Lc) of the floating gate 110 minus the width W2. In this way, without changing the design of the floating gate 110 and the second doping region 106, by controlling the overlap area between the floating gate 110 and the first doping region 104a, the coupling effect between the floating gate 110 and the first doping region 104a can be effectively improved due to the increase in the coupling ratio.

[0043] In the present embodiment, the overlapping width W2 of the floating gate 110 and the first doping region 104a is between 0.2 and 0.5 times, preferably between 0.25 and 0.3 times, of the width Wg of the floating gate 110. Within this range, the coupling effect between the floating gate 110 and the first doping region 104a can be effectively improved, and the channel length of the channel region 102a will not be too short to affect the performance of the memory device. For example, when the width Wg1 of the floating gate 110 is about 4.5 μm, the width W2 can be between 0.9 μm and 2.25 μm, preferably between 1.125 μm and 1.35 μm.

[0044] Similar to the memory device 30, since the floating gate 110 and the first doped region 104a partially overlap, the overlapping area between the floating gate 110 and the first doped region 104a is increased, thereby effectively improving the weak programming or fixed bit.

[0045] The programming operation of the memory component 40 is similar to the programming operation of the memory component 30 and thus will not be described further.

[0046] Figure 5A FIG. 5 is a cross-sectional schematic diagram of a memory component according to a fifth embodiment of the present invention. Figure 5AThe difference between this embodiment and the first embodiment is that the memory component 50 of this embodiment includes a memory structure 103c, and the memory structure 103c includes a channel region 102b with a larger channel length Lc2 and a second doping region 106a with a width smaller than the first doping region 104.

[0047] In the present embodiment, the channel region 102b extends from the sidewall SW2 of the floating gate 110, so that the sidewall of the floating gate 110 and the second doping region 106a are separated by a distance, and the width of the second doping region 106a is smaller than the width of the second doping region 106. That is, from a plan view, the sidewall SW1 of the floating gate 110 adjacent to the first doping region 104 is aligned with the boundary BD1 between the first doping region 104 and the channel region 102b, while the sidewall SW2 of the floating gate 110 adjacent to the second doping region 106 is not aligned with the boundary BD2 between the second doping region 106 and the channel region 102b.

[0048] Figure 5B yes Figure 5A A top view of the memory components of FIG. Figure 5B As shown, from a top view, in the length direction (X direction) of the channel region 102b, the sidewall SW2 of the floating gate 110 and the boundary BD2 between the second doping region 106 and the channel region 102b are separated by a distance W3. In other words, the floating gate 110 and the second doping region 106 are separated by a distance W3 in the length direction (X direction) of the channel region 102b. Therefore, compared with the channel region 102 of the memory structure 103, the channel region 102b has a larger channel length. Therefore, the channel length Lc2 of the channel region 102b is the sum of the distance W3 and the width Wg of the floating gate 110 (or the channel length Lc of the channel region 102). In this way, without changing the design of the first doping region 104 and the floating gate 110, the coupling effect between the floating gate 110 and the second doping region 106a can be effectively reduced by controlling the distance W3.

[0049] In the present embodiment, the distance W3 is between 0.05 and 0.5 times the width Wg of the floating gate 110, preferably between 0.1 and 0.2 times. Within the above range, the coupling effect between the floating gate 110 and the second doping region 106a can be effectively reduced, and the size of the channel region 102b will not be too large to affect the layout design of the memory device. For example, when the width Wg is about 4.5 μm, the distance W3 can be between 0.225 μm and 2.25 μm, preferably between 0.45 μm and 0.9 μm.

[0050] During a programming operation, when the memory element 50 is subjected to weak programming, since the sidewall SW2 of the floating gate 110 is separated from the boundary BD2 between the second doping region 106a and the channel region 102b by a distance W3, the distance between the floating gate 110 and the second doping region 106a is increased, and thus the second doping region 106a can serve as a drain, and thus the coupling ratio at the drain can be reduced. Therefore, the weak programming can be improved.

[0051] In addition, during a programming operation, when the memory element 50 is subjected to a stuck bit, since the sidewall SW2 of the floating gate 110 is separated from the boundary BD2 between the second doping region 106a and the channel region 102b by a distance W3, the distance between the floating gate 110 and the second doping region 106a is increased, and thus the second doping region 106a can serve as a source, and thus the coupling ratio at the source can be reduced. Therefore, the stuck bit can be improved.

[0052] The programming operation of the memory component 50 is similar to the programming operation of the memory component 30 and thus will not be described further.

[0053] Figure 6 FIG. 4 is a cross-sectional schematic diagram of a memory component according to a sixth embodiment of the present invention. Figure 6 The difference between this embodiment and the first embodiment is that the memory element 60 of this embodiment includes a memory structure 103d, and the memory structure 103d includes a floating gate 110b with a smaller width Wg2.

[0054] In the present embodiment, the floating gate 110b is shortened from the boundary between the second doping region 106 and the channel region 102, so that the floating gate 110b is separated from the second doping region 106 by a distance. That is, from a top view, the side wall SW1 of the floating gate 110b adjacent to the first doping region 104 is aligned with the boundary BD1 between the first doping region 104 and the channel region 102, while the side wall SW2 of the floating gate 110b adjacent to the second doping region 106 is not aligned with the boundary BD2 between the second doping region 106 and the channel region 102.

[0055] In this embodiment, in the length direction of the channel region 102 ( Figure 5B In the X direction in the direction of the channel region 102), the sidewall SW2 of the floating gate 110b is separated from the boundary BD2 between the second doping region 106 and the channel region 102 by a distance W4. In other words, the floating gate 110b and the second doping region 106 are spaced apart in the length direction of the channel region 102 ( Figure 5B104 and 106). The first doping region 104 and the second doping region 106 are separated by a distance W4 in the X direction (in the X direction). Therefore, compared with the floating gate 110 of the memory structure 103, the floating gate 110b has a smaller width. Therefore, the width Wg2 of the floating gate 110b is the channel length Lc of the channel region 102 (or the width Wg of the floating gate 110) minus the distance W4. In this way, without changing the design of the first doping region 104 and the second doping region 106 (the width of the first doping region 104 is substantially equal to the width of the second doping region 106), the coupling effect between the floating gate 110b and the second doping region 106 can be effectively reduced by controlling the distance W4.

[0056] In the present embodiment, the distance W4 is between 0.05 and 0.5 times, preferably between 0.1 and 0.2 times, of the channel length Lc of the channel region 102. Within the above range, the coupling effect between the floating gate 110b and the second doping region 106 can be effectively reduced, and the width of the floating gate 110b will not be too small to affect the performance of the memory device. For example, when the channel length Lc of the channel region 102 is about 4.5 μm, the distance W4 can be between 0.225 μm and 2.25 μm, preferably between 0.45 μm and 0.9 μm.

[0057] Similar to the memory device 50, since the sidewall SW2 of the floating gate 110 is separated from the boundary BD2 between the second doping region 106 and the channel region 102b by a distance W4, the distance between the floating gate 110b and the second doping region 106 is increased, thereby effectively improving weak programming or fixed bits.

[0058] The programming operation of the memory component 60 is similar to the programming operation of the memory component 30 and thus will not be described further.

[0059] Figure 7 FIG. 1 is a cross-sectional schematic diagram of a memory component according to a seventh embodiment of the present invention. In this embodiment, the third embodiment and the fifth embodiment are combined. Figure 7 The difference between this embodiment and the first embodiment is that the memory component 70 of this embodiment includes a memory structure 103e, and the memory structure 103e includes a floating gate 110a with a larger width Wg1, a channel region 102b with a larger channel length Lc2, and a second doped region 106a with a smaller width.

[0060] In the present embodiment, since the overlap area between the floating gate 110a and the first doping region 104 is increased and the distance between the floating gate 110a and the second doping region 106a is increased, the weak programming or fixed bit can be effectively improved.

[0061] Likewise, according to actual needs, the above embodiments may be combined to increase the overlapping area between the floating gate and the first doped region and to increase the distance between the floating gate and the second doped region, so as to effectively improve weak programming or fixed bits.

[0062] In addition, like the second embodiment, the memory element of each of the above embodiments may further include a selection transistor connected in series with the memory structure.

[0063] For example, similar to the memory element 20, the memory element 80 may include a memory structure 103a, a conductive line 112, a conductive line 114, and a selection transistor ST. Figure 8 The memory structure 103a and the selection transistor ST share the first doping region 104. The conductive line 112 is connected to the third doping region 118 of the selection transistor ST.

[0064] In the present embodiment, during the programming operation, when the memory element 80 is subjected to weak programming, since the overlap area between the floating gate 110a and the first doped region 104 increases, the first doped region 104 can serve as a source and the selection transistor ST is disposed between the source of the memory structure 103a and the conductive line 112 as a source line, the coupling ratio at the source can be increased. Therefore, the weak programming can be improved.

[0065] In another embodiment, Fig. 9 As shown, in the memory element 90, the memory structure 103a and the selection transistor ST share the second doping region 106. The conductive line 114 is connected to the third doping region 118 of the selection transistor ST. During the programming operation, when the memory element 90 is subjected to a fixed bit, since the overlap area between the floating gate 110a and the first doping region 104 increases, the first doping region 104 can serve as a drain and the selection transistor ST is arranged between the source of the memory structure 103a and the conductive line 114 as a source line, the coupling ratio at the drain can be increased. Therefore, the fixed bit can be improved.

[0066] Similarly, each of the above-mentioned memory structures 103b to 103e may be included in a memory component together with a selection transistor ST according to actual needs.

[0067] In other embodiments, the memory structure may include a spacer disposed on the sidewall of the floating gate according to actual needs. In addition, the memory structure may be integrated with other semiconductor structures in a memory component according to actual needs.

[0068] It should be noted that the above embodiments can preferably be implemented using a thin film transistor (TFT) process, but the present invention is not limited thereto.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory component, characterized in that: include: Memory structure, including: substrate; A channel region is disposed on the substrate; A first doping region and a second doping region are disposed on the substrate and are respectively located on two sides of the channel region, wherein a width of the first doping region is equal to a width of the second doping region; A floating gate is disposed on the channel region; and a dielectric layer disposed between the floating gate and the channel region, between the floating gate and the first doped region, and between the floating gate and the second doped region; and a bit line connected to the first doped region and a source line connected to the second doped region, wherein during a programming operation of the memory component, the first doped region is used to receive a first voltage via the bit line, the second doped region is used to receive a second voltage via the source line, and the first voltage is lower than the second voltage, The floating gate and the second doped region do not overlap, and in the length direction of the channel region, the side wall of the floating gate adjacent to the first doped region and the boundary between the first doped region and the channel region are aligned, and the side wall of the floating gate adjacent to the second doped region and the boundary between the second doped region and the channel region are separated by a distance.

2. The memory component according to claim 1, characterized in that The distance is between 0.05 and 0.5 times the width of the floating gate.

3. The memory component according to claim 1, characterized in that The distance is between 0.05 and 0.5 times the length of the channel region.

4. The memory component according to claim 1, characterized in that The distance is between 0.225 μm and 2.25 μm.

5. The memory component according to claim 1, characterized in that The doping concentration of the first doping region is the same as the doping concentration of the second doping region.

6. The memory component according to claim 1, characterized in that The channel region is undoped.

7. The memory component according to claim 1, characterized in that The substrate includes a glass substrate and a buffer layer disposed on the glass substrate.

8. The memory component according to claim 1, wherein: A select transistor is further included to be connected in series with the memory structure.

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