Phase change memory and manufacturing method thereof

Abstract

The disclosed embodiment of the present invention discloses a phase change memory and a method for manufacturing the phase change memory. The method for manufacturing the phase change memory includes: sequentially forming a stacked first conductive layer, a first electrode layer, a first functional layer, a second electrode layer, a second functional layer, and a third electrode layer on a substrate; forming a first isolation structure on a first area of ​​the substrate that passes through the third electrode layer to the first conductive layer; wherein the first isolation structure extends along a first direction parallel to the substrate; the first isolation structure divides the first electrode layer into first electrode strips; forming a first sacrificial layer on the third electrode layer; forming a second isolation structure that passes through the first sacrificial layer to the first electrode strips; wherein the second isolation structure extends along a second direction perpendicular to the first direction; the second isolation structure divides the first sacrificial layer into first sacrificial strips; the first sacrificial strips form a first groove; and forming a second address line in the first groove.

Description

Technical Field

[0001] The disclosed embodiments relate to the field of semiconductor technology, and in particular to a phase change memory and a method for manufacturing the phase change memory. Background Art

[0002] As an emerging non-volatile memory device, phase change memory has great advantages over flash memory in many aspects such as read and write speed, read and write times, data retention time, unit area, and multi-value realization.

[0003] However, with the development of phase change memory, there are still many problems in the formation of phase change memory cells. Summary of the invention

[0004] The embodiments of the present disclosure provide a phase change memory and a method for manufacturing the phase change memory.

[0005] According to a first aspect of an embodiment of the present disclosure, a method for manufacturing a phase change memory is provided, comprising:

[0006] Forming a stacked first conductive layer, a first electrode layer, a first functional layer, a second electrode layer, a second functional layer, and a third electrode layer in sequence on a substrate;

[0007] forming a first isolation structure on the first region of the substrate that penetrates the third electrode layer to the first conductive layer; wherein the first isolation structure extends along a first direction parallel to the substrate; and the first isolation structure divides the first electrode layer into first electrode strips;

[0008] forming a first sacrificial layer on the third electrode layer;

[0009] forming a second isolation structure penetrating the first sacrificial layer to the first electrode strip; wherein the second isolation structure extends along a second direction perpendicular to the first direction; and the second isolation structure divides the first sacrificial layer into first sacrificial strips;

[0010] removing the first sacrificial strip to form a first trench;

[0011] A second address line is formed in the first trench.

[0012] In the above solution, the substrate further includes a second region arranged in parallel with the first region; a peripheral circuit is formed on the second region;

[0013] The method further comprises:

[0014] Before forming the first sacrificial layer on the third electrode layer, a dielectric layer is formed on the second region.

[0015] In the above scheme, the method further comprises:

[0016] When the first sacrificial layer is formed on the third electrode layer, the first sacrificial layer simultaneously covers the dielectric layer;

[0017] When forming the second isolation structure that penetrates the first sacrificial layer to the first electrode strip, the second isolation structure simultaneously penetrates the dielectric layer;

[0018] When the first sacrificial strip is removed to form the first trench, the first trench is simultaneously formed on the dielectric layer.

[0019] In the above scheme, the method further comprises:

[0020] After forming the first trench, forming a first mask layer on the first trench;

[0021] Using the first mask layer, etching the dielectric layer at the bottom of the first trench to form a second trench that partially deepens the first trench; the bottom of the second trench exposes the peripheral circuit;

[0022] When forming the second address line in the first groove, an extended portion of the second address line and a contact structure are formed in the second groove; the second address line is electrically connected to the peripheral circuit through the contact structure.

[0023] In the above solution, the material of the first mask layer includes carbon.

[0024] In the above scheme, the method further comprises:

[0025] Before forming the first sacrificial layer on the third electrode layer, a contact structure is formed in the dielectric layer; the contact structure is in contact with and electrically connected to the peripheral circuit.

[0026] In the above scheme, the method further comprises:

[0027] When the first sacrificial layer is formed on the third electrode layer, the first sacrificial layer covers the dielectric layer and the contact structure at the same time;

[0028] When forming the second isolation structure that penetrates the first sacrificial layer to the first electrode strip, the second isolation structure simultaneously penetrates the dielectric layer;

[0029] When the first sacrificial strip is removed to form the first groove, the first groove is simultaneously formed on the contact structure;

[0030] When forming the second address line in the first groove, an extended portion of the second address line is formed in the first groove formed on the contact structure; the second address line is electrically connected to the peripheral circuit through the contact structure.

[0031] In the above scheme, the method further comprises:

[0032] Before forming a first isolation structure penetrating from the third electrode layer to the first conductive layer on the first region of the substrate, forming a stop layer on the third electrode layer; the material of the stop layer is the same as that of the second address line;

[0033] The first isolation structure formed on the first region of the substrate and extending from the third electrode layer to the first conductive layer comprises:

[0034] forming a first isolation structure penetrating the stop layer to the first conductive layer;

[0035] The removing the first sacrificial strip to form a first trench comprises:

[0036] The first sacrificial strip is removed by a first etching to form a first trench; wherein the stop layer is used as a stop layer for the first etching.

[0037] In the above scheme, the method further comprises:

[0038] Before forming a first isolation structure penetrating the third electrode layer to the first conductive layer on the first region of the substrate, forming a second sacrificial layer on the third electrode layer;

[0039] The first isolation structure formed on the first region of the substrate and extending from the third electrode layer to the first conductive layer comprises:

[0040] forming a first isolation structure penetrating from the second sacrificial layer to the first conductive layer on the first region of the substrate; the first isolation structure divides the second sacrificial layer into a plurality of second sacrificial strips;

[0041] The forming of a first sacrificial layer on the third electrode layer comprises:

[0042] forming a first sacrificial layer on the second sacrificial strip;

[0043] The forming of the second isolation structure penetrating through the first sacrificial layer to the first electrode strip comprises:

[0044] forming a second isolation structure that runs through the second sacrificial strip to the first electrode strip; the second isolation structure divides the second sacrificial strip into second sacrificial blocks;

[0045] The removing the first sacrificial strip to form a first trench comprises:

[0046] removing the first sacrificial strip to form a first trench; and removing the second sacrificial block to form a third trench;

[0047] The forming of a second address line in the first trench comprises:

[0048] A second address line is formed in the first trench and an additional portion of the second address line is formed in the third trench.

[0049] In the above scheme, the method further comprises:

[0050] Before forming the first isolation structure, forming a third isolation structure that penetrates the third electrode layer and the second functional layer; wherein the first isolation structure penetrates the third isolation structure, and the third isolation structure divides the third electrode layer and the second functional layer into third electrode strips and second functional strips;

[0051] and / or,

[0052] Before forming the second isolation structure, a fourth isolation structure is formed which penetrates the first sacrificial layer, the third electrode strip, and the second functional strip; wherein the second isolation structure penetrates the fourth isolation structure.

[0053] In the above scheme, the first functional layer includes a gating layer, and the conduction of the gating element formed by the gating layer realizes the heating or quenching of the phase change memory element formed by the phase change memory layer by the electrode, so as to realize the switching between the crystalline state and the amorphous state of the phase change memory element; the second functional layer includes the phase change memory layer, and the data storage is realized by the switching between the crystalline state and the amorphous state of the phase change memory element.

[0054] According to a second aspect of an embodiment of the present disclosure, a phase change memory is provided, including:

[0055] A first address line, a phase change memory unit, and a second address line are sequentially stacked on a first region of a substrate; wherein the first address line and the second address line are parallel to the same plane and perpendicular to each other; the phase change memory unit comprises a first electrode, a first functional element, a second electrode, a second functional element, and a third electrode which are sequentially stacked; the first electrode, the first functional element, the second electrode, the second functional element, and the third electrode are perpendicular to the first address line and the second address line;

[0056] A contact structure and an extended portion of a second address line are disposed on a second region of the substrate; a peripheral circuit is disposed on the second region, the contact structure contacts the peripheral circuit, and the contact structure contacts and is perpendicular to the second address line;

[0057] A second isolation structure; wherein the second isolation structure extends along the second direction, the second isolation structure is alternately arranged in parallel with the stacked phase-change memory unit and the second address line on the first region, and the second isolation structure covers part of the side wall of the contact structure on the second region.

[0058] In the above scheme, the phase change memory further includes: an additional portion of the second address line;

[0059] The additional portion of the second address line is located between the third electrode and the second address line on the first region, and the additional portion of the second address line is perpendicular to both the first address line and the second address line.

[0060] In the above solution, the phase change memory further includes: a stop block; the stop block is located between the third electrode and the second address line, and the stop block is perpendicular to both the first address line and the second address line.

[0061] The disclosed embodiment provides a phase change memory and a method for manufacturing the phase change memory. The method for manufacturing the phase change memory includes: sequentially forming a stacked first conductive layer, a first electrode layer, a first functional layer, a second electrode layer, a second functional layer, and a third electrode layer on a substrate; forming a first isolation structure penetrating the third electrode layer to the first conductive layer on a first region of the substrate; wherein the first isolation structure extends in a first direction parallel to the substrate; the first isolation structure divides the first electrode layer into first electrode strips; forming a first sacrificial layer on the third electrode layer; forming a second isolation structure penetrating the first sacrificial layer to the first electrode strips; wherein the second isolation structure extends in a second direction perpendicular to the first direction; the second isolation structure divides the first sacrificial layer into first sacrificial strips; removing the first sacrificial strips to form a first trench; and forming a second address line in the first trench. In the embodiment of the present disclosure, the first sacrificial layer is removed to form a first groove, and a second address line is formed at the position of the first groove. That is to say, in the embodiment of the present disclosure, the material for forming the second address line is directly filled in the formed first groove to form the second address line. In this way, there is no need to etch the material for forming the second address line to form the second address line. In this way, the problem of damage to the second address line caused by insufficient thickness of the mask layer when etching the material for forming the second address line is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 is a partial three-dimensional schematic diagram of a phase change memory according to an embodiment of the present disclosure;

[0063] Figure 2a-2fis a cross-sectional schematic diagram of an implementation process of a phase change memory manufacturing method according to an embodiment of the present disclosure;

[0064] Figure 3 It is a schematic diagram of the implementation process of a phase change memory manufacturing method according to an embodiment of the present disclosure;

[0065] Figure 4a-Figure 4o is a cross-sectional schematic diagram of an implementation process of another phase change memory manufacturing method according to an embodiment of the present disclosure;

[0066] Figure 5a-5k is a cross-sectional schematic diagram of an implementation process of another phase change memory manufacturing method according to an embodiment of the present disclosure;

[0067] Figure 6a is a partial cross-sectional schematic diagram of a phase change memory in the yoz axis plane according to an embodiment of the present disclosure;

[0068] Figure 6b is a partial cross-sectional schematic diagram of a phase change memory in an xoz axis plane according to an embodiment of the present disclosure;

[0069] Figure 7 is a partial schematic diagram of a phase change memory in the yox axis plane according to an embodiment of the present disclosure;

[0070] Figure 8 It is a partial schematic diagram of another phase change memory in the yox axis plane according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0072] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0073] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0074] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0075] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0076] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0077] Phase change memory includes a memory cell array and a peripheral circuit (which can be referred to as CMOS for short); wherein the memory cell array can be integrated on the same die as the peripheral circuit, which allows a wider bus and a higher operating speed. In practical applications, the memory cell array and the peripheral circuit can be formed in different areas on the same plane; or the memory cell array and the peripheral circuit can form a stacked structure, that is, the two are formed on different planes. For example, the memory cell array can be formed above the peripheral circuit to reduce the chip size.

[0078] The following combination Figure 1 The memory cell array is introduced. Figure 1 3D schematic diagram of a phase change memory in an embodiment of the present disclosure. Figure 1 As shown, the phase change memory includes a first address line 1010, a phase change memory unit 1100, and a second address line 1050 stacked in sequence from bottom to top; wherein the phase change memory unit 1100 includes a first electrode 1020a, a first functional element 1030, a second electrode 1020b, a second functional element 1040, and a third electrode 1020c stacked in sequence from bottom to top.

[0079] from Figure 1 It can be seen that the first address line 1010 is perpendicular to the second address line 1050; at the same time, the phase change memory unit 1100 is perpendicular to both the first address line 1010 and the second address line 1050. The first address line 1010 can be used as a bit line (expressed as Bit Line in English), and the second address line 1050 can be used as a word line (expressed as Word Line in English).

[0080] The memory cell array of the three-dimensional phase change memory is composed of a plurality of small memory cell array blocks having bit lines, word lines and phase change memory cells. The word lines and bit lines are formed perpendicular to each other, and the phase change memory cells are self-aligned at the intersection of the word lines and the bit lines. The phase change memory cells are vertical square columns. In practical applications, the word lines and bit lines are usually composed of 20nm / 20nm equal width (L / S, line / space) formed after the patterning process.

[0081] In practical applications, the peripheral circuit may include any suitable digital, analog and / or mixed signal circuits for facilitating the phase change memory to implement various operations such as read operation, write operation, erase operation, etc. For example, the peripheral circuit may include control logic, data buffer, decoder (decoder may also be called decoder), driver and read / write circuit, etc. When the control logic receives the read / write operation command and address data, under the action of the control logic, the decoder may apply the corresponding voltage generated by the driver to the corresponding bit line and word line based on the decoded address to realize data reading and writing, and perform data exchange with the outside through the data buffer.

[0082] In some embodiments, both word lines and bit lines are formed using double patterning technology. The bit lines are formed first, and then the contact structure of the word lines (also called contacts) is formed. Thereafter, metal material for forming the word lines is deposited, and a second mask layer is used to etch the metal material forming the word lines through a double pattern to form the word lines.

[0083] Figure 2a-2f The following is a cross-sectional schematic diagram of the implementation process of a phase change memory manufacturing method provided by an embodiment of the present disclosure. Figure 2a-2f The phase change memory manufacturing method provided in the above embodiment of the present disclosure is specifically described.

[0084] like Figure 2a As shown, a first conductive layer 1010-1, a first electrode layer 1020a-1, a first functional layer 1030-1, a second electrode layer 1020b-1, a second functional layer 1040-1, a third electrode layer 1020c-1, and a second sacrificial layer 1070-1 are sequentially formed on a substrate 1001;

[0085] like Figure 2b As shown, a fourth groove 1081 is formed on the first area 1001a of the substrate 1001, which penetrates the second sacrificial layer 1070-1, the third electrode layer 1020c-1, and the second functional layer 1040-1; the fourth groove 1081 divides the second sacrificial layer 1070-1, the third electrode layer 1020c-1, and the second functional layer 1040-1 into a second sacrificial strip 1070-2, a third electrode strip 1020c-2, and a second functional strip 1040-2.

[0086] like Figure 2cAs shown, a first insulating layer 1061 covering the sidewall of the fourth trench 1081 is formed at least on the sidewall of the fourth trench 1081; a second insulating layer 1062 covering the first insulating layer 1061 is formed; and the second insulating layer 1062 and the first insulating layer 1061 together constitute a third isolation structure. A sixth groove is formed, the sixth groove runs through the fourth groove 1081, the second electrode layer 1020b-1, the first functional layer 1030-1, the first electrode layer 1020a-1, and the first conductive layer 1010-1, the sixth groove divides the second electrode layer 1020b-1, the first functional layer 1030-1, the first electrode layer 1020a-1, and the first conductive layer 1010-1 into a second electrode strip 1020b-2, a first functional strip 1030-2, a first electrode strip 1020a-2, and a first address line 1010, respectively, to form a third insulating layer 1063 covering the sidewall of the sixth groove and the sidewall of the third isolation structure; and a fourth insulating layer 1064 covering the sidewall of the third insulating layer 1063 is formed. The third insulating layer 1063 and the fourth insulating layer 1064 together constitute a first isolation structure.

[0087] The substrate 1001 further includes a second region 1001b arranged in parallel with the first region 1001a; a peripheral circuit is formed on the second region 1001b, such as Figure 2c As shown, a dielectric layer 1080 is formed on the second region 1001 b of the substrate 1001 , and a contact structure 1002 is formed in the dielectric layer 1080 , wherein the contact structure 1002 is electrically connected to the peripheral circuit.

[0088] Here, the contact structure 1002 is electrically connected to the peripheral circuit, and specifically can be electrically connected to a decoder and / or a driver of a second address line in the peripheral circuit. In some specific examples, the contact structure 1002 can be electrically connected to a metal layer in the peripheral circuit, or can be electrically connected to a semiconductor transistor in the peripheral circuit.

[0089] Figure 2e for Figure 2d The cross-sectional view at the AA' position, where AA' and the AA' mentioned below can be specifically combined with Figure 7 The corresponding top view can be understood. Figure 7A partial schematic diagram of a phase change memory in the yox axis plane is shown, and the arrangement of the second address line 1050, the extension part 1052 of the second address line, and the contact structure 1002 are exemplarily shown. The second address line 1050 is arranged at the position corresponding to the first area 1001a, and the extension part 1052 of the second address line is arranged at the position corresponding to the second area 1001b. It should be noted that the contact structure 1002 here cannot be observed from the yox axis plane. The contact structure 1002 is displayed here only for the convenience of showing the positional relationship between the second address line 1050 and the contact structure 1002. In addition, some structures other than the second address line 1050 and the contact structure 1002 are omitted here. The shape of the contact structure here is only an exemplary demonstration and is not used to limit the embodiments of the present disclosure. In actual applications, the shape of the contact structure may include a circle, a rectangle, a square, etc.

[0090] like Figure 2d-Figure 2e As shown, a second conductive layer 1050-1 is formed on the third electrode layer 1020c-1 and the dielectric layer 1080, and a second mask layer 1092-1 is formed on the second conductive layer 1050-1.

[0091] like Figure 2f As shown, a fourth isolation structure is formed that penetrates the second mask layer 1092-1, the second conductive layer 1050-1, the third electrode strip 1020c-2, and the second functional strip 1040-2. The fourth isolation structure includes a first insulating layer 1061 and a second insulating layer 1062, forming a second isolation structure that penetrates the second conductive layer 1050-1, the third electrode strip 1020c-2, the second functional strip 1040-2, the second electrode strip 1020b-2, the first functional strip 1030-2, and the first electrode strip 1020a-2. The second isolation structure includes a third insulating layer 1063 and a fourth insulating layer 1064. The second isolation structure divides the second conductive layer 1050-1, the third electrode strip 1020c-2, the second functional strip 1040-2, the second electrode strip 1020b-2, the first functional strip 1030-2, and the first electrode strip 1020a-2 into a second address line 1050, a third electrode 1020c, a second functional element 1040, a second electrode 1020b, a first functional element 1030, and a first electrode 1020a, respectively.

[0092] In the manufacturing process of the phase change memory provided in the above embodiment, firstly, since the etching to form the first address line 1010 stops at the third electrode layer 1020c-1, the chemical mechanical polishing (CMP) after the contact structure 1002 of the second address line 1050 is formed is performed. The remaining second sacrificial layer 1070-1 will be removed during the chemical polishing process. When removing the second sacrificial layer 1070-1, certain damage will be caused to the third electrode layer 1020c-1, thereby causing the performance of the phase change memory to be out of control. Secondly, since the metal material forming the second address line 1050 is deposited, the metal material forming the second address line 1050 is etched using the second mask layer 1092-1 to form the second address line 1050. Since the process of etching the metal material forming the second address line 1050 to form the second address line 1050 requires a large amount of the second mask layer 1092-1, the insufficiency of the second mask layer 1092-1 will cause erosion on the top of the second address line 1050, and the insufficiency of the second mask layer 1092-1 will also cause a stop problem during subsequent chemical mechanical polishing. Therefore, a thicker second mask layer 1092-1 is required to meet the requirements of high aspect ratio etching.

[0093] Based on some problems existing in the method for manufacturing the phase change memory provided in the above embodiment, the following is proposed: Figure 3 The implementation process of the phase change memory manufacturing method shown in the figure includes the following steps:

[0094] Step 3001: sequentially forming a first conductive layer, a first electrode layer, a first functional layer, a second electrode layer, a second functional layer, and a third electrode layer on a substrate;

[0095] Step 3002: forming a first isolation structure on a first region of the substrate, the first isolation structure extending through the third electrode layer to the first conductive layer; wherein the first isolation structure extends along a first direction parallel to the substrate; and the first isolation structure divides the first electrode layer into first electrode strips;

[0096] Step 3003: forming a first sacrificial layer on the third electrode layer;

[0097] Step 3004: forming a second isolation structure penetrating the first sacrificial layer to the first electrode strip; wherein the second isolation structure extends along a second direction perpendicular to the first direction; and the second isolation structure divides the first sacrificial layer into first sacrificial strips;

[0098] Step 3005: removing the first sacrificial strip to form a first groove;

[0099] Step 3006: Form a second address line in the first trench.

[0100] Figure 4a to Figure 4o FIG. 1 is a cross-sectional schematic diagram of the implementation process of a phase change memory manufacturing method according to an embodiment of the present disclosure. Figure 4a to Figure 4o The manufacturing process of the phase change memory of the embodiment of the present disclosure is described in detail.

[0101] It should be noted that in the xoz axis plane and yoz axis plane involved in the drawings of the present disclosure, the x-axis and the y-axis are parallel to the substrate 1001, the z-axis is perpendicular to the substrate 1001, and the x-axis, y-axis and z-axis are perpendicular to each other.

[0102] Wherein, in step 3001, reference Figure 4a A first conductive layer 1010-1, a first electrode layer 1020a-1, a first functional layer 1030-1, a second electrode layer 1020b-1, a second functional layer 1040-1, and a third electrode layer 1020c-1 are sequentially formed on the surface of the substrate 1001 from bottom to top.

[0103] Here, the constituent material of the substrate 1001 may include a semiconductor material, such as silicon, germanium, or gallium arsenide.

[0104] It should be noted that “from bottom to top” in the embodiment of the present disclosure refers to the direction from the direction close to the surface of the substrate 1001 to the direction away from the surface of the substrate 1001 .

[0105] Here, the constituent material of the first conductive layer 1010 - 1 includes a conductive material, and the conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), and the like.

[0106] Here, the constituent materials of the first electrode layer 1020a-1, the second electrode layer 1020b-1, and the third electrode layer 1020c-1 include amorphous carbon, such as α-phase carbon.

[0107] Here, a first conductive layer 1010-1, a first electrode layer 1020a-1, a first functional layer 1030-1, a second electrode layer 1020b-1, a second functional layer 1040-1, and a third electrode layer 1020c-1 can be formed in sequence on the surface of the substrate 1001 through a deposition process, and the deposition process includes but is not limited to a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a combination thereof, wherein CVD includes metal-organic chemical vapor deposition (MOCVD) and plasma enhanced chemical vapor deposition (PECVD), etc.

[0108] Here, the first functional layer 1030-1 can be a phase change storage layer or a selection layer, and the second functional layer 1040-1 can also be a phase change storage layer or a selection layer. Exemplarily, when the first functional layer 1030-1 is a phase change storage layer, the second functional layer 1040-1 can be a selection layer; when the first functional layer 1030-1 is a selection layer, the second functional layer 1040-1 can be a phase change storage layer.

[0109] In some embodiments, the first functional layer 1030-1 includes a gating layer, and the conduction of the gating element formed by the gating layer realizes the heating or quenching of the phase change memory element formed by the electrode on the phase change memory layer, so as to realize the switching between the crystalline state and the amorphous state of the phase change memory element; the second functional layer 1040-1 includes the phase change memory layer, and the storage of data is realized by the switching between the crystalline state and the amorphous state of the phase change memory element, and then the data is stored by utilizing the difference between the resistivity of the phase change memory element in the amorphous phase and the resistivity of the crystalline phase.

[0110] Here, the constituent materials of the gating layer may include: threshold selection switch (OTS, Ovonic Threshold Switching) materials, such as zinc telluride (Zn a Te b ), Germanium Telluride (Ge a Te b ), niobium oxide (Nb a O b ) or silicon arsenic telluride (Si a As b Te c )wait.

[0111] Here, the constituent materials of the phase change memory layer may include: chalcogenide-based alloys, such as GST (Ge-Sb-Te) alloys, but are not limited thereto. The constituent materials of the phase change memory layer may also include any other suitable phase change materials. It should be noted that when the phase change memory element formed by the phase change memory layer undergoes a phase change, the resistance of the phase change memory element changes. The phase change memory can store data according to the change in the resistance state of the phase change memory element.

[0112] Wherein, in step 3002, a first isolation structure is formed on the first area 1001a of the substrate 1001, which penetrates the third electrode layer 1020c-1, the second functional layer 1040-1, the second electrode layer 1020b-1, the first functional layer 1030-1, the first electrode layer 1020a-1, and the first conductive layer 1010-1; wherein the first isolation structure extends along a first direction parallel to the substrate 1001; the first isolation structure divides the third electrode layer 1020c-1, the second functional layer 1040-1, the second electrode layer 1020b-1, the first functional layer 1030-1, the first electrode layer 1020a-1, and the first conductive layer 1010-1 into a third electrode strip 1020c-2, a second functional strip 1040-2, a second electrode strip 1020b-2, a first functional strip 1030-2, a first electrode strip 1020a-2, and a first address line 1010, respectively.

[0113] Here, the first direction is parallel to the surface of the substrate 1001. In practical applications, the first direction can be understood as the y-axis direction shown in the drawings provided in the present disclosure. It can be understood that the first direction is not limited to the y-axis direction.

[0114] In some embodiments, the method further comprises:

[0115] Before forming a first isolation structure penetrating from the third electrode layer 1020c-1 to the first conductive layer 1010-1 on the first region 1001a of the substrate 1001, forming a stop layer 1060-1 on the third electrode layer 1020c-1; the material of the stop layer 1060-1 is the same as that of the second address line 1050;

[0116] The first isolation structure formed on the first region 1001a of the substrate 1001 and extending through the third electrode layer 1020c-1 to the first conductive layer 1010-1 includes:

[0117] A first isolation structure is formed that penetrates the stop layer 1060 - 1 to the first conductive layer 1010 - 1 .

[0118] The first isolation structure divides the stop layer 1060 - 1 into stop bars 1060 - 2 .

[0119] In some embodiments, the method further comprises:

[0120] Before forming a first isolation structure penetrating the third electrode layer 1020c-1 to the first conductive layer 1010-1 on the first region 1001a of the substrate 1001, forming a second sacrificial layer 1070-1 on the third electrode layer 1020c-1;

[0121] The first isolation structure formed on the first region 1001a of the substrate 1001 and extending through the third electrode layer 1020c-1 to the first conductive layer 1010-1 includes:

[0122] A first isolation structure penetrating the second sacrificial layer 1070 - 1 to the first conductive layer 1010 - 1 is formed on the first region 1001 a of the substrate 1001 ; the first isolation structure divides the second sacrificial layer 1070 - 1 into a plurality of second sacrificial strips 1070 - 2 .

[0123] Here, the second sacrificial layer 1070 - 1 may include a photoresist mask or a hard mask patterned based on a photolithography mask, for example, silicon nitride or the like.

[0124] In some embodiments, the method further comprises:

[0125] Before forming the first isolation structure, a third isolation structure is formed that penetrates the third electrode layer 1020c-1 and the second functional layer 1040-1; wherein the first isolation structure penetrates the third isolation structure, and the third isolation structure divides the third electrode layer 1020c-1 and the second functional layer 1040-1 into a third electrode strip 1020c-2 and a second functional strip 1040-2.

[0126] In practical applications, combined with Figure 4b-4d The method for forming the first isolation structure is described in detail.

[0127] like Figure 4b As shown, etching is first performed in a direction parallel to the z-axis to form a fourth groove 1081 that penetrates the second sacrificial layer 1070-1, the stop layer 1060-1, the third electrode layer 1020c-1, and the second functional layer 1040-1, wherein the bottom of the fourth groove 1081 exposes the surface of the second electrode layer 1020b-1, and the fourth groove 1081 divides the second sacrificial layer 1070-1, the stop layer 1060-1, the third electrode layer 1020c-1, and the second functional layer 1040-1 into a second sacrificial strip 1070-2, a stop strip 1060-2, a third electrode strip 1020c-2, and a second functional strip 1040-2, respectively.

[0128] Here, a method of forming the fourth trench 1081 may include dry plasma etching, but is not limited thereto.

[0129] In practical applications, the fourth groove 1081 may include one or more grooves. The following description will take multiple grooves as an example. Figure 4b As shown, a plurality of fourth grooves 1081 are arranged in parallel along a direction parallel to the x-axis, and each fourth groove 1081 extends along the y-axis direction.

[0130] After forming the fourth trench 1081, refer to Figure 4c As shown, a first insulating layer 1061 is formed to cover the sidewall of the fourth trench 1081 and the upper surface of the second sacrificial strip 1070 - 2 ; a second insulating layer 1062 is formed to cover the first insulating layer 1061 ; the first insulating layer 1061 and the second insulating layer 1062 together constitute a third isolation structure.

[0131] A sixth groove is formed that penetrates the fourth groove 1081, the second electrode layer 1020b-1, the first functional layer 1030-1, the first electrode layer 1020a-1, and the first conductive layer 1010-1, the sixth groove exposes the surface of the substrate 1001, and the sixth groove divides the second electrode layer 1020b-1, the first functional layer 1030-1, the first electrode layer 1020a-1, and the first conductive layer 1010-1 into a second electrode strip 1020b-2, a first functional strip 1030-2, a first electrode strip 1020a-2, and a first address line 1010. The sixth grooves are arranged in parallel along a direction parallel to the x-axis, and each sixth groove extends along the y-axis.

[0132] After the sixth trench is formed, a third insulating layer 1063 is formed to cover the sidewalls of the sixth trench and the sidewalls of the second insulating layer 1062, and the third insulating layer 1063 also covers the bottom of the sixth trench; and a fourth insulating layer 1064 is formed to cover the third insulating layer 1063. The third insulating layer 1063 and the fourth insulating layer 1064 together constitute a first isolation structure.

[0133] In practical applications, the first insulating layer 1061, the second insulating layer 1062, the third insulating layer 1063 and the fourth insulating layer 1064 can be formed by CVD or ALD. The constituent material of the first insulating layer 1061 may include nitrides, such as silicon nitride, but is not limited thereto. The constituent material of the second insulating layer 1062 may include oxides, such as silicon oxide, but is not limited thereto. The constituent material of the third insulating layer 1063 may include nitrides, such as silicon nitride, but is not limited thereto. The constituent material of the fourth insulating layer 1064 may include oxides, such as silicon oxide, but is not limited thereto. The constituent material of the fourth insulating layer 1064 may also be a material with low thermal conductivity.

[0134] In practical applications, after forming the first isolation structure and the third isolation structure, the method further includes: removing the first insulating layer 1061, the second insulating layer 1062, the third insulating layer 1063 and the fourth insulating layer 1064 covering the surface of the second sacrificial strip 1070-2, and exposing the second sacrificial strip 1070-2.

[0135] In practical applications, the first insulating layer 1061 , the second insulating layer 1062 , the third insulating layer 1063 and the fourth insulating layer 1064 covering the surface of the second sacrificial strip 1070 - 2 may be removed by chemical mechanical polishing.

[0136] In some embodiments, reference Figure 4e The substrate 1001 further includes a second region 1001b arranged in parallel with the first region 1001a; a peripheral circuit is formed on the second region 1001b;

[0137] The method further comprises:

[0138] A dielectric layer 1080 is formed on the second region 1001b.

[0139] Here, when the first conductive layer 1010-1, the first electrode layer 1020a-1, the first functional layer 1030-1, the second electrode layer 1020b-1, the second functional layer 1040-1 and the third electrode layer 1020c-1 are sequentially formed on the substrate 1001, the first conductive layer 1010-1, the first electrode layer 1020a-1, the first functional layer 1030-1, the second electrode layer 1020b-1, the second functional layer 1040-1 and the third electrode layer 1020c-1 can be simultaneously formed on the second region 1001b of the substrate 1001; or the first conductive layer 1010-1, the first electrode layer 1020a-1, the first functional layer 1030-1, the second electrode layer 1020b-1, the second functional layer 1040-1 and the third electrode layer 1020c-1 can be only formed on the first region 1001a of the substrate 1001 by setting a cover.

[0140] When the first conductive layer 1010-1, the first electrode layer 1020a-1, the first functional layer 1030-1, the second electrode layer 1020b-1, the second functional layer 1040-1, and the third electrode layer 1020c-1 are simultaneously formed on the second region 1001b of the substrate 1001, the method includes: removing the third electrode layer 1020c-1 to the first conductive layer 1010-1 on the second region 1001b, and forming a dielectric layer 1080 at the removed position. When the first conductive layer 1010-1, the first electrode layer 1020a-1, the first functional layer 1030-1, the second electrode layer 1020b-1, the second functional layer 1040-1, and the third electrode layer 1020c-1 are not formed on the second region 1001b of the substrate 1001, the dielectric layer 1080 can be directly formed on the second region 1001b of the substrate 1001.

[0141] In step 3003, refer to Figure 4f , a first sacrificial layer 1071 - 1 is formed on the third electrode layer 1020c - 1.

[0142] Here, the first sacrificial layer 1071-1 may include a photoresist mask or a hard mask patterned based on a photolithography mask, for example, silicon nitride, etc. The material compositions of the first sacrificial layer 1071-1 and the second sacrificial layer 1070-1 may be the same or different.

[0143] Figure 4g Shown in Figure 4f Sectional view of the AA' position in the zoy plane.

[0144] In some embodiments, the forming of the first sacrificial layer 1071-1 on the third electrode layer 1020c-1 includes:

[0145] A first sacrificial layer 1071 - 1 is formed on the second sacrificial strip 1070 - 2 .

[0146] In some embodiments, the method further comprises:

[0147] When the first sacrificial layer 1071 - 1 is formed on the third electrode layer 1020 c - 1 , the first sacrificial layer 1071 - 1 covers the dielectric layer 1080 at the same time.

[0148] In step 3004, a second isolation structure is mainly formed.

[0149] In some embodiments, when the second isolation structure penetrating the first sacrificial layer 1071 - 1 to the first electrode strip 1020 a - 2 is formed, the second isolation structure simultaneously penetrates the dielectric layer 1080 .

[0150] Here, the second isolation structure extends along a second direction perpendicular to the first direction.

[0151] Here, the second direction is parallel to the surface of the substrate 1001. In practical applications, the second direction can be understood as the x-axis direction shown in the drawings of the embodiments of the present disclosure. It can be understood that the second direction is not limited to the x-axis direction.

[0152] In some embodiments, before forming the second isolation structure, a fourth isolation structure is formed that penetrates the first sacrificial layer 1071-1, the third electrode strip 1020c-2, and the second functional strip 1040-2; wherein the second isolation structure penetrates the fourth isolation structure.

[0153] Here, the fourth isolation structure extends along a second direction perpendicular to the first direction.

[0154] In some embodiments, the forming of the second isolation structure penetrating the first sacrificial layer 1071-1 to the first electrode strip 1020a-2 includes:

[0155] A second isolation structure is formed that penetrates the second sacrificial strip 1070 - 2 to the first electrode strip 1020 a - 2 ; the second isolation structure divides the second sacrificial strip 1070 - 2 into second sacrificial blocks 1070 .

[0156] In practical applications, combined with Figure 4h-Figure 4i The method for forming the second isolation structure is described below.

[0157] like Figure 4h As shown, a fifth groove 1082 is formed along the direction parallel to the z-axis, penetrating the first sacrificial layer 1071-1, the second sacrificial strip 1070-2, the stop strip 1060-2, the third electrode strip 1020c-2, and the second functional strip 1040-2, wherein the bottom of the fifth groove 1082 exposes the second electrode strip 1020b-2. A plurality of fifth grooves 1082 are arranged in parallel along the direction parallel to the y-axis, and each fifth groove 1082 extends along the direction parallel to the x-axis. The fifth groove 1082 divides the first sacrificial layer 1071-1, the second sacrificial strip 1070-2, the stop strip 1060-2, the third electrode strip 1020c-2, and the second functional strip 1040-2 into the first sacrificial strip 1071-2, the second sacrificial block 1070, the stop block 1060, the third electrode 1020c, and the second functional element 1040.

[0158] Here, a method of forming the fifth trench 1082 may include dry plasma etching, but is not limited thereto.

[0159] In practical applications, the fifth grooves 1082 are arranged in parallel along a direction parallel to the y-axis, and each fifth groove 1082 extends along the x-axis.

[0160] After forming the fifth trench 1082, refer to Figure 4i As shown, a first insulating layer 1061 is formed to cover the sidewalls of the fifth trench 1082 and the upper surface of the first sacrificial strip 1071 - 2 ; a second insulating layer 1062 is formed to cover the first insulating layer 1061 ; the first insulating layer 1061 and the second insulating layer 1062 together constitute a fourth isolation structure.

[0161] A seventh groove is formed that penetrates the fifth groove 1082, the second electrode strip 1020b-2, the first functional strip 1030-2, and the first electrode strip 1020a-2, and the seventh groove exposes the surface of the first address line 1010. The seventh groove divides the second electrode strip 1020b-2, the first functional strip 1030-2, and the first electrode strip 1020a-2 into the second electrode 1020b, the first functional element 1030, and the first electrode 1020a, respectively. The seventh grooves are arranged in parallel along a direction parallel to the y-axis, and each seventh groove extends along the x-axis.

[0162] After forming the seventh trench, a third insulating layer 1063 is formed to cover the sidewall of the seventh trench and the second insulating layer 1062, and the third insulating layer 1063 also covers the bottom of the seventh trench; and a fourth insulating layer 1064 is formed to cover the third insulating layer 1063. The third insulating layer 1063 and the fourth insulating layer 1064 together constitute a second isolation structure.

[0163] In step 3005, reference Figure 4j , remove the first sacrificial strip 1071 - 2 to form a first trench 1083 .

[0164] In practical applications, methods for removing the first sacrificial strip 1071 - 2 include wet etching and dry etching, but are not limited thereto.

[0165] In some embodiments, removing the first sacrificial strip 1071 - 2 to form the first trench 1083 includes:

[0166] The first sacrificial strip 1071 - 2 is removed by a first etching process to form a first trench 1083 ; wherein the stop layer 1060 - 1 is used as a stop layer for the first etching process.

[0167] It can be understood that the first etching includes dry etching and wet etching. When the dry etching process is used to remove the first sacrificial strip 1071-2, certain damage will be caused to the third electrode strip 1020c-2. Here, by setting the stop layer 1060-1, the damage to the third electrode strip 1020c-2 when the first sacrificial strip 1071-2 is removed by dry etching can be improved.

[0168] Figure 4k Shown in Figure 4j Cross-sectional view of the BB' position in the zox plane.

[0169] In some embodiments, reference Figure 4j-Figure 4k , the removing of the first sacrificial strip 1071 - 2 to form the first trench 1083 includes:

[0170] The first sacrificial strip 1071 - 2 is removed to form a first trench 1083 ; and the second sacrificial block 1070 is removed to form a third trench 1085 .

[0171] In some embodiments, when the first sacrificial strip 1071 - 2 is removed to form the first trench 1083 , the first trench 1083 is simultaneously formed on the dielectric layer 1080 .

[0172] In some embodiments, reference Figure 4l-4m , after forming the first trench 1083 , forming a first mask layer 1090 on the first trench 1083 ;

[0173] The dielectric layer 1080 at the bottom of the first trench 1083 is etched by using the first mask layer 1090 to form a second trench 1084 that partially deepens the first trench 1083 ; the bottom of the second trench 1084 exposes the peripheral circuit.

[0174] Here, the first mask layer may include a photoresist mask or a hard mask patterned based on a photolithography mask.

[0175] In some embodiments, the material of the first mask layer 1090 includes carbon.

[0176] Here, a method of forming the first mask layer 1090 includes, but is not limited to, CVD.

[0177] Here, the pattern on the first mask layer 1090 can be specifically referred to Figure 8 The top view shown is for understanding, Figure 8A partial schematic diagram of a phase change memory in the yox axis plane is shown, and the first groove 1083 and the pattern 1084' on the first mask layer 1090 when the second groove 1084 is formed are exemplarily shown. The first groove 1083 is set at the position corresponding to the first area 1001a, and the pattern 1084' on the first mask layer 1090 is set at the position corresponding to the second area 1001b. It should be noted that the shape of the pattern 1084' on the first mask layer 1090 here is only an exemplary demonstration and is not used to limit the embodiments of the present disclosure. In actual applications, the shape of the pattern 1084' on the first mask layer 1090 may include a circle, a rectangle, a square, etc.

[0178] Here, local deepening can be combined with Figure 8 It is understood that the dielectric layer 1080 at the bottom of the first trench 1083 is etched using the first mask layer 1090. Since the pattern on the first mask layer 1090 is as follows Figure 8 As shown in the pattern 1084', since only the position 1084' is not blocked by the photoresist, during the etching process, only the local area of ​​the first groove not blocked by the photoresist will be further etched to form the second groove 1084, and the other parts of the first groove will not be further etched to deepen. Figure 4n , a second address line 1050 is formed in the first trench 1083 .

[0179] Figure 4o Shown in Figure 4n Cross-sectional view of the BB' position in the zox plane.

[0180] In some embodiments, reference Figure 4o The forming of the second address line 1050 in the first trench 1083 comprises:

[0181] A second address line 1050 is formed in the first trench 1083 , and an additional portion 1051 of the second address line is formed in the third trench 1085 .

[0182] In some embodiments, when the second address line 1050 is formed in the first groove 1083 , an extended portion 1052 of the second address line and a contact structure 1002 are formed in the second groove 1084 ; the second address line 1050 is electrically connected to the peripheral circuit through the contact structure 1002 .

[0183] Here, combined Figure 7The extended portion 1052 of the second address line is connected to the second address line 1050, and both the extended portion 1052 of the second address line and the second address line 1050 extend along the x-axis direction. The second address line 1050 is located on the first area 1001a, and the extended portion 1052 of the second address line is located on the second area 1001b. The extended portion 1052 of the second address line is connected to the contact structure 1002.

[0184] Here, combined Figure 4n as well as Figure 4o The additional portion 1051 of the second address line is located between the second address line 1050 and the third electrode 1020c, and the additional portion 1051 of the second address line extends along the z-axis direction. The additional portion 1051 of the second address line is perpendicular to the second address line 1050 and the first address line 1010.

[0185] It can be understood that, on the one hand, the additional portion 1051 of the second address line can enable a better connection between the second address line 1050 and the third electrode 1020c; on the other hand, the additional portion 1051 of the second address line is formed by removing the second sacrificial layer 1070-1, and the second sacrificial layer 1070-1 can be used to protect the third electrode layer when forming the contact structure 1002 on the second area 1001b.

[0186] It can be seen that in the aforementioned embodiment, the second address line 1050 and the contact structure 1002 are formed simultaneously, so that the second address line 1050 and the contact structure 1002 can form a good and stable contact. In the following embodiment, the contact structure 1002 is formed first, and then the second address line 1050 is formed. Specifically:

[0187] Figures 5a to 5k FIG. 1 is a cross-sectional schematic diagram of another implementation process of a phase change memory manufacturing method according to an embodiment of the present disclosure. Figures 5a to 5k The manufacturing process of the phase change memory of the embodiment of the present disclosure is specifically described.

[0188] In step 3001, refer to Figure 5a A first conductive layer 1010-1, a first electrode layer 1020a-1, a first functional layer 1030-1, a second electrode layer 1020b-1, a second functional layer 1040-1, and a third electrode layer 1020c-1 are sequentially formed on the surface of the substrate 1001 from bottom to top.

[0189] The details of forming the first conductive layer 1010-1, the first electrode layer 1020a-1, the first functional layer 1030-1, the second electrode layer 1020b-1, the second functional layer 1040-1 and the third electrode layer 1020c-1 have been described in detail in the aforementioned embodiments and will not be repeated here.

[0190] In step 3002, a first isolation structure is mainly formed. Figure 5b-5d , a first isolation structure is formed on the first area 1001a of the substrate 1001, which penetrates the third electrode layer 1020c-1, the second functional layer 1040-1, the second electrode layer 1020b-1, the first functional layer 1030-1, the first electrode layer 1020a-1, and the first conductive layer 1010-1; wherein the first isolation structure extends along a first direction parallel to the substrate 1001; the first isolation structure divides the third electrode layer 1020c-1, the second functional layer 1040-1, the second electrode layer 1020b-1, the first functional layer 1030-1, the first electrode layer 1020a-1, and the first conductive layer 1010-1 into a third electrode strip 1020c-2, a second functional strip 1040-2, a second electrode strip 1020b-2, a first functional strip 1030-2, a first electrode strip 1020a-2, and a first address line 1010, respectively.

[0191] The method of forming the first isolation structure is similar to the method of forming the first isolation structure in the aforementioned embodiment, and will not be described again here.

[0192] In some embodiments, reference Figure 5e , the substrate 1001 further includes a second region 1001b arranged in parallel with the first region 1001a; a peripheral circuit is formed on the second region 1001b;

[0193] The method further comprises:

[0194] A dielectric layer 1080 is formed on the second region 1001b.

[0195] In some embodiments, the method further comprises:

[0196] A contact structure 1002 is formed in the dielectric layer 1080 ; the contact structure 1002 is in contact with and electrically connected to the peripheral circuit.

[0197] In step 3003, refer to Figure 5f-5g , a first sacrificial layer 1071 - 1 is formed on the third electrode layer 1020c - 1.

[0198] Figure 5g for Figure 5f Cross-sectional view at position AA'.

[0199] In some embodiments, the method further comprises:

[0200] When the first sacrificial layer 1071 - 1 is formed on the third electrode layer 1020 c - 1 , the first sacrificial layer 1071 - 1 covers both the dielectric layer 1080 and the contact structure 1002 ;

[0201] In step 3004, reference Figure 5h-Figure 5i , mainly to form a second isolation structure.

[0202] In some embodiments, when the second isolation structure penetrating the first sacrificial layer 1071 - 1 to the first electrode strip 1020 a - 1 is formed, the second isolation structure simultaneously penetrates the dielectric layer 1080 .

[0203] Here, the method of forming the second isolation structure is similar to the method of forming the second isolation structure in the aforementioned embodiment, and will not be described again here.

[0204] In step 3005, reference Figure 5j , remove the first sacrificial strip 1071 - 2 to form a first trench 1083 .

[0205] In some embodiments, when the first sacrificial strip 1071 - 2 is removed to form the first trench 1083 , the first trench 1083 is simultaneously formed on the contact structure 1002 .

[0206] In step 3006, reference Figure 5k , a second address line 1050 is formed in the first trench 1083 .

[0207] In some embodiments, when the second address line 1050 is formed in the first groove 1083 , an extended portion 1052 of the second address line is formed in the first groove 1083 formed on the contact structure 1002 ; the second address line 1050 is electrically connected to the peripheral circuit through the contact structure 1002 .

[0208] It is understandable that in some embodiments of the present disclosure, it is necessary to first deposit the metal material forming the second address line and then etch the metal material forming the second address line. Due to the high density and high hardness of the metal material (such as W) forming the second address line, the etching rate produced by the traditional reactive ion etching process is low, and the lateral drilling is also large, and it is impossible to achieve high aspect ratio etching in a relatively short time. With the continuous improvement of the requirements for memory density, the traditional reactive ion etching process for the etching of the metal material forming the second address line may not meet the manufacturing requirements of high-density memory. In other embodiments of the present disclosure, the second address line is formed by directly depositing in the first groove, without first depositing the metal material forming the second address line and then etching the metal material forming the second address line. This is not limited by the process limitations and is conducive to the manufacture of high-density memory.

[0209] It is understandable that in some embodiments of the present disclosure, since it is necessary to first deposit the metal material forming the second address line and then etch the metal material forming the second address line, a thicker second mask layer is required. When the thickness of the second mask layer is insufficient, it will cause erosion on the top of the second address line, thereby affecting the performance of the phase change memory. In other embodiments of the present disclosure, the second address line is formed by direct deposition in the first trench, so that the top of the second address line will not be corroded, thereby improving the performance of the phase change memory.

[0210] It can be understood that the disclosed embodiment proposes a new dual damascene scheme for the second address line and contact structure of a three-dimensional phase change memory to improve process margin and reduce cost. The second address line is formed by a dual damascene scheme, wherein the metal material forming the second address line is deposited in the first trench, and the metal material is filled in the second trench to form a contact structure. The formation of the second address line does not require etching of a thick metal material forming the second address line, so a thinner mask layer may be required.

[0211] In the embodiments of the present disclosure, on the one hand, the thickness requirement of the mask layer can be thinner; on the second hand, since the formation of the second address line does not require etching of the thick metal material forming the second address line, the process is simpler and easier; on the third hand, the damage to the third electrode layer can be improved; on the fourth hand, the process flow is simplified and the process cost is reduced.

[0212] The embodiment of the present disclosure provides a method for manufacturing a phase change memory, comprising: forming a stacked first conductive layer, a first electrode layer, a first functional layer, a second electrode layer, a second functional layer, and a third electrode layer in sequence on a substrate; forming a first isolation structure on a first area of ​​the substrate that passes through the third electrode layer to the first conductive layer; wherein the first isolation structure extends along a first direction parallel to the substrate; the first isolation structure divides the first electrode layer into first electrode strips; forming a first sacrificial layer on the third electrode layer; forming a second isolation structure that passes through the first sacrificial layer to the first electrode strips; wherein the second isolation structure extends along a second direction perpendicular to the first direction; the second isolation structure divides the first sacrificial layer into first sacrificial strips; removing the first sacrificial strips to form a first trench; and forming a second address line in the first trench. The first sacrificial layer is removed to form a first groove, and a second address line is formed at the position of the first groove. That is to say, in the embodiment of the present disclosure, the material for forming the second address line is directly filled in the formed first groove to form the second address line. In this way, there is no need to etch the material for forming the second address line to form the second address line. In this way, the problem of damage to the second address line caused by insufficient thickness of the mask layer when etching the material for forming the second address line is improved.

[0213] Based on the above-mentioned method for manufacturing a phase change memory, the present disclosure also provides a phase change memory, referring to Figure 6a-Figure 6b ,include:

[0214] A first address line 1010, a phase change memory unit 1100, and a second address line 1050 are sequentially stacked on a first region 1001a of a substrate 1001; wherein the first address line 1010 and the second address line 1050 are parallel to the same plane and perpendicular to each other; the phase change memory unit 1100 comprises a first electrode 1020a, a first functional element 1030, a second electrode 1020b, a second functional element 1040, and a third electrode 1020c which are sequentially stacked; the first electrode 1020a, the first functional element 1030, the second electrode 1020b, the second functional element 1040, and the third electrode 1020c are perpendicular to the first address line 1010 and the second address line 1050;

[0215] A contact structure 1002 and an extended portion of a second address line are disposed on a second region 1001b of the substrate; a peripheral circuit is disposed on the second region 1001b, the contact structure 1002 contacts the peripheral circuit, and the contact structure 1002 contacts and is perpendicular to the second address line 1050;

[0216] A second isolation structure; wherein the second isolation structure extends along the second direction, the second isolation structure is alternately arranged in parallel with the stacked phase change memory unit 1100 and the second address line 1050 on the first region, and the second isolation structure covers part of the side wall of the contact structure 1002 on the second region 1001b.

[0217] In some embodiments, the phase change memory further comprises: an additional portion of a second address line;

[0218] The additional portion of the second address line is located between the third electrode 1020 c and the second address line 1050 on the first region 1001 a , and the additional portion of the second address line is perpendicular to both the first address line 1010 and the second address line 1050 .

[0219] In some embodiments, the phase change memory further includes: a stop block 1060 ; the stop block is located between the third electrode 1020 c and the second address line 1050 , and the stop block is perpendicular to both the first address line 1010 and the second address line 1050 .

[0220] In some embodiments, the first functional element 1030 includes a gating element, and the conduction of the gating element formed by the gating layer enables the electrode to heat or quench the phase change memory element formed by the phase change memory layer, so as to achieve switching between the crystalline state and the amorphous state of the phase change memory element; the second functional element 1040 includes the phase change memory element, and data storage is achieved by switching between the crystalline state and the amorphous state of the phase change memory element.

[0221] The relevant details of the phase change memory introduced above have been described in detail in the corresponding method, and will not be repeated here.

[0222] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0223] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0224] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a phase change memory, It is characterized in that include: Forming a stacked first conductive layer, a first electrode layer, a first functional layer, a second electrode layer, a second functional layer, and a third electrode layer in sequence on a substrate; forming a first isolation structure on the first region of the substrate that penetrates the third electrode layer to the first conductive layer; wherein the first isolation structure extends along a first direction parallel to the substrate; and the first isolation structure divides the first electrode layer into first electrode strips; forming a first sacrificial layer on the third electrode layer; forming a second isolation structure penetrating the first sacrificial layer to the first electrode strip; wherein the second isolation structure extends along a second direction perpendicular to the first direction; and the second isolation structure divides the first sacrificial layer into first sacrificial strips; removing the first sacrificial strip to form a first trench; A second address line is formed in the first trench.

2. The method according to claim 1, It is characterized in that The substrate further includes a second region arranged in parallel with the first region; a peripheral circuit is formed on the second region; The method further comprises: Before forming the first sacrificial layer on the third electrode layer, a dielectric layer is formed on the second region.

3. The method according to claim 2, It is characterized in that The method further comprises: When the first sacrificial layer is formed on the third electrode layer, the first sacrificial layer simultaneously covers the dielectric layer; When forming the second isolation structure that penetrates the first sacrificial layer to the first electrode strip, the second isolation structure simultaneously penetrates the dielectric layer; When the first sacrificial strip is removed to form the first trench, the first trench is simultaneously formed on the dielectric layer.

4. The method according to claim 3, It is characterized in that The method further comprises: After forming the first trench, forming a first mask layer on the first trench; Using the first mask layer, etching the dielectric layer at the bottom of the first trench to form a second trench that partially deepens the first trench; the bottom of the second trench exposes the peripheral circuit; When forming the second address line in the first groove, an extended portion of the second address line and a contact structure are formed in the second groove; the second address line is electrically connected to the peripheral circuit through the contact structure.

5. The method according to claim 4, It is characterized in that The material of the first mask layer includes carbon.

6. The method according to claim 2, It is characterized in that The method further comprises: Before forming the first sacrificial layer on the third electrode layer, a contact structure is formed in the dielectric layer; the contact structure is in contact with and electrically connected to the peripheral circuit.

7. The method according to claim 6, It is characterized in that The method further comprises: When the first sacrificial layer is formed on the third electrode layer, the first sacrificial layer covers the dielectric layer and the contact structure at the same time; When forming the second isolation structure that penetrates the first sacrificial layer to the first electrode strip, the second isolation structure simultaneously penetrates the dielectric layer; When the first sacrificial strip is removed to form the first groove, the first groove is simultaneously formed on the contact structure; When forming the second address line in the first groove, an extended portion of the second address line is formed in the first groove formed on the contact structure; the second address line is electrically connected to the peripheral circuit through the contact structure.

8. The method according to claim 1, It is characterized in that The method further comprises: Before forming a first isolation structure penetrating from the third electrode layer to the first conductive layer on the first region of the substrate, forming a stop layer on the third electrode layer; the material of the stop layer is the same as that of the second address line; The first isolation structure formed on the first region of the substrate and extending from the third electrode layer to the first conductive layer comprises: forming a first isolation structure penetrating the stop layer to the first conductive layer; The removing the first sacrificial strip to form a first trench comprises: The first sacrificial strip is removed by a first etching to form a first trench; wherein the stop layer is used as a stop layer for the first etching.

9. The method according to claim 1, It is characterized in that The method further comprises: Before forming a first isolation structure penetrating the third electrode layer to the first conductive layer on the first region of the substrate, forming a second sacrificial layer on the third electrode layer; The first isolation structure formed on the first region of the substrate and extending from the third electrode layer to the first conductive layer comprises: forming a first isolation structure penetrating from the second sacrificial layer to the first conductive layer on the first region of the substrate; the first isolation structure divides the second sacrificial layer into a plurality of second sacrificial strips; The forming of a first sacrificial layer on the third electrode layer comprises: forming a first sacrificial layer on the second sacrificial strip; The forming of the second isolation structure penetrating through the first sacrificial layer to the first electrode strip comprises: forming a second isolation structure that runs through the second sacrificial strip to the first electrode strip; the second isolation structure divides the second sacrificial strip into second sacrificial blocks; The removing the first sacrificial strip to form a first trench comprises: removing the first sacrificial strip to form a first trench; and removing the second sacrificial block to form a third trench; The forming of a second address line in the first trench comprises: A second address line is formed in the first trench and an additional portion of the second address line is formed in the third trench.

10. The method according to claim 1, It is characterized in that The method further comprises: Before forming the first isolation structure, forming a third isolation structure that penetrates the third electrode layer and the second functional layer; wherein the first isolation structure penetrates the third isolation structure, and the third isolation structure divides the third electrode layer and the second functional layer into third electrode strips and second functional strips; and / or, Before forming the second isolation structure, a fourth isolation structure is formed which penetrates the first sacrificial layer, the third electrode strip, and the second functional strip; wherein the second isolation structure penetrates the fourth isolation structure.

11. The method according to claim 1, It is characterized in that The first functional layer includes a gating layer, and the conduction of the gating element formed by the gating layer realizes the heating or quenching of the phase change memory element formed by the phase change memory layer by the electrode, so as to realize the switching between the crystalline state and the amorphous state of the phase change memory element; the second functional layer includes the phase change memory layer, and the data storage is realized by the switching between the crystalline state and the amorphous state of the phase change memory element.

12. A phase change memory, It is characterized in that The phase change memory is obtained by the manufacturing method according to claim 1, and the phase change memory comprises: A first address line, a phase change memory unit, and a second address line are sequentially stacked on a first region of a substrate; wherein the first address line and the second address line are parallel to the same plane and perpendicular to each other; the phase change memory unit comprises a first electrode, a first functional element, a second electrode, a second functional element, and a third electrode which are sequentially stacked; the first electrode, the first functional element, the second electrode, the second functional element, and the third electrode are perpendicular to the first address line and the second address line; the first address line extends along a first direction, and the second address line extends along a second direction; A contact structure and an extended portion of a second address line are disposed on a second region of the substrate; a peripheral circuit is disposed on the second region, the contact structure contacts the peripheral circuit, and the contact structure contacts and is perpendicular to the second address line; A second isolation structure; wherein the second isolation structure extends along the second direction, the second isolation structure is alternately arranged in parallel with the stacked phase-change memory unit and the second address line on the first region, and the second isolation structure covers part of the side wall of the contact structure on the second region.

13. The phase change memory according to claim 12, It is characterized in that The phase change memory further includes: an additional portion of a second address line; The additional portion of the second address line is located between the third electrode and the second address line on the first region, and the additional portion of the second address line is perpendicular to both the first address line and the second address line.

14. The phase change memory according to claim 12, It is characterized in that The phase change memory further includes: a stop block; the stop block is located between the third electrode and the second address line, and the stop block is perpendicular to both the first address line and the second address line.

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