Instruction processing method for multi-core processor and multi-core processor

Abstract

The present application discloses an instruction processing method and a multi-core processor applied to a multi-core processor. Among them, an instruction processing method applied to a multi-core processor includes: after the first processing core obtains the target instruction address of the first thread, querying the first branch jump history record of the first processing core and the second branch jump history record of the second processing core; selecting branch jump information including the target instruction address from the first branch jump history record and the second branch jump history record; performing branch prediction based on the selected branch jump information; and obtaining the instruction corresponding to the first jump address based on the first jump address obtained by the branch prediction. According to this implementation, each processing core can query multiple branch jump history records, which can improve the success rate of obtaining branch jump information, thereby increasing the accuracy of branch prediction and improving instruction processing efficiency. The present application also provides a multi-core processor that can implement the above-mentioned instruction processing method.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction processing method applied to a multi-core processor and a multi-core processor. Background Art

[0002] Processor pipelining breaks down instructions into multiple steps and overlaps the steps of different instructions, allowing them to be processed in parallel, accelerating program execution. Processors incorporating pipelining may generate jumps when processing branch instructions. A jump error can interrupt the processing of instructions in the pipeline. Branch predictors are currently being used to mitigate the impact of pipeline interruptions caused by jump errors. A branch predictor is a digital circuit that predicts which branch will be taken before the branch instruction completes execution.

[0003] Currently, there is an instruction processing method that is roughly as follows: in a multi-core processor, each processing core generates branch jump history information based on the historical jump record of the processing core, performs branch prediction based on the branch jump history record, and pre-fetches instructions based on the branch prediction result.

[0004] In practical applications, the branch jump history record of a processing core may be missing. In this case, the success rate of branch prediction by the processing core is low, which easily interrupts the pipeline, thus reducing the processing efficiency of the processing core. Summary of the Invention

[0005] In view of this, the present application provides an instruction processing method and a multi-core processor applied to a multi-core processor, which can improve the accuracy of branch prediction and improve the efficiency of instruction processing.

[0006] A first aspect provides an instruction processing method for a multi-core processor. In this method, after a first processing core obtains a target instruction address of a first thread, it queries a first branch jump history record and a second branch jump history record, and then selects branch jump information including the target instruction address from the first branch jump history record and the second branch jump history record; performs branch prediction based on the selected branch jump information; and obtains an instruction corresponding to the first jump address based on the first jump address obtained by the branch prediction. The first branch jump history record is stored in the first processing core, and the second branch jump history record is stored in the second processing core. The number of branch jump information including the target instruction address can be one or more.

[0007] According to this implementation, the first processing core can not only query the first branch jump history record stored by the first processing core, but also query the second branch jump history record stored by the second processing core. When the first branch jump history record does not include the target address and the second branch jump history record includes the target address, the first processing core can obtain the branch jump information including the target address from the second branch jump history record, and predict the address of the next instruction based on the branch jump information. This can improve the branch prediction accuracy, reduce the situation where the pipeline is interrupted, and thus improve the instruction processing efficiency of the first processing core. Similarly, when the second branch jump history record does not include the target address and the first branch jump history record includes the target address, the second processing core can also obtain the branch jump information including the target address from the first branch jump history record, and then predict the next instruction address based on the branch jump information to improve the instruction processing efficiency of the second processing core.

[0008] In one possible implementation, the first processing core selects branch jump information including the target instruction address from the first branch jump history record and the second branch jump history record, including: when the first branch jump history record and the second branch jump history record both include the target instruction address, the branch jump information including the target instruction address is selected from the branch jump history record with the highest priority. When more than two branch jump history records are found to include the target instruction address, the branch jump information can be selected according to the priority. Optionally, the priority of the first branch jump history record is higher than the priority of the second branch jump history record. Since the first branch jump history record is stored in the first processing core, the first processing core obtains the branch jump information from the first branch jump history record the fastest, which can provide a method for quickly reading branch jump information.

[0009] In another possible implementation, selecting the branch jump information including the target instruction address from the first branch jump history record and the second branch jump history record includes: if the first branch jump history record includes the target instruction and the second branch jump history record does not include the target instruction address, selecting the branch jump information including the target instruction address from the first branch jump history record; and if the first branch jump history record does not include the target instruction and the second branch jump history record does include the target instruction address, selecting the branch jump information including the target instruction address from the second branch jump history record. This can increase the success rate of obtaining branch jump information.

[0010] In another possible implementation, after the first processing core obtains the instruction corresponding to the first jump address based on the first jump address obtained by branch prediction, if the first branch jump history record does not include the target instruction address and the second branch jump history record includes the target instruction address, the second jump address is obtained based on the execution result of the target instruction, and the target instruction corresponds to the target instruction address; when the second jump address is the same as the first jump address, branch jump information including the target instruction address and the first jump address is added to the first branch jump history record; when the second jump address is different from the first jump address, branch jump information including the target instruction address and the second jump address is added to the first branch jump history record. In this way, the first branch jump history record can be refreshed, and when the address of the next instruction is predicted based on the target instruction address, the branch jump information can be obtained from the first branch jump history record, without having to obtain the branch jump information from other processing cores, thereby improving the subsequent branch prediction speed.

[0011] In another possible implementation, before the first processing core obtains the target instruction address of the first thread, the scheduling unit obtains multiple threads; the scheduling unit selects a thread with the same sub-function from the multiple threads; the scheduling unit selects a first thread and a second thread from the threads with the same sub-function, wherein the ratio of the number of the same sub-functions to the total number of sub-functions in the first thread is greater than or equal to a first preset ratio, and the ratio of the number of the same sub-functions to the total number of sub-functions in the second thread is greater than or equal to a second preset ratio; the scheduling unit sends the second thread to the second processing core; and the second processing core generates a second branch jump history record based on the jump instruction of the second thread. The scheduling unit is a multi-core processor. In this implementation, the scheduling unit can assign similar threads to the first and second processing cores, such that the branch jump history records generated by the first and second processing cores include some identical branch jump information. When the first processing core queries the branch jump history record of the second processing core, the success rate and accuracy of obtaining branch jump information can be improved.

[0012] The second aspect provides a multi-core processor, which includes a first processing core and a second processing core; the first processing core is used to obtain a target instruction address of a first thread; query a first branch jump history record and a second branch jump history record, the first branch jump history record is stored in the first processing core, and the second branch jump history record is stored in the second processing core; from the first branch jump history record and the second branch jump history record, select branch jump information including a target instruction address; perform branch prediction based on the selected branch jump information; and obtain an instruction corresponding to the first jump address based on the first jump address obtained by the branch prediction.

[0013] In one possible implementation, the first processing core is specifically configured to select the branch jump information including the target instruction address from the branch jump history record with the highest priority when both the first branch jump history record and the second branch jump history record include the target instruction address.

[0014] In another possible implementation, the priority of the first branch jump history record is higher than the priority of the second branch jump history record.

[0015] In another possible implementation, the first processing core is specifically used to select branch jump information including the target instruction address from the first branch jump history record when the first branch jump history record includes the target instruction and the second branch jump history record does not include the target instruction address; and to select branch jump information including the target instruction address from the second branch jump history record when the first branch jump history record does not include the target instruction and the second branch jump history record includes the target instruction address.

[0016] In another possible implementation, the first processing core is used to obtain the second jump address according to the execution result of the target instruction when the first branch jump history record does not include the target instruction address and the second branch jump history record includes the target instruction address, and the target instruction corresponds to the target instruction address; when the second jump address is the same as the first jump address, branch jump information including the target instruction address and the first jump address is added to the first branch jump history record; when the second jump address is different from the first jump address, branch jump information including the target instruction address and the second jump address is added to the first branch jump history record.

[0017] In another possible implementation, a multi-core processor includes a scheduling unit, which can be a processing core for scheduling or a circuit with scheduling functions; the scheduling unit is used to obtain multiple threads before the first processing core obtains the target instruction address of the first thread; select threads with the same sub-function from the multiple threads; select a first thread and a second thread from the threads with the same sub-function, the ratio of the number of identical sub-functions to the number of all sub-functions in the first thread is greater than or equal to a first preset ratio, and the ratio of the number of identical sub-functions to the number of all sub-functions in the second thread is greater than or equal to a second preset ratio; send the second thread to the second processing core; the second processing core is used to generate a second branch jump history record according to the jump instruction of the second thread.

[0018] In another possible implementation, the first processing core is adjacent to the second processing core.

[0019] In another possible implementation, the first processing core includes a prediction unit and a branch target buffer, and the second processing core includes a prediction unit and a branch target buffer; the prediction unit of the first processing core is connected to the branch target buffer of the second processing core via a wire, and / or the prediction unit of the second processing core is connected to the branch target buffer of the first processing core via a wire.

[0020] The steps and beneficial effects performed by each processing core or unit in the multi-core processor of the second aspect can be referred to the corresponding description in the first aspect and will not be repeated here.

[0021] A third aspect provides an electronic device, which includes a memory and a multi-core processor as in the second aspect, wherein the memory is used to store instructions and data.

[0022] A fourth aspect provides a computer storage medium comprising instructions, which, when executed on a computer, enables the computer to execute the instruction processing method of the first aspect.

[0023] A fifth aspect provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the instruction processing method of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A structural diagram of a multi-core processor in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of the connection relationship between two processing cores in an embodiment of the present application;

[0026] Figure 3 A flowchart of the instruction processing method in an embodiment of the present application;

[0027] Figure 4 This is another structural diagram of a multi-core processor in an embodiment of the present application;

[0028] Figure 5 This is another structural diagram of a multi-core processor in an embodiment of the present application;

[0029] Figure 6 This is another structural diagram of a multi-core processor in an embodiment of the present application;

[0030] Figure 7 This is a structural diagram of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The instruction processing method of the present application can be applied to a multi-core processor. The number of processing cores in a multi-core processor can be two or more. In a multi-core processor, multiple processing cores can be connected via an on-chip network or an internal bus of the multi-core processor.

[0032] Figure 1 A schematic diagram of the structure of a multi-core processor. Figure 1 Multi-core processor 100 includes processing cores 101, 102, 103, 104, 105, 106, 107, and 108, as well as processor caches 111, 112, 113, 114, 115, 116, 117, and 118. Processing cores 101 and 102 are connected via wires, processing cores 103 and 104 are connected via wires, processing cores 105 and 106 are connected via wires, and processing cores 107 and 108 are connected via wires. When processing cores 101 and 102 are connected via wires, processing core 101 can directly obtain data from processing core 102 without waiting for bus scheduling. The same applies to other processing cores.

[0033] Figure 1 The diagram shows the connection method between the upper processing core and the lower processing core. In the multi-core processor 100, the connection method of the processing cores is not limited to the above examples and can be set according to actual conditions. For example, each processing core is connected to the left processing core and / or the right processing core. Alternatively, one processing core is connected to two or more processing cores. Specifically, each processing core is connected to three processing cores, or each processing core is connected to four processing cores in the upper, lower, left, and right directions.

[0034] In multi-core processor 100, each processing core is connected to a processor cache. For example, processing core 101 is connected to processor cache 111, processing core 102 is connected to processor cache 112, processing core 103 is connected to processor cache 113, processing core 104 is connected to processor cache 114, processing core 105 is connected to processor cache 115, processing core 106 is connected to processor cache 116, processing core 107 is connected to processor cache 117, and processing core 108 is connected to processor cache 118.

[0035] It should be understood that in a multi-core processor, two processing cores may be connected to the same processor cache, or three or more processing cores may be connected to the same processor cache.

[0036] It should be noted that the number of processing cores and processor caches can be set according to actual circumstances. In a multi-core processor, caches can be set both internally and externally for each processing core. Optionally, a level 1 cache is set internally within the processing core, and the processor cache connected to the processing core is a level 2 cache. Alternatively, a level 1 cache and a level 2 cache are set internally within the processing core, and the processor cache connected to the processing core is a level 3 cache. The level 1 cache is the L1 cache, the level 2 cache is the L2 cache, and the level 3 cache is the L3 cache. The caches inside and outside the processing core can be set according to actual circumstances and are not limited in this application.

[0037] Figure 2 A schematic diagram of the connection relationship between the two processing cores. Figure 1 Taking the processing core 101 and the processing core 102 as an example, the connection relationship between the processing cores is described in detail below. Figure 2 The processing core 101 includes an instruction side unit 201, a prediction unit 202, a branch target buffer (BTB) 203, an out-of-order unit 204, and an instruction processing unit 205. The instruction side unit 201, the prediction unit 202, and the branch target buffer 203 may constitute an instruction prefetch module.

[0038] The processing core 102 includes an instruction side unit 207, a prediction unit 208, a branch target buffer 209, an out-of-order unit 210, and an instruction processing unit 211. The instruction side unit 207, the prediction unit 208, and the branch target buffer 209 may constitute another instruction prefetch module.

[0039] The branch target buffer 203 and the branch target buffer 209 store branch jump history records. The branch jump history records can be considered as a table, which includes multiple records. Each record includes an address and a jump address of the address. The jump address is also called the next hop address.

[0040] Prediction unit 202 may include, but is not limited to, a TAGE predictor. Prediction unit 202 is connected to branch target buffer 203 and to branch target buffer 209 via a wire. Prediction unit 202 can query branch target buffer 203 and branch target buffer 209 and then make predictions based on the branch jump history stored in branch target buffer 203, based on the branch jump history stored in branch target buffer 209, or based on pre-set prediction rules.

[0041] The instruction-side unit 201 is connected to the processor cache 111 and the prediction unit 202 respectively. The instruction-side unit 201 can read instructions from the processor cache 111 according to the prediction result of the prediction unit 202 .

[0042] The out-of-order unit 204 is used for out-of-order scheduling.

[0043] The instruction processing unit 205 is used to dispatch instructions or execute instructions.

[0044] The instruction-side unit 207, prediction unit 208, branch target buffer 209, out-of-order unit 210, and instruction processing unit 211 of processing core 102 have similar functions to the instruction-side unit 201, prediction unit 202, branch target buffer 203, out-of-order unit 204, and instruction processing unit 205 of processing core 101. The connections between the various units of processing core 102 are also similar to the connections between the various units of processing core 101 and will not be further described here. For example, prediction unit 208 is connected to branch target buffer 209 and to branch target buffer 203 via wires, so that prediction unit 208 can directly query branch target buffer 209 and branch target buffer 203.

[0045] See Figure 2 The following describes the process of performing branch prediction based on the branch jump history records in the branch target buffer 203:

[0046] After the instruction side unit 201 obtains instruction 1, it can send the address of instruction 1 to the prediction unit 202. The prediction unit 202 queries whether the branch target buffer 203 stores the instruction address based on the address of instruction 1. When the branch target buffer 203 stores the instruction address, the prediction unit 202 reads the jump address of the instruction address from the branch target buffer 203 and sends the jump address to the instruction side unit 201. The instruction side unit 201 reads the instruction 2 corresponding to the jump address from the memory based on the jump address, stores instruction 2 in the processor cache 111, and transmits instruction 2 to the processing core 101 for execution.

[0047] It should be noted that instruction 2 may or may not be the next instruction after instruction 1. If instruction 2 is the next instruction after instruction 1, the instruction processing unit 205 will directly execute instruction 2 after executing instruction 1. This will prevent the pipeline from being interrupted, and therefore, instruction processing efficiency is very high when the prediction is correct. If the next instruction after instruction 1 is not instruction 2 but instruction 3, when the instruction processing unit 205 needs to execute instruction 3, since instruction 3 is not pre-stored in the processing core 101, the instruction-side unit 201 first reads instruction 3 from the memory or processor cache 111 based on the address of instruction 3, and then transmits instruction 3 to the instruction processing unit 205 through the out-of-order unit 204. Only then can the instruction processing unit 205 execute instruction 3. It should be understood that before instruction 3 is transmitted from the memory or processor cache 111 to the instruction processing unit 205, the instruction processing unit 205 is in a waiting state, which interrupts the pipeline and reduces instruction processing efficiency. Predicted erroneous branch instructions (such as instruction 2 and its subsequent instructions) will be discarded within the processing core 101.

[0048] Based on the multi-core processor of this application, the instruction processing method of this application is introduced below. Figure 3 , an embodiment of the instruction processing method of the present application includes:

[0049] Step 301: A first processing core obtains a target instruction address of a first thread.

[0050] In this embodiment, the first processing core may be any processing core in a multi-core processor. The target instruction address corresponds to the target instruction, and the target instruction may be any instruction of the first thread. The first thread may be any thread executed by the first processing core.

[0051] Step 302: The first processing core queries the first branch jump history record and the second branch jump history record.

[0052] The first branch jump history record is stored in the first processing core, and the second branch jump history record is stored in the second processing core. Specifically, the first branch jump history record may be stored in the branch target buffer of the first processing core, and the second branch jump history record may be stored in the branch target buffer of the second processing core.

[0053] The first processing core can synchronously query the first branch jump history record and the second branch jump history record, or asynchronously query the first branch jump history record and the second branch jump history record. Synchronous query is faster than asynchronous query.

[0054] The second processing core is another processing core connected to the first processing core. Optionally, the second processing core is a processing core adjacent to the first processing core. When the first processing core and the second processing core are adjacent, the wiring between the two processing cores is very short, so that the first processing core can quickly query the second processing core for instructions, instruction addresses, or data.

[0055] Step 303: The first processing core selects branch jump information including a target instruction address from the first branch jump history record and the second branch jump history record.

[0056] Optionally, step 303 includes: when both the first branch jump history record and the second branch jump history record include the target instruction address, the first processing core selects the branch jump information including the target instruction address from the branch jump history record with the highest priority.

[0057] Optionally, the priority of the branch jump history record of the current processing core is higher than the priority of the branch jump history record of other processing cores. When the first processing core predicts the address of the next instruction based on the target instruction address, the priority of the first branch jump history record is higher than the priority of the second branch jump history record. When the second processing core predicts the address of the next instruction based on the target instruction address, the priority of the second branch jump history record is higher than the priority of the first branch jump history record. The priorities of the branch jump history records of other processing cores can be the same or different. For example, the distance from each processing core to the first processing core is obtained, and the priority of the branch jump history record of each processing core is set according to the distance. The distance has a negative correlation with the priority.

[0058] Optionally, step 303 includes: when the first branch jump history record includes the target instruction and the second branch jump history record does not include the target instruction address, selecting branch jump information including the target instruction address from the first branch jump history record; when the first branch jump history record does not include the target instruction and the second branch jump history record includes the target instruction address, selecting branch jump information including the target instruction address from the second branch jump history record.

[0059] It should be noted that when neither the first branch jump history record nor the second branch jump history record includes the target instruction address, the first processing core obtains the jump address of the target instruction address according to a preset prediction rule, and then performs branch prediction based on the jump address.

[0060] Step 304: The first processing core performs branch prediction according to the selected branch jump information.

[0061] Step 305: The first processing core obtains an instruction corresponding to the first jump address according to the first jump address obtained by branch prediction.

[0062] Specifically, the first processing core searches the processor cache based on the first jump address obtained by branch prediction. If the processor cache stores an instruction corresponding to the first jump address, the first processing core retrieves the instruction from the processor cache. If the processor cache does not store the instruction corresponding to the first jump address, the first processing core searches the memory for the instruction corresponding to the first jump address based on the first jump address, copies the instruction to the processor cache, and then reads the instruction from the processor cache.

[0063] The process of copying the instruction from the memory to the processor cache is also called instruction prefetching. It should be understood that when the first processing core reads the instruction again according to the first jump address, the first processing core does not need to read it from the memory, but can directly read the instruction from the processor cache.

[0064] In this embodiment, the first processing core can query the branch jump history records of the first processing core and the second processing core, which can reduce branch prediction errors caused by the missing branch jump information of the first processing core. Therefore, the method of this embodiment can improve the success rate of obtaining branch jump information including the target address, thereby improving the accuracy of branch prediction, reducing the interruption of the pipeline, and thus improving instruction processing efficiency.

[0065] In another optional embodiment, after step 305, the instruction processing method further includes:

[0066] In a case where the first branch jump history record does not include the target instruction address and the second branch jump history record includes the target instruction address, obtaining the second jump address according to the execution result of the target instruction, the target instruction corresponding to the target instruction address;

[0067] When the second jump address is the same as the first jump address, adding branch jump information including the target instruction address and the first jump address to the first branch jump history record;

[0068] When the second jump address is different from the first jump address, branch jump information including the target instruction address and the second jump address is added to the first branch jump history record.

[0069] In this embodiment, the first jump address is predicted based on the branch jump history and may be correct or incorrect. After the target instruction is executed, the processing core can determine the second jump address based on the execution result of the target instruction. The second jump address is the actual next jump address of the target instruction.

[0070] If the second jump address is the same as the first jump address, it indicates that the branch jump information including the target instruction address and the first jump address is correct. This information is added to the first branch jump history record for subsequent branch prediction. Optionally, the confidence level of this branch jump information is increased, which can improve the accuracy of subsequent branch predictions.

[0071] When the second jump address is different from the first jump address, it indicates that the branch jump information including the target instruction address and the first jump address is wrong. The branch jump information including the target instruction address and the second jump address is added to the first branch jump history record, and the branch jump information including the target instruction address and the first jump address is discarded.

[0072] The above method can be used to refresh the first branch jump history record, thereby improving the accuracy of subsequent branch predictions performed by the first processing core.

[0073] In another optional embodiment, before the first processing core obtains the target instruction address of the first thread, the instruction processing method further includes:

[0074] The scheduling unit acquires multiple threads;

[0075] The scheduling unit selects a thread with the same sub-function from multiple threads;

[0076] The scheduling unit selects a first thread and a second thread from threads having identical sub-functions, wherein a ratio of the number of identical sub-functions to the number of all sub-functions in the first thread is greater than or equal to a first preset ratio, and a ratio of the number of identical sub-functions to the number of all sub-functions in the second thread is greater than or equal to a second preset ratio;

[0077] The scheduling unit sends the second thread to the second processing core;

[0078] The second processing core generates a second branch jump history record according to the jump instruction of the second thread.

[0079] In this embodiment, each thread may include one or more sub-functions, and each thread may be considered as a task. The values of the first preset ratio and the second preset ratio may be set according to actual conditions, and may be, but not limited to, 10%, which is not limited in this application.

[0080] When the first thread and the second thread contain the same sub-function and the proportion of the same sub-function is greater than a preset ratio, it indicates that the first thread is similar to the second thread. The scheduling unit can send the first thread to the first processing core and the second thread to the second processing core. The first processing core can generate a branch jump history record of the first processing core based on the jump instruction of the first thread, and the second processing core can generate a second branch jump history record based on the jump instruction of the second thread. In this way, the branch jump history records of the two processing cores contain some of the same branch jump information. In the case that the branch jump history record of the first processing core loses one or more branch jump information and the lost branch jump information belongs to the same branch jump information mentioned above, the first processing core can obtain the correct branch jump information from the second branch jump history record.

[0081] In another alternative embodiment, the multi-core processor includes at least one processing core group, and each processing core in each processing core group shares a branch buffer history record. In this embodiment, the scheduling unit can assign multiple similar threads to a processing core group. Each processing core, based on the thread's instructions, can query the branch buffer history records of other processing cores and then perform branch prediction based on the query results. This can improve the branch prediction accuracy of each processing core.

[0082] In another embodiment, after the first processing core obtains the target instruction address of the first thread, it queries multiple branch jump historical records; then selects branch jump information including the target instruction address from the multiple branch jump historical records; performs branch prediction based on the selected branch jump information; and obtains the address corresponding to the first jump address based on the first jump address obtained by the branch prediction.

[0083] In this embodiment, a processing core can be connected to the branch target buffers of multiple processing cores, and the processing core can query the branch jump history records of multiple processing cores, which can further improve the success rate of obtaining branch jump information including target addresses, thereby improving the accuracy of branch prediction.

[0084] See Figure 4 In an optional embodiment, the multi-core processor provided by the present application includes a first processing core 401 and a second processing core 402;

[0085] The first processing core 401 is configured to obtain a target instruction address of a first thread;

[0086] The first processing core 401 is used to query the first branch jump history record and the second branch jump history record. The first branch jump history record is stored in the first processing core 401, and the second branch jump history record is stored in the second processing core 402;

[0087] The first processing core 401 is further configured to select branch jump information including a target instruction address from the first branch jump history record and the second branch jump history record;

[0088] The first processing core 401 is further configured to perform branch prediction based on the selected branch jump information;

[0089] The first processing core 401 is further configured to obtain an instruction corresponding to the first jump address according to the first jump address obtained by branch prediction.

[0090] In this embodiment, the first processing core 401 can not only query the first branch jump history record stored by the first processing core 401, but also query the second branch jump history record stored by the second processing core 402. When the first branch jump history record does not include the target address and the second branch jump history record includes the target address, the first processing core 401 can obtain the branch jump information including the target address from the second branch jump history record and predict the next instruction address based on the branch jump information. This can improve the branch prediction accuracy, reduce the situation where the pipeline is interrupted, and thus improve the processing efficiency of the first processing core 401. Similarly, in a multi-core processor, each processing core can query the branch jump history records of other processing cores. This can improve the branch prediction accuracy of each processing core, reduce the situation where the pipeline is interrupted, and thus improve the processing efficiency of the multi-core processor.

[0091] See Figure 5 In an optional embodiment, the first processing core 401 includes a first instruction-side unit 501, a first prediction unit 502, and a first branch target buffer 503; the second processing core 402 includes a second instruction-side unit 504, a second prediction unit 505, and a second branch target buffer 506;

[0092] The first prediction unit 502 is connected to the first instruction side unit 501, the first branch target buffer 503 and the second branch target buffer 506 respectively, and the second prediction unit 505 is connected to the second instruction side unit 504, the second branch target buffer 506 and the first branch target buffer 503 respectively;

[0093] A first instruction-side unit 501 is configured to obtain a target instruction address of a first thread;

[0094] A first prediction unit 502 is configured to query a first branch jump history record and a second branch jump history record, wherein the first branch jump history record is stored in a first branch target buffer 503 and the second branch jump history record is stored in a second branch target buffer 506;

[0095] The first prediction unit 502 is further configured to select branch jump information including a target instruction address from the first branch jump history record and the second branch jump history record;

[0096] The first prediction unit 502 is further configured to perform branch prediction based on the selected branch jump information;

[0097] The first instruction-side unit 501 is further configured to obtain an instruction corresponding to the first jump address according to the first jump address obtained by branch prediction.

[0098] In another optional embodiment, the first processing core 401 is specifically configured to select the branch jump information including the target instruction address from the branch jump history record with the highest priority when both the first branch jump history record and the second branch jump history record include the target instruction address. Optionally, the priority of the first branch jump history record is higher than the priority of the second branch jump history record. When the first processing core 401 includes a prediction unit, the prediction unit of the first processing core 401 can perform this function.

[0099] In another optional embodiment, the first processing core 401 is specifically configured to, when the first branch jump history record includes the target instruction and the second branch jump history record does not include the target instruction address, select branch jump information including the target instruction address from the first branch jump history record; and when the first branch jump history record does not include the target instruction and the second branch jump history record does include the target instruction address, select branch jump information including the target instruction address from the second branch jump history record. When the first processing core 401 includes a prediction unit, this function can be performed by the prediction unit of the first processing core 401.

[0100] In another optional embodiment, the first processing core 401 is also used to obtain the second jump address according to the execution result of the target instruction when the first branch jump history record does not include the target instruction address and the second branch jump history record includes the target instruction address, and the target instruction corresponds to the target instruction address; when the second jump address is the same as the first jump address, add branch jump information including the target instruction address and the first jump address to the first branch jump history record; when the second jump address is different from the first jump address, add branch jump information including the target instruction address and the second jump address to the first branch jump history record.

[0101] See Figure 6 ,In another optional embodiment, the multi-core processor 400 further includes a scheduling unit 601;

[0102] The scheduling unit 601 is configured to obtain multiple threads before the first processing core 401 obtains the target instruction address of the first thread; select a thread having the same sub-function from the multiple threads; select a first thread and a second thread from the threads having the same sub-function, wherein the ratio of the number of the same sub-functions to the number of all sub-functions in the first thread is greater than or equal to a first preset ratio, and the ratio of the number of the same sub-functions to the number of all sub-functions in the second thread is greater than or equal to a second preset ratio; and send the second thread to the second processing core 402;

[0103] The second processing core 402 is configured to generate a second branch jump history record according to the jump instruction of the second thread.

[0104] In this embodiment, the scheduling unit 601 may be a processing core other than the first processing core 401 and the second processing core 402 in the multi-core processor 400 for implementing the scheduling function, or a circuit in the multi-core processor 400 for implementing the scheduling function.

[0105] In another optional embodiment, the first processing core 401 is adjacent to the second processing core 402 .

[0106] In another optional embodiment, the first processing core 401 includes a prediction unit and a branch target buffer, and the second processing core 402 includes a prediction unit and a branch target buffer; the prediction unit of the first processing core 401 is connected to the branch target buffer of the second processing core 402 via a wire; and / or, the prediction unit of the second processing core 402 is connected to the branch target buffer of the first processing core 401 via a wire.

[0107] In this embodiment, the steps and beneficial effects performed by each processing core or unit in the multi-core processor 400 may refer to the corresponding descriptions in the above embodiments or optional embodiments, and will not be repeated here.

[0108] See Figure 7 , the present application provides an electronic device 700, the electronic device 700 includes a multi-core processor 400 and a memory 701 connected via a bus 702;

[0109] The memory 701 is used to store instructions and data. The memory 701 can be a volatile memory or a non-volatile memory, or can include both volatile memory and non-volatile memory. Volatile memory is also called internal memory.

[0110] The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory.

[0111] The volatile memory may be random access memory (RAM). By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DRRAM).

[0112] The present application provides a computer storage medium including instructions, which, when executed on a computer, enables the computer to execute the method described in any one of the above embodiments or optional embodiments.

[0113] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0114] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in this application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be stored by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (SSD)).

[0115] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An instruction processing method applied to a multi-core processor, wherein the multi-core processor includes a first processing core and a second processing core, characterized in that: The instruction processing method includes: The first processing core obtains a target instruction address of the first thread; The first processing core queries a first branch jump history record and a second branch jump history record, the first branch jump history record is stored in the first processing core, and the second branch jump history record is stored in the second processing core; The first processing core selects branch jump information including the target instruction address from the first branch jump history record and the second branch jump history record; The first processing core performs branch prediction according to the selected branch jump information; The first processing core obtains, according to the first jump address obtained by branch prediction, an instruction corresponding to the first jump address; Selecting the branch jump information including the target instruction address from the first branch jump history record and the second branch jump history record includes: selecting the branch jump information including the target instruction address from the first branch jump history record when the first branch jump history record includes the target instruction address and the second branch jump history record does not include the target instruction address; selecting the branch jump information including the target instruction address from the second branch jump history record when the first branch jump history record does not include the target instruction address and the second branch jump history record includes the target instruction address; The method further comprises: If the first branch jump history record does not include a target instruction address and the second branch jump history record includes the target instruction address, obtaining a second jump address according to an execution result of a target instruction, the target instruction corresponding to the target instruction address; When the second jump address is the same as the first jump address, adding branch jump information including the target instruction address and the first jump address to the first branch jump history record; When the second jump address is different from the first jump address, branch jump information including the target instruction address and the second jump address is added to the first branch jump history record.

2. The method according to claim 1, characterized in that The first processing core extracting the branch jump information including the target instruction address from the first branch jump history record and the second branch jump history record includes: In a case where both the first branch jump historical record and the second branch jump historical record include the target instruction address, the first processing core selects the branch jump information including the target instruction address from the branch jump historical record with the highest priority.

3. The method according to claim 2, characterized in that The priority of the first branch jump history record is higher than the priority of the second branch jump history record.

4. The method according to any one of claims 1 to 3, characterized in that Before the first processing core obtains the target instruction address of the first thread, the method further includes: A scheduling unit acquires a plurality of threads, the scheduling unit belonging to the multi-core processor; The scheduling unit selects a thread having the same sub-function from the multiple threads; The scheduling unit selects the first thread and the second thread from threads having identical sub-functions, wherein a ratio of the number of identical sub-functions to the number of all sub-functions in the first thread is greater than or equal to a first preset ratio, and a ratio of the number of identical sub-functions to the number of all sub-functions in the second thread is greater than or equal to a second preset ratio; The scheduling unit sends the second thread to the second processing core; The second processing core generates the second branch jump history record according to the jump instruction of the second thread.

5. A multi-core processor, comprising a first processing core and a second processing core, characterized in that: The first processing core is configured to obtain a target instruction address of the first thread; The first processing core is further configured to query a first branch jump history record and a second branch jump history record, wherein the first branch jump history record is stored in the first processing core, and the second branch jump history record is stored in the second processing core; The first processing core is further configured to select branch jump information including the target instruction address from the first branch jump history record and the second branch jump history record; The first processing core is further configured to perform branch prediction based on the selected branch jump information; The first processing core is further configured to obtain an instruction corresponding to the first jump address according to the first jump address obtained by branch prediction; The first processing core is specifically configured to, when the first branch jump history record includes the target instruction address and the second branch jump history record does not include the target instruction address, select branch jump information including the target instruction address from the first branch jump history record; and when the first branch jump history record does not include the target instruction address and the second branch jump history record includes the target instruction address, select branch jump information including the target instruction address from the second branch jump history record; The first processing core is further configured to, when the first branch jump history record does not include a target instruction address and the second branch jump history record includes the target instruction address, obtain a second jump address according to an execution result of a target instruction, the target instruction corresponding to the target instruction address; and when the second jump address is the same as the first jump address, add branch jump information including the target instruction address and the first jump address to the first branch jump history record; When the second jump address is different from the first jump address, branch jump information including the target instruction address and the second jump address is added to the first branch jump history record.

6. The multi-core processor according to claim 5, wherein: The first processing core is specifically configured to select the branch jump information including the target instruction address from the branch jump history record with the highest priority when both the first branch jump history record and the second branch jump history record include the target instruction address.

7. The multi-core processor according to claim 6, wherein: The priority of the first branch jump history record is higher than the priority of the second branch jump history record.

8. The multi-core processor according to any one of claims 5 to 7, characterized in that: The multi-core processor further includes a scheduling unit; The scheduling unit is configured to obtain a plurality of threads before the first processing core obtains a target instruction address of the first thread; select a thread having an identical sub-function from the plurality of threads; and select the first thread and the second thread from the threads having the identical sub-function, wherein a ratio of the number of identical sub-functions to the number of all sub-functions in the first thread is greater than or equal to a first preset ratio, and a ratio of the number of identical sub-functions to the number of all sub-functions in the second thread is greater than or equal to a second preset ratio; The scheduling unit is further configured to send the second thread to the second processing core; The second processing core is configured to generate the second branch jump history record according to the jump instruction of the second thread.

9. The multi-core processor according to any one of claims 5 to 7, characterized in that: The first processing core is adjacent to the second processing core.

10. The multi-core processor according to any one of claims 5 to 7, characterized in that: The first processing core includes a prediction unit and a branch target buffer, and the second processing core includes a prediction unit and a branch target buffer; The prediction unit of the first processing core is connected to the branch target buffer of the second processing core via a wire, and / or, The prediction unit of the second processing core is connected to the branch target buffer of the first processing core via a wire.

11. An electronic device, characterized in that: The electronic device includes a memory and the multi-core processor according to any one of claims 5 to 10.

12. A computer storage medium comprising instructions, characterized in that When the instruction processing method is executed on a computer, the computer is caused to execute the instruction processing method according to any one of claims 1 to 4.

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