An IGZO backplane structure and manufacturing method applied to an OLED panel

Abstract

The present invention discloses an IGZO backplane structure and a manufacturing method applied to an OLED panel. A metal layer M0 is provided on a substrate Sub; an insulating layer PV is further provided on the substrate Sub, and the insulating layer PV covers the metal layer M0; a semiconductor layer IGZO is provided on the insulating layer PV; a metal layer M0.5 is provided on the IGZO semiconductor layer; an insulating layer GI is further provided on the insulating layer PV, and the insulating layer GI covers the metal layer M0.5 and the semiconductor layer IGZO; a metal layer M1 is provided on the insulating layer GI; an insulating layer IP is further provided on the insulating layer GI, and the insulating layer IP covers the metal layer M1; a metal layer M2 is provided on the insulating layer IP, and the metal layer M2 and the metal layer M0.5 form a storage capacitor; an organic planarization layer OP is further provided on the insulating layer IP, and the organic planarization layer OP covers the metal layer M2; an anode metal layer Anode is provided on the organic planarization layer OP; a pixel definition layer PDL is further provided on the organic planarization layer OP, and the pixel definition layer PDL has an opening at the anode metal layer Anode. The present invention can improve the disadvantage of low resolution of the IGZO OLED panel.

Description

Technical Field

[0001] The present invention relates to the technical field of OLED display, and particularly relates to an IGZO backplane structure and manufacturing method applied to an OLED panel. Background Art

[0002] Currently, LTPS driving backplanes are mainly used in OLED panels on the market. LTPS has the advantage of high electron mobility, which means that smaller component sizes can achieve the same on-state current as other semiconductor TFTs, so pixel driving circuits can be made smaller and the resolution is higher. Although LTPS has high electron mobility, its leakage current is also large. Therefore, the capacitor needs to be frequently charged during display to maintain the stability of the current driving the OLED component, resulting in high driving power consumption and being not suitable for low-frequency refreshing. In addition, the manufacturing cost of LTPS backplanes is also high, and the uniformity performance is not good, making it not suitable for the manufacturing of large-size panels.

[0003] The IGZO backplane has lower electron mobility than LTPS. To achieve the same on-state current as LTPS, larger-size components are required, and the single sub-pixel driving circuit is larger, resulting in lower resolution. However, the leakage current of IGZO is smaller, so the driving power consumption is lower. Since the manufacturing process is similar to the very mature amorphous silicon backplane technology, the existing amorphous silicon backplane production line can be modified to produce IGZO panels. The production cost is cheaper than that of LTPS backplanes, and due to good uniformity, the IGZO backplane is applicable to large-size display screens such as TVs and computers, having a broad application prospect. Summary of the Invention

[0004] To overcome the deficiencies in the prior art, the purpose of the present invention is to provide an IGZO backplane structure and manufacturing method applied to an OLED panel, which can improve the disadvantage of low resolution of IGZO OLED panels.

[0005] To achieve the above purpose, the present invention adopts the following technical solutions:

[0006] An IGZO backplane structure applied to an OLED panel, which includes a substrate Sub;

[0007] A metal layer M0 is provided on the substrate Sub, and the metal layer M0 is used to receive the OVDD signal;

[0008] An insulating layer PV is further provided on the substrate Sub, and the insulating layer PV covers the metal layer M0;

[0009] A semiconductor layer IGZO is provided on the insulating layer PV;

[0010] A metal layer M0.5 is provided on the semiconductor layer IGZO, and the metal layer M0.5 is connected to the metal layer M0;

[0011] An insulating layer GI is further provided on the insulating layer PV, and the insulating layer GI covers the metal layer M0.5 and the semiconductor layer IGZO;

[0012] A metal layer M1 is provided on the insulating layer GI, and the metal layer M1 is used to receive the SCAN scan signal;

[0013] An insulating layer IP is further provided on the insulating layer GI, and the insulating layer IP covers the metal layer M1;

[0014] A metal layer M2 is provided on the insulating layer IP, and the metal layer M2 forms a storage capacitor with the metal layer M0.5, and the metal layer M2 is respectively connected to the semiconductor layer IGZO and the metal layer M1;

[0015] An organic planarization layer OP is further provided on the insulating layer IP, and the organic planarization layer OP covers the metal layer M2;

[0016] An anode metal layer Anode is provided on the organic planarization layer OP, and the anode metal layer Anode is connected to the metal layer M2, and the anode metal layer Anode is used to receive the OVDD voltage signal;

[0017] A pixel definition layer PDL is further provided on the organic planarization layer OP, and the pixel definition layer PDL has an opening at the anode metal layer Anode.

[0018] Furthermore, a PV hole is provided on the insulating layer PV, and the metal layer M0.5 is connected to the metal layer M0 through the PV hole.

[0019] Furthermore, an IP hole is provided on the insulating layer IP, and the metal layer M2 is respectively connected to the semiconductor layer IGZO and the metal layer M1 through the IP hole.

[0020] Furthermore, an OP hole is provided on the organic planarization layer OP, and the anode metal layer Anode is connected to the metal layer M2 through the OP hole.

[0021] A manufacturing method of an IGZO backplane structure applied to an OLED panel according to the present invention, the manufacturing method includes the following steps:

[0022] 1) A metal layer M0 is plated on the substrate Sub;

[0023] 2) An insulating layer PV is plated to cover the metal layer M0;

[0024] 3) A semiconductor layer IGZO is plated on the insulating layer PV;

[0025] 4) A PV hole is drilled on the insulating layer PV;

[0026] 5) A metal layer M0.5 is plated on the semiconductor layer IGZO, and the metal layer M0.5 is connected to the metal layer M0 through the PV hole;

[0027] 6) Deposit an insulating layer GI to cover the metal layer M0.5 and the semiconductor layer IGZO;

[0028] 7) Deposit a metal layer M1 on the insulating layer GI;

[0029] 8) Deposit an insulating layer IP to cover the metal layer M1;

[0030] 9) Drill IP holes in the insulating layer IP;

[0031] 10) Deposit a metal layer M2 on the insulating layer IP. The metal layer M2 and the metal layer M0.5 form a storage capacitor, and the metal layer M2 is connected to the semiconductor layer IGZO and the metal layer M1 respectively through the IP holes;

[0032] 11) Deposit an organic planarization layer OP to cover the metal layer M2;

[0033] 12) Drill OP holes in the organic planarization layer OP;

[0034] 13) Deposit an anode metal layer Anode on the organic planarization layer OP. The anode metal layer Anode is connected to the metal layer M2 through the OP holes;

[0035] 14) Deposit a pixel definition layer PDL on the organic planarization layer OP and open an aperture at the anode metal layer Anode.

[0036] The present invention adopts the above technical solutions, manufactures signal traces through dedicated metal layers, reduces the planar space occupied by the pixel driving circuit, and further reduces the pixel area, so that more pixels can be accommodated per unit area, thereby improving the resolution of the panel. At the same time, the advantages of low leakage current, low power consumption and low cost of the IGZO backplane can be exerted. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The following further describes the present invention in detail with reference to the drawings and specific embodiments;

[0038] Figure 1 is a schematic diagram of the IGZO backplane structure of the present invention applied to an OLED panel;

[0039] Figure 2 is the manufacturing process of the IGZO backplane structure of the present invention applied to an OLED panel. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] Please refer to Figure 1 , an IGZO backplane structure of the present invention applied to an OLED panel, which includes a substrate Sub;

[0041] A metal layer M0 is provided on the substrate Sub, and the metal layer M0 is used to receive the OVDD signal;

[0042] An insulating layer PV is also provided on the substrate Sub, and the insulating layer PV covers the metal layer M0;

[0043] A semiconductor layer IGZO is provided on the insulating layer PV;

[0044] A metal layer M0.5 is provided on the semiconductor layer IGZO, and the metal layer M0.5 is connected to the metal layer M0;

[0045] An insulating layer GI is also provided on the insulating layer PV, and the insulating layer GI covers the metal layer M0.5 and the semiconductor layer IGZO;

[0046] A metal layer M1 is provided on the insulating layer GI, and the metal layer M1 is used to receive the SCAN scan signal;

[0047] An insulating layer IP is also provided on the insulating layer GI, and the insulating layer IP covers the metal layer M1;

[0048] A metal layer M2 is provided on the insulating layer IP, the metal layer M2 forms a storage capacitor with the metal layer M0.5, and the metal layer M2 is respectively connected to the semiconductor layer IGZO and the metal layer M1;

[0049] An organic planarization layer OP is also provided on the insulating layer IP, and the organic planarization layer OP covers the metal layer M2;

[0050] An anode metal layer Anode is provided on the organic planarization layer OP, the anode metal layer Anode is connected to the metal layer M2, and the anode metal layer Anode is used to receive the OVDD voltage signal;

[0051] A pixel definition layer PDL is also provided on the organic planarization layer OP, and the pixel definition layer PDL has an opening at the anode metal layer Anode.

[0052] Furthermore, PV holes are provided on the insulating layer PV, and the metal layer M0.5 is connected to the metal layer M0 through the PV holes.

[0053] Furthermore, IP holes are provided on the insulating layer IP, and the metal layer M2 is respectively connected to the semiconductor layer IGZO and the metal layer M1 through the IP holes.

[0054] Furthermore, OP holes are provided on the organic planarization layer OP, and the anode metal layer Anode is connected to the metal layer M2 through the OP holes.

[0055] Please refer to Figure 2 , a manufacturing method of an IGZO backplane structure applied to an OLED panel according to the present invention, the manufacturing method includes the following steps:

[0056] 1) Deposit the metal layer M0 on the substrate Sub;

[0057] 2) Deposit the insulating layer PV to cover the metal layer M0;

[0058] 3) Deposit a semiconductor layer IGZO on the insulating layer PV;

[0059] 4) Drill PV holes in the insulating layer PV;

[0060] 5) Deposit a metal layer M0.5 on the semiconductor layer IGZO, and the metal layer M0.5 is connected to the metal layer M0 through the PV holes;

[0061] 6) Deposit an insulating layer GI to cover the metal layer M0.5 and the semiconductor layer IGZO;

[0062] 7) Deposit a metal layer M1 on the insulating layer GI;

[0063] 8) Deposit an insulating layer IP to cover the metal layer M1;

[0064] 9) Drill IP holes in the insulating layer IP;

[0065] 10) Deposit a metal layer M2 on the insulating layer IP, the metal layer M2 forms a storage capacitor with the metal layer M0.5, and the metal layer M2 is respectively connected to the semiconductor layer IGZO and the metal layer M1 through the IP holes;

[0066] 11) Deposit an organic planarization layer OP to cover the metal layer M2;

[0067] 12) Drill OP holes in the organic planarization layer OP;

[0068] 13) Deposit an anode metal layer Anode on the organic planarization layer OP, and the anode metal layer Anode is connected to the metal layer M2 through the OP holes;

[0069] 14) Deposit a pixel definition layer PDL on the organic planarization layer OP and open an aperture at the anode metal layer Anode.

[0070] The present invention has the following beneficial effects: (1) In terms of display effect, placing the OVDD signal at the bottom layer enables it not to compete with other metal traces for planar space, effectively reducing the area of the pixel driving circuit, increasing the number of pixels per unit area, and thus increasing the resolution; (2) In terms of design, placing the OVDD signal trace at the bottom layer increases the space, facilitating the placement planning of other metal traces and TFT components.

[0071] The implementation of the present invention has been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific implementation manners. The above specific implementation manners are illustrative rather than restrictive of the present invention. Those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and the specification of the present invention.

Claims

1. An IGZO backplane structure for an OLED panel, comprising a substrate Sub; characterized in that: A metal layer M0 is provided on the substrate Sub, and the metal layer M0 is used to receive the OVDD signal; An insulating layer PV is also provided on the substrate Sub, and the insulating layer PV covers the metal layer M0; A semiconductor layer IGZO is provided on the insulating layer PV; A metal layer M0.5 is provided on the semiconductor layer IGZO, and the metal layer M0.5 is connected to the metal layer M0; An insulating layer GI is also provided on the insulating layer PV, and the insulating layer GI covers the metal layer M0.5 and the semiconductor layer IGZO; A metal layer M1 is provided on the insulating layer GI, and the metal layer M1 is used to receive the SCAN scanning signal; An insulating layer IP is further provided on the insulating layer GI, and the insulating layer IP covers the metal layer M1; A metal layer M2 is provided on the insulating layer IP, the metal layer M2 and the metal layer M0.5 form a storage capacitor, and the metal layer M2 is connected to the semiconductor layer IGZO and the metal layer M1 respectively; An organic planar layer OP is further provided on the insulating layer IP, and the organic planar layer OP covers the metal layer M2; An anode metal layer Anode is provided on the organic planar layer OP. The anode metal layer Anode is connected to the metal layer M2. The anode metal layer Anode is used to receive an OVDD voltage signal. A pixel definition layer PDL is further provided on the organic planar layer OP, and the pixel definition layer PDL is provided with an opening at the anode metal layer Anode; The insulating layer PV is provided with a PV hole, and the metal layer M0.5 is connected to the metal layer M0 through the PV hole; An IP hole is provided on the insulating layer IP, and the metal layer M2 is connected to the semiconductor layer IGZO and the metal layer M1 respectively through the IP hole.

2. The IGZO backplane structure for an OLED panel according to claim 1, wherein: An OP hole is provided on the organic planar layer OP, and the anode metal layer Anode is connected to the metal layer M2 through the OP hole.

3. A method for manufacturing an IGZO backplane structure for an OLED panel according to claim 1 or 2, characterized in that: The manufacturing method comprises the following steps: 1) Plate a metal layer M0 on the substrate Sub; 2) Plate the insulating layer PV and cover the metal layer M0; 3) Coating a semiconductor layer IGZO on the insulating layer PV; 4) Drill PV holes on the insulation layer; 5) A metal layer M0.5 is plated on the semiconductor layer IGZO, and the metal layer M0.5 is connected to the metal layer M0 through the PV hole; 6) Plating an insulating layer GI to cover the metal layer M0.5 and the semiconductor layer IGZO; 7) Plating a metal layer M1 on the insulating layer GI; 8) Plate the insulating layer IP to cover the metal layer M1; 9) Drill IP holes on the insulation layer IP; 10) A metal layer M2 is plated on the insulating layer IP. The metal layer M2 and the metal layer M0.5 form a storage capacitor. The metal layer M2 is connected to the semiconductor layer IGZO and the metal layer M1 through the IP hole. 11) Plate an organic flat layer OP to cover the metal layer M2; 12) Drilling OP holes in the organic flat layer; 13) An anode metal layer Anode is plated on the organic planar layer OP, and the anode metal layer Anode is connected to the metal layer M2 through the OP hole; 14) A pixel definition layer (PDL) is plated on the organic planar layer (OP) and an opening is opened at the anode metal layer (Anode).

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