Loading Circuit, Method and System

Abstract

The present application provides a loading circuit, method and system, belonging to the field of semiconductor technology. In the solution provided by the present application, the loading circuit includes a JTAG circuit and a channel selection circuit, the channel selection circuit has a first SPI, a second SPI and a third SPI, and the third SPI is used to connect to an SPI flash memory. Since each pin of the JTAG circuit can be correspondingly connected to each pin of the first SPI, and the JTAG circuit can control the first SPI and the third SPI to conduct, communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can be connected to the JTAG circuit in the loading circuit through the JTAG interface, and when the first SPI and the third SPI in the channel selection circuit are conducting, data can be loaded into the SPI flash memory. Thus, out-of-band upgrade of the firmware stored in the SPI flash memory through the JTAG interface is realized, and the flexibility of firmware upgrade is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technologies, and particularly to a loading circuit, method, and system. Background Art

[0002] A processor board includes a printed circuit board (PCB), a processor disposed on the PCB board, and a serial peripheral interface (SPI) flash connected to the processor. The SPI flash is used to store firmware, and the processor is used to run the firmware.

[0003] In related technologies, the firmware in the SPI flash is generally upgraded through an in-band upgrade method, that is, the processor directly loads data into the SPI flash to implement the upgrade of the firmware. However, if an exception occurs during the in-band upgrade, an out-of-band upgrade method needs to be used to upgrade the firmware. For a processor board supporting SPI, during out-of-band upgrade, the baseboard management controller (BMC) can be connected to the SPI flash through the SPI of the processor board, and the BMC loads data into the SPI flash through the SPI to upgrade the firmware in the SPI flash.

[0004] However, currently, mainstream processor boards are all peripheral component interconnect express (PCIE) boards or open compute project accelerator modules (OAM). The hardware interfaces of both PCIE boards and OAMs do not include an external SPI and cannot support out-of-band upgrade through SPI, resulting in poor flexibility. Summary of the Invention

[0005] This application provides a loading circuit, method, and system, which can solve the problem of poor flexibility during out-of-band upgrade of a processor board.

[0006] On the one hand, a loading circuit is provided. The loading circuit includes: a Joint Test Action Group (JTAG) circuit, a flash memory controller (SFC), and a channel selection circuit; the channel selection circuit has a first Serial Peripheral Interface (SPI), a second SPI, and a third SPI, the second SPI is connected to the SFC, and the third SPI is used to connect to an SPI flash; the JTAG circuit is used to control the first SPI and the third SPI in the channel selection circuit to conduct, or control the second SPI and the third SPI to conduct; moreover, the test clock (TCK) pin of the JTAG circuit is connected to the serial clock (SCLK) pin in the first SPI, the test data input (TDI) pin of the JTAG circuit is connected to the master output slave input (MOSI) pin in the first SPI, the test data output (TDO) pin of the JTAG circuit is connected to the master input slave output (MISO) pin in the first SPI, and the test access port (TAP) controller of the JTAG circuit is connected to the chip select (CS) pin in the first SPI; wherein, after the TAP controller is in the data register (DR) state, the level of the target CS signal provided to the CS pin jumps from an invalid level to a valid level.

[0007] The channel selection circuit in the loading circuit provided in this application has a first SPI, a second SPI, and a third SPI, and the third SPI is used to connect to an SPI flash. Since each pin of the JTAG circuit in the loading circuit can be correspondingly connected to each pin of the first SPI, and the JTAG circuit can control the first SPI and the third SPI to conduct, communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can be connected to the JTAG circuit in the loading circuit through the JTAG interface, and when the first SPI and the third SPI in the channel selection circuit are conducting, data can be loaded into the SPI flash. Thus, out-of-band upgrade of the firmware stored in the SPI flash through the JTAG interface is realized, improving the flexibility of firmware upgrade.

[0008] Optionally, the JTAG circuit is used to control the first SPI and the third SPI to conduct according to the received loading instruction.

[0009] Among them, the loading instruction can be issued by the controller. When the JTAG circuit controls the conduction of the first SPI and the third SPI, the SPI flash memory is gated with the loading circuit. At this time, the controller can perform out-of-band upgrade on the firmware stored in the SPI flash memory through the loading circuit.

[0010] Optionally, if the loading instruction is a parallel loading instruction, the JTAG circuit is further configured to connect the TDI pin and the TDO pin according to the loading instruction.

[0011] By connecting the TDI pin and the TDO pin, the loading circuit can transmit the TDI signal to the next loading circuit in series while loading data into the SPI flash memory, so as to realize parallel loading of the SPI flash memories connected by multiple series-connected loading circuits.

[0012] Optionally, at the first target jump edge of the TCK pin after the TAP controller is in the shift DR state, the level of the target CS signal provided to the CS pin jumps from an invalid level to a valid level; at the first target jump edge of the TCK pin after the TAP controller ends the shift DR state, the level of the target CS signal provided to the CS pin jumps from a valid level to an invalid level; wherein, the target jump edge is a rising edge or a falling edge.

[0013] Among them, the JTAG circuit can read and write data in the stage when the TAP controller is in the shift DR state, and the first SPI can read and write data when the target CS signal is at a valid level. For the scenario where the controller is only connected to one loading circuit, the TDI signal transmitted by the controller to the TDI pin of the loading circuit will not be delayed, and the TDO signal transmitted by the TDO pin of the loading circuit to the controller will not be delayed either. Therefore, in this scenario, the loading circuit can directly refer to the stage when the TAP controller is in the shift DR state to determine the stage when the target CS signal is at a valid level.

[0014] Optionally, the JTAG circuit is configured to provide the target CS signal to the CS pin; or, the loading circuit further includes a timing conversion circuit, and the TAP controller is connected to the CS pin through the timing conversion circuit; the timing conversion circuit is configured to provide the target CS signal to the CS pin according to the state of the TAP controller and the level of the TCK pin.

[0015] In the solution provided by this application, the target CS signal can be provided by the JTAG circuit or by the timing conversion circuit, thereby effectively improving the flexibility of providing the target CS signal to the CS pin.

[0016] Optionally, the loading circuit may further include a timing conversion circuit, and the TAP controller is connected to the CS pin through the timing conversion circuit; the JTAG circuit is configured to provide an initial CS signal to the timing conversion circuit, wherein, at the first target jump edge of the TCK pin after the TAP controller enters the shift DR state, the level of the initial CS signal is adjusted from an invalid level to a valid level, and at the first target jump edge of the TCK pin after the TAP controller ends the shift DR state, the level of the initial CS signal is adjusted from a valid level to an invalid level, and the target jump edge is a rising edge or a falling edge; the timing conversion circuit is configured to perform timing conversion on the initial CS signal to obtain a target CS signal, and provide the target CS signal to the CS pin; wherein, the moment when the level of the target CS signal jumps from an invalid level to a valid level is delayed by n clock cycles relative to the moment when the level of the initial CS signal jumps from an invalid level to a valid level; and / or, the moment when the level of the target CS signal jumps from a valid level to an invalid level is advanced by m clock cycles relative to the moment when the level of the initial CS signal jumps from a valid level to an invalid level; both n and m are positive integers.

[0017] For the scenario where n other loading circuits are connected in series before the loading circuit, there will be a delay in the TDI signal transmitted by the controller to the TDI pin of the loading circuit. For the scenario where m other loading circuits are connected in series after the loading circuit, there will be a delay in the TDO signal transmitted from the TDO pin of the loading circuit to the controller. Therefore, in the solution provided in this application, the timing conversion circuit can delay the jump edge of the initial CS signal by n clock cycles, and / or advance it by m clock cycles, so that the data signal and the control signal received by the first SPI can be synchronized.

[0018] Optionally, the loading circuit further includes a first configuration register connected to the timing conversion circuit, and a first value for indicating n is configured in the first configuration register; the timing conversion circuit is configured to delay the moment when the initial CS signal jumps from an invalid level to a valid level by n clock cycles according to the first value.

[0019] Wherein, the first value can be configured by the controller, that is, the controller can configure the first configuration register in the to-be-loaded loading circuit according to the position of the to-be-loaded loading circuit in the multiple series-connected loading circuits.

[0020] Optionally, a second value for indicating the duration when the target CS signal is at a valid level is further configured in the first configuration register; the timing conversion circuit is configured to advance the moment when the initial CS signal jumps from a valid level to an invalid level by m clock cycles according to the second value.

[0021] Among them, the second value can also be configured by the controller, that is, the controller can configure the first configuration register in the loading circuit to be loaded according to the position of the loading circuit to be loaded in multiple series-connected loading circuits.

[0022] Optionally, the TDI pin is connected to the MOSI pin in the first SPI through the timing conversion circuit; the timing conversion circuit is further configured to delay the TDI signal provided by the TDI pin by i clock cycles and then provide it to the MOSI pin, where i is a positive integer not greater than n.

[0023] In the solution provided by this application, the controller can perform parallel loading on x series-connected loading circuits, where x is an integer not greater than n + 1. In this scenario, the (x - i)-th loading circuit can delay the TDI signal provided by its TDI pin by i clock cycles and then provide it to the MOSI pin, so that the x loading circuits can load data into the SPI flash simultaneously. Among them, i is a positive integer less than x.

[0024] Optionally, the loading circuit further includes a second configuration register connected to the timing conversion circuit, and a third value for indicating i is configured in the second configuration register; the timing conversion circuit is configured to delay the TDI signal provided by the TDI pin by i clock cycles according to the third value and then provide it to the MOSI pin.

[0025] Among them, the third value can also be configured by the controller, that is, the controller can configure the second configuration register in the loading circuit to be loaded according to the position of the loading circuit to be loaded in multiple series-connected loading circuits and the number of loading circuits for parallel loading.

[0026] On the other hand, a loading method is provided, which is applied to the loading circuit provided in the above aspect; the method includes: conducting the first SPI and the third SPI in the channel selection circuit of the loading circuit; after the TAP controller in the loading circuit is in the shift DR state, adjusting the level of the target CS signal provided to the CS pin from an invalid level to a valid level.

[0027] Optionally, conducting the first SPI and the third SPI in the channel selection circuit of the loading circuit includes: conducting the first SPI and the third SPI in the channel selection circuit of the loading circuit according to the received loading instruction.

[0028] Optionally, the loading instruction is a parallel loading instruction; the method further includes: connecting the TDI pin and the TDO pin of the JTAG circuit in the loading circuit according to the loading instruction.

[0029] Optionally, after the TAP controller in the loading circuit is in the shift DR state, the level of the target CS signal provided to the CS pin is adjusted from an invalid level to a valid level, including: at the first target jump edge of the TCK pin after the TAP controller in the loading circuit is in the shift DR state, adjusting the level of the target CS signal provided to the CS pin from an invalid level to a valid level; the method further includes: at the first target jump edge of the TCK pin after the TAP controller ends the shift DR state, adjusting the level of the target CS signal provided to the CS pin from a valid level to an invalid level; wherein, the target jump edge is a rising edge or a falling edge.

[0030] Optionally, after the TAP controller in the loading circuit is in the shift DR state, the level of the target CS signal provided to the CS pin is adjusted from an invalid level to a valid level, including: at the nth target jump edge of the TCK pin after the TAP controller in the loading circuit is in the shift DR state, adjusting the level of the target CS signal provided to the CS pin from an invalid level to a valid level; and / or, the method further includes: at the mth target jump edge of the TCK pin before the TAP controller in the loading circuit ends the shift DR state, the level of the target CS signal provided to the CS pin jumps from a valid level to an invalid level; wherein, the target jump edge is a rising edge or a falling edge, and both n and m are positive integers.

[0031] Optionally, the method further includes: delaying the TDI signal provided by the TDI pin of the JTAG circuit in the loading circuit by i clock cycles and then providing it to the MOSI pin of the first SPI, where i is a positive integer not greater than n.

[0032] The beneficial effects of the loading method provided in the above aspect can refer to the effect description of the loading circuit provided in the above aspect.

[0033] In another aspect, a loading system is provided, the loading system includes: a controller, x first loading circuits, and x serial peripheral interface SPI flash memories, where x is a positive integer; wherein, each of the first loading circuits is a loading circuit as described in any one of claims 1 to 10; the controller is connected to the JTAG circuit in each of the first loading circuits through a JTAG interface, and each SPI flash memory is connected to the third SPI of the channel selection circuit in one of the first loading circuits; the controller is configured to send a loading instruction and data to the JTAG circuit, and the loading instruction is used to instruct the JTAG circuit to conduct the first SPI of the channel selection circuit with the third SPI and load the data into the SPI flash memory.

[0034] In the loading system provided by this application, since each pin of the JTAG circuit in the loading circuit can be correspondingly connected to each pin of the first SPI, and the JTAG circuit can control the first SPI and the third SPI to conduct, communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can be connected to the JTAG circuit in the loading circuit through the JTAG interface, and when the first SPI and the third SPI in the channel selection circuit are conducting, data can be loaded into the SPI flash memory. Thus, out-of-band upgrade of the firmware stored in the SPI flash memory is realized through the JTAG interface, improving the flexibility of firmware upgrade.

[0035] Optionally, x = 1, and the system further includes: n second loading circuits connected in series between the TDI pin of the JTAG interface of the controller and the first loading circuit, where n is a positive integer; the controller is further configured to send a first configuration instruction to the first loading circuit, and the first configuration instruction is used to indicate configuring a first value for indicating n in the first configuration register of the first loading circuit.

[0036] For the scenario where n other loading circuits are connected in series before the first loading circuit, there will be a delay in the TDI signal transmitted by the controller to the TDI pin of the loading circuit. Therefore, in the solution provided by this application, the controller can also configure a first value for indicating n in the first configuration register of the first loading circuit, and the timing conversion circuit can delay the falling edge of the initial CS signal by n clock cycles according to the first value, so that the data signal and the control signal received by the first SPI can be synchronized.

[0037] Optionally, x = 1; the system further includes: m third loading circuits connected in series between the first loading circuit and the TDO pin of the JTAG interface of the controller, where m is a positive integer; the controller is further configured to determine the duration for which the target CS signal is at the valid level according to the number m of the third loading circuits, and send a second configuration instruction to the first loading circuit, and the second configuration instruction is further used to indicate configuring a second value for indicating the duration for which the target CS signal is at the valid level in the first configuration register; where the target CS signal is the signal received by the CS pin of the first SPI in the first loading circuit.

[0038] For the scenario where m other loading circuits are connected in series after this loading circuit, there will be a delay in the TDO signal transmitted from the TDO pin of this loading circuit to the controller. Therefore, in the solution provided in this application, the controller can also configure the first configuration register of the first loading circuit according to the number m of the third loading circuits, so that the timing conversion circuit can advance the rising edge of the initial CS signal by m clock cycles according to the configuration in the first configuration register, thereby enabling the data signal and control signal received by the first SPI to be synchronized.

[0039] Optionally, x>1, and the x first loading circuits are connected in series; the system further includes: n - x + 1 second loading circuits connected in series between the TDI pin of the JTAG interface of the controller and the x first loading circuits, where n is a positive integer and x is an integer not greater than n + 1; the controller is configured to perform parallel loading on the SPI flash memories connected to the x first loading circuits, the loading instruction is a parallel loading instruction, and the loading instruction is further used to instruct the first to the (x - 1)th first loading circuits among the x first loading circuits to connect the TDI pin and the TDO pin of their JTAG circuits; the controller is further configured to send a first configuration instruction to each of the first loading circuits and a third configuration instruction to the first to the (x - 1)th first loading circuits, where the first configuration instruction is used to indicate a first value for indicating n in the first configuration register of the first loading circuit, and the third configuration instruction sent to the (x - i)th first loading circuit is used to indicate a third value for indicating i in the second configuration register of the (x - i)th first loading circuit, and i is a positive integer less than x.

[0040] Since the controller can send a parallel loading instruction to the x first loading circuits connected in series, and the first to the (x - 1)th first loading circuits can connect the TDI pin and the TDO pin of their JTAG circuits according to the parallel loading instruction, the controller can parallel load data to the SPI flash memories connected to the x first loading circuits and perform out-of-band upgrade on the firmware stored in the SPI flash memories, effectively reducing the time consumed for firmware upgrade; also, since the controller can send the first value for indicating n to the first to the (x - 1)th first loading circuits, even if there are other loading circuits connected in series before the x first loading circuits, the controller can still correctly perform parallel loading on the SPI flash memories connected to the x first loading circuits; furthermore, since the controller can send the third value for indicating i to the (x - i)th first loading circuit, the (x - i)th first loading circuit can provide the TDI signal to the MOSI pin after delaying it by i clock cycles, enabling the controller to load the SPI flash memories connected to the x first loading circuits simultaneously and simplifying the control complexity.

[0041] In summary, the present application provides a loading circuit, method, and system. In the solution provided by the present application, the channel selection circuit in the loading circuit has a first SPI, a second SPI, and a third SPI, and the third SPI is used to connect to the SPI flash memory. Since each pin of the JTAG circuit in the loading circuit can be correspondingly connected to each pin of the first SPI, and the JTAG circuit can control the first SPI and the third SPI to conduct, communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can be connected to the JTAG circuit in the loading circuit through the JTAG interface, and when the first SPI and the third SPI in the channel selection circuit are conducting, data can be loaded into the SPI flash memory. Thus, out-of-band upgrade of the firmware stored in the SPI flash memory through the JTAG interface is realized, improving the flexibility of firmware upgrade. Description of the Drawings

[0042] Figure 1 is a schematic structural diagram of a loading system provided by an embodiment of the present application;

[0043] Figure 2 is a schematic structural diagram of a loading circuit provided by an embodiment of the present application;

[0044] Figure 3 is a schematic diagram of a JTAG interface timing and an SPI timing provided by an embodiment of the present application;

[0045] Figure 4 is a schematic diagram of a state machine of a TAP controller provided by an embodiment of the present application;

[0046] Figure 5 is a schematic structural diagram of another loading circuit provided by an embodiment of the present application;

[0047] Figure 6 is a schematic structural diagram of yet another loading circuit provided by an embodiment of the present application;

[0048] Figure 7 is a schematic structural diagram of still another loading circuit provided by an embodiment of the present application;

[0049] Figure 8 is a schematic structural diagram of another loading system provided by an embodiment of the present application;

[0050] Figure 9 is a schematic diagram of another JTAG interface timing and an SPI timing provided by an embodiment of the present application;

[0051] Figure 10 is a schematic structural diagram of yet another loading system provided by an embodiment of the present application;

[0052] Figure 11It is a schematic diagram of another JTAG interface timing and SPI timing provided by an embodiment of the present application;

[0053] Figure 12 It is a schematic diagram of yet another JTAG interface timing and SPI timing provided by an embodiment of the present application;

[0054] Figure 13 It is a flowchart of a loading method provided by an embodiment of the present application;

[0055] Figure 14 It is a schematic structural diagram of yet another loading system provided by an embodiment of the present application;

[0056] Figure 15 It is a schematic structural diagram of yet another loading system provided by an embodiment of the present application;

[0057] Figure 16 It is a schematic structural diagram of yet another loading system provided by an embodiment of the present application. Detailed implementation manners

[0058] The loading circuit, method and system provided by the embodiments of the present application will be introduced in detail below with reference to the accompanying drawings.

[0059] In the related art, when firmware upgrading a processor board supporting SPI in an out-of-band upgrading manner, the SPI of the BMC needs to be connected to the SPI flash in the processor board through a multiplexer (MUX). Since an additional MUX needs to be set on the processor board, the size of the processor board is large and the cost is high. Among them, the multiplexer can also be called a channel selection circuit.

[0060] Moreover, since the processor board mainly upgrades the firmware in an in-band upgrading manner and only considers using the out-of-band upgrading manner when the in-band upgrading fails. Therefore, the out-of-band upgrading manner is used less frequently, and the overhead of setting an additional MUX on the processor board for out-of-band upgrading is large.

[0061] Figure 1 It is a schematic structural diagram of a loading system provided by an embodiment of the present application. As Figure 1 shown, the loading system may include: a controller 01, x first loading circuits 02, and x SPI flashes 03. Wherein, x is a positive integer, and the x first loading circuits 02 are connected to the x SPI flashes 03 in a one-to-one correspondence. For example, Figure 1 a first loading circuit 02 and a SPI flash 03 are schematically shown (i.e., x = 1). It should be understood that if x is greater than 1, the x first loading circuits 02 can be connected in series.

[0062] As Figure 1As shown, the controller 01 can be connected to each first loading circuit 02 through a JTAG interface, and is used to send a loading instruction and data to be loaded to each first loading circuit 02. Each first loading circuit 02 is connected to a corresponding SPI flash 03 through SPI. Each first loading circuit 02 can, under the indication of the loading instruction, load the data sent by the controller 01 to the SPI flash 03 it is connected to through SPI, thereby realizing the upgrade of the firmware stored in the SPI flash.

[0063] Figure 2 is a schematic structural diagram of a loading circuit provided by an embodiment of the present application. The loading circuit can be applied to a system such as Figure 1 shown, that is, the loading circuit can be Figure 1 the first loading circuit 02 in Figure 2 shown. The following takes the loading circuit as the first loading circuit 02 as an example for description. As Figure 2 shown, the first loading circuit 02 may include: a JTAG circuit 021, an SFC 022, and a channel selection circuit 023. The channel selection circuit 023 has a first SPI, a second SPI, and a third SPI. The second SPI is connected to the SFC 022, and the third SPI is used to connect to the SPI flash 03.

[0064] Among them, the JTAG circuit 021 is used to control the conduction between the first SPI and the third SPI of the channel selection circuit 023, or to control the conduction between the second SPI and the third SPI. For example, the JTAG circuit 021 can be connected to the control interface of the channel selection circuit 023 and can send an instruction to the control interface. The channel selection circuit 023 can, according to the instruction, conduct the first SPI and the third SPI, or conduct the second SPI and the third SPI. Among them, when the first SPI and the third SPI are conducted, the JTAG circuit 021 can communicate with the SPI flash 03, for example, can load data to the SPI flash 03. When the second SPI and the third SPI are conducted, the SFC 022 can control the SPI flash 03.

[0065] Referring to Figure 1 and Figure 2 it can be seen that the JTAG interface of the JTAG circuit 021 may include a TCK pin, a TDI pin, a TDO pin, a test mode selection (TMS) pin, and a test reset input (TRST) pin. Each SPI may include an SCLK pin, a MOSI pin, a MISO pin, and a CS pin.

[0066] Among them, the JTAG circuit 021 is compatible with the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 standard. The TCK pin of the JTAG circuit 021 is connected to the SCLK pin in the first SPI. The TDI pin of the JTAG circuit 021 is connected to the MOSI pin in the first SPI. The TDO pin of the JTAG circuit 021 is connected to the MISO pin in the first SPI. The TAP controller 021a of the JTAG circuit 021 is connected to the CS pin in the first SPI. After the TAP controller 021a is in the shift DR state, the level of the target CS signal provided to the CS pin jumps from an invalid level to a valid level.

[0067] Figure 3 is a timing diagram of each pin in a JTAG interface and an SPI provided by an embodiment of the present application. Refer to Figure 3 It can be seen that the timing of the TCK pin of the JTAG interface is the same as the timing of the SCLK pin in the first SPI. The timing of the TDI pin of the JTAG interface is the same as the timing of the MOSI pin in the first SPI. The timing of the TDO pin of the JTAG interface is the same as the timing of the MISO pin in the first SPI. Therefore, the TCK pin of the JTAG interface can be directly connected to the SCLK pin in the first SPI, so that the TCK signal transmitted by the TCK pin serves as the SCLK signal of the first SPI. And the TDI pin of the JTAG interface can be directly connected to the MOSI pin in the first SPI, so that the TDI signal transmitted by the TDI pin can serve as the MOSI signal of the first SPI. And the TDO pin of the JTAG interface can be directly connected to the MISO pin in the first SPI, so that the TDO signal transmitted by the TDO pin can serve as the MISO signal of the first SPI.

[0068] Since in the JTAG protocol, refer to Figure 3 , the JTAG circuit 021 can obtain the TDI signal (i.e., write data) transmitted by the TDI pin and transmit the TDO signal (i.e., read data) to the TDO pin when the TAP controller 021a is in the shift DR state. The above timing characteristics are the same as the characteristics of the write data timing and the read data timing of the SPI respectively. Therefore, the target CS signal transmitted to the CS pin of the first SPI can be generated based on the shift DR state of the TAP controller 021a.

[0069] Among them, the valid level of the target CS signal received by the CS pin in the first SPI may be a low level, and the invalid level may be a high level. For example, the CS signal may be represented as CS#, where # indicates that the signal is active low. The first SPI can read and write data when the target CS signal is at the valid level, that is, write data through the MOSI pin and read data through the MISO pin.

[0070] Figure 4 It is a schematic diagram of the state machine of a TAP controller provided by an embodiment of the present application. As Figure 4 shown, the TAP controller 021a has 16 synchronous states: test-logic / reset, run-test / idle, select-DR-scan, capture-DR, shift-DR, exit1-DR, pause-DR, exit2-DR, update-DR, select-IR-scan, capture-IR, shift-IR, exit1-IR, pause-IR, exit2-IR, and update-IR. Among them, the synchronous states of the TAP controller 021a can be changed under the control of the TMS signal. In Figure 4 the state machine shown, TMS = 1 indicates that the TMS signal is at a high level, and TMS = 0 indicates that the TMS signal is at a low level. Since the timing of reading / writing data by the JTAG circuit 021 depends on the shift-DR state of the TAP controller 021a, as long as the synchronous state of the TAP controller 021a passes through the shift-DR state, the JTAG circuit 021 can read / write data. Referring to Figure 4 it can be seen that the path for the synchronous state of the TAP controller 021a to transition to the shift-DR state is not unique.

[0071] Based on the above pin connection method, the conversion of the timing of the JTAG circuit to the timing of the SPI can be realized, that is, the communication between the JTAG interface and the SPI can be realized. Since most PCIE boards support the JTAG interface, the controller can perform out-of-band upgrade on the SPI flash on the PCIE board through the JTAG interface.

[0072] In summary, the embodiment of the present application provides a loading circuit. The loading circuit includes a JTAG circuit and a channel selection circuit. The channel selection circuit has a first SPI, a second SPI, and a third SPI. The third SPI is used to connect to an SPI flash memory. Since each pin of the JTAG circuit can be correspondingly connected to each pin of the first SPI, and the JTAG circuit can control the first SPI and the third SPI to conduct, communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can be connected to the JTAG circuit in the loading circuit through the JTAG interface, and when the first SPI and the third SPI in the channel selection circuit are conducting, data can be loaded into the SPI flash memory, thereby realizing out-of-band upgrade of the firmware stored in the SPI flash memory.

[0073] Optionally, the JTAG circuit 021 can be used to control the first SPI and the third SPI to conduct according to the received loading instruction. Among them, the loading instruction can be issued by the controller 01 in the loading system. When the controller 01 needs to upgrade the firmware in the SPI flash memory 03 connected to the first loading circuit 02 in an out-of-band upgrade manner, it can issue a loading instruction to the JTAG circuit 021 in the first loading circuit 02 through the JTAG interface.

[0074] Figure 5 is a schematic structural diagram of another loading circuit provided by the embodiment of the present application. As Figure 5 shown, the JTAG circuit 021 in the first loading circuit 02 may further include an instruction register (IR) 021b and an instruction decoder 021c. The IR 021b is connected to the TDI pin and can be used to receive a loading instruction and control the channel selection circuit 023 to conduct the first SPI and the third SPI according to the loading instruction. The instruction decoder 021c can be used to decode the instruction received by the IR 021b and send a control signal to the channel selection circuit 023 to control the channel selection circuit 023 to conduct the first SPI and the third SPI. It should be understood that the JTAG circuit 021 in the first loading circuit 02 may further include a data register (DR) 021d, and the IR 021b can configure the DR 021d according to the received loading instruction. The channel selection circuit 023 can then conduct the first SPI and the third SPI based on the configuration in the DR 021d. It should also be understood that the IR 021b can also generate a control signal by combining the internal state of the JTAG circuit 021 through a logic circuit (such as an AND gate and an OR gate, etc.) to control the channel selection circuit 023 to conduct the first SPI and the third SPI.

[0075] Refer toFigure 5 It can also be seen that the JTAG circuit 021 can further include two MUXs. The IR 021b, instruction decoder 021c, bypass register 021d1, identification code register 021d2 in the JTAG circuit 021, and the MISO pin in the first SPI can be connected to the TDO pin through the two MUXs.

[0076] As an alternative implementation, the number of the first loading circuits 02 included in the loading system can be greater than 1, that is, x can be greater than 1. In this scenario, the controller 01 can perform parallel loading on the x first loading circuits 02. Correspondingly, the loading instructions sent by the controller 01 to the JTAG circuits 021 in the first x - 1 first loading circuits 02 can be parallel loading instructions. The JTAG circuit 021 that receives the parallel loading instruction can also be used to connect the TDI pin and the TDO pin according to the parallel loading instruction, so that the TDI signal received through the TDI pin can be directly transmitted through the TDO pin to the next first loading circuit 02. Among them, the TDI signal can include the instruction sent by the controller and the data to be loaded.

[0077] Exemplarily, as Figure 5 and Figure 6 shown, the DR 021d can include a bypass register 021d1 and an identification code register 021d2 that are respectively connected to the TDI pin and the TDO pin. The identification code register 021d2 is used to store the identification code of the first loading circuit 02, and the identification code is used to uniquely identify the first loading circuit 02. The bypass register 021d1 is used to connect the TDI pin and the TDO pin in response to the parallel loading instruction after the IR 021b receives the parallel loading instruction, so as to realize the direct transmission of the TDI signal while loading data into the SPI flash memory. Figure 6 The thick black line in the figure indicates the transmission path of the TDI signal in the first loading circuit 02.

[0078] As another alternative implementation, as Figure 1 shown, only one first loading circuit 02 can be included in the loading system, that is, x = 1. In this scenario, the TDI pin of the first loading circuit 02 is directly connected to the TDI pin of the JTAG interface of the controller 01, and the TDO pin is directly connected to the TDO pin of the JTAG interface of the controller 01. Therefore, there is no delay in the TDI signal transmitted by the controller 01 to the TDI pin of the first loading circuit 02, and there is also no delay in the TDO signal transmitted by the TDO pin of the first loading circuit 02 to the controller 01. Therefore, the stage at which the target CS signal is at the valid level can be directly determined by referring to the stage at which the TAP controller 021a is in the shift DR state.

[0079] Correspondingly, as Figure 3 shown, at the first target jump edge of the TCK pin after the TAP controller 021a is in the shift DR state, the level of the target CS signal provided to the CS pin jumps from an invalid level to a valid level. At the first target jump edge of the TCK pin after the TAP controller 021a ends the DR state, the level of the target CS signal provided to the CS pin jumps from a valid level to an invalid level. Among them, the target jump edge is a rising edge or a falling edge.

[0080] And, referring to Figure 7 it can be seen that in this scenario, the bypass register 021d1 does not connect the TDI pin to the TDO pin. Figure 7 The bold black lines in Figure 7 indicate the data transmission path in the first loading circuit 02. Referring to

[0081] For example, assume Figure 3 that in the timing of each pin shown, the valid level is a low level, then the target jump edge can be a falling edge. Referring to Figure 3 , at the first falling edge of the TCK pin after the TAP controller 021a is in the shift DR state, the target CS signal provided by the TAP controller 021a to the CS pin jumps from a high level to a low level. At the first falling edge of the TCK pin after the TAP controller 021a ends the DR state, the level of the target CS signal provided by the TAP controller 021a to the CS pin jumps from a low level to a high level.

[0082] In the embodiment of the present application, the target CS signal can be provided by the JTAG circuit 021 to the CS pin. That is, the JTAG circuit 021 can provide the target CS signal to the CS pin according to the state of the TAP controller 021a and the level of the TCK pin.

[0083] Or, as Figures 5 to 7As shown, the first loading circuit 02 may further include a timing conversion circuit 024. The TAP controller 021a is connected to the CS pin through the timing conversion circuit 024, and the target CS signal may be provided to the CS pin by the timing conversion circuit 024. That is, the timing conversion circuit 024 may provide the target CS signal to the CS pin according to the state of the TAP controller 021a and the level of the TCK pin.

[0084] For example, the timing conversion circuit 024 may adjust the level of the target CS signal provided to the CS pin from high level to low level at the first falling edge of the TCK pin after the TAP controller 021a is in the shift DR state. At the first falling edge of the TCK pin after the TAP controller 021a ends the DR state, the level of the target CS signal provided to the CS pin is adjusted from low level to high level.

[0085] Figure 8 It is a schematic structural diagram of another loading system provided by an embodiment of the present application. As Figure 8 shown, the loading system may further include: n second loading circuits 04 connected in series between the TDI pin of the JTAG interface of the controller 01 and the TDI pin of the first loading circuit 02, and / or, m third loading circuits 05 connected in series between the TDO pin of the first loading circuit 02 and the TDO pin of the JTAG interface of the controller 01. Wherein, each second loading circuit 04 is correspondingly connected to an SPI flash memory 03, and each third loading circuit 05 is correspondingly connected to an SPI flash memory 03, and both n and m are positive integers. For example, in Figure 8 the system shown, both n and m are integers greater than 1.

[0086] The JTAG circuit 021 of the first loading circuit 02 may be used to provide an initial CS signal to the timing conversion circuit 024. Referring to Figure 9 , at the first target jump edge of the TCK pin after the TAP controller 021a is in the shift DR state, the level of the initial CS signal is adjusted from an invalid level to a valid level. At the first target jump edge of the TCK pin after the TAP controller 021a ends the shift DR state, the level of the initial CS signal is adjusted from a valid level to an invalid level, and the target jump edge is a rising edge or a falling edge.

[0087] The timing conversion circuit 024 is used to perform timing conversion on the initial CS signal to obtain a target CS signal and provide the target CS signal to the CS pin. The timing conversion circuit 024 may implement the timing conversion of the initial CS signal through logic circuits such as a counter or a state machine.

[0088] Among them, for the scenario where n second loading circuits 04 are connected in series between the TDI pin of the controller 01 and the first loading circuit 02, the moment when the level of the target CS signal received by the CS pin of the first SPI in the loading circuit 02 jumps from the invalid level to the valid level can be delayed by n clock cycles relative to the moment when the initial CS signal jumps from the invalid level to the valid level.

[0089] n second loading circuits 04 are connected in series between the TDI pin of the first loading circuit 02 and the TDI pin of the JTAG interface of the controller 01. Each of the second loading circuits 04 can enter the bypass state under the instruction of the controller 01 to transparently transmit the TDI signal sent by the controller 01. Moreover, the time required for each second loading circuit 04 to transparently transmit the TDI signal is one clock cycle. Therefore, the TDI signal sent by the controller 01 needs to pass through n clock cycles before it can be transmitted to the first loading circuit 02. Correspondingly, the timing conversion circuit 021 in the first loading circuit 02 can delay the moment when the level of the initial CS signal jumps from the invalid level to the valid level by n clock cycles and then provide it to the CS pin.

[0090] Optionally, referring to Figure 6 and Figure 7 , the first loading circuit 02 may further include a first configuration register 025 connected to the timing conversion circuit 024. A first value for indicating the n is configured in the first configuration register 025. Among them, as Figure 6 and Figure 7 shown, the first configuration register 025 may be a register in the DR 021d of the JTAG circuit 021. And the first value may be configured by the controller 01. Alternatively, the first configuration register 025 may also be a register independent of the JTAG circuit 021. For example, the first configuration register 025 may be connected to an inter-integrated circuit (I2C) interface, and the first value may be configured through the I2C interface.

[0091] The timing conversion circuit 024 is used to delay the moment when the initial CS signal jumps from the invalid level to the valid level by n clock cycles according to the first value.

[0092] For the scenario where m third loading circuits 05 are connected in series between the TDO pin of the first loading circuit 02 and the controller 01, the moment when the level of the target CS signal received by the CS pin of the first SPI in the loading circuit 02 jumps from the valid level to the invalid level can be advanced by m clock cycles relative to the moment when the initial CS signal jumps from the valid level to the invalid level.

[0093] Since m third loading circuits 05 are connected in series between the TDO pin of the first loading circuit 02 and the TDO pin of the JTAG interface of the controller 01, and each third loading circuit 05 can enter a bypass state under the instruction of the controller 01 to transparently transmit the TDO signal sent by the first loading circuit 02. Moreover, the time required for each third loading circuit 05 to transparently transmit the TDO signal is one clock cycle. Therefore, the TDO signal sent by the TDO pin of the first loading circuit 02 needs to pass through m clock cycles before it can be transmitted to the controller 01. Correspondingly, the timing conversion circuit 021 in the first loading circuit 02 can advance the moment when the level of the initial CS signal jumps from the valid level to the invalid level by m clock cycles and provide it to the CS pin.

[0094] Optionally, the first configuration register 025 may also be configured with a second value for indicating the duration of the target CS signal at the valid level. The timing conversion circuit 024 is configured to advance the moment when the initial CS signal jumps from the valid level to the invalid level by m clock cycles according to the second value.

[0095] Wherein, the second value may be configured by the controller 01. And since the JTAG circuit 021 can write or read data when the CS signal is at the valid level, the duration of the target CS signal at the valid level may be determined by the controller according to the lengths of the data to be loaded and the data to be read.

[0096] Figure 10 It is a schematic structural diagram of another loading system provided by an embodiment of the present application. As Figure 10 shown, the loading system may include: x first loading circuits 02 connected in series. Moreover, the loading system may further include: n - x + 1 second loading circuits 04 connected in series between the TDI pin of the JTAG interface of the controller 01 and the x first loading circuits 02, and / or, m third loading circuits 05 connected in series between the x first loading circuits 02 and the TDO pin of the JTAG interface of the controller 01. Wherein, x is an integer greater than 1 and less than n + 1, and both n and m are positive integers.

[0097] If the loading system includes m third loading circuits 05, then since there is no need to read data when loading the SPI flash memory, the delay caused by the m third loading circuits 05 transparently transmitting the TDO signal does not need to be considered.

[0098] In this scenario, as an alternative implementation, among the x first loading circuits 02, the number of clock cycles delayed by the timing conversion circuit 024 in each first loading circuit 02 at the moment when the initial CS signal jumps from an invalid level to a valid level can be equal to the number of loading circuits before this first loading circuit 02. The number of clock cycles advanced by the timing conversion circuit 024 in each first loading circuit 02 at the moment when the initial CS signal jumps from a valid level to an invalid level can be equal to the number of first loading circuits after this first loading circuit 02.

[0099] For example, since there are n - x + 1 second loading circuits 04 connected in series between the first first loading circuit 02 and the controller 01, and there are x - 1 first loading circuits 02 connected in series after the first first loading circuit 02. Therefore, referring to Figure 11 , the moment when the target chip select signal provided by the timing conversion circuit 024 in the first first loading circuit 02 jumps from a high level to a low level to the CS pin of the first SPI is delayed by n - x + 1 clock cycles relative to the moment when the initial CS signal jumps from a high level to a low level. And, the moment when the target chip select signal provided by the timing conversion circuit 024 to the CS pin of the first SPI jumps from a low level to a high level is advanced by x - 1 clock cycles relative to the moment when the initial CS signal jumps from a low level to a high level.

[0100] Since before the x-th first loading circuit 02, there are: x - 1 first loading circuits 01 and n - x + 1 second loading circuits 04, that is, there are n loading circuits before the x-th first loading circuit 02, and there are no other first loading circuits connected in series after the x-th first loading circuit 02. Therefore, referring to Figure 11 , the moment when the target chip select signal provided by the timing conversion circuit 024 in the x-th first loading circuit 02 jumps from a high level to a low level to the CS pin of the first SPI is delayed by n clock cycles relative to the moment when the initial CS signal jumps from a high level to a low level. And, the moment when the target chip select signal provided by the timing conversion circuit 024 to the CS pin of the first SPI jumps from a low level to a high level does not need to be advanced relative to the moment when the initial CS signal jumps from a low level to a high level.

[0101] In this scenario, as another alternative implementation, among the x first loading circuits 02, the timing conversion circuit 024 in each first loading circuit 02 can send the initial chip select signal to the CS pin after delaying it by n clock cycles. And, the number of clock cycles advanced by the timing conversion circuit 024 in each first loading circuit 02 at the moment when the initial CS signal jumps from a valid level to an invalid level can all be equal to 0, that is, there is no need to advance the moment when the initial CS signal jumps from a valid level to an invalid level.

[0102] Moreover, in the x first loading circuits 02, the timing conversion circuit 024 in the (x - i)-th first loading circuit 02 can also be used to delay the TDI signal provided by the TDI pin by i clock cycles and then provide it to the MOSI pin. Here, i is a positive integer less than x. And the timing conversion circuit 024 in the x-th first loading circuit 02 does not need to delay the TDI signal provided by the TDI pin. Thus, the x first loading circuits 02 can load data into the SPI flash 03 simultaneously.

[0103] Exemplarily, referring to Figure 12 , the moments when the target chip select signal provided by the timing conversion circuit 024 in the first first loading circuit 02 and the timing conversion circuit 024 in the x-th first loading circuit 02 jumps from high level to low level with respect to the CS pin in the first SPI are both delayed by n clock cycles compared to the moment when the initial CS signal jumps from high level to low level. And for the first first loading circuit 02, its timing conversion circuit 024 can delay the TDI signal received by the TDI pin: TDI_1 by x - 1 clock cycles and then provide it to the MOSI_1 of the first SPI. For the x-th first loading circuit 02, its timing conversion circuit 024 does not need to delay the TDI signal provided by the TDI pin.

[0104] Optionally, as shown in Figure 6 and Figure 7 , in the x first loading circuits 02, the (x - i)-th first loading circuit 02 may further include: a second configuration register 026 connected to the timing conversion circuit 024, and a third value for indicating i is configured in the second configuration register 026. Here, as shown in Figure 6 and Figure 7 , the second configuration register 026 may be a register in the DR 021d of the JTAG circuit 021. And the second value may be configured by the controller 01. Alternatively, the second configuration register 026 may also be a register independent of the JTAG circuit 021. For example, the second configuration register 026 may be connected to the I2C interface, and the first value may be configured through the I2C interface.

[0105] The timing conversion circuit 024 in the (x - i)-th first loading circuit 02 can be used to delay the TDI signal provided by the TDI pin by i clock cycles and then provide it to the MOSI pin according to the third value.

[0106] In summary, the embodiment of the present application provides a loading circuit. The loading circuit includes a JTAG circuit and a channel selection circuit. The channel selection circuit has a first SPI, a second SPI, and a third SPI. The third SPI is used to connect to an SPI flash memory. Since each pin of the JTAG circuit can be correspondingly connected to each pin of the first SPI, and the JTAG circuit can control the first SPI and the third SPI to conduct, communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can be connected to the JTAG circuit in the loading circuit through the JTAG interface, and when the first SPI and the third SPI in the channel selection circuit are conducting, data can be loaded into the SPI flash memory, thereby realizing out-of-band upgrade of the firmware stored in the SPI flash memory.

[0107] Moreover, for the scenario where the loading circuit is one of multiple cascaded loading circuits in a loading system, the timing conversion circuit in the loading circuit can delay and / or advance the moment when the level of the target CS signal provided to the CS pin jumps from an invalid level to a valid level by several clock cycles. Thus, the controller can realize the loading of the SPI flash memory connected to any one of the multiple cascaded loading circuits, effectively improving the flexibility of loading.

[0108] Also, since the loading circuit can connect the TDI pin and the TDO pin after receiving a parallel loading instruction, TDI signal can be transparently transmitted while loading data into the SPI flash memory, thereby ensuring that the controller can perform parallel loading on multiple cascaded loading circuits, improving the loading efficiency. And the timing conversion circuit in the loading circuit can also delay the TDI signal provided by the TDI pin by i clock cycles and then provide it to the MOSI pin, so that multiple loading circuits can load data into the SPI flash memory simultaneously during the parallel loading process.

[0109] The embodiment of the present application also provides a loading method. This method can be applied to the loading circuit provided in the above embodiment, for example, it can be applied to the first loading circuit 02 shown in any one of the Figure 2 , and Figures 5 to 7 any one of the attached drawings. The following takes the application of this loading method to the first loading circuit 02 as an example for illustration. As Figure 13 shown, this method may include:

[0110] Step 101, receive a loading instruction sent by the controller.

[0111] In the embodiment of the present application, when it is necessary to upgrade the firmware stored in the SPI flash memory by means of out-of-band upgrade, the controller can send a loading instruction to the first loading circuit connected to the SPI flash memory.

[0112] Step 102: According to the loading instruction, conduct the first SPI and the third SPI of the channel selection circuit in the first loading circuit.

[0113] The JTAG circuit in the loading circuit can respond to the loading instruction issued by the controller and control the channel selection circuit to conduct the first SPI and the third SPI.

[0114] Step 103: After the TAP controller in the first loading circuit is in the shift DR state, adjust the level of the target CS signal provided to the CS pin of the first SPI from the invalid level to the valid level.

[0115] In the embodiment of the present application, the target CS signal can be provided by the JTAG circuit in the loading circuit. Alternatively, the loading circuit may include a timing conversion circuit, and the target CS signal can be provided by the timing conversion circuit.

[0116] As an optional implementation, refer to Figure 1 or Figure 6 , the loading system may only include one first loading circuit 02. In this implementation, the loading circuit 02 can respond to the loading instruction and only conduct the first SPI and the third SPI.

[0117] As another optional implementation, refer to Figure 8 , the loading system may include x first loading circuits 02, and x is greater than 1. In this implementation, the controller 01 can perform parallel loading on the x first loading circuits 02, that is, the loading instruction is a parallel loading instruction. Correspondingly, the first loading circuit can also respond to the parallel loading instruction and connect the TDI pin and the TDO pin of the JTAG circuit. Thus, the TDI signal can be transparently transmitted while loading data into the SPI flash memory, and further ensure that the controller can perform parallel loading on multiple series-connected first loading circuits, improving the loading efficiency.

[0118] For the scenario where the loading system only includes one first loading circuit 02, the implementation process of step 103 may include:

[0119] At the first target jump edge of the TCK pin after the TAP controller 021a in the first loading circuit 02 is in the shift DR state, adjust the level of the target CS signal provided to the CS pin from the invalid level to the valid level.

[0120] And, refer to Figure 10 , the method may further include:

[0121] Step 104a: At the first target jump edge of the TCK pin after the TAP controller in the first loading circuit finishes shifting the DR state, adjust the level of the target CS signal provided to the CS pin from the active level to the inactive level.

[0122] Among them, the target jump edge can be a rising edge or a falling edge, the active level of the target CS signal received by the CS pin can be a low level, and the inactive level can be a high level.

[0123] For the scenario where there are n second loading circuits connected in series between the controller and the TDI pin of the first loading circuit in the loading system, the implementation process of step 103 can include:

[0124] At the nth target jump edge of the TCK pin after the TAP controller in the loading circuit is in the shift DR state, adjust the level of the target CS signal provided to the CS pin from the inactive level to the active level.

[0125] Since the TDI signal sent by the controller needs n clock cycles to be transmitted to the first loading circuit, the timing conversion circuit in the first loading circuit can delay the moment when the level of the initial CS signal jumps from the inactive level to the active level by n clock cycles and then provide it to the CS pin.

[0126] For the scenario where there are m third loading circuits connected in series between the TDO pin of the first loading circuit and the controller in the loading system, refer to Figure 10 , the method can further include:

[0127] Step 104b: At the mth target jump edge of the TCK pin before the TAP controller in the loading circuit finishes shifting the DR state, the level of the target CS signal provided to the CS pin jumps from the active level to the inactive level.

[0128] Since the TDO signal sent by the TDO pin of the first loading circuit needs m clock cycles to be transmitted to the controller, the timing conversion circuit in the first loading circuit can advance the moment when the level of the initial CS signal jumps from the active level to the inactive level by m clock cycles and then provide it to the CS pin. Among them, both n and m are positive integers.

[0129] For the scenario where the loading system includes x first loading circuits and x > 1, as Figure 10 shown, the method that the ith first loading circuit among the x first loading circuits executes can further include:

[0130] Step 105: Delay the TDI signal provided by the TDI pin in the first loading circuit by i clock cycles and then provide it to the MOSI pin of the first SPI.

[0131] Among them, i is a positive integer less than x. When the loading system includes x first loading circuits connected in series, the controller can perform parallel loading on these x first loading circuits. Among these x first loading circuits 02, the timing conversion circuit 024 in the (x - i)-th first loading circuit 02 can also be used to delay the TDI signal provided by the TDI pin by i clock cycles and then provide it to the MOSI pin. And the timing conversion circuit 024 in the x-th first loading circuit 02 does not need to delay the TDI signal provided by the TDI pin. Thus, it can be made that these x first loading circuits 02 can load data into the SPI flash 03 simultaneously.

[0132] In summary, the embodiment of the present application provides a loading method, which can be applied to the loading circuit provided in the above embodiment. The loading circuit includes a JTAG circuit and a channel selection circuit. The channel selection circuit has a first SPI, a second SPI, and a third SPI, and the third SPI is used to connect to the SPI flash. Since each pin of the JTAG circuit can be correspondingly connected to each pin of the first SPI, and the loading circuit can receive a loading instruction issued by the controller and conduct the first SPI and the third SPI according to the loading instruction, communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can load data into the SPI flash when the first SPI and the third SPI in the channel selection circuit are conducted, thereby realizing out-of-band upgrade of the firmware stored in the SPI flash.

[0133] Moreover, for the scenario where the loading circuit is one of multiple series-connected loading circuits in the loading system, the timing conversion circuit in the loading circuit can delay and / or advance the moment when the level of the target CS signal provided to the CS pin jumps from an invalid level to a valid level by several clock cycles. Thus, the controller can realize the loading of the SPI flash connected to any one of the multiple series-connected loading circuits, effectively improving the flexibility of loading.

[0134] Also, since the loading circuit can connect the TDI pin and the TDO pin after receiving a parallel loading instruction, it can thus realize the transparent transmission of the TDI signal while loading data into the SPI flash, and further ensure that the controller can perform parallel loading on multiple series-connected loading circuits, improving the loading efficiency. And the timing conversion circuit in the loading circuit can also delay the TDI signal provided by the TDI pin by i clock cycles and then provide it to the MOSI pin, so that multiple loading circuits can load data into the SPI flash simultaneously during the parallel loading process.

[0135] The embodiment of the present application also provides a loading system. Refer to Figure 1 and Figure 14, the loading system may include: a controller 01, x first loading circuits 02, and x SPI flash memories 03, where x is a positive integer. Each of the first loading circuits 02 may be the loading circuit provided in the above embodiments. For example, Figure 1 Figure 1 schematically shows a first loading circuit 02 and an SPI flash memory 03 (i.e., x = 1). It should be understood that if x is greater than 1, the x first loading circuits 02 may be connected in series.

[0136] The controller 01 may be connected to the JTAG circuit 021 in each of the first loading circuits 02 through a JTAG interface, and each SPI flash memory 03 is connected to the third SPI of the channel selection circuit 023 in one of the first loading circuits 02.

[0137] Referring to Figure 14 It can be seen that the first loading circuit 02 may include: a JTAG circuit 021, an SFC 022, and a channel selection circuit 023. The JTAG interface of the controller 01 may include: a TRST pin, a TCK pin, a TMS pin, a TDI pin, and a TDO pin. The controller 01 is connected to the JTAG circuit 021 in the first loading circuit 02 through the above pins of the JTAG interface, and the SPI flash memory 03 is connected to the third SPI of the channel selection circuit 023 in the first loading circuit 02.

[0138] The controller 01 is configured to send a loading instruction and data to the JTAG circuit 021. The loading instruction is used to instruct the JTAG circuit 021 to conduct the first SPI of the channel selection circuit 023 with the third SPI, and load the data to the SPI flash memory 03. Wherein, the controller 01 may be a BMC or a JTAG emulator.

[0139] Continuing to refer to Figure 14 , the controller 01 may send a TDI signal to the JTAG circuit 021 in the first loading circuit 02 through the TDI pin of the JTAG interface. Wherein, the TDI signal may include a loading instruction or data.

[0140] In the embodiments of the present application, a loading software may be configured in the controller 01, and the loading software may be a serial vector format (SVF) file parser. When the controller 01 needs to load the SPI flash memory 03, it may first parse and execute the SVF file through the loading software. Wherein, the SVF file may be obtained by converting the target binary file that needs to be loaded into the SPI flash memory 03. The process of the controller 01 loading the SPI flash memory 03 connected to the first loading circuit 02 may include the following steps:

[0141] 1. The controller 01 performs a de - reset on the first loading circuit 02. For example, the controller 01 can adjust the level of the TRST signal sent to the first loading circuit 02 to an invalid level. If the controller 01 is connected to multiple cascaded loading circuits including the first loading circuit 02, the controller 01 needs to perform a de - reset on all of these cascaded loading circuits. Among them, these multiple cascaded loading circuits can be called a JTAG chain.

[0142] 2. The controller 01 issues a configuration instruction to the first loading circuit 02 through an IR instruction. This configuration instruction is used to configure timing parameters. The timing conversion circuit 024 in the first loading circuit 02 can read these timing parameters to achieve the conversion from JTAG timing to SPI timing. By way of example, as Figure 14 shown, for the scenario where there are n second loading circuits 04 in series between the TDI pin of the controller 01 and the first loading circuit 02, and / or there can be m third loading circuits 05 in series between the TDO pin of the first loading circuit 02 and the controller 01, the timing parameters can include a first value for indicating n and a second value for indicating m.

[0143] 3. The controller 01 issues a loading instruction to the first loading circuit 02 through an IR instruction. This loading instruction is used to indicate to conduct the first SPI and the third SPI of the channel selection circuit 023.

[0144] 4. The controller 01 issues the data to be loaded to the first loading circuit 02 through a DR instruction, so as to load the SPI flash memory 03 connected to the first loading circuit 02.

[0145] The above process can be described by the following pseudo - process in SVF format:

[0146]

[0147] Among them, the detailed syntax of the SVF file can refer to the serial vector format specification. Since the erasing process of the SPI flash memory 03 takes a certain amount of time, it can be seen from the above pseudo - process that after the first loading circuit 02 executes the erase instruction, it needs to wait for k ms in response to the wait instruction. The k can be a positive number, and the value of k can be set according to the duration required to clear the storage space of the SPI flash memory 03.

[0148] For Figure 1Taking the loading system including only one first loading circuit 02 as an example, the process of the controller 01 loading the SPI flash memory 03 connected to the first loading circuit 02 will be described. Assume that the length of the IR 021a in the JTAG circuit 021 is 4 bits (bit), the instruction length of the SPI flash memory 03 is 8 bits, and the address length of the SPI flash memory 03 is 3 bytes (byte), that is, 24 bits. If the loading instruction is defined as the hexadecimal number: 3, the erase instruction is defined as the hexadecimal number: C7, and the programming instruction is defined as the hexadecimal number: 02. Then when the controller 01 loads the SPI flash memory 03 connected to the first loading circuit 02, the executed SVF file can be:

[0149]

[0150] Since the SVF file parser configured in the controller 01 reads the instructions in the SVF file from the low bit to the high bit, the order of the high and low bits of the instruction value configured in the SVF file is opposite to that of the actual instruction. For example, if the loading instruction is defined as the hexadecimal number: 3 (binary representation: 0011), then since the arrangement order of this loading instruction from the low bit to the high bit is: 1100 (hexadecimal representation: c), the instruction value of the loading instruction in this SVF file is c. The erase instruction is defined as the hexadecimal number: C7 (binary representation: 11000111), and since the arrangement order of this erase instruction from the low bit to the high bit is: 11100011 (hexadecimal representation: e3), the instruction value of the erase instruction in this SVF file is e3.

[0151] When executing the programming instruction to write the data to be loaded: ff5a to the 0 address, since the programming instruction is defined as the hexadecimal number: 02 (binary representation: 00000010), and its arrangement order from the low bit to the high bit is: 01000000 (hexadecimal representation: 40), the last two bits of the TDI signal "5aff00000040" used to write the data to be loaded: ff5a are 40. Also, since the address length of the SPI flash memory 03 is 3 bytes (24 bits), the 0000000 in the middle of this TDI signal "5aff00000040" represents the 0 address with a length of 3 bytes. Also, since the data to be loaded ff5a binary representation is: 1111111101011010, and its arrangement order from the low bit to the high bit is: 0101101011111111 (that is, the hexadecimal number: 5aff), the first four bits of this TDI signal "5aff00000040" are 5aff.

[0152] It should be understood that the above SVF file is described by taking a loading system that only includes a first loading circuit 02 (i.e., x = 1) as an example. Therefore, the controller 01 does not need to issue a configuration instruction to the first loading circuit 02 to configure the timing parameters.

[0153] Optionally, for the scenario where the loading system only includes a first loading circuit 02, as Figure 14 shown, the loading system may further include: n second loading circuits 04 connected in series between the TDI pin of the JTAG interface of the controller 01 and the first loading circuit 02, where n is a positive integer. The controller 01 may also be used to send a first configuration instruction to the first loading circuit 02, and the first configuration instruction is used to indicate configuring a first value for indicating n in the first configuration register 025 of the first loading circuit 02.

[0154] Refer to Figure 9 , the timing conversion circuit 024 in the first loading circuit 02 may determine the value of n according to the first value, and delay the moment when the target chip select signal provided to the CS pin in the first SPI changes from high level to low level by n clock cycles relative to the moment when the initial CS signal changes from high level to low level.

[0155] Optionally, for the scenario where the loading system only includes a first loading circuit 02, as Figure 14 shown, the loading system may further include: m third loading circuits 05 connected in series between the TDO pin of the first loading circuit 02 and the controller 01, where m is a positive integer. The controller 01 is further used to determine the duration when the target CS signal is at the valid level according to the number m of the third loading circuits 04, and send a second configuration instruction to the first loading circuit 02, and the second configuration instruction is also used to indicate configuring a second value for indicating the duration when the target CS signal is at the valid level in the first configuration register 025.

[0156] Refer to Figure 9 , the timing conversion circuit 024 in the first loading circuit 02 may determine the value of m according to the second value, and advance the moment when the target chip select signal provided to the CS pin in the first SPI changes from low level to high level by m clock cycles relative to the moment when the initial CS signal changes from low level to high level.

[0157] In the above scenario, when the controller 01 loads the SPI flash memory 03 connected to the first loading circuit 02, the n second loading circuits 04 and the m third loading circuits 05 may both be adjusted to the bypass state, as Figure 15As shown, the n second loading circuits 04 are equivalent to n bypass registers, and the m third loading circuits 05 are equivalent to m bypass registers. The n bypass registers only pass through the TDI signal sent by the controller 01, and the m bypass registers only pass through the TDO signal sent by the first loading circuit 02. Among them, each bypass register takes 1 clock cycle to pass through the TDI or TDO signal. It should be understood that the first loading circuit 02 can also load the data to be loaded during the transmission of the TDI signal, and the loading duration is j clock cycles, and the value of j is determined by the length of the data to be loaded.

[0158] Since the TDI signal sent by the controller 01 needs to pass through n clock cycles to reach the first loading circuit 02, and the TDO signal sent by the first loading circuit 02 needs to pass through m clock cycles to reach the controller 01, and the first loading circuit 02, each second loading circuit 04, and each third loading circuit 05 all perform state transitions under the same TCK signal and TMS signal sent by the controller 01, this will cause the data signals (including the TDI signal and the TDO signal) to be out of sync with the control signals (including the TCK signal and the TMS signal).

[0159] In the embodiment of the present application, the controller 01 can send a first configuration instruction and a second configuration instruction to the first loading circuit 02 to configure timing parameters (including the first value and the second value) in the first configuration register of the first loading circuit 02. The timing conversion circuit 024 in the first loading circuit 02 can adjust the timing of the initial CS signal to obtain the target CS signal by reading the timing parameters, so as to achieve the synchronization of the data signal and the control signal.

[0160] The following takes a loading system in which 2 second loading circuits 04 are connected in series between the TDI pin of the controller 01 and the first loading circuit 02, and 2 third loading circuits 05 are connected in series between the TDO pin of the first loading circuit 02 and the controller 01 as an example, that is, n = m = 2, to illustrate the process of the controller 01 loading the SPI flash memory 03 connected to the first loading circuit 02. Assume that the length of the IR in each loading circuit is 4 bits, the instruction length of the SPI flash memory 03 is 8 bits, and the address length of the SPI flash memory 03 is 3 bytes (i.e., 24 bits). If the select instruction is defined as the hexadecimal number: 2, the first configuration instruction is defined as the hexadecimal number: 02, the loading instruction is defined as the hexadecimal number: 3, the bypass instruction is defined as the hexadecimal number: f, the erase instruction is defined as the hexadecimal number: C7, and the programming instruction is defined as the hexadecimal number 02. Then when the controller 01 loads the SPI flash memory 03 connected to the first loading circuit 02, the executed SVF file can be:

[0161]

[0162] Since the loading system includes a total of 5 loading circuits, the controller 01 can adjust 2 second loading circuits 04 and 2 third loading circuits 05 except the first loading circuit 02 to the bypass state. Also, since the 5 loading circuits are connected in series, when the controller 01 issues a loading instruction: 3 to the first loading circuit 02, it issues a bypass instruction: f to the 2 second loading circuits 04 and 2 third loading circuits 05. Therefore, the instruction issued by the controller 01 can be: ffcff.

[0163] When issuing a first configuration instruction: 02 to the first configuration register 025 in the first loading circuit 02, the configuration instruction value in the SVF file is a hexadecimal number: 100, the instruction value length is 10 bits, and its binary representation is: 0100000000. Since there are 2 second loading circuits 04 before the first loading circuit 02, for the first configuration register 025 in the first loading circuit 02, the actually read instruction value is the high 8 bits of 0100000000: 01000000. Among them, the SVF file parser reads the instructions in the SVF file from the low bit to the high bit. 01000000 is read from the low bit to the high bit as: 00000010 (which is the hexadecimal number: 02).

[0164] Similarly, when the controller 01 issues an erase instruction: C7 to the SPI flash 03 connected to the first loading circuit 02, the instruction value of the erase instruction in the SVF file is a hexadecimal number: 38c, the instruction value length is 10 bits, and the binary representation is: 1110001100. Since there are 2 second loading circuits 04 before the first loading circuit 02, for the SPI flash 03 connected to the first loading circuit 02, the actually read instruction value is the high 8 bits of 1110001100: 11100011. Among them, the SVF file parser reads the instructions in the SVF file from the low bit to the high bit. 11100011 is read from the low bit to the high bit as: 11000111 (which is the hexadecimal number: C7).

[0165] The TDI signal used to write the data ff5a to be loaded into the SPI flash memory 03 is represented as: 16bfc00000100, with a length of 50 bits. In binary representation, it is: 01011010111111110000000000000000000000000100000000. Among them, since there are 2 second loading circuits 04 before the first loading circuit 02, the TDI signal needs to be delayed by 2 clock cycles. Therefore, the lowest 2 bits of the TDI signal are: 00. Also, since the programming instruction is defined as the hexadecimal number: 02 (binary representation: 00000010), and its arrangement order from low to high is: 01000000, the 3rd bit to the 10th bit of the TDI signal from low to high are: 01000000. Moreover, since the address length of the SPI flash memory 03 is 3 bytes (24 bits), the "000000000000000000000000" of the 11th bit to the 34th bit of this TDI signal from low to high represents the 0 address with a length of 3 bytes. Additionally, since the data ff5a to be loaded is represented in binary as: 1111111101011010, and its arrangement order from low to high is: 0101101011111111, the highest 16 bits of this TDI signal are: 0101101011111111.

[0166] Optionally, the loading system may include multiple first loading circuits 02 connected in series (i.e., x > 1). Refer to Figure 10 , the loading system may further include: n - x + 1 second loading circuits 04 connected in series between the TDI pin of the JTAG interface of the controller 01 and the x first loading circuits 02, where n is a positive integer and x is an integer not greater than n + 1.

[0167] If the data to be loaded in the SPI flash memories 03 connected by the x first loading circuits 02 is the same, the controller 01 can perform parallel loading on the SPI flash memories 03 connected by the x first loading circuits 02, thereby improving the loading efficiency.

[0168] The loading of the SPI flash memory 03 may include 3 steps: 1. Erasing; 2. Programming; 3. Verifying. Among them, both erasing and programming are one-way operations and do not require reading the data returned by the SPI flash memory 03. Since these two steps take a relatively long time, the erasing and programming steps can be executed in parallel, thereby saving the time spent on loading the SPI flash memory 03.

[0169] For example, assume that the erasing step takes 3 minutes, the programming step takes 1 minute, and the verification step takes 1 minute. If the loading system includes 8 first loading circuits 02 (i.e., x = 8), the time taken for serial loading of the SPI flash memory 03 connected to each first loading circuit 02 is: (3 + 1 + 1) * 8 = 40 minutes. If parallel loading is performed on the SPI flash memories 03 connected to the 8 first loading circuits 02, the time taken is: 3 + 1 + 1 * 8 = 12 minutes. It can be seen that the loading time is reduced by 70%, significantly improving the loading efficiency.

[0170] When performing parallel loading, the controller 01 can send parallel loading instructions to the x first loading circuits 02 respectively. The parallel loading instructions are used to instruct the first to (x - 1) first loading circuits 02 among the x first loading circuits 02 to connect the TDI pin and the TDO pin of their JTAG circuits 021. Refer to Figure 6 , the bypass register 021d1 in the first loading circuit 02 can respond to the parallel loading instruction and connect the TDI pin and the TDO pin of the JTAG circuit 021 to achieve transparent transmission of the TDI signal.

[0171] Refer to Figure 6 the thick black lines in. The transmission path of the data to be loaded sent by the controller 01 in each of the first to (x - 1) first loading circuits 02 includes two paths:

[0172] Path 1: TDI pin → bypass register 021d1 → TDO pin;

[0173] Path 2: TDI pin → timing conversion circuit 024 → channel selection circuit 023 → SPI flash memory 03.

[0174] Among them, Path 1 can transmit the data to be loaded to the next first loading circuit 02. The above Path 2 can achieve writing data to the SPI flash memory 03.

[0175] As Figure 16 shown, in the scenario of this parallel loading, the first to (x - 1) first loading circuits 02 in the loading system can all transparently transmit the data to be loaded sent by the controller 01 through the bypass register, and each transparent transmission takes 1 clock cycle. Moreover, each of the x first loading circuits 02 can load the data to be loaded, and the loading duration is j clock cycles. The value of j is determined by the length of the data to be loaded.

[0176] It can be understood that, in the embodiment of the present application, the x-th first loading circuit 02 can also respond to the parallel loading instruction to connect the TDI pin and the TDO pin of the JTAG circuit 021, so as to realize the transparent transmission of the TDI signal.

[0177] For the scenario where the loading system includes x serially connected first loading circuits 02, and there are n - x + 1 second loading circuits 04 connected in series between the TDI pin of the controller 01 and the x first loading circuits 02, the process of the controller 01 performing parallel loading on the x first loading circuits 02 can be described by the following pseudo - process in SVF format:

[0178]

[0179] "Valid data" refers to the data stream formed by the combination of programming instructions and data to be loaded, and "M + N" represents the length of the data stream. Wherein, M represents the length of the data to be loaded, for example, it can be: 2048; N represents the length of the programming instruction.

[0180] Taking the loading system including 3 serially connected first loading circuits 02, and there is 1 second loading circuit 04 connected in series between the TDI pin of the JTAG interface of the controller 01 and the 3 first loading circuits 02, and there is 1 third loading circuit 05 connected in series between the TDI pin of the first loading circuit 02 and the controller 01 as an example, that is, taking x = n = 3 and m = 1 as an example, the process of the controller 01 performing parallel loading on the SPI flash memory 03 connected to the 3 first loading circuits 02 is described. Assume that the length of the IR in each loading circuit is 4 bits, the length of the first configuration register 025 is 8 bits, the address length of the SPI flash memory 03 is 3 bytes (i.e., 24 bits), and the instruction length of the SPI flash memory 03 is 8 bits. If the select instruction is defined as the hexadecimal number: 2, the first configuration instruction is defined as the hexadecimal number 02, the parallel loading instruction is defined as the hexadecimal number 4, the bypass instruction is defined as the hexadecimal number f, the erase instruction is defined as the hexadecimal number C7, and the programming instruction is defined as the hexadecimal number 02. Then when the controller 01 loads data to the SPI flash memory 03 connected to the first loading circuit 02, the SVF file that can be executed is:

[0181]

[0182] Among them, since the parallel loading instruction is defined as the hexadecimal number: 4 (binary representation: 0100), and since the arrangement order of the parallel loading instruction from low to high is: 0010 (hexadecimal representation: 2), the loading instruction in the SVF file can be f222f, and the controller 01 can issue the parallel loading instruction 4 to the 3 first loading circuits 02 based on this SVF file.

[0183] When issuing the first configuration instruction: 02 to the first configuration register in the three first loading circuits 02, the configuration instruction value in the SVF file is the hexadecimal number: 0808080, the instruction value length is 25 bits, and its binary representation is: 0100000001000000010000000. Since there is one second loading circuit 04 before the three first loading circuits 02, for the first configuration register 025 in the three first loading circuits 02, the actually read instruction value is the high 24 bits of 0100000001000000010000000: 010000000100000001000000. Among them, the SVF file parser reads the instructions in the SVF file from the low bit to the high bit, and 010000000100000001000000 is read from the low bit to the high bit as: 000000100000001000000010 (which is the hexadecimal number: 020202), so that the first configuration instruction: 02 can be issued to the first configuration registers in the three first loading circuits 02.

[0184] Similarly, it can be known that when the controller 01 issues the erase instruction: C7 to the SPI flash 03 connected to the first loading circuit 02, the instruction value of the erase instruction in the SVF file is the hexadecimal number: 1c7c7c6, the instruction value length is 25 bits, and the binary representation is: 1110001111100011111000110. Since there is one second loading circuit 04 before the three first loading circuits 02, for the SPI flash 03 connected to the three first loading circuits 02, the actually read instruction value is the high 24 bits of 1110001111100011111000110: 111000111110001111100011. Among them, the SVF file parser reads the instructions in the SVF file from the low bit to the high bit, and 111000111110001111100011 is read from the low bit to the high bit as: 110001111100011111000111 (which is the hexadecimal number: c7c7c7), so that the erase instruction c7 can be issued to the SPI flash 03 connected to the three first loading circuits 02.

[0185] The TDI signal for writing the data ff5a to be loaded into the SPI flash memory 03 is represented as: 0b5fe00000040, with a length of 49 bits, and its binary representation is: 0101101011111111000000000000000000000000010000000. Among them, since there is 1 second loading circuit 04 before the first loading circuit 02, the TDI signal needs to be delayed by 1 clock cycle, so the lowest 1 bit of the TDI signal is: 0. Also, since the programming instruction is defined as the hexadecimal number: 02 (binary representation: 00000010), and its arrangement order from low to high is: 01000000, so the 2nd bit to the 9th bit of the lower bits of the TDI signal are: 01000000. Also, since the address length of the SPI flash memory 03 is 3 bytes (24 bits), the "000000000000000000000000" from the 10th bit to the 33rd bit of this TDI signal from low to high represents the 0 address with a length of 3 bytes. Also, since the data ff5a to be loaded has a binary representation of: 1111111101011010, and its arrangement order from low to high is: 0101101011111111, so the highest 16 bits of this TDI signal are: 0101101011111111.

[0186] Optionally, in the above loading system, the controller 01 is further configured to send a first configuration instruction to each of the first loading circuits 02, and send a third configuration instruction to the first to the (x - 1)th first loading circuits 02, where the first configuration instruction is used to indicate configuring a first value for indicating the n in the first configuration register 025 of the first loading circuit 02, and the third configuration instruction sent to the (x - i)th first loading circuit 02 is used to indicate configuring a third value for indicating the i in the second configuration register 026 of the (x - i)th first loading circuit 02, and the i is a positive integer less than x.

[0187] Among them, the timing conversion circuit 024 in the (x - i)th first loading circuit 02 can delay the TDI signal provided by the TDI pin by i clock cycles and then provide it to the MOSI pin according to the third value. And the timing conversion circuit 024 in the xth first loading circuit 02 does not need to delay the TDI signal provided by the TDI pin. Thus, it can be made that the x first loading circuits 02 can load data into the SPI flash memory 03 simultaneously.

[0188] In summary, the embodiment of the present application provides a loading system. The first loading circuit in the loading system includes a JTAG circuit and a channel selection circuit. The channel selection circuit has a first SPI, a second SPI, and a third SPI, and the third SPI is used to connect to an SPI flash memory. Since each pin of the JTAG circuit can be correspondingly connected to each pin of the first SPI, and the JTAG circuit can control the first SPI and the third SPI to conduct, communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can be connected to the JTAG circuit in the first loading circuit through the JTAG interface, and when the first SPI and the third SPI in the channel selection circuit are conducting, data can be loaded into the SPI flash memory, thereby realizing out-of-band upgrade of the firmware stored in the SPI flash memory.

[0189] Moreover, for the scenario where the loading system includes multiple cascaded loading circuits and the controller loads the SPI flash memory connected to one of the first loading circuits. The controller can configure the configuration register in the first loading circuit so that the timing conversion circuit in the first loading circuit can delay and / or advance the moment when the level of the target CS signal provided to the CS pin jumps from an invalid level to a valid level by several clock cycles. Thus, the controller can realize the loading of the SPI flash memory connected to the first loading circuit in multiple cascaded loading circuits, effectively improving the flexibility of loading.

[0190] For the scenario where the loading system includes multiple cascaded first loading circuits and the controller performs parallel loading on the SPI flash memories connected to the multiple first loading circuits. The controller can issue a parallel loading instruction to the first loading circuit, and the first loading circuit can then connect the TDI pin and the TDO pin in response to the parallel loading instruction. Thus, the first loading circuit can realize transmitting the TDI signal to the next first loading circuit while loading data into the SPI flash memory, and further ensure that the controller can perform parallel loading on multiple cascaded first loading circuits, reducing the time required for loading and improving the loading efficiency.

[0191] Based on the above analysis, in the loading system provided by the present application, the controller can directly perform out-of-band upgrade on the SPI flash memory connected to the loading circuit through its JTAG interface. Thus, the problem that the mainstream processor boards (such as PCIE boards or OAM modules) do not have an external SPI and cannot perform out-of-band upgrade on the SPI flash memory can be solved, effectively improving the flexibility of firmware upgrade. Moreover, the solution provided by the embodiments of the present application can normalize the loading processes of the SPI flash memories connected to different types of processor boards, and can also normalize the hardware designs of the processor boards, promoting the standardization of the software and hardware designs of the processor boards. Also, since the solution provided by the embodiments of the present application can integrate the channel selection circuit (i.e., MUX) into the loading circuit, it can be ensured that when performing out-of-band upgrade on the SPI flash memory, there is no need to additionally set up a MUX on the processor board, thereby saving the layout space of the processor board and reducing the hardware design cost.

[0192] Optionally, each loading circuit in the loading system provided by the embodiments of the present application can be an integrated circuit chip (IC), an application-specific integrated circuit (ASIC), or a programmable logic device (PLD). The above PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0193] Moreover, for the scenario where the loading circuit is an IC (i.e., a chip), the loading circuit can be a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), an image processing unit (IPU), a tensor processing unit (TPU), or the like.

[0194] The above embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that includes one or more collections of available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, or magnetic tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0195] In the present application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions. It should be understood that there is no logical or chronological dependency between "first", "second", and "nth", nor are the quantity and execution order limited. It should also be understood that although the following description uses terms such as first and second to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various examples, the first configuration register can be referred to as the second configuration register, and similarly, the second configuration register can be referred to as the first configuration register.

[0196] In the present application, the meaning of the term "at least one" refers to one or more, and the meaning of the term "a plurality" refers to two or more. For example, a plurality of loading circuits refers to two or more loading circuits. In this document, the terms "system" and "network" are often used interchangeably.

[0197] As described above, only the optional implementation manners of the present application are provided, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A loading circuit, characterized in that, The loading circuit includes: a Joint Test Action Group (JTAG) circuit, a flash memory controller, and a channel selection circuit; the channel selection circuit has a first Serial Peripheral Interface (SPI), a second SPI, and a third SPI, the second SPI is connected to the flash memory controller, and the third SPI is used to connect to an SPI flash memory; The JTAG circuit is used to control the conduction between the first SPI and the third SPI of the channel selection circuit, or to control the conduction between the second SPI and the third SPI; Moreover, the test clock pin of the JTAG circuit is connected to the serial clock pin in the first SPI, the test data input pin of the JTAG circuit is connected to the master transmit and slave receive pin in the first SPI, the test data output pin of the JTAG circuit is connected to the master receive and slave transmit pin in the first SPI, and the test access port controller of the JTAG circuit is connected to the chip select pin in the first SPI; Wherein, after the test access port controller is in the shift data register state, the level of the target chip select signal provided to the chip select pin jumps from an invalid level to a valid level.

2. The loading circuit according to claim 1, wherein The JTAG circuit is used to control the conduction between the first SPI and the third SPI according to the received loading instruction.

3. The loading circuit according to claim 2, wherein The loading instruction is a parallel loading instruction; The JTAG circuit is further used to connect the test data input pin and the test data output pin according to the loading instruction.

4. The loading circuit according to any one of claims 1 to 3, characterized in that, At the first target jump edge of the test clock pin after the test access port controller is in the shift data register state, the level of the target chip select signal provided to the chip select pin jumps from an invalid level to a valid level; At the first target jump edge of the test clock pin after the test access port controller ends the shift data register state, the level of the target chip select signal provided to the chip select pin jumps from a valid level to an invalid level; Wherein, the target jump edge is a rising edge or a falling edge.

5. The loading circuit according to claim 4, wherein The JTAG circuit is used to provide the target chip select signal to the chip select pin; Alternatively, the loading circuit further includes: a timing conversion circuit, and the test access port controller is connected to the chip select pin through the timing conversion circuit; The timing conversion circuit is used to provide the target chip select signal to the chip select pin according to the state of the test access port controller and the level of the test clock pin.

6. The loading circuit according to any one of claims 1 to 3, characterized in that The loading circuit further includes: a timing conversion circuit, and the test access port controller is connected to the chip select pin through the timing conversion circuit; The JTAG circuit is used to provide an initial chip select signal to the timing conversion circuit. Among them, at the first target jump edge of the test clock pin after the test access port controller is in the shift data register state, the level of the initial chip select signal is adjusted from an invalid level to a valid level. At the first target jump edge of the test clock pin after the test access port controller ends the shift data register state, the level of the initial chip select signal is adjusted from a valid level to an invalid level. The target jump edge is a rising edge or a falling edge; The timing conversion circuit is used to perform timing conversion on the initial chip select signal to obtain a target chip select signal and provide the target chip select signal to the chip select pin; Among them, the moment when the level of the target chip select signal jumps from an invalid level to a valid level is delayed by n clock cycles relative to the moment when the level of the initial chip select signal jumps from an invalid level to a valid level; and / or, the moment when the level of the target chip select signal jumps from a valid level to an invalid level is advanced by m clock cycles relative to the moment when the level of the initial chip select signal jumps from a valid level to an invalid level; both n and m are positive integers.

7. The loading circuit according to claim 6, wherein The loading circuit further includes: a first configuration register connected to the timing conversion circuit, and a first value for indicating n is configured in the first configuration register; The timing conversion circuit is used to delay the moment when the initial chip select signal jumps from an invalid level to a valid level by n clock cycles according to the first value.

8. The loading circuit according to claim 7, wherein A second value for indicating the duration when the target chip select signal is at a valid level is further configured in the first configuration register; The timing conversion circuit is used to advance the moment when the initial chip select signal jumps from a valid level to an invalid level by m clock cycles according to the second value.

9. The loading circuit according to any one of claims 6 to 8, characterized in that, The test data input pin is connected to the master transmit and slave receive pin in the first SPI through the timing conversion circuit; The timing conversion circuit is further used to delay the test data input signal provided by the test data input pin by i clock cycles and then provide it to the master transmit and slave receive pin, where i is a positive integer not greater than n.

10. The loading circuit according to claim 9, characterized in that, The loading circuit further includes: a second configuration register connected to the timing conversion circuit, and a third value for indicating i is configured in the second configuration register; The timing conversion circuit is used to delay the test data input signal provided by the test data input pin by i clock cycles and then provide it to the master transmit and slave receive pin according to the third value.

11. A loading method, characterized in that, Applied to the loading circuit according to any one of claims 1 to 10; the method includes: Connect the first serial peripheral interface SPI of the channel selection circuit in the loading circuit to the third SPI; After the test access port controller in the loading circuit is in the shift data register state, adjust the level of the target chip select signal provided to the chip select pin from an invalid level to a valid level.

12. The method according to claim 11, wherein The connecting the first SPI of the channel selection circuit in the loading circuit to the third SPI includes: According to the received loading instruction, the first SPI and the third SPI of the channel selection circuit in the loading circuit are conducted.

13. The method according to claim 12, wherein The loading instruction is a parallel loading instruction; the method further includes: According to the loading instruction, the test data input pin and the test data output pin of the Joint Test Action Group (JTAG) circuit in the loading circuit are connected.

14. The method according to any one of claims 11 to 13, characterized in that, After the test access port controller in the loading circuit is in the shift data register state, adjusting the level of the target chip select signal provided to the chip select pin from an invalid level to a valid level includes: At the first target jump edge of the test clock pin after the test access port controller in the loading circuit is in the shift data register state, adjusting the level of the target chip select signal provided to the chip select pin from an invalid level to a valid level; The method further includes: At the first target jump edge of the test clock pin after the test access port controller ends the shift data register state, adjusting the level of the target chip select signal provided to the chip select pin from a valid level to an invalid level; Wherein, the target jump edge is a rising edge or a falling edge.

15. The method according to any one of claims 11 to 13, characterized in that After the test access port controller in the loading circuit is in the shift data register state, adjusting the level of the target chip select signal provided to the chip select pin from an invalid level to a valid level includes: At the nth target jump edge of the test clock pin after the test access port controller in the loading circuit is in the shift data register state, adjusting the level of the target chip select signal provided to the chip select pin from an invalid level to a valid level; And / or, the method further includes: at the mth target jump edge of the test clock pin before the test access port controller in the loading circuit ends the shift data register state, the level of the target chip select signal provided to the chip select pin jumps from a valid level to an invalid level; Wherein, the target jump edge is a rising edge or a falling edge, and both n and m are positive integers.

16. The method according to claim 15, characterized in that, The method further includes: Delaying the test data input signal provided by the test data input pin of the JTAG circuit in the loading circuit by i clock cycles and then providing it to the master transmit and slave receive pin of the first SPI, where i is a positive integer not greater than n.

17. A loading system, characterized in that, The loading system includes: a controller, x first loading circuits, and x Serial Peripheral Interface (SPI) flash memories, where x is a positive integer; Wherein, each of the first loading circuits is the loading circuit according to any one of claims 1 to 10; The controller is connected to the JTAG circuit in each of the first loading circuits through a Joint Test Action Group (JTAG) interface, and each SPI flash memory is connected to the third SPI of the channel selection circuit in one of the first loading circuits; The controller is configured to send a loading instruction and data to the JTAG circuit, and the loading instruction is used to instruct the JTAG circuit to conduct the first SPI and the third SPI of the channel selection circuit, and load the data into the SPI flash memory.

18. The loading system according to claim 17, wherein x = 1; The loading system further includes: n second loading circuits connected in series between the test data input pin of the JTAG interface of the controller and the first loading circuit, where n is a positive integer; The controller is further configured to send a first configuration instruction to the first loading circuit, and the first configuration instruction is used to indicate to configure a first value indicating n in the first configuration register of the first loading circuit.

19. The loading system according to claim 17 or 18, characterized in that, x = 1; The loading system further includes: m third loading circuits connected in series between the first loading circuit and the test data output pin of the JTAG interface of the controller, where m is a positive integer; The controller is further configured to determine the duration for which the target chip select signal is at an active level according to the number m of the third loading circuits, and send a second configuration instruction to the first loading circuit, and the second configuration instruction is further used to indicate to configure a second value indicating the duration for which the target chip select signal is at an active level in the first configuration register; Wherein, the target chip select signal is the signal received by the chip select pin of the first SPI in the first loading circuit.

20. The loading system according to claim 17, wherein x is greater than 1, and the x first loading circuits are connected in series; The loading system further includes: n - x + 1 second loading circuits connected in series between the test data input pin of the JTAG interface of the controller and the x first loading circuits, where n is a positive integer and x is an integer not greater than n + 1; The controller is configured to perform parallel loading on the SPI flash memories connected to the x first loading circuits, and the loading instruction is a parallel loading instruction, and the loading instruction is further used to indicate that the test data input pins and the test data output pins of the JTAG circuits of the first to the x - 1th first loading circuits among the x first loading circuits are connected; The controller is further configured to send a first configuration instruction to each of the first loading circuits, and send a third configuration instruction to the first to the x - 1th first loading circuits, where the first configuration instruction is used to indicate to configure a first value indicating n in the first configuration register of the first loading circuit, and the third configuration instruction sent to the x - i-th first loading circuit is used to indicate to configure a third value indicating i in the second configuration register of the x - i-th first loading circuit, and i is a positive integer less than x.

Images