RISC-V hardware test method and system based on SoC FPGA

Abstract

The application provides a RISC-V hardware test method based on an SoC FPGA, and comprises the following steps: step 1, a RISC-V processor is configured in an FPGA, and bus interconnection with an HPS is completed; step 2, the HPS sends a reset signal to the RISC-V processor, and the RISC-V processor is started; step 3, the RISC-V processor sends access storage and peripheral control signals to the HPS, and the memory and the peripheral controller are accessed; and step 4, the HPS prints data generated by accessing the peripheral controller through a serial port, and the RISC-V test is completed. The scheme provided by the application is convenient to use and can be adapted to various RISC-V processors, thereby saving a lot of time for users to familiarize with hardware test environments and platforms provided by various manufacturers or to build a separate hardware test platform for testing and verifying the functions of the RISC-V processor.

Description

Technical Field

[0001] This invention relates to the field of hardware testing, and in particular to a RISC-V hardware testing method and system based on SoC FPGA. Background Technology

[0002] SoC FPGA is a new type of SoC chip that integrates a single-core or dual-core ARM processor and FPGA logic resources on a single chip. Compared to traditional single ARM processors or FPGA chips, SoC FPGA has both the flexible and efficient data processing and transaction processing capabilities of ARM processors and the high-speed parallel processing advantages of FPGAs. Furthermore, based on the unique on-chip interconnect structure of the two, the general-purpose logic resources on the FPGA can be configured and mapped to one or more peripherals with specific functions of the ARM processor, communicating through the AXI high-speed bus to complete the interaction of data and control commands.

[0003] RISC-V, on the other hand, is an open-source instruction set architecture (ISA) based on the Reduced Instruction Set Computing (RISC) principle. Its simple architecture and completely open-source nature allow it to be freely used for any purpose, enabling anyone to design, manufacture, and sell RISC-V chips and software. Currently, there are many open-source RISC-V processors on the market, such as the Xiangshan RISC-V processor, Alibaba's XuanTie RISC-V series processors, and Nuclei Technology's Hummingbird E203 open-source processor, etc. Each RISC-V manufacturer has its own corresponding hardware testing platform for testing RISC-V processor functionality. The structure and usage methods of these hardware testing platforms vary greatly, which is extremely inconvenient for users. Summary of the Invention

[0004] To address the problems existing in the prior art, a convenient hardware testing method and system that is compatible with various RISC-V processors is provided. It mainly utilizes the characteristics of SoC FPGA, which integrates ARM processors and FPGA logic resources, to configure various RISC-V processors onto FPGAs with abundant general-purpose logic resources. Then, the flexible and efficient data processing and transaction processing capabilities of ARM processors are used to debug and test the correctness of the functions of the RISC-V processors configured on the FPGA. This saves users a lot of time in becoming familiar with the hardware testing environments and platforms provided by various RISC-V manufacturers, and even in building and designing separate hardware testing platforms to achieve debugging purposes for testing and verifying the functions of RISC-V processors.

[0005] The technical solution adopted in this invention is as follows: A RISC-V hardware testing method based on SoC FPGA, comprising:

[0006] Step 1: Configure the RISC-V processor on the FPGA and complete the bus interconnection with the HPS;

[0007] Step 2: HPS sends a reset signal to the RISC-V processor, and the RISC-V processor starts up;

[0008] Step 3: The RISC-V processor sends memory and peripheral control signals to the HPS to access the memory and peripheral controller.

[0009] Step 4: HPS prints the data generated by accessing the peripheral controller via the serial port to complete the RISC-V test.

[0010] Furthermore, the RISC-V configuration method is as follows:

[0011] Step 1.1: Convert the RISC-V processor source code into Verilog hardware description language code, and break down the different functional modules according to the internal structure of the RISC-V processor.

[0012] Step 1.2: Complete the full compilation of the Verilog source code for the RISC-V processor on the Intel hardware development platform and generate a binary .sof file that can be used to configure the FPGA;

[0013] Step 1.3: Write the sof file to the FPGA via JTAG to complete the configuration of the RISC-V processor on the FPGA.

[0014] Furthermore, an address filter is set in the FPGA and configured on the interconnect bus between the HPS and the RISC-V processor to transfer the corresponding data generated by the RISC-V processor accessing the peripheral controller to a specified memory space.

[0015] Furthermore, in step 4, HPS sends a memory access signal to access the specified memory space where the address filter transfers the data, and then prints the data in the specified memory space via the serial port.

[0016] This invention also provides a RISC-V hardware testing system based on SoC FPGA, comprising:

[0017] The FPGA is configured with the RISC-V processor to be tested and provides the RISC-V processor AXI memory bus interface and AXI peripheral control bus interface.

[0018] HPS includes a general-purpose input / output interface for sending reset signals to the RISC-V; an AXI bus slave interface for exchanging data with the RISC-V processor's AXI memory bus interface and AXI peripheral control bus interface; and a UART serial port for printing data generated by the RISC-V processor accessing the peripheral controller.

[0019] Furthermore, it also includes an address filter, configured in the FPGA and set on the AXI peripheral control bus of the RISC-V processor, used to transfer the corresponding data generated by the RISC-V processor accessing the peripheral controller through the AXI peripheral control bus to the specified memory space.

[0020] Furthermore, HPS sends a memory access signal to the specified memory space where the data is transferred by the address filter, and then prints the data in the specified memory space through the serial port.

[0021] Compared with the prior art, the beneficial effects of adopting the above technical solution are as follows: the solution proposed in this invention is convenient to use and can be adapted to a variety of RISC-V processors, saving users a lot of time to familiarize themselves with the hardware testing environments and platforms provided by various manufacturers, or to build and design a separate hardware testing platform in order to test and verify the functions of RISC-V processors. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the RISC-V hardware test system based on SOC FPGA proposed in this invention.

[0023] Figure 2 This is a flowchart of the RISC-V hardware testing method based on SOC FPGA proposed in this invention. Detailed Implementation

[0024] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar modules or modules having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Rather, the embodiments of this application include all variations, modifications, and equivalents falling within the spirit and scope of the appended claims.

[0025] Example 1

[0026] like Figure 2As shown, this embodiment proposes a RISC-V hardware testing method based on SoC FPGA. Various RISC-V processors are configured onto an FPGA with abundant general-purpose logic resources. Then, the flexible and efficient data processing and transaction processing capabilities of the ARM processor are utilized to debug and test the functionality of the RISC-V processor configured on the FPGA. This saves users a significant amount of time in becoming familiar with the hardware testing environments and platforms provided by various RISC-V vendors, and even in building and designing a separate hardware testing platform to achieve debugging purposes for testing and verifying RISC-V processor functionality. The specific method is as follows:

[0027] Step 1: Configure the RISC-V processor on the FPGA and complete the bus interconnection with the HPS;

[0028] Step 2: HPS sends a reset signal to the RISC-V processor, and the RISC-V processor starts up;

[0029] Step 3: The RISC-V processor sends memory access and peripheral control signals to the HPS to access the memory and peripheral controller; among them, the memory access signals are used to control the operation of the HPS.

[0030] Step 4: HPS prints the data generated by accessing the peripheral controller via the serial port to complete the RISC-V test.

[0031] Specifically, the RISC-V processor configuration is as follows: First, the RISC-V processor source code is converted into Verilog hardware description language code, and different functional modules are decomposed according to the internal structure of the RISC-V processor, i.e., modularization; then, the entire process of compiling the RISC-V processor Verilog source code is completed in the Intel hardware development platform Quartus Prime, and a binary sof file that can be used to configure the FPGA is generated; finally, the sof file is burned onto the FPGA via JTAG to complete the configuration of the RISC-V processor on the FPGA.

[0032] Meanwhile, an address filter is set in the FPGA and configured on the interconnect bus between the HPS and the RISC-V processor. It is used to transfer the corresponding data generated by the RISC-V processor accessing the peripheral controller to the specified memory space. The address filter is set on the AXI peripheral control bus.

[0033] In this embodiment, in step 4, HPS sends a memory access signal to access the specified memory space where the address filter transfers the data, and then prints the data in the specified memory space through the serial port.

[0034] When it is necessary to perform secondary development on an existing open-source RISC-V processor but the specific hardware functions and usage methods of the RISC-V processor are not understood, or when a RISC-V processor design is completed independently and hardware functional testing and verification are required, the testing method proposed in this embodiment can effectively perform functional testing.

[0035] Example 2

[0036] like Figure 2 As shown, this embodiment provides a RISC-V hardware test system based on SoC FPGA, including:

[0037] The FPGA is configured with the RISC-V processor to be tested and provides the RISC-V processor AXI memory bus interface and AXI peripheral control bus interface.

[0038] HPS includes a general-purpose input / output interface for sending reset signals to the RISC-V; an AXI bus slave interface for exchanging data with the RISC-V processor's AXI memory bus interface and AXI peripheral control bus interface; and a UART serial port for printing data generated by the RISC-V processor accessing the peripheral controller.

[0039] Specifically, Figure 2 In the SoC / FPGA section, HPS represents the SoC / ARM processor portion within the overall SoC / FPGA architecture, while FPGA represents the FPGA / logic resource portion. Within the FPGA section, RISC-V refers to the RISC-V processor currently configured on the FPGA that requires testing.

[0040] GPIO stands for General Purpose Input / Output Interface, located on the HPS side. It is mainly used to send a reset signal to the RISC-V processor to start the RISC-V processor.

[0041] MEM_AXI_MASTER and MMIO_AXI_MASTER represent the external AXI bus interfaces provided by the RISC-V processor, namely the AXI memory bus interface and the AXI peripheral control bus interface, respectively. They are mainly used to pass the access signal (MASTER) to the external SDRAM controller and multiple peripheral controllers (SLAVE) to achieve the purpose of accessing the address space.

[0042] F2H_AXI_SLAVE indicates the AXI bus slave interface connecting the FPGA and HPS, through which data exchange between the FPGA and HPS can be realized.

[0043] The main function of the ADDRESS_FILTER module (address filter) is to transfer the corresponding data generated by the RISC-V processor accessing the peripheral controller through MMIO_AXI_MASTER to the specified memory space.

[0044] UART refers to the serial port peripheral located on the HPS side, which is mainly used for printing the data generated.

[0045] During testing, the RISC-V processor is configured onto the FPGA portion of the SoC FPGA, and the RISC-V processor's memory and peripheral AXI bus interfaces (MEM_AXI_MASTER, MMIO_AXI_MASTER) are connected to the HPS side of the SoC FPGA. The interconnection between the FPGA and the SoC's AXI bus slave interface (F2H_AXI_SLAVE) is also established. A reset signal (RESET) is sent to the RISC-V processor via the HPS side's general purpose input / output (GPIO) ports to start the RISC-V processor. After startup, the RISC-V processor immediately sends memory access and peripheral control signals to the HPS side to access memory and peripherals.

[0046] During peripheral access, the ADDRESS_FILTER module transfers the corresponding data generated by the RISC-V processor's access to the peripheral controller to the specified address space. Finally, HPS reads and prints the data transferred to the specified memory space by the ADDRESS_FILTER module (address filter) and prints the data generated by the RISC-V processor's memory access.

[0047] It should be noted that, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances. The accompanying drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0048] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A RISC-V hardware testing method based on SoC FPGA, characterized in that, include: Step 1: Configure the RISC-V processor on the FPGA and complete the bus interconnection with the HPS; Step 2: HPS sends a reset signal to the RISC-V processor, and the RISC-V processor starts up; Step 3: The RISC-V processor sends memory and peripheral control signals to the HPS to access the memory and peripheral controller. Step 4: HPS prints the data generated by accessing the peripheral controller via the serial port to complete the RISC-V test; The FPGA is equipped with an address filter configured on the interconnect bus between the HPS and the RISC-V processor. This filter is used to transfer the corresponding data generated by the RISC-V processor accessing the peripheral controller to a specified memory space. In step 4, the HPS sends a memory access signal to access the specified memory space where the address filter has transferred the data, and then prints the data in the specified memory space via a serial port.

2. The RISC-V hardware testing method based on SoC FPGA according to claim 1, characterized in that, The configuration process for RISC-V processing is as follows: Step 1.1: Convert the RISC-V processor source code into Verilog hardware description language code, and break down the different functional modules according to the internal structure of the RISC-V processor. Step 1.2: Complete the full compilation of the Verilog source code for the RISC-V processor on the Intel hardware development platform and generate a binary .sof file that can be used to configure the FPGA; Step 1.3: Write the sof file to the FPGA via JTAG to complete the configuration of the RISC-V processor on the FPGA.

3. A RISC-V hardware testing system based on SoC FPGA, characterized in that, include: The FPGA is equipped with a RISC-V processor and provides a RISC-V processor AXI memory bus interface and an AXI peripheral control bus interface. HPS includes a general-purpose input / output interface for sending reset signals to RISC-V; an AXI bus slave interface for exchanging data with the RISC-V processor's AXI memory bus interface and AXI peripheral control bus interface; and a UART serial port for printing data generated by the RISC-V processor accessing the peripheral controller. It also includes an address filter, configured in the FPGA and set on the AXI peripheral control bus of the RISC-V processor, used to transfer the corresponding data generated by the RISC-V processor accessing the peripheral controller through the AXI peripheral control bus to the specified memory space; the HPS sends a memory access signal to access the specified memory space where the address filter transfers the data, and then prints the data in the specified memory space through the serial port.

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