Fan-out packaged devices

Abstract

The present application discloses a fan-out packaging device, which includes: a first chip, including a functional surface and a non-functional surface arranged opposite to each other, and a side surface located between the functional surface and the non-functional surface; a plurality of blocking members, which are arranged around the side periphery of the first chip; an adhesive layer, which covers the blocking members and at least part of the side periphery of the first chip; a first heat sink, which is at least partially located on one side of the non-functional surface, and the positive projections of the non-functional surface and the plurality of blocking members on the first heat sink are located inside the first heat sink; through the above-mentioned device, the present application can reduce the probability of chip warping in the fan-out packaging device and improve the heat dissipation performance of the fan-out packaging device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a fan-out packaging device. Background Art

[0002] In traditional fan-out packaging methods, after the chip is plastic-sealed, the plastic sealing material in the packaging structure shrinks and deforms, which easily causes the chip to shift within the packaging structure, reducing the chip's service life. In addition, traditional fan-out packaging devices are easily affected by poor heat dissipation performance, which affects the performance of fan-out devices. Summary of the Invention

[0003] The main technical problem solved by the present application is to provide a fan-out packaging device that can reduce the probability of chip warping in the fan-out packaging device and improve the heat dissipation performance of the fan-out packaging device.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a fan-out packaging device, comprising: a first chip, comprising a functional surface and a non-functional surface arranged opposite to each other, and a side surface located between the functional surface and the non-functional surface; a plurality of blocking members, arranged around the side periphery of the first chip; an adhesive layer, covering the blocking members and at least part of the side periphery of the first chip; a first heat sink, at least partially located on one side of the non-functional surface, and the positive projections of the non-functional surface and the plurality of blocking members on the first heat sink are located within the first heat sink.

[0005] In which, the fan-out packaging device also includes: a plurality of conductive columns, which are located on the side of the first heat sink where the first chip is provided, and are arranged around the periphery of the plurality of blocking members, and the height of the conductive columns is greater than the height of the blocking members; a first electrical connector, which is stacked on one side of the functional surface, and the solder pads on the functional surface and at least one end of the conductive columns are electrically connected to the first electrical connector; a second electrical connector, which is stacked on the side of the first heat sink away from the first chip, and the other end of at least part of the conductive columns is electrically connected to the second electrical connector.

[0006] The orthographic projections of the non-functional surface, the plurality of blocking members, and a portion of the conductive pillars adjacent to the plurality of blocking members on the first heat sink are located within the first heat sink.

[0007] In which, the conductive column is located in the adhesive layer, and the adhesive layer is an insulating adhesive layer; the fan-out packaging device also includes: a first redistribution layer, located between the adhesive layer and the first electrical connector; one end of the conductive column and the pad on the functional surface are electrically connected to the first electrical connector through the first redistribution layer.

[0008] The fan-out packaging device further includes: a second redistribution layer, which is provided on the same layer as the first heat sink, and the other ends of at least some of the conductive pillars are electrically connected to the second electrical connector through the second redistribution layer.

[0009] In which, the multiple conductive pillars are located on the periphery of the adhesive layer, and the adhesive layer is an insulating adhesive layer or a conductive adhesive layer; the first heat sink includes a base plate and a plurality of side plates extending from the base plate; in which, the orthographic projection of the base plate on the first electrical connector covers the first chip and the blocking member, the side plates are arranged through the gap between the blocking member and the conductive pillars and are fixed to the first electrical connector, and there is no contact between the conductive pillars and the side plates.

[0010] Wherein, the blocking member has conductive properties, and the blocking member and the conductive column are formed of the same material.

[0011] Wherein, a plurality of the blocking members are connected to each other to form an annular structure.

[0012] Wherein, the fan-out packaging device further includes: a second heat sink located between the non-functional surface and the first heat sink; wherein the orthographic projection of the non-functional surface on the second heat sink is located within the second heat sink.

[0013] The second heat sink extends between the blocking member and the first heat sink, and the orthographic projections of the non-functional surface and the plurality of blocking members on the second heat sink are located within the second heat sink; or, the plurality of blocking members are located on the periphery of the second heat sink, and the blocking member and the second heat sink are arranged flush on the side adjacent to the non-functional surface.

[0014] The beneficial effects of the present application are as follows: Unlike the prior art, the fan-out package device provided by the present application has multiple blocking members disposed around the periphery of the first chip. These blocking members act as cofferdam walls, helping to limit the movement of materials within the fan-out package device and reducing the probability of chip warping. The provision of heat sinks helps improve the heat dissipation performance of the fan-out package device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0016] Figure 1 This is a schematic structural diagram of a fan-out packaging device according to an embodiment of the present invention;

[0017] Figure 2 It is a structural schematic diagram corresponding to another embodiment of the fan-out packaging device of the present application;

[0018] Figure 3 It is a structural schematic diagram of another embodiment of the fan-out packaging device of the present application;

[0019] Figure 4 It is a structural schematic diagram corresponding to another embodiment of the fan-out packaging device of the present application;

[0020] Figure 5 1 is a flow chart of a method for preparing a fan-out packaging device according to an embodiment of the present invention;

[0021] Figure 6 yes Figure 5 Steps S101-S104 correspond to a schematic structural diagram of an embodiment;

[0022] Figure 7 yes Figure 5 Flowchart of another embodiment corresponding to step S102

[0023] Figure 8 yes Figure 7 Steps S201-S204 correspond to a structural diagram of an embodiment. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] See also Figure 1 , Figure 1 It is a structural diagram of a fan-out packaging device corresponding to an embodiment of the present application. The fan-out packaging device provided by the present application includes: a first chip 100, a plurality of blocking members 20, an adhesive layer 60 and a first heat sink 40.

[0026] Specifically, the first chip 100 includes a functional surface 101 and a non-functional surface 102 disposed opposite each other, and a side surface 106 located between the functional surface 101 and the non-functional surface 102. The functional surface 101 is provided with a plurality of bonding pads 103. In this embodiment, there may be multiple first chips 100, and the chip types may be the same or different, without limitation. Furthermore, the functional surface 101 is provided with a plurality of conductive bumps 105, each conductive bump 105 being electrically connected to a bonding pad 103.

[0027] A plurality of blocking members 20 are disposed around the periphery of the side surface 106 of the first chip 100. Figure 1 As shown in , multiple blocking members 20 can be arranged at intervals. Of course, in other embodiments, multiple blocking members 20 can also be connected to each other to form an annular structure, that is, in this case, multiple blocking members 20 are equivalent to forming a ring or other annular structure, which is arranged around the periphery of the side 106 of the first chip 100. The blocking member 20 helps to limit the movement of the material in the adhesive layer 60 in the fan-out packaging device to reduce the deformation of the adhesive layer 60 caused by shrinkage and reduce the probability of chip warping. In addition, the material of the blocking member 20 can be a metal material or a non-metal material. When the blocking member 20 is made of metal, the blocking member 20 can also play the role of electromagnetic shielding.

[0028] The adhesive layer 60 covers at least a portion of the side periphery of the blocking member 20 and the first chip 100. Figure 1 As shown, the side of the adhesive layer 60 away from the non-functional surface 102 is flush with the functional surface of the first chip 100, and the conductive bumps 105 are exposed from the adhesive layer 60. The adhesive layer 60 can at least provide a certain degree of fixation and protection for the first chip 100 and the barrier 20. The adhesive layer 60 can be an insulating adhesive; alternatively, the adhesive layer 60 can be a conductive adhesive layer to provide better electromagnetic shielding.

[0029] At least a portion of the first heat sink 40 is located on one side of the non-functional surface 102, and the orthographic projections of the non-functional surface 102 and the plurality of blocking members 20 on the first heat sink 40 are located within the first heat sink 40. The provision of the first heat sink 40 facilitates overall heat dissipation of the fan-out packaged device, thereby improving the heat dissipation performance of the fan-out device. The first heat sink 40 can be made of a metal material such as elemental indium, an indium alloy, or a silver alloy, or an organic material. When the first heat sink 40 is made of a metal material, flux is required during the formation of the first heat sink 40 to remove the oxide layer and foreign matter on the surface of the metal heat dissipation material and to improve wettability and weldability.

[0030] In the fan-out package device provided herein, a plurality of blocking members 20 are disposed around the periphery of the first chip 100. These blocking members 20 act as cofferdam walls, helping to limit material movement within the fan-out package device and reducing the likelihood of chip warping. Furthermore, the provision of a first heat sink helps improve the heat dissipation performance of the fan-out package device.

[0031] Also, please continue to read Figure 1A second heat sink 50 may also be provided between the non-functional surface 102 and the first heat sink 40. The second heat sink 50 may be formed into a metal layer by a sputtering metal process, and the metal layer may serve as the second heat sink 50. In this embodiment, the second heat sink extends between the blocking member 20 and the first heat sink 40, and the orthographic projections of the non-functional surface 102 and the plurality of blocking members 20 on the second heat sink 50 are located within the second heat sink 50, i.e., the plurality of blocking members 20 are provided on the second heat sink 50. In other embodiments, the plurality of blocking members 20 are located on the periphery of the second heat sink 50, and the blocking members 20 and the second heat sink 50 are provided flush with each other on the side adjacent to the non-functional surface 102. The second heat sink 50 can at least provide centralized heat dissipation for the first chip 100, further improving the heat dissipation performance of the fan-out device.

[0032] In one embodiment, see Figure 1 The fan-out packaging device provided in this application also includes: a plastic packaging layer 65 and a first electrical connector 110.

[0033] The plastic layer 65 is disposed on the outer sides of the second heat sink 50 and the adhesive layer 60 to fix and protect the first chip 100 , the blocking member 20 and the second heat sink 50 .

[0034] The first electrical connector 110 is stacked on one side of the functional surface 101 and is electrically connected to the conductive bumps 105 on the functional surface 101. Through the first electrical connector 110, the first chip 100 can be connected to a substrate or other chips.

[0035] In another embodiment, see Figure 2 , Figure 2 FIG. 1 is a schematic structural diagram of another embodiment of the fan-out packaging method of the present application. In this embodiment, the fan-out packaging device includes: a first chip 100 , a plurality of blocking members 20 , and a first heat sink 40 .

[0036] Specifically, the first chip 100 includes a functional surface 101 and a non-functional surface 102 disposed opposite each other, and a side surface 106 located between the functional surface 101 and the non-functional surface 102. A plurality of blocking members 20 are disposed around the side of the first chip 100. The first heat sink 40 is located on one side of the non-functional surface 102, and the orthographic projections of the non-functional surface 102 and the plurality of blocking members 20 on the first heat sink 40 are located within the first heat sink 40.

[0037] In an application mode, please continue to see Figure 2The fan-out package device provided in the present application further includes: a plurality of conductive pillars 30, which are located on the side of the first heat sink 40 where the first chip 100 is provided, and are arranged around the periphery of the plurality of blocking members 20, and the height of the conductive pillars 30 is greater than the height of the blocking members 20. In addition, the orthographic projections of the non-functional surface 102, the plurality of blocking members 20, and some of the conductive pillars 30 adjacent to the plurality of blocking members 20 on the first heat sink 40 are located within the first heat sink 40. The conductive pillars 30 can realize a three-dimensional vertical interconnection structure, which is conducive to reducing the height of the fan-out package device. The design of blocking members 20 and conductive pillars 30 of different heights can also effectively save material costs. Optionally, the material of the conductive pillars 30 can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. When the blocking member 20 is conductive, the conductive pillars 30 and the blocking member 20 can be formed of the same material.

[0038] In an application mode, please continue to see Figure 2 , the fan-out packaging device provided in this application also includes:

[0039] The first electrical connector 110 is stacked on one side of the functional surface 101, and the pads 103 on the functional surface 101 and one end of at least some of the conductive pillars 30 are electrically connected to the first electrical connector 110. Through the first electrical connector 110, the fan-out package device can be connected to the substrate or other chips.

[0040] The second electrical connector 120 is stacked on the side of the first heat sink 40 facing away from the first chip 100, and the other ends of at least some of the conductive pillars 30 are electrically connected to the second electrical connector 120. The other ends of at least some of the conductive pillars 30 are electrically connected to the second electrical connector 120 via a plurality of solder balls 115. Through the second electrical connector 120, the fan-out device can be connected to a substrate or other chips, thereby enabling information exchange between the two opposing sides of the fan-out packaged device and the substrate or other chips.

[0041] In addition, if Figure 2 As shown in FIG, an adhesive layer 60 may be disposed between the first electrical connector 110 and the second electrical connector 120. This adhesive layer 60 is an insulating adhesive. The conductive pillars 30, the blocking member 20, and the side surface 106 of the first chip 100 are encapsulated by the adhesive layer 60. The conductive pillars 30, the blocking member 20, and the adhesive layer 60 are flushly disposed adjacent to the non-functional surface 102, and the first heat sink 40 is located on the adhesive layer 60. The adhesive layer 60 provides a certain degree of fixation and protection for the conductive pillars 30, the blocking member 20, and the first chip 100.

[0042] In one embodiment, see Figure 2The fan-out packaging device provided in the present application further includes: a first redistribution layer 80, located between the glue layer 60 and the first electrical connector 110. One end of the conductive pillar 30 and the pad 103 on the functional surface 102 are electrically connected to the first electrical connector 110 through the first redistribution layer 80. A plurality of solder balls 115 are provided between the first electrical connector 110 and the first redistribution layer 80 to facilitate connection between the first electrical connector 110 and the first redistribution layer 80. The provision of the first redistribution layer 80 facilitates connection between the conductive pillar 30, the first chip 100 and the first electrical connector 110, thereby reducing process difficulty.

[0043] In the above embodiment, the orthographic projections of the non-functional surface 102, the plurality of blocking members 20, and the portion of the conductive pillars 30 adjacent to the plurality of blocking members 20 on the first heat sink 40 are located within the first heat sink 40. Of course, in other embodiments, the orthographic projections of the portion of the conductive pillars 30 adjacent to the plurality of blocking members 20 on the first heat sink 40 may not be located within the first heat sink 40, that is, the first heat sink 40 does not contact the conductive pillars 30. For details, please refer to Figure 3 , Figure 3 This is a structural diagram of another embodiment of the fan-out packaging device of the present application. Figure 2 Unlike the embodiment in the previous section, the fan-out package device provided in this embodiment further includes a second redistribution layer 90, which is disposed on the same layer as the first heat sink 40. The other ends of at least some of the conductive pillars 30 are electrically connected to the second electrical connector 120 via the second redistribution layer 90. The provision of the second redistribution layer 90 facilitates the connection between the conductive pillars 30 and the second electrical connector 120. A plurality of solder balls 115 are disposed between the second redistribution layer 90 and the second electrical connector 120 to facilitate the connection, thereby reducing process complexity.

[0044] In another embodiment, see Figure 4 , Figure 4 This is a structural diagram of another embodiment of the fan-out package device of the present application. In this embodiment, the fan-out package device includes: a first chip 100, a plurality of blocking members 20, and a plurality of conductive pillars 30. For details, please refer to Figure 2 In addition, in this embodiment, the fan-out device further includes: a first heat sink 40 , a first electrical connector 110 and a second electrical connector 120 .

[0045] Specifically, the first heat sink 40 is at least partially located on one side of the non-functional surface 102. The orthographic projections of the non-functional surface 102 and the plurality of blocking members 20 on the first heat sink 40 are located within the first heat sink 40, and the plurality of conductive pillars 30 are exposed from the first heat sink 40. In this embodiment, the first heat sink 40 includes a base plate 41 and a plurality of side plates 42 extending from the base plate. The orthographic projection of the base plate 41 on the first electrical connector 110 covers the first chip 100 and the blocking members 20. The side plates 42 extend through the gap between the blocking members 20 and the conductive pillars 30 and are secured to the first electrical connector 110. The provision of the first heat sink 40, comprising the base plate 41 and the plurality of side plates 42, increases the area of ​​the first heat sink 40, thereby enhancing heat dissipation. The side plates 42 extend through the gap between the blocking members 20 and the conductive pillars 30 and are secured to the first electrical connector 110, thereby facilitating heat dissipation from the first electrical connector 110 and also separating the blocking members 20 from the conductive pillars 30 to prevent short circuits. Of course, in other embodiments, the first heat sink 40 may also only include the bottom plate 41 , which is not limited in this application.

[0046] A first electrical connector 110 is stacked on one side of the functional surface 101. The pads 103 on the functional surface 101 and at least one end of the conductive pillars 30 are electrically connected to the first electrical connector 110. Specifically, the first electrical connector 110 is provided with a plurality of solder joints 112; the conductive pillars 30 and the conductive bumps 105 are electrically connected to the first electrical connector 110 via the solder joints 112. Through the first electrical connector 110, the fan-out package device can be connected to a substrate or other chips.

[0047] A second electrical connector 120 is stacked on the side of the first heat sink 40 facing away from the first chip 100. The other end of the conductive pillar 30 is electrically connected to the second electrical connector 120. Specifically, a plurality of solder balls 115 are disposed between the conductive pillar 30 and the second electrical connector 120 to facilitate connection between the conductive pillar 30 and the second electrical connector. Through the second electrical connector 120, the fan-out device can be connected to the substrate or other chips, thereby enabling information exchange between the two opposing sides of the fan-out packaged device and the substrate or other chips.

[0048] In this example, please continue to refer to Figure 4 The fan-out device provided in the present application also includes: an adhesive layer 60, which continuously covers at least part of the side surface of the blocking member 20 and at least part of the side surface 106 of the first chip 100, so that the first chip 100 and the blocking member 20 form an integral structure, and plays a certain role in fixing and protecting the first chip 100 and the blocking member 20.

[0049] In one embodiment, see Figure 4The fan-out package device provided in the present application further includes: a third electrical connector 130, which is stacked and arranged on the side of the first electrical connector 110 facing away from the first chip 100. A plurality of solder balls 115 are included between the third electrical connector 130 and the first electrical connector 110 to facilitate connection between the third electrical connector 130 and the first electrical connector 110. The provision of the third electrical connector 130 facilitates connection of other devices disposed on the side of the third electrical connector 130 facing away from the first electrical connector 110 with the fan-out package device provided in the present application.

[0050] The following is a specific application scenario to illustrate the above Figure 2 The specific preparation process of fan-out packaged devices is described in detail. Figure 5 and Figure 6 , Figure 5 1 is a flow chart of a method for preparing a fan-out packaging device according to an embodiment of the present invention. Figure 6 for Figure 5 Steps S101-S104 correspond to a schematic structural diagram of an embodiment, wherein the fan-out packaging method includes:

[0051] S101: providing a carrier board, and disposing at least one first chip on one side of a first surface of the carrier board.

[0052] Specifically, if Figure 6 As shown in Figure a, the carrier 10 includes a first surface 11 and a second surface 12 arranged in opposite directions. Among them, the first surface 11 has a higher flatness. The material of the carrier 10 can be a hard material such as metal, plastic, etc. Furthermore, at least one first chip 100 is arranged on one side of the first surface 11 of the carrier 10. The first chip 100 includes a functional surface 101 and a non-functional surface 102 arranged in opposite directions. A plurality of pads 103 are provided on the functional surface 101 for information transmission; the functional surface 101 also includes a plurality of conductive bumps 105, and one conductive bump 105 is electrically connected to one pad 103. In addition, a second heat sink 50 is provided between the non-functional surface 102 and the carrier 10. Figure 6 Only one first chip 100 is drawn in a, but in other embodiments, 1, 2, 3, etc. first chips 100 can be spaced apart on one side of the first surface 11 of the carrier 10, and multiple first chips 100 can be packaged at the same time. After the packaging is completed, multiple independent fan-out packaging structures can be obtained by cutting the connecting part between the two packaging bodies.

[0053] S102: Dispose a plurality of blocking members and a plurality of conductive pillars.

[0054] Specifically, if Figure 6As shown in FIG. 1 b, a plurality of blocking members 20 are arranged around the periphery of the first chip 100; a plurality of conductive pillars 30 are arranged around the periphery of the plurality of blocking members 20. The height of the conductive pillars 30 is greater than the height of the blocking members 20. In addition, the plurality of blocking members 20 can be connected to each other to form a ring structure around the periphery of the first chip 100, or can be arranged at intervals around the periphery of the first chip 100. When the blocking members 20 have conductive properties, the blocking members 20 and the conductive pillars 30 are formed of the same material. The provision of the conductive pillars 30 helps to realize the three-dimensional vertical interconnection structure of the fan-out packaging device; the provision of the blocking members 20 helps to improve the stability of the fan-out device and reduce the probability of warping of the first chip 100.

[0055] In this embodiment, the plurality of blocking members 20 and the plurality of conductive pillars 30 can be formed by disposing a dielectric layer with grooves on one side of the first surface 11 of the carrier 10, forming a plurality of first vias on the sidewalls of the dielectric layer and a plurality of second vias at the bottom of the dielectric layer through an etching process, and then filling the first and second vias with conductive metal to form the plurality of conductive pillars 30 and the plurality of blocking members 20. Alternatively, the blocking members 20 and the conductive pillars 30 can also be formed by disposing a first and second photoresist layer on one side of the first surface 11 of the carrier 10. One of the first and second photoresist layers is a positive photoresist and the other is a negative photoresist. The plurality of first and second vias are formed by simultaneously performing exposure and development processes, and the plurality of blocking members 20 and the conductive pillars 30 are formed by filling the first and second vias with conductive metal.

[0056] S103: providing a glue layer and a first redistribution layer.

[0057] Specifically, if Figure 6 As shown in Figure c, an adhesive layer 60 is formed on the side of the carrier 10 where the first chip 100 is disposed. The adhesive layer 60 wraps around the conductive pillars 30, the blocking member 20, and the first chip 100, thereby securing and protecting the conductive pillars 30, the blocking member 20, and the first chip 100. The adhesive layer 60 can be formed by filling with insulating adhesive, with the conductive pillars 30 and the conductive bumps 105 exposed from the adhesive layer 60.

[0058] Furthermore, step S103 further includes: disposing a first redistribution layer 80 on the side of the adhesive layer 60 facing away from the carrier 10 , wherein the first redistribution layer 80 is electrically connected to one end of the conductive pillar 30 and the conductive bump 105 .

[0059] S104: Disposing a first heat sink on the non-functional surface.

[0060] Specifically, if Figure 6As shown in Figure d, the specific implementation process of step S104 includes: removing the carrier 10, and setting a first heat sink 40 on one side of the non-functional surface 102, and the non-functional surface 102, multiple blocking members 20, and part of the conductive columns 30 adjacent to the multiple blocking members 20 are projected on the first heat sink 40. The projection is located within the first heat sink 40, that is, the first heat sink 40 is in contact with the second heat sink 50, one end of the blocking member 20, and one end of the part of the conductive column 30.

[0061] S105: Arrange a first electrical connector and a second electrical connector along the length direction of the conductive column.

[0062] Specifically, if Figure 6 As shown in FIG. 5 , the specific implementation process of step S105 includes: disposing a first electrical connector 110 on the functional surface 101 side of the first chip 100. A plurality of solder balls 115 are disposed between the first electrical connector 110 and the first redistribution layer 80. The solder pads 103 on the functional surface 101 and one end of the conductive pillars 30 are electrically connected to the first electrical connector 110 via the first redistribution layer 80. Furthermore, a second electrical connector 120 is disposed on the side of the first heat sink 40 facing away from the first chip 100. The other ends of at least some of the conductive pillars 30 are electrically connected to the second electrical connector 120 via the plurality of solder balls 115.

[0063] In another embodiment, the first heat sink 40 provided in step S104 may not be connected to the conductive column 30, that is, the orthographic projections of the non-functional surface 102 and the plurality of blocking members 20 on the first heat sink 40 are located within the first heat sink 40. After the first heat sink 40 is formed, a second redistribution layer 90 provided on the same layer as the first heat sink 40 is formed on one side of the non-functional surface 102. Furthermore, a first electrical connector 110 and a second electrical connector 120 are provided in the length direction of the conductive column 30, and are electrically connected to the first redistribution layer 80 or the second redistribution layer 90 through a plurality of solder balls. The structural schematic diagram of the fan-out packaging method proposed in this embodiment can be referred to Figure 3 .

[0064] In another embodiment, after step S102, the adhesive layer 60 may be provided and the carrier 10 provided with the first chip 100 may be placed upside down on the first electrical connection body 110. For details, see Figure 7 and Figure 8 , Figure 7 for Figure 5 The flowchart after step S102 corresponds to another embodiment. Figure 8 for Figure 7 Steps S201-S204 correspond to a schematic structural diagram of an embodiment, and after step S102, the following steps may also be included:

[0065] S201: Setting a glue layer.

[0066] Specifically, see Figure 8 a. The specific implementation process of step S201 includes: forming an adhesive layer 60 on at least part of the side surface of the blocking member 20 and at least part of the side surface of the first chip 100, so that the first chip 100 and the blocking member 20 form an integral structure.

[0067] S202: Arrange the carrier with the first chip on one side thereof facing the first electrical connector, so that the conductive pillars and the first chip are electrically connected to the first electrical connector.

[0068] Specifically, see Figure 8 b. The specific implementation process of step S202 includes: providing a first electrical connector 110, which includes a plurality of solder joints 112. The conductive pillars 30 are electrically connected to the first electrical connector 110 via the solder joints 112; the conductive bumps 105 are electrically connected to the first electrical connector 110 via the solder joints 112, and the first chip 100 is also electrically connected to the first electrical connector 110.

[0069] S203: Setting a first heat sink.

[0070] Specifically, see Figure 8 c. The specific implementation process of step S203 includes: removing the carrier 10, and setting a first heat sink 40 on the side of the non-functional surface 102. The conductive column 30 is exposed from the first heat sink 40. In addition, the first heat sink 40 includes a base plate 41 and a plurality of side plates 42 extending from the base plate. Among them, the positive projection of the base plate 41 on the first electrical connector 110 covers the first chip 100 and the blocking member 20, and the side plate 42 is passed through the gap between the blocking member 20 and the conductive column 30 and is fixed to the first electrical connector 110. The heat dissipation performance of the fan-out packaging device is further improved by the first heat sink 40. Of course, in other embodiments, the first heat sink may also include only the base plate 41, and this application is not limited to this.

[0071] S204: Provide a second electrical connection body and a third electrical connection body.

[0072] Specifically, see Figure 8 d. The specific implementation process of step S204 includes: disposing a second electrical connector 120 and a third electrical connector 130 along the length direction of the conductive pillar 30. The second electrical connector 120 is electrically connected to the other end of the conductive pillar 30 via a plurality of solder balls 115, and the third electrical connector 130 is electrically connected to the first electrical connector 110 via a plurality of solder balls 115.

[0073] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A fan-out packaging device, characterized in that: include: The first chip comprises a functional surface and a non-functional surface disposed opposite to each other, and a side surface located between the functional surface and the non-functional surface; A plurality of blocking members are arranged around the outer periphery of the side of the first chip, and the plurality of blocking members are arranged at intervals; an adhesive layer covering the blocking member and at least a portion of a side periphery of the first chip, wherein the plurality of blocking members are used to limit movement of the adhesive layer; a first heat sink, at least partially located on one side of the non-functional surface, and orthographic projections of the non-functional surface and the plurality of blocking members on the first heat sink are located within the first heat sink; a plurality of conductive pillars, located on a side of the first heat sink where the first chip is disposed, and arranged around the periphery of the plurality of blocking members, wherein the height of the conductive pillars is greater than the height of the blocking members; a first electrical connection body, stacked on one side of the functional surface; The first heat sink includes a base plate and a plurality of side plates extending from the base plate; wherein, the orthographic projection of the base plate on the first electrical connector covers the first chip and the blocking member, the side plates are arranged through the gap between the blocking member and the conductive column and are fixed to the first electrical connector, and there is no contact between the conductive column and the side plates.

2. The fan-out package device according to claim 1, wherein: The pads on the functional surface and one end of at least some of the conductive pillars are electrically connected to the first electrical connector, and the fan-out package device further includes: The second electrical connector is stacked on a side of the first heat sink facing away from the first chip, and the other ends of at least some of the conductive pillars are electrically connected to the second electrical connector.

3. The fan-out package device according to claim 1, wherein: The adhesive layer is an insulating adhesive layer.

4. The fan-out package device according to claim 1, wherein: The plurality of conductive pillars are located on the periphery of the adhesive layer, and the adhesive layer is an insulating adhesive layer or a conductive adhesive layer.

5. The fan-out package device according to claim 1, wherein: The blocking member has conductive properties, and the blocking member and the conductive column are formed of the same material.

6. The fan-out package device according to claim 1, wherein: A plurality of the blocking members are connected to each other to form an annular structure.

7. The fan-out package device according to any one of claims 1 to 6, characterized in that: Also includes: The second heat sink is located between the non-functional surface and the first heat sink; wherein the orthographic projection of the non-functional surface on the second heat sink is located inside the second heat sink.

8. The fan-out package device according to claim 7, wherein: The second heat sink extends between the blocking member and the first heat sink, and the orthographic projections of the non-functional surface and the plurality of blocking members on the second heat sink are located within the second heat sink; or, The plurality of blocking members are located on the periphery of the second heat sink, and the blocking members and the second heat sink are arranged flush with each other on a side adjacent to the non-functional surface.

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