Oxide semiconductor thin film transistor and manufacturing method thereof

Abstract

The present invention relates to an oxide semiconductor thin film transistor and a method for manufacturing the same. In an oxide semiconductor thin film transistor, an oxide semiconductor portion includes a channel region and a first source / drain region and a second source / drain region sandwiching the channel region. An insulator portion made of a metal compound having a relative dielectric constant of not less than 8 is located between the gate electrode portion and the oxide semiconductor portion. The first compound interface portion contains constituent elements of the oxide semiconductor portion and constituent elements of the insulator portion, and has an interface with the first source / drain electrode portion and another interface with the first source / drain region. The second compound interface portion contains constituent elements of the oxide semiconductor portion and constituent elements of the insulator portion, and has an interface with the second source / drain electrode portion and another interface with the second source / drain region.

Description

Technical Field

[0001] The present invention relates to an oxide semiconductor thin film transistor. Background Art

[0002] The technology of combining low-temperature polysilicon thin-film transistors (LTPS TFTs) and oxide semiconductor TFTs into a single circuit is already available in practical applications. For example, a pixel circuit including a low-temperature polysilicon TFT and an oxide semiconductor TFT has been proposed. By combining a low-temperature polysilicon TFT with high mobility and an oxide semiconductor TFT with low leakage current into a single circuit, circuit characteristics are improved and power consumption is reduced.

[0003] Since the mobility of oxide semiconductor TFTs is low, in order to increase the on-current of the oxide semiconductor TFTs or reduce the driving voltage of the oxide semiconductor TFTs, it is proposed to use a high-k insulator as a gate insulator of the oxide semiconductor TFTs. Summary of the Invention

[0004] High-k insulators can improve the on-current characteristics of oxide semiconductor TFTs. However, including oxide semiconductor TFTs in thin film transistor circuits requires further improvement in characteristics.

[0005] One aspect of the present invention is an oxide semiconductor thin film transistor including: an oxide semiconductor portion including a channel region and first and second source / drain regions sandwiching the channel region;

[0006] a gate electrode portion;

[0007] an insulator portion, the insulator portion being located between the gate electrode portion and the oxide semiconductor portion, the insulator portion being made of a metal compound having a relative dielectric constant of not less than 8;

[0008] a first source / drain electrode portion;

[0009] a second source / drain electrode portion;

[0010] a first compound interface portion, the first compound interface portion having an interface with the first source / drain electrode portion and another interface with the first source / drain region, the first compound interface portion containing constituent elements of the oxide semiconductor portion and constituent elements of the insulator portion; and

[0011] The second compound interface portion has an interface with the second source / drain electrode portion and another interface with the second source / drain region, and the second compound interface portion contains constituent elements of the oxide semiconductor portion and constituent elements of the insulator portion.

[0012] One aspect of the present invention is a method for manufacturing an oxide semiconductor thin film transistor, the method comprising:

[0013] forming an oxide semiconductor layer including an oxide semiconductor portion of an oxide semiconductor thin film transistor;

[0014] forming an insulator layer including an insulator portion of the oxide semiconductor thin film transistor on an upper layer of the oxide semiconductor layer, the insulator layer being made of a metal compound having a relative dielectric constant of not less than 8;

[0015] forming a conductive layer including a gate electrode portion of an oxide semiconductor thin film transistor on an upper layer of the insulator layer; and

[0016] A compound interface portion containing constituent elements of the oxide semiconductor layer and constituent elements of the insulating layer is generated between the source / drain regions of the oxide semiconductor layer and the insulating layer.

[0017] One aspect of the present invention improves the current characteristics of an oxide semiconductor TFT.

[0018] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematically shows an example configuration of an OLED display device;

[0020] Figure 2 shows a configuration example of a pixel circuit;

[0021] Figure 3 Schematically shows a cross-sectional structure of a portion of a TFT substrate;

[0022] Figure 4 schematically shows a cross-sectional structure of another portion of the TFT substrate;

[0023] Figure 5 is a top view of a portion of a TFT substrate;

[0024] Figure 6 An example of a CMOS (Complementary Metal Oxide Semiconductor) circuit is shown;

[0025] Figure 7 Schematically shows Figure 6 An example of a cross-sectional structure of a CMOS circuit is shown;

[0026] Figure 8A Shown Figure 3 The steps of an example method of manufacturing the structure shown;

[0027] Figure 8B Shown Figure 3 The steps of an example method of manufacturing the structure shown;

[0028] Figure 8C Shown Figure 3 The steps of an example method of manufacturing the structure shown;

[0029] Figure 8D Shown Figure 3 The steps of an example method of manufacturing the structure shown;

[0030] Figure 8E Shown Figure 3 The steps of an example method of manufacturing the structure shown;

[0031] Figure 8F Shown Figure 3 The steps of an example method of manufacturing the structure shown;

[0032] Figure 9 A schematic cross-sectional structure of a portion of a pixel circuit in Embodiment 2 is shown;

[0033] Figure 10 Schematically shows a cross-sectional structure of a CMOS circuit in Embodiment 2;

[0034] Figure 11 is a cross-sectional view showing an example of the configuration of an oxide semiconductor TFT in Embodiment 3;

[0035] Figure 12 is a cross-sectional view of another configuration example of the oxide semiconductor TFT in Embodiment 3;

[0036] Figure 13A Shown Figure 11 The steps of an example of a method for manufacturing an oxide semiconductor TFT shown in FIG;

[0037] Figure 13B Shown Figure 11 The steps of an example of a method for manufacturing an oxide semiconductor TFT shown in FIG;

[0038] Figure 13C Shown Figure 11 The steps of an example of a method for manufacturing an oxide semiconductor TFT shown in FIG;

[0039] Figure 13D Shown Figure 11 The steps of an example of a method for manufacturing an oxide semiconductor TFT shown in FIG;

[0040] Figure 13E Shown Figure 11 The steps of an example of a method for manufacturing an oxide semiconductor TFT shown in FIG;

[0041] Figure 13F Shown Figure 11 The steps of an example of a method for manufacturing an oxide semiconductor TFT shown in FIG;

[0042] Figure 14 Shown with Figure 11 The oxide semiconductor TFT structure shown is applied to Figure 4 Examples of pixel circuits shown; and

[0043] Figure 15 Shown with Figure 11 The oxide semiconductor TFT structure shown is applied to Figure 7 An example of a CMOS circuit is shown. DETAILED DESCRIPTION

[0044] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the above embodiments are merely examples of implementing the present invention and are not intended to limit the technical scope of the present invention. Common elements in the drawings are represented by the same reference numerals, and some elements in the drawings are exaggerated in size or shape to facilitate a clearer understanding of the description.

[0045] Overview

[0046] The following description uses an organic light-emitting diode (OLED) display device as an example of a device including a thin-film transistor circuit. The OLED display device in the present invention includes low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) and oxide semiconductor TFTs in pixel circuits and / or peripheral circuits. An example of an oxide semiconductor is indium gallium zinc oxide (IGZO).

[0047] Oxide semiconductor TFTs generate little leakage current, so, for example, they can be used as switching transistors connected to a storage capacitor (capacitive element) for maintaining the gate potential of a drive transistor in a pixel circuit. For example, a low-temperature polysilicon TFT with high mobility can be used as a drive transistor. The configuration of the present invention can be applied to devices other than display devices.

[0048] In one embodiment, an oxide semiconductor TFT has a top-gate structure, and its gate insulator portion is made of a high-k insulator having a high relative dielectric constant. The high-k insulator described below has a relative dielectric constant of not less than 8. Using an insulator with a high relative dielectric constant for the gate insulator portion improves the on-current characteristics of the oxide semiconductor TFT, thereby enabling a smaller device size or lower drive voltage. One example of a high-k insulator has a relative dielectric constant of not more than 100, and another example has a relative dielectric constant of not more than 50.

[0049] In a thin film transistor circuit having a stacked structure, the gate electrode portion of the oxide semiconductor TFT is included in one conductor layer, and the gate insulator portion of the oxide semiconductor TFT is included in one high-k insulator layer. The oxide semiconductor portion of the oxide semiconductor TFT is included in one oxide semiconductor layer.

[0050] The gate electrode portion, the gate insulator portion, and the oxide semiconductor portion are part of the oxide semiconductor TFT, and each of them is all or part of a film of a specific material. One layer is made of the same material by the same process and can be composed of one unseparated film or multiple separated films. One film can have a single-layer structure or a multi-layer structure.

[0051] In one embodiment, an oxide semiconductor TFT includes compound interface portions, each of which has an interface with the source / drain region and the source / drain electrode portion of the oxide semiconductor portion. The compound interface portions include an element constituting a high-k insulator of a metal compound and an element constituting an oxide semiconductor and have a resistance lower than that of the source / drain region. These compound interface portions reduce the contact resistance of the source / drain electrode portion and improve the on-current characteristics of the oxide semiconductor TFT.

[0052] Implementation Method 1

[0053] Display device configuration

[0054] Figure 1 An example configuration of an OLED display device 1 is schematically shown. The OLED display device 1 includes a thin film transistor (TFT) substrate 10 on which an organic light-emitting element (OLED element) and pixel circuit are fabricated, an encapsulation substrate 20 for encapsulating the organic light-emitting element, and a bonding portion (glass frit sealant) 30 for bonding the TFT substrate 10 to the encapsulation substrate 20. The space between the TFT substrate 10 and the encapsulation substrate 20 is filled with dry nitrogen and sealed with the bonding portion 30. The encapsulation substrate 20 and the bonding portion 30 constitute a structural encapsulation unit. The structural encapsulation unit may be a thin film encapsulation (TFE) unit.

[0055] A scan driver 31, an emission driver 32, a protection circuit 33, a driver IC 34, and a demultiplexer 36 are provided around the cathode electrode region 14 outside the display region 25 of the TFT substrate 10. The driver IC 34 is connected to an external device via a flexible printed circuit (FPC) 35. The scan driver 31, the emission driver 32, and the protection circuit 33 are peripheral circuits fabricated on the TFT substrate 10.

[0056] The scanning driver 31 drives the scanning lines on the TFT substrate 10. The emission driver 32 drives the emission control lines to control the light emission period of the pixels. The driver IC 34 is mounted with, for example, an anisotropic conductive film (ACF).

[0057] The protection circuit 33 protects elements in the pixel circuit from electrostatic discharge. The driver IC 34 supplies power and timing signals (control signals) to the scan driver 31 and the emission driver 32, and also supplies power and data signals to the demultiplexer 36.

[0058] The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d data lines (d is an integer greater than 1). The demultiplexer 36 switches the data line to which the data signal is output from the driver IC 34 d times per scanning period to drive data lines that are d times the number of output pins of the driver IC 34.

[0059] Pixel circuit configuration

[0060] A plurality of pixel circuits are formed on the TFT substrate 10 to control the current supplied to the anode electrode portion of the sub-pixel (also simply referred to as pixel). Figure 2 1 shows an example configuration of a pixel circuit. Each pixel circuit includes a drive transistor T1, a select transistor T2, an emission transistor T3, and a storage capacitor C1. The pixel circuit controls the light emission of the OLED element E1. The transistors are TFTs. Transistors other than the drive transistor T1 are switching transistors.

[0061] The selection transistor T2 is a switch for selecting a sub-pixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, and its gate terminal is connected to the scanning line 16. Its source terminal is connected to the data line 15. Its drain terminal is connected to the gate terminal of the driving transistor T1.

[0062] The drive transistor T1 is a transistor (drive TFT) for driving the OLED element E1. The drive transistor T1 is a p-channel low-temperature polysilicon TFT, and its gate terminal is connected to the drain terminal of the select transistor T2. The source terminal of the drive transistor T1 is connected to the drain terminal of the emission transistor T3, and the drain terminal of the drive transistor T1 is connected to the OLED element E1. A storage capacitor C1 is provided between the gate terminal of the drive transistor T1 and the power supply line 18.

[0063] Emission transistor T3 is a switch for controlling the supply and stop of drive current to OLED element E1. Emission transistor T3 is a p-channel low-temperature polysilicon TFT, and its gate is connected to emission control line 17. The source terminal of emission transistor T3 is connected to power supply line 18, and the drain terminal of emission transistor T3 is connected to the source terminal of drive transistor T1.

[0064] Next, the operation of the pixel circuit will be described. Scan driver 31 outputs a select pulse to scan line 16, turning on select transistor T2. A data voltage supplied from driver IC 34 via data line 15 is stored in storage capacitor C1. Storage capacitor C1 holds the stored voltage for the duration of a frame. The conductance of drive transistor T1 varies in an analog manner based on the stored voltage, causing drive transistor T1 to supply a forward bias current corresponding to the light emission level to OLED element E1.

[0065] Emission transistor T3 is located in the drive current supply path. Emission driver 32 outputs a control signal to emission control line 17 to control the on / off switching of emission transistor T3. When emission transistor T3 is on, drive current is supplied to OLED element E1. When emission transistor T3 is off, this supply of drive current is stopped. By controlling the on / off switching of transistor T3, the lighting period (duty cycle) within a frame period can be controlled. Figure 2 The circuit configuration in FIG. 1 is just one example; the pixel circuit can have a different configuration.

[0066] TFT substrate configuration

[0067] Hereinafter, a configuration example of a TFT substrate including a low-temperature polysilicon TFT and an oxide semiconductor TFT will be described. The oxide semiconductor may be IGZO. The configuration described in this specification can be applied to circuits including TFTs of other types of oxide semiconductors.

[0068] Figure 3 The cross-sectional structure of a portion of the TFT substrate is schematically shown. A low-temperature polysilicon TFT 141, an oxide semiconductor TFT 142, a storage capacitor 143, and an OLED element 144 are fabricated on an insulating substrate 101. These elements correspond to Figure 2 The driving transistor T1, the selecting transistor T2, the storage capacitor C1 and the OLED element E1 in FIG.

[0069] Insulating substrate 101 is a flexible or non-flexible substrate made of resin or glass. Low-temperature polysilicon TFT 141 includes low-temperature polysilicon portion 102. Low-temperature polysilicon portion 102 may be an island-shaped low-temperature polysilicon active film and includes source / drain regions 104 and 105 and a channel region 103 sandwiched in-plane between source / drain regions 104 and 105.

[0070] Source / drain regions 104 and 105 are made of low-temperature polysilicon with reduced resistance caused by doping with high-concentration impurities; they are connected to source / drain electrode portions 109 and 110. Channel region 103 is made of low-temperature polysilicon with unreduced resistance (high-resistance low-temperature polysilicon).

[0071] The low temperature polysilicon portion 102 is included in the low temperature polysilicon layer. The low temperature polysilicon layer includes the low temperature polysilicon portion of the low temperature polysilicon TFT in the plurality of pixel circuits. The low temperature polysilicon layer is directly formed on the insulating substrate 101. Figure 3 The low-temperature polysilicon portion 102 in the example is in contact with the insulating substrate 101 , but another insulator layer such as a silicon nitride layer may be provided therebetween.

[0072] The low-temperature polysilicon TFT 141 has a top gate structure. In addition to the top gate, the low-temperature polysilicon TFT 141 may also have a bottom gate. The same applies to other embodiments. The low-temperature polysilicon TFT 141 also includes a gate electrode portion 107 and a gate insulator portion 106 located between the gate electrode portion 107 and the channel region 103 in the stacking direction. The gate insulator portion 106 is included in the insulating layer including the gate insulator portions of other low-temperature polysilicon TFTs. The channel region 103, the gate insulator portion 106, and the gate electrode portion 107 are arranged in this order from the bottom (the side closer to the insulating substrate 101); the gate insulator portion 106 is in contact with the channel region 103 and the gate electrode portion 107.

[0073] The gate electrode portion 107 is made of a conductor and is included in the conductor layer. The gate electrode portion 107 may be made of a metal. For example, the metal material may be desirably selected from Mo, W, Nb, and Al. Figure 3 In the configuration example shown in FIG1 , the metal film comprising gate electrode portion 107 and the insulating film comprising gate insulator portion 106 have an island shape; the entire insulating film is covered by the metal film. In this example, gate insulator portion 106 is made of silicon oxide and is contained within the silicon oxide layer. This configuration provides high operational stability for low-temperature polysilicon TFT 141.

[0074] An interlayer insulating film 108 is provided to cover the low-temperature polysilicon portion 102, the gate insulator portion 106, and the gate electrode portion 107. The interlayer insulating film 108 may be a silicon oxide film or a silicon nitride film. Source / drain electrode portions 109 and 110 are provided above the interlayer insulating film 108 and are connected to the source / drain regions 104 and 105 via contact holes in the interlayer insulating film 108. The material of the source / drain electrode portions 109 and 110 may be, for example, Al or Ti.

[0075] The storage capacitor 143 includes a lower electrode portion 111, an upper electrode portion 120 opposite to the lower electrode portion 111, and an insulator portion 118 sandwiched between the lower electrode portion 111 and the upper electrode portion 120. The lower electrode portion 111 is located above the interlayer insulating film 108 and is continuous with the source / drain electrode portion 110. The lower electrode portion 111 is included in the same conductor layer as the source / drain electrode portions 109 and 110.

[0076] Another interlayer insulating film 112 is placed above the interlayer insulating film 108. The interlayer insulating film 112 may be a silicon oxide film. The interlayer insulating film 112 is provided to cover the lower electrode portion 111, the source / drain electrode portions 109 and 110, and the interlayer insulating film 108. The interlayer insulating film 112 has an opening in the portion between the lower electrode portion 111 and the upper electrode portion 120. The insulator portion 118 is provided inside the opening and around the periphery of the opening.

[0077] The insulator portion 118 is made of a high-k insulator; it is in contact with the lower electrode portion 111 within the opening, and the top surface of the insulator portion 118 is in contact with the upper electrode portion 120. The entire insulating portion of the storage capacitor 143 is composed of the high-k insulator portion 118 and a portion of the interlayer insulating film 112. In one embodiment of the present specification, the high-k insulator can be a metal compound, such as a metal oxide or a metal nitride. For example, TaOx, AlOx, HfOx, ZrOx, YOx, or NbOx can be used. The configuration in which at least a portion of the insulator portion 118 is located in the opening increases the average relative dielectric constant of the storage capacitor 143, thereby obtaining a higher electrostatic capacitance.

[0078] Oxide semiconductor TFT 142 includes oxide semiconductor portion 113. Oxide semiconductor portion 113 may be an island-shaped oxide semiconductor active film and includes source / drain regions 115 and 116 and channel region 114 sandwiched between source / drain regions 115 and 116 in the in-plane direction.

[0079] The source / drain regions 115 and 116 are made of IGZO with reduced resistance; they are connected to the source / drain electrode portions 122 and 123. The channel region 114 is made of IGZO with unreduced resistance (high-resistance IGZO).

[0080] The oxide semiconductor portion 113 is included in an oxide semiconductor layer. The oxide semiconductor layer includes oxide semiconductor portions of a plurality of oxide semiconductor TFTs. The oxide semiconductor layer is provided over the interlayer insulating film 112 .

[0081] The oxide semiconductor TFT 142 has a top gate structure. In addition to the top gate, the oxide semiconductor TFT 142 may also have a bottom gate. The same applies to other embodiments. The oxide semiconductor TFT 142 further includes a gate electrode portion 119 and a gate insulator portion 117 located between the gate electrode portion 119 and the channel region 114 in the stacking direction. The channel region 114, the gate insulator portion 117, and the gate electrode portion 119 are arranged in this order from the bottom (the side close to the insulator substrate 101); the gate insulator portion 117 is in contact with the channel region 114 and the gate electrode portion 119.

[0082] The gate electrode portion 119 is made of a conductor and included in a conductor layer. The gate electrode portion 119 may be made of a metal. For example, the metal material may be desirably selected from Mo, W, Nb, and Al.

[0083] The gate insulator portion 117 is included in a high-k insulator layer made of a high-k insulator. The high-k insulator layer includes an insulator portion 118 of the storage capacitor 143. The high-k insulator layer includes the insulator portions of the oxide semiconductor TFTs of the plurality of pixel circuits and the storage capacitors. Figure 3 In the configuration example, the metal film including the gate electrode portion 119 and the insulating film including the gate insulator portion 117 have an island shape; the entire region of the insulating film is covered with the metal film. Figure 3 One low-temperature polysilicon TFT and one oxide semiconductor TFT are shown, but the other low-temperature polysilicon TFTs and oxide semiconductor TFTs in the pixel circuit have the same structure.

[0084] The interlayer insulating film 121 is provided to cover the oxide semiconductor portion 113, the gate insulator portion 117, and the gate electrode portion 119 of the oxide semiconductor TFT 142, and the insulator portion 118 and the upper electrode portion 120 of the storage capacitor 143. The interlayer insulating film 121 covers a portion of the interlayer insulating film 112. The interlayer insulating film 121 may be a silicon oxide film.

[0085] The source / drain electrode portions 122 and 123 of the oxide semiconductor TFT 142 are provided above the interlayer insulating film 121. The source / drain electrode portions 122 and 123 are connected to the source / drain regions 115 and 116 of the oxide semiconductor TFT 142 through contact holes in the interlayer insulating film 121.

[0086] The connection portion 129, which is continuous from the source / drain electrode portion 123, is connected to the upper electrode portion 120 of the storage capacitor 143 through a contact hole opened through the interlayer insulating film 121 and is further connected to the gate electrode portion 107 of the low-temperature polysilicon TFT 141 through a contact hole opened through the interlayer insulating films 121, 112, and 108. The connection portion 129 connects the source / drain electrode portion 123, the upper electrode portion 120, and the gate electrode portion 107 to each other. The source / drain electrode portions 122 and 123 and the connection portion 129 are included in a conductor layer. The material of the conductor layer is selected as desired; for example, Al or Ti can be used.

[0087] An insulating planarizing film 124 is arranged to cover the exposed portion of the conductive layer and the interlayer insulating film 121. The planarizing film 124 can be made of an organic material. An anode electrode portion 125 is provided above the planarizing film 124. The anode electrode portion 125 is connected to the source / drain electrode portion 109 of the low-temperature polysilicon TFT 141 via a contact hole opened through the planarizing film 124 and the interlayer insulating films 121 and 112.

[0088] The anode electrode portion 125 may include three layers, namely, a transparent film of ITO or IZO, a reflective film of a metal such as Ag, Mg, Al, or Pt, or an alloy containing such a metal, and another transparent film, for example, as described above. This three-layer structure of the anode electrode portion 125 is only an example; the anode electrode portion 125 may have a two-layer structure.

[0089] An insulating pixel-defining layer 126 is disposed above the anode electrode portion 125 to isolate the OLED element 144. The pixel-defining layer 126 can be made of an organic material. An organic light-emitting film 127 is disposed above the anode electrode portion 125. The organic light-emitting film 127 is composed, for example, of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, in that order from the bottom. The stacked structure of the organic light-emitting film 127 is determined according to the design.

[0090] Furthermore, a cathode electrode portion 128 is provided above the organic light-emitting film 127. The cathode electrode portion 128 of one OLED element 144 is a portion of the unseparated conductive film. The cathode electrode portion 128 transmits a portion of the visible light from the organic light-emitting film 127. The stack of the anode electrode portion 125, the organic light-emitting film 127, and the cathode electrode portion 128 provided within the opening of the pixel-defining layer 126 corresponds to the OLED element 144.

[0091] Figure 4 The cross-sectional structure of another portion of the TFT substrate is schematically shown. Figure 4 Not included Figure 3 The OLED element 144 is not included in the TFT 142, but includes a scan line 130 for transmitting a selection signal for selecting a sub-pixel to which a data signal is to be supplied. The scan line 130 is provided above the planarization film 124 and is connected to the gate electrode portion 119 of the oxide semiconductor TFT 142 via a contact hole opened through the planarization film 124 and the interlayer insulating film 121.

[0092] Figure 4Reference numerals are provided for layers including conductive elements. In the following example, the conductive layer is a metal layer. Specifically, the gate electrode portion 107 of the low-temperature polysilicon TFT 141 is included in the metal layer M1. The lower electrode portion 111 of the storage capacitor 143 and the source / drain electrode portions 109 and 110 of the low-temperature polysilicon TFT 141 are included in the metal layer M2.

[0093] The gate electrode portion 119 of the oxide semiconductor TFT 142 and the upper electrode portion 120 of the storage capacitor 143 are included in the metal layer M3. The source / drain electrode portions 122 and 123 and the connection portion 129 of the oxide semiconductor TFT 142 are included in the metal layer M4. The scan line 130 is included in the metal layer M5. As described above, the gate insulator portion of the oxide semiconductor TFT 142 and the insulator portion of the storage capacitor 143 are included in the same high-k insulator layer.

[0094] Figure 5 1 is a top view of a portion of a TFT substrate. Metal film 151 included in the lowest metal layer M1 includes gate electrode portion 107 of low-temperature polysilicon TFT 141. Gate electrode portion 107 may be the overlapping portion of metal film 151 and low-temperature polysilicon portion 102 when viewed in a plan view (in the stacking direction).

[0095] The metal layer M2 above the metal layer M1 includes metal films 152 and 153. The metal film 152 includes the source / drain electrode portion 109 of the low-temperature polysilicon TFT 141. The metal film 153 includes the source / drain electrode portion 110 of the low-temperature polysilicon TFT 141 and the lower electrode portion 111 of the storage capacitor 143. The lower electrode portion 111 may be an overlapping portion of the metal film 153 and the upper electrode portion 120 of the storage capacitor 143 when viewed in a plan view.

[0096] The metal layer M3 above the metal layer M2 includes a metal film 154 and a metal film corresponding to the upper electrode portion 120 of the storage capacitor 143. The metal film 154 includes the gate electrode portion 119 of the oxide semiconductor TFT 142 and a connection portion connecting the scan line 130 and the gate electrode portion 119. The gate electrode portion 119 may be an overlapping portion of the metal film 154 and the oxide semiconductor portion 113 when viewed in a planar manner (in the stacking direction). The upper electrode portion 120 is composed of a metal film. The upper electrode portion 120 is smaller than the metal film 153, and the outer periphery of the upper electrode portion 120 is located on the inner side of the outer periphery of the metal film 153; the entire upper electrode portion 120 is located within the area of ​​the metal film 153.

[0097] A high-k insulator film including gate insulator portion 117 is provided directly below metal film 154. The entire region of this insulator film is covered by metal film 154. In one example, the outer periphery of this insulator film coincides with the outer periphery of metal film 154. Furthermore, insulator portion 118 of storage capacitor 143, which is a high-k insulator film, is provided directly below upper electrode portion 120 of storage capacitor 143. The entire region of this insulator portion (insulator film) 118 is covered by upper electrode portion 120. In one example, the outer periphery of this insulator portion 118 coincides with the outer periphery of upper electrode portion 120.

[0098] As described above, gate insulator portion 117 and insulator portion 118 are included in the same high-k insulator layer. The insulator films including the gate insulator portions of the other oxide semiconductor TFTs in the pixel circuit are all covered in the same manner by the metal film including the gate electrode portion. The gate insulator portions of all oxide semiconductor TFTs in the pixel circuit are included in the same high-k insulator layer. The entire area of ​​the high-k insulator layer including these insulator portions is covered by the metal layer M3 in the pixel circuit. This configuration suppresses the increase in parasitic capacitance caused by the high-k insulator.

[0099] Metal layer M4 above metal layer M3 includes metal film 155. Metal film 155 includes source / drain electrode portion 123 of oxide semiconductor TFT 142 and connection portion 129 connecting source / drain electrode portion 123, upper electrode portion 120, and gate electrode portion 107 of low-temperature polysilicon TFT 141.

[0100] Metal layer M5 above metal layer M4 includes scan line 130. Since scan line 130 connected to gate electrode portion 119 of oxide semiconductor TFT 142 is provided on a metal layer different from that of gate electrode portion 119, no high-k insulator is provided below scan line 130, thereby suppressing parasitic capacitance.

[0101] In one example of a pixel circuit, the conductor located below the high-k insulator layer and overlapping the high-k insulator layer when viewed in plan is only the lower electrode portion 111 of the storage capacitor 143. In addition, the semiconductor overlapping the high-k insulator layer is only the oxide semiconductor portion of all oxide semiconductor TFTs in the pixel circuit. This configuration effectively suppresses the generation of parasitic capacitance caused by the high-k insulator. The entire insulator portion of the storage capacitor 143 can be made of an insulator other than the high-k insulator (e.g., silicon oxide or silicon nitride).

[0102] Next, the configuration of the CMOS circuit included in the driving circuit 31 or 32 on the TFT substrate will be described. Figure 6An example of a CMOS circuit is shown. The CMOS circuit includes a p-channel low-temperature polysilicon TFT 201 and an n-channel oxide semiconductor TFT 202. The source / drain of the low-temperature polysilicon TFT 201 is connected to the source / drain of the n-channel oxide semiconductor TFT 202. The gate of the low-temperature polysilicon TFT 201 and the gate of the oxide semiconductor TFT 202 are connected and the same signal is supplied to them.

[0103] Figure 7 Schematically shows Figure 6 The cross-sectional structure of the CMOS circuit shown in FIG. Figure 3 The cross-sectional structure shown is different from the example. Figure 7 In the configuration example, the Figure 3 The storage capacitor 143 in the configuration example of is connected. Furthermore, the source / source electrode portion 210 of the low-temperature polysilicon TFT 201 and the source / drain electrode portion 223 of the oxide semiconductor TFT 202 are connected, and further, the gate electrode portion 207 and the gate electrode portion 219 are connected.

[0104] Figure 7 The low temperature polysilicon TFT 201 in the Figure 3 The low-temperature polysilicon TFT 201 has the same configuration as the low-temperature polysilicon TFT 141 in FIG. Their sizes may differ. The low-temperature polysilicon TFT 201 includes a low-temperature polysilicon portion 208, a gate insulator portion 206, and a gate electrode portion 207. The low-temperature polysilicon portion 208 includes a channel region 203 and source / drain regions 204 and 205. Source / drain electrode portions 209 and 210 are connected to the source / drain regions 204 and 205 through contact holes in the interlayer insulating film 108.

[0105] The low-temperature polysilicon portion 208, the gate insulator portion 206, the gate electrode portion 207, and the source / drain electrode portions 209 and 210 correspond to Figure 3 The low-temperature polysilicon portion 102, the gate insulator portion 106, the gate electrode portion 107, and the source / drain electrode portions 109 and 110 are included in the same layer as the corresponding element.

[0106] Figure 7 The oxide semiconductor TFT 202 in the Figure 3 The oxide semiconductor TFT 202 has the same configuration as the oxide semiconductor TFT 142 in FIG. Their sizes may be different. The oxide semiconductor TFT 202 includes an oxide semiconductor portion 213, a gate insulator portion 217, and a gate electrode portion 219. The oxide semiconductor portion 213 includes a channel region 214 and source / drain regions 215, 216. The oxide semiconductor portion 213, the gate insulator portion 217, and the gate electrode portion 219 correspond to Figure 3 The oxide semiconductor portion 113, the gate insulator portion 117, and the gate electrode portion 119 are included in the same layer as the corresponding element.

[0107] The connection portion 229 is continuous from the source / drain electrode portion 223 of the oxide semiconductor TFT 202 and is connected to the source / drain electrode portion 210 of the low-temperature polysilicon TFT 201 through a contact hole opened through the interlayer insulating films 112 and 121. The connection portion 230 is connected to the gate electrode portion 219 of the oxide semiconductor TFT 202 through a contact hole opened through the interlayer insulating film 121 and the planarizing film 124. The connection portion 230 is also connected to the gate electrode portion 207 of the low-temperature polysilicon TFT 201 through a contact hole opened through the interlayer insulating films 108, 112, and 121 and the planarizing film 124. The connection portion 230 is included in the metal layer M5.

[0108] Similar to reference Figure 3 In the configuration described above, the gate insulator portion 217 of the oxide semiconductor TFT 202 is included in the high-k insulator layer. In the driver circuits 31 and 32, the entire region of the insulating film including the gate insulator portion of each oxide semiconductor TFT is covered by the metal film including the gate electrode portion of the oxide semiconductor TFT.

[0109] The gate insulator portions of all oxide semiconductor TFTs in the driver circuits 31 and 32 are included in the same high-k insulator layer. In the CMOS circuit, the entire area of ​​the high-k insulator layer including these insulator portions is covered by the metal layer including the gate electrode portion 219 of the oxide semiconductor TFT 202. This configuration of the insulator layer suppresses the increase in parasitic capacitance caused by the high-k insulator. In one example, the periphery of each high-k insulator film coincides with the periphery of the metal film covering it.

[0110] In the driver circuits 31 and 32, the conductors and semiconductors located below and overlapping the high-k insulator layer when viewed in plan are simply the oxide semiconductor portion of one or more oxide semiconductor TFTs in the driver circuits, or the oxide semiconductor portion of one or more oxide semiconductor TFTs in the driver circuits and the lower electrode portion of one or more capacitors. This configuration effectively suppresses the generation of parasitic capacitance caused by the high-k insulator.

[0111] Manufacturing method

[0112] Reference Figures 8A to 8F describe Figure 3 The manufacturing method of the structure shown in Figure 8AAs shown, this process produces a low-temperature polysilicon TFT 141. This process begins by forming a low-temperature polysilicon portion 102 on an insulating substrate 101. Specifically, this process deposits amorphous silicon by CVD (chemical vapor deposition) and crystallizes the amorphous silicon by excimer laser annealing to form a low-temperature polysilicon film. This process then patterns the low-temperature polysilicon film by photolithography to form island-shaped polysilicon portions 102.

[0113] Next, the manufacturing process forms an insulator layer (eg, SiOx film) including the gate insulator portion 106 by, for example, CVD. Furthermore, the manufacturing process forms a metal layer M1 (see FIG. 1 ) by sputtering. Figure 4 ) The metal layer M1 and the insulator layer are patterned (etched) together by photolithography (in the same process using the same mask) to form the gate electrode portion 107 and the gate insulator portion 106. As a result of this process, the insulator remains only below the metal layer M1. Another example of manufacturing is to first etch the metal layer including the gate electrode portion 107, and then etch the insulator layer thereunder using the metal layer M1 as a mask.

[0114] Furthermore, the manufacturing process implants impurities into the low temperature polysilicon portion 102 using the gate electrode portion 107 as a mask to generate low resistance regions 104 and 105. The high resistance region covered by the gate electrode portion 107 corresponds to the channel region 103.

[0115] Next, the fabrication forms an interlayer insulating film 108 by CVD, and further opens contact holes in the laminated insulating film by anisotropic etching. Further, the fabrication forms a metal layer M2 by sputtering (see Figure 4 ) and patterning the metal layer M2 by photolithography to form source / drain electrode portions 109 and 110 and a lower electrode portion 111 of the storage capacitor 143 (see Figure 4 ).

[0116] Next, refer to Figure 8B In this manufacturing, an interlayer insulating film 112 is formed on the interlayer insulating film 108 and the source / drain electrode portions 109 and 110 by CVD. Next, an oxide semiconductor layer is formed by sputtering and patterned by photolithography. As a result, an island-shaped oxide semiconductor portion 113 (see FIG. 14 ) of the oxide semiconductor TFT 142 is formed. Figure 4 ).

[0117] Next, refer to Figure 8C , which removes a portion of the interlayer insulating film 112 by etching to expose a portion of the lower electrode portion 111 of the storage capacitor 143 from the opening of the interlayer insulating film 112 (see Figure 4 ).

[0118] Next, refer to Figure 8DThe manufacturing process forms a high-k insulator film by sputtering. The manufacturing process further forms a metal layer M3 (see Figure 4 ). This manufacturing is to pattern (etch) the metal layer M3 and the high-k insulator film together by photolithography (through the same process using the same mask) to form the gate electrode portion 119 of the oxide semiconductor TFT 142, the upper electrode portion 120 of the storage capacitor 143, the gate insulator portion 117 of the oxide semiconductor TFT 142, and the insulator portion 118 of the storage capacitor 143.

[0119] As a result of this process, the high-k insulator remains only below the metal layer M3 and the remaining active area of ​​the high-k insulator layer is entirely covered by the metal layer M3. Another example of manufacturing is to pattern the metal layer M3 to form the gate electrode portion 119 and the upper electrode portion 120, and then pattern the high-k insulator layer using the metal layer (metal pattern) M3 as a mask. The insulator portion 118 of the storage capacitor 143 is also disposed within the opening in the interlayer insulating film 112. This configuration increases the average relative dielectric constant of the storage capacitor 143, thereby providing a higher electrostatic capacitance for the storage capacitor 143.

[0120] Next, refer to Figure 8E This manufacturing process uses the gate electrode portion 119 as a mask to reduce the resistance of the end regions 115 and 116 of the oxide semiconductor portion 113. The resistance can be reduced by exposing the oxide semiconductor portion 113 in the region not covered by the gate electrode portion 119 to He plasma. The region 114 covered by the gate electrode portion 119 corresponds to the high-resistance channel region. This resistance reduction can be performed in the next step of forming the interlayer insulating film 121.

[0121] Next, refer to Figure 8F The manufacturing process forms an interlayer insulating film 121 by CVD, and anisotropically etches the interlayer insulating film 121 by photolithography to open contact holes. Further, the manufacturing process forms a metal layer M4 (see FIG. 1 ) by sputtering. Figure 4 ) and patterning the metal layer M4 by photolithography. As a result, the source / drain electrode portions 122 and 123 and the connection portion 129 of the oxide semiconductor TFT 142 are formed.

[0122] Although not shown in the figure, the manufacturing process further forms a planarization film 124 and a metal layer M5, and then forms an anode electrode portion 125. In addition, the manufacturing process forms a pixel defining layer 126, and then forms an organic light-emitting film on the anode electrode portion 125. The organic light-emitting film is formed by vapor deposition at positions corresponding to pixels through a metal mask. The manufacturing process further deposits a metal material for the cathode electrode portion 128.

[0123] Implementation Method 2

[0124] An example of a circuit including an oxide semiconductor TFT having a structure different from that in Embodiment Mode 1 is described below. Figure 9 The cross-sectional structure of a portion of the pixel circuit is schematically shown. Figure 3 Differences from the configuration shown.

[0125] The gate insulator portion of the oxide semiconductor TFT 142 is composed of a plurality of stacked insulator portions, specifically, a high-k insulator portion 136 and an interface insulator portion 135. The interface insulator portion 135 has an interface with the high-k insulator portion 136 and the oxide semiconductor portion 113.

[0126] In one example, the interface insulator portion 135 is included in a silicon-based insulator layer that includes the interface insulator portion of another oxide semiconductor TFT. An example of a silicon-based insulator layer is made of silicon oxide (SiOx). Another example is made of silicon nitride. Interposing the silicon-based insulator between the high-k insulator and the oxide semiconductor stabilizes the characteristics of the oxide semiconductor TFT 142.

[0127] The relative dielectric constant of silicon oxide is lower than that of the high-k insulator. The interface insulator portion 135 may be thinner than the high-k insulator portion 136. This configuration prevents the overall relative dielectric constant of the gate insulator portion from being low.

[0128] In another example, interface insulator portion 135 is made of a high-k insulator containing carbon (carbon-containing high-k insulator), and high-k insulator portion 136 is made of a high-k insulator substantially free of carbon (carbon-free high-k insulator). Interface insulator portion 135 is included in a carbon-containing high-k insulator layer that includes the interface insulator portion of another oxide semiconductor TFT. High-k insulator portion 136 is included in a carbon-free high-k insulator layer that includes the high-k insulator portion of another oxide semiconductor TFT. Interposing the carbon-containing high-k insulator between the carbon-free high-k insulator and the oxide semiconductor stabilizes the characteristics of oxide semiconductor TFT 142.

[0129] At the same time, when the carbon concentration in the carbon-containing high-k insulator is not less than 1×10 18 cm -3 The carbon concentration in carbon-free high-k insulators is less than 1×10 18 cm -3 When , the characteristics of the oxide semiconductor TFT 142 are more stable.

[0130] The interface insulator portion 135 made of a carbon-containing high-k insulator can be thinner than the high-k insulator portion 136 made of a carbon-free high-k insulator. The carbon-free high-k insulator can be formed into a film by conventional sputtering. On the other hand, the carbon-containing high-k insulator is formed into a film by atomic layer deposition (ALD), which is a CVD process using an organic metal as a precursor. The film formation time of the carbon-containing high-k insulator is longer than that of the carbon-free high-k insulator. Therefore, the above-mentioned film thickness relationship achieves a shorter process time.

[0131] exist Figure 9 In the configuration example of FIG, the insulator portion of storage capacitor 143 is composed as a whole of interface insulator portion 137, high-k insulator portion 138, and a portion of interlayer insulating film 112. Interface insulator portion 137 is included in the same layer as interface insulator portion 135. High-k insulator portion 138 is included in the same layer as high-k insulator portion 136.

[0132] Metal layer M3, the insulator layer including interface insulator portions 135 and 137, and the insulator layer including high-k insulator portions 136 and 138 have the same planar shape. These stacked structures can be formed by etching the two insulator layers together with metal layer M3 (in the same process using the same mask) or by etching the two insulator layers using metal layer M3 as a mask. Interface insulator portion 137 is optional.

[0133] Figure 10 The cross-sectional structure of the CMOS circuit is schematically shown. Figure 7 . The gate insulator portion of the oxide semiconductor TFT 202 is composed of a high-k insulator portion 236 and an interface insulator portion 235. The high-k insulator portion 236 may be included in the same layer as the high-k insulator portions 136 and 138. The interface insulator portion 235 may be included in the same layer as the interface insulator portions 135 and 137.

[0134] The interface insulator portion 235 has an interface with the high-k insulator portion 236 and the oxide semiconductor portion 213. In one example, the interface insulator portion 235 can be made of silicon oxide (SiOx). Interposing silicon oxide between the high-k insulator and the oxide semiconductor stabilizes the characteristics of the oxide semiconductor TFT 202.

[0135] The interface insulator portion 235 may be thinner than the high-k insulator portion 236. This configuration prevents the overall relative dielectric constant of the gate insulator portion from becoming low.

[0136] In another example, the interface insulator portion 235 is made of a carbon-containing high-k insulator, and the high-k insulator portion 236 is made of a carbon-free high-k insulator. This configuration stabilizes the characteristics of the oxide semiconductor TFT 202. The interface insulator portion 235 made of a carbon-containing high-k insulator can be thinner than the high-k insulator portion 236 made of a carbon-free high-k insulator. This film thickness relationship enables a shorter process time.

[0137] Implementation 3

[0138] Another configuration example of an oxide semiconductor TFT is described below. The oxide semiconductor TFT described below includes a compound layer of a high-k insulator and an oxide semiconductor as an interface layer between the low-resistance region of the oxide semiconductor portion and the source / drain electrode portion. The interface layer has an interface with each low-resistance region and each source / drain electrode portion. The interface layer provides good contact characteristics between the low-resistance region and the source / drain electrode portion of the oxide semiconductor TFT.

[0139] Described below is an oxide semiconductor TFT having a top gate structure, but the interface layer may be applied to an oxide semiconductor TFT having a bottom gate in addition to a top gate.

[0140] Figure 11 : This is a cross-sectional view of an example of such an oxide semiconductor TFT configuration. The oxide semiconductor TFT is fabricated on an insulating substrate 301. An example of an oxide semiconductor is IGZO. The oxide semiconductor TFT includes an oxide semiconductor portion 311. The oxide semiconductor portion 311 may be an island-shaped oxide semiconductor active film and includes source / drain regions (low resistance regions) 315 and 316 and a channel region (high resistance region) 314 between the source / drain regions 315 and 316 in the in-plane direction.

[0141] The source / drain regions 315 and 316 are made of an oxide semiconductor with reduced resistance. The channel region 314 is made of an oxide semiconductor with unreduced resistance. A mixture interface portion 317 made of a mixture of an oxide semiconductor and a high-k insulator is provided above the channel region 314. The high-k insulator may be the high-dielectric metal compound mentioned in Embodiment 1 or a ferroelectric metal compound having remanent polarization (e.g., PZT). The mixture interface portion 317 has an interface with the gate insulator portion 321 made of the high-k insulator and the channel region 314.

[0142] Compound interface portions (first and second compound interface portions) 318 and 319 made of a compound of an oxide semiconductor and a high-k insulator are provided above the source / drain regions 315 and 316. The source / drain regions 315 and 316 are connected to the source / drain electrode portions 322 and 323 via the compound interface portions 318 and 319. The compound interface portion 318 interfaces with the source / drain electrode portion 323 and the source / drain region 315, and the compound interface portion 319 interfaces with the source / drain electrode portion 322 and the source / drain region 316.

[0143] In the use of InGaZnO x As an oxide semiconductor, AlO y As an example of a high-k insulator, the mixture interface portion 317 can be represented as (IGZO x +AlO y The compound interface portions 318 and 319 can be represented as (IGZO x-1 AlO y+1 ). As noted from this example, in the compound interface portions 318 and 319, oxygen deficiency in the oxide semiconductor increases.

[0144] As a result, the resistance of the compound interface portions 318 and 319 becomes lower than the resistance of the source / drain regions 315 and 316, thereby achieving better contact characteristics and on-current characteristics. The resistance of the portion including the compound interface portions 318 and 319 and the source / drain regions 315 and 316 (the entire source / drain region of the TFT) is lower than the resistance of the same portion made solely of an oxide semiconductor in the past, thereby achieving higher on-current and drive capability.

[0145] Compound interface portions 318 and 319 may be composed not only of the aforementioned element oxide semiconductor and high-k insulator (e.g., In-Ga-Zn-Al-O), but also of elements contained in the process gas during the manufacturing step. For example, as described below, when the film is exposed to a fluorine-containing plasma, compound interface portions 318 and 319 may be composed of In-Ga-Zn-Al-F0. As described above, the high-k insulator may include Ta or Hf elements in addition to Al.

[0146] The gate electrode portion 320 is placed above the gate insulator portion 321. The gate electrode portion 320 is made of a conductor; for example, a metal such as Mo, W, Nb, or Al can be used. Similar to the configurations in the other embodiments described above, the entire region of the insulator layer including the gate insulator portion 321 is covered by the metal layer including the gate electrode portion 320 in the oxide semiconductor TFT.

[0147] An interlayer insulating film 324 is provided to cover the above-mentioned elements of the oxide semiconductor portion. Interlayer insulating film 324 may be a silicon oxide film. Source / drain electrode portions 322 and 323 of the oxide semiconductor TFT are provided above interlayer insulating film 324. Source / drain electrode portions 322 and 323 are connected to source / drain regions 315 and 316 via contact holes in interlayer insulating film 324 and compound interface portions 318 and 319.

[0148] Figure 12 1 is a cross-sectional view of another configuration example of an oxide semiconductor TFT. Figure 11 The configuration example in . Figure 12 In the oxide semiconductor TFT of the embodiment, the high-k insulator portion located between the gate electrode portion 320 and the oxide semiconductor portion 311 is included in the high-k insulator film 325 extending to the outside of the gate electrode portion 320. The high-k insulator film 325 covers the oxide semiconductor portion 311. Unlike the configurations in Embodiments 1 and 2, the compound interface portions 318 and 319 can be applied to circuits in which the high-k insulator extends from the region below the gate electrode portion to the outside of the gate electrode portion.

[0149] These compound interface portions are generated when the surface of the oxide semiconductor portion 311 is exposed to fluorine-containing plasma before depositing the high-k insulator film 325. The resistance of the compound interface portion is further reduced by the kinetic energy and thermal energy of particles (plasma particles and radical particles) during the formation of the high-k insulator film 325. Figure 11 and Figure 12 In the illustrated configuration, the gate insulator portion 321 may have a stacked structure of a lower high-k insulator and an upper low-k insulator having a relative dielectric constant lower than 8.

[0150] Next, refer to 13A to 13F describe Figure 11 An example of a method for manufacturing an oxide semiconductor TFT is shown. Figure 13A In this manufacturing process, an oxide semiconductor layer is formed on an insulating substrate 301 by sputtering and then patterned by photolithography. As a result, an island-shaped oxide semiconductor film 351 is formed.

[0151] Next, refer to Figure 13B This process forms a high-k insulator film 352 by sputtering. As a result, a mixture portion 354 of a high-k insulator and an oxide semiconductor is formed in the oxide semiconductor film 351. The layer below the mixture portion 354 is the oxide semiconductor portion 311 composed solely of an oxide semiconductor. Furthermore, this process forms a metal film 353 by sputtering.

[0152] Next, refer to Figure 13CThe manufacturing method etches the metal film 353 and the high-k insulator film 352 together by photolithography (through the same process using the same mask) to form the gate electrode portion 320 and the gate insulator portion 321. In another example, the manufacturing method etches the metal film 353 and then etches the high-k insulator film 352 using the gate electrode portion 320 as a mask to form the gate insulator film 321.

[0153] Next, refer to Figure 13D , which exposes the mixture portion 354 and the oxide semiconductor portion 311 to fluorine plasma in the area not covered by the gate electrode portion 320 used as a mask. As a result of this process, compound interface portions 318 and 319 and source / drain regions 315 and 316 are generated. The compound interface portions 318 and 319 may contain fluorine elements in addition to the elements constituting the oxide semiconductor and the high-k insulator. The area between the compound interface portions 318 and 319 corresponds to the mixture interface portion 317, and the area between the source / drain regions 315 and 316 corresponds to the high-resistance channel region 314. This process using fluorine plasma can be performed by Figure 13C This is achieved by exposing the mixture portion 354 and the oxide semiconductor portion 311 to plasma of a gas such as CF 4 after etching is performed.

[0154] Next, refer to Figure 13E , the interlayer insulating film 324 is formed by CVD. Next, referring to Figure 13F In this manufacturing process, the interlayer insulating film 324 is anisotropically etched by photolithography to open contact holes in the interlayer insulating film 324. Furthermore, a metal film is formed by sputtering and patterned by photolithography. As a result, the source / drain electrode portions 322 and 323 of the oxide semiconductor TFT are formed.

[0155] Figure 14 and Figure 15 shows that will have a reference Figure 11 The structure of the oxide semiconductor TFT described is applied to Figure 4 The pixel circuit shown and Figure 7 An example of a CMOS circuit is shown. Figure 14 In the pixel circuit of , the oxide semiconductor TFT 142 includes compound interface portions (a first compound interface portion and a second compound interface portion) 401 and 402. Figure 15 In the CMOS circuit of FIG. 1 , the oxide semiconductor TFT 202 includes compound interface portions (a first compound interface portion and a second compound interface portion) 405 and 406. These circuits exhibit the effects described in Embodiment Modes 1 and 3. As noted from these examples, the oxide semiconductor TFT in this embodiment mode can be applied to various circuits.

[0156] The compound interface portion described in Embodiment 3 and the interface insulator portion described in Embodiment 2 can be applied to one oxide semiconductor TFT. This configuration provides the oxide semiconductor TFT with higher operational stability and better on-current characteristics.

[0157] As described above, the embodiments of the present invention have been described; however, the present invention is not limited to the above-described embodiments. Those skilled in the art can easily modify, add, or convert the various elements in the above-described embodiments within the scope of the present invention. A portion of the configuration of one embodiment may be replaced with the configuration of another embodiment, or the configuration of one embodiment may be incorporated into the configuration of another embodiment.

Claims

1. An oxide semiconductor thin film transistor, comprising: an oxide semiconductor portion including a channel region and first and second source / drain regions sandwiching the channel region; a gate electrode portion; an insulator portion, the insulator portion being located between the gate electrode portion and the oxide semiconductor portion, the insulator portion being made of a metal compound having a relative dielectric constant of not less than 8; a first source / drain electrode portion; a second source / drain electrode portion; a first compound interface portion, the first compound interface portion having an interface with the first source / drain electrode portion and another interface with the first source / drain region, the first compound interface portion including a constituent element of the oxide semiconductor portion and a metal constituent element of the insulator portion; as well as A second compound interface portion has an interface with the second source / drain electrode portion and another interface with the second source / drain region, and the second compound interface portion contains constituent elements of the oxide semiconductor portion and metal constituent elements of the insulator portion.

2. The oxide semiconductor thin film transistor according to claim 1, wherein The metal compound is TaOx, AlOx, HfOx, ZrOx, YOx or NbOx.

3. The oxide semiconductor thin film transistor according to claim 2, wherein: The first compound interface portion and the second compound interface portion contain fluorine element.

4. The oxide semiconductor thin film transistor according to claim 2 , further comprising an interface insulator portion having an interface with the oxide semiconductor portion and another interface with the insulator portion, in, The relative dielectric constant of the interface insulator portion is not less than 8, The carbon concentration in the interface insulator portion is not less than 1×10 18 cm -3 , the carbon concentration in the insulator portion is less than 1×10 18 cm -3 . 5 . The oxide semiconductor thin film transistor according to claim 2 , further comprising a silicon-based insulator portion having an interface with the oxide semiconductor portion and another interface with the insulator portion.

6. A thin film transistor circuit comprising the oxide semiconductor thin film transistor according to claim 2, wherein: The entire region of the insulating layer including the insulator portion is covered by the conductive layer including the gate electrode portion.

7. The thin film transistor circuit according to claim 6, in, The conductive layer includes an upper electrode portion of the capacitor element, and The insulating layer includes an insulating portion of the capacitor element.

8. A method for manufacturing an oxide semiconductor thin film transistor, the method comprising: forming an oxide semiconductor layer including an oxide semiconductor portion of the oxide semiconductor thin film transistor; forming an insulator layer including a gate insulator portion of the oxide semiconductor thin film transistor on an upper layer of the oxide semiconductor layer so as to generate a mixture portion above the oxide semiconductor portion of the oxide semiconductor layer, wherein the insulator layer is made of a metal compound having a relative dielectric constant of not less than 8, and the mixture portion contains a constituent element of the oxide semiconductor layer and a metal constituent element of the insulator layer; forming a conductive layer including a gate electrode portion of the oxide semiconductor thin film transistor on an upper layer of the insulator layer; etching the conductor layer and the insulator layer to form the gate electrode portion and the gate insulator portion; and Source / drain regions are generated in the oxide semiconductor portion and a compound interface portion is generated in the mixture portion.

9. The method for manufacturing an oxide semiconductor thin film transistor according to claim 8, wherein: Generating the source / drain region and the compound interface portion includes exposing the areas of the oxide semiconductor portion and the mixture portion that are not covered by the gate electrode portion and the gate insulation portion to a fluorine-containing plasma, wherein the compound interface portion contains fluorine in addition to the constituent elements of the oxide semiconductor layer and the metal constituent elements of the insulator layer.

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