A method for reducing the probability of FPGA initialization failure caused by FLASH chip defects

Abstract

The application provides a method for reducing the probability of FPGA initialization failure caused by FLASH chip defects. By using the method, the electronic device can rewrite the configuration data stored in the FLASH chip in a predetermined period of time without changing the original hardware circuit, so as to reduce the probability of data invalidation caused by time accumulation of the FLASH chip.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic information manufacturing, and particularly relates to a method for reducing the probability of FPGA initialization failure caused by FLASH chip defects. BACKGROUND

[0002] SRAM type FPGA is widely used in electronic devices as a data processing unit of the device. The SRAM type FPGA needs to complete the initialization configuration process by loading the configuration file bit stream to the internal memory. The so-called initialization configuration refers to that after the power-on of the FPGA, the peripheral device (such as the FLASH configuration chip) starts to load the full bit stream file to the first configuration of all the logic resources in it, so as to realize the preset logic function of the FPGA. Since the configuration memory of the SRAM type FPGA is volatile, it needs to be reconfigured every time it is powered on, so it is necessary to externally connect a non-volatile memory storing the configuration file to complete the configuration file bit stream loading through the configuration interface. The more commonly used non-volatile configuration file memory is the FLASH type memory. The current mainstream FLASH chip used as a program memory is mainly of the NOR type. The NOR type FLASH chip uses a special floating gate field effect transistor as a storage unit. This field effect transistor has two gates, one of which is like the gate of a normal field tube and is led out by a wire, called the "selection gate"; the other is surrounded by silicon dioxide and not connected to any part, which is called the "floating gate". Under normal circumstances, the floating gate is not charged, and the field effect transistor is in a non-conductive state, and the drain level of the field effect transistor is high, which indicates data 1. When programming, the drain and selection gate of the field effect transistor are applied with a relatively high programming voltage, and the source is grounded. In this way, a large number of electrons flow from the source to the drain, forming a large current and generating a large number of hot electrons, which are captured by the silicon dioxide layer of the substrate. Since the density of electrons is large, some electrons reach the silicon dioxide layer between the substrate and the floating gate. At this time, due to the high voltage applied to the selection gate, these electrons also pass through the silicon dioxide layer to reach the floating gate and form an electron group on the floating gate. The electron group on the floating gate remains on the floating gate even in the case of power failure, so the information can be stored for a long time (usually up to 10 years). Since the floating gate is negative, the selection gate is positive, and the source is grounded in the memory circuit, so it is equivalent to that the field effect transistor is turned on, and the drain level is low, that is, data 0 is written. When erasing, the source is applied with a relatively high programming voltage, the selection gate is grounded, and the drain is open. According to the principle of tunneling effect and quantum mechanics, the electrons on the floating gate will pass through the potential barrier to reach the source, and after the floating gate is free of electrons, it means that the information is erased. If there is a process defect in the manufacturing process of the FLASH chip, it will cause the floating gate electron leakage of part of the storage unit, and its macroscopic manifestation is that the data retention capability of the storage unit is lower than the typical value (the floating gate electron leakage will also be accelerated under the action of voltage or high temperature stress).

[0003] As described above, when the program storage FLASH chip used in electronic devices has defects, long-term use may lead to the invalidation of internal stored information, resulting in FPGA configuration failure. For electronic devices that require long-term use and high controllability, reducing the probability of such FPGA configuration failures is a problem that the electronics manufacturing industry needs to solve. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a method for reducing the probability of FPGA initialization failure due to defects in FLASH chips, thereby reducing the probability of FPGA configuration failure.

[0005] A method for reducing the probability of FPGA initialization failure due to defects in FLASH chips includes the following steps:

[0006] After the S00 electronic device's functional circuits, FPGA chip, and FLASH chip are powered on, the FPGA completes initialization, and the host computer recognizes the electronic device through the communication interface and is able to communicate with the FPGA chip.

[0007] S01. The host computer reads the FLASH chip programming log file and extracts the most recent programming date X1.

[0008] S02. The host computer compares X1 with the current real-time date X2 to obtain the time difference ΔX = (X2-X1) between the last writing time of the FLASH chip and the current time.

[0009] S03. Determine whether △X has reached the preset time standard X. If △X≥X, it means that the FLASH chip needs to be reinforced.

[0010] S04. Determine whether to use the existing bitstream configuration file in the FLASH chip or the bitstream configuration file reserved by the host computer for hardening. If the bitstream configuration file reserved by the host computer is used for hardening, jump directly to process S06; if the bitstream configuration file in the FLASH chip is used for hardening, execute S05.

[0011] S05. Strengthen the FLASH chip by using the bitstream configuration file in the existing FLASH chip. The host computer controls the bitstream file read and write control module inside the FPGA to read the bitstream configuration file in the FLASH chip to the host computer.

[0012] S06. The host computer sends instructions to the FPGA's internal bitstream file read / write control module, and the read / write control module writes the bitstream configuration file in the host computer software into the FLASH chip.

[0013] S07. After the flashing is complete, store the time of this hardening process.

[0014] Preferably, in the S07, after the storage is completed, the host computer software verifies the reinforcement.

[0015] Preferably, in the S07, when the reinforcement is verified, the host computer software controls the FPGA internal bit stream file read-write control module to read the bit stream configuration file in the FLASH chip into the host computer software again, and compares it with the bit stream configuration file stored in the host computer software.

[0016] Preferably, in the S07, when the reinforcement is verified, the host computer software controls the FPGA internal bit stream file read-write control module to read the bit stream configuration file in the FLASH chip into the host computer software again, and compares it with the bit stream configuration file read out from the FLASH chip before the reinforcement.

[0017] Preferably, in the S07, if the reinforcement verification is unsuccessful, the method returns to the S06 to re-perform the reinforcement.

[0018] The present application has the following beneficial effects:

[0019] The present application provides a method for reducing the probability of FPGA initialization failure caused by FLASH chip defects. By using the method, the electronic device can rewrite the configuration data stored in the FLASH chip according to the predetermined period under the premise of not changing the original hardware circuit, so as to reduce the probability of data invalidation caused by time accumulation of the FLASH chip. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The figure is a general principle diagram of the present application;

[0021] Figure 2 The figure is a principle diagram of the embodiment of the present application. DETAILED DESCRIPTION

[0022] The present application will be described in detail below in combination with the drawings and examples.

[0023] The application provides a method for reducing the probability of FPGA initialization failure caused by FLASH chip defects, which comprises adding a FLASH reading and writing control logic module in the FPGA, adding a FLASH reading and writing control function in the upper computer software, and storing the bit stream configuration file of the FPGA configuration in the upper computer. The upper computer judges whether to perform FLASH configuration information reinforcement by judging the FLASH writing interval time, and the user can select manual confirmation or let the software automatically perform FLASH configuration information reinforcement according to actual work needs. In the FLASH configuration information reinforcement process, the existing bit stream configuration file in the FLASH chip or the upper computer reserved bit stream configuration file can be selected for reinforcement. If the existing bit stream configuration file in the FLASH chip is selected for reinforcement, the bit stream configuration file stored in the FLASH chip is read out by using the upper computer to control the FPGA internal reading and writing logic first, and if the upper computer reserved bit stream configuration file is selected for reinforcement, the configuration file stored in the FLASH is not needed to be read out, then the bit stream configuration file is written into the FLASH chip, and then the configuration file in the FLASH chip is read out by controlling the FPGA internal reading and writing logic, and the read out or saved bit stream configuration file is compared, and if the comparison is correct, it is proved that the writing is successful, and the FLASH chip configuration information reinforcement is completed.

[0024] The method provided by the application comprises the following specific steps in an electronic device:

[0025] S00, after the power-on of the functional circuit of the electronic device, the FPGA chip and the FLASH chip, the FPGA completes initialization, and the upper computer recognizes the electronic device through a communication interface and has a condition for communicating with the FPGA chip;

[0026] S01, the upper computer reads the FLASH chip writing log file and extracts the latest writing date X1;

[0027] S02, the upper computer compares X1 with the current real-time date X2, obtains the time difference △X=(X2-X1) from the last FLASH chip writing time to the present time;

[0028] S03, whether △X reaches a preset time standard X is judged, if △X≥X, it is indicated that the FLASH chip needs to be reinforced again, and the upper computer controls to start the reinforcement process;

[0029] S04, whether the existing bit stream configuration file in the FLASH chip or the upper computer reserved bit stream configuration file is used for reinforcement is judged, if the upper computer reserved bit stream configuration file is used for reinforcement, the process directly jumps to S06; if the bit stream configuration file in the FLASH chip is used for reinforcement, S05 is executed;

[0030] S05. To strengthen the FLASH chip by using the existing bitstream configuration file, it is necessary to control the bitstream file read / write control module inside the FPGA to read the bitstream configuration file in the FLASH chip to the host computer software.

[0031] S06. Send instructions to the FPGA internal bitstream file read / write control module via the host computer, and the read / write control module will burn the bitstream configuration file in the host computer software into the FLASH chip.

[0032] S07. After the programming is completed, the time of this hardening is stored (stored in the FLASH chip or the host computer). The host computer software can choose whether to perform hardening verification. If no hardening verification is required, the entire hardening process ends; if hardening verification is required, proceed to S08.

[0033] S08. The host computer software once again controls the FPGA internal bitstream file read / write control module to read the bitstream configuration file in the FLASH chip into the host computer software, and compares it with the bitstream configuration file read from the FLASH chip before the host computer software has stored or hardened it.

[0034] S09. If the comparison is successful, the reinforcement verification passes and the entire process ends; if the comparison is unsuccessful, repeat steps S06 to S09 until the reinforcement and reinforcement verification process is completed.

[0035] Example:

[0036] A method to reduce the probability of FPGA initialization failure due to FLASH chip defects, such as... Figure 2 As shown, the system includes: a host computer (which has oscilloscope driver software installed and stores the oscilloscope's bitstream configuration file) and an oscilloscope board (which contains oscilloscope functional circuits, a FLASH configuration chip, and an FPGA chip. The FPGA chip has internal bitstream file read / write control logic that can control the reading and writing of the FLASH chip's bitstream file).

[0037] In this embodiment, the bitstream configuration information in the FLASH chip of the oscilloscope board is hardened every 6 months. The bitstream configuration information is directly stored in the host computer oscilloscope driver software. After the hardening is completed, hardening verification is required.

[0038] The specific steps of the method provided by this invention in the embodiments are as follows:

[0039] S00, an electronic device such as an oscilloscope board card, comprising an oscilloscope function circuit, a FLASH configuration chip and an FPGA chip, the FPGA chip is internally provided with FPGA internal bit stream file read-write control logic simulation capable of controlling the bit stream file read-write of the FLAS chip, when the oscilloscope board card is powered on, the FPGA and the FLASH chip are powered on and the initialization configuration process is completed, the host computer control computer identifies the device through the bus interface and can communicate with the FPGA of the board card;

[0040] S01, the oscilloscope drive software in the host computer control computer reads the FLASH chip burning log file, and extracts the latest burning date X1;

[0041] S02, compare X1 with the current real-time date X2, get the time difference △X=(X2-X1) of the last FLASH chip burning time from the current time;

[0042] S03, judge whether △X reaches 6 months, if △X≥6 months, it is indicated that the FLASH chip of the oscilloscope board card needs to be re-hardened, and the host computer will control the oscilloscope board card to start the hardening process;

[0043] S04, the bit stream configuration file is reserved in the oscilloscope drive software, and the FLASH information does not need to be read;

[0044] S05, this step is skipped;

[0045] S06, the bit stream configuration file in the host computer software is written into the FLASH chip through the FPGA internal bit stream file read-write control module in the host computer control computer;

[0046] S07, after the writing is completed, the time of this hardening is stored, and the random hardening verification is started;

[0047] S08, the oscilloscope drive software in the host computer control computer controls the FPGA internal bit stream file read-write control module on the oscilloscope board card again, reads the bit stream configuration file in the FLASH chip to the host computer, and compares with the bit stream configuration file stored in the oscilloscope drive software;

[0048] S09, if the comparison is successful, the hardening verification is passed, and the whole process is ended; if the comparison is not successful, the steps S06-S09 are re-executed until the hardening and hardening verification process are completed.

[0049] In summary, the above is only a preferred embodiment of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for reducing the probability of FPGA initialization failure due to defects in FLASH chips, characterized in that, Includes the following steps: After the S00 electronic device's functional circuits, FPGA chip, and FLASH chip are powered on, the FPGA completes initialization, and the host computer recognizes the electronic device through the communication interface and is able to communicate with the FPGA chip. S01. The host computer reads the FLASH chip programming log file and extracts the most recent programming date X1. S02. The host computer compares X1 with the current real-time date X2 to obtain the time difference ΔX = (X2-X1) between the last writing time of the FLASH chip and the current time. S03. Determine whether △X has reached the preset time standard X. If △X≥X, it means that the FLASH chip needs to be reinforced. S04. Determine whether to use the existing bitstream configuration file in the FLASH chip or the bitstream configuration file reserved by the host computer for hardening. If the bitstream configuration file reserved by the host computer is used for hardening, jump directly to process S06; if the bitstream configuration file in the FLASH chip is used for hardening, execute S05. S05. Strengthen the FLASH chip by using the bitstream configuration file in the existing FLASH chip. The host computer controls the bitstream file read and write control module inside the FPGA to read the bitstream configuration file in the FLASH chip to the host computer. S06. The host computer sends instructions to the FPGA's internal bitstream file read / write control module, and the read / write control module writes the bitstream configuration file in the host computer software into the FLASH chip. S07. After the flashing is complete, store the time of this hardening process.

2. The method for reducing the probability of FPGA initialization failure due to FLASH chip defects as described in claim 1, characterized in that, In step S07, after storage is completed, the host computer software verifies the hardening process.

3. The method for reducing the probability of FPGA initialization failure due to FLASH chip defects as described in claim 2, characterized in that, In step S07, during the hardening verification, the host computer software again controls the FPGA internal bitstream file read / write control module to read the bitstream configuration file in the FLASH chip into the host computer software and compare it with the bitstream configuration file already stored in the host computer software.

4. The method for reducing the probability of FPGA initialization failure due to defects in FLASH chips as described in claim 2, characterized in that, In step S07, during the hardening verification, the host computer software once again controls the FPGA internal bitstream file read / write control module to read the bitstream configuration file in the FLASH chip into the host computer software, and compares it with the bitstream configuration file read from the FLASH chip before this hardening.

5. The method for reducing the probability of FPGA initialization failure due to FLASH chip defects as described in claim 2, characterized in that, In step S07, if the reinforcement verification fails, the process returns to step S06 to perform reinforcement again.

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