A method for preparing a vertical MOS transistor

Abstract

The present invention provides a method for fabricating a vertical MOS transistor, comprising the following steps: Step S22: forming sidewalls on the sidewalls of a trench, and performing ion implantation on the bottom wall of the trench using the sidewalls as a mask; Step S23: forming a first insulating film layer on the bottom wall of the trench, and removing the sidewalls; and Step S24: forming a second insulating film layer on the inner wall of the trench. By adding Steps S22 and S23, the present invention increases the thickness of the insulating layer on the bottom wall of the trench, that is, increases the thickness of the first insulating film layer. This also increases the breakdown voltage of the vertical MOS transistor, thereby preventing dielectric layer breakdown at the bottom corners of the trench. It also reduces the parasitic capacitance of the vertical MOS transistor, thereby improving the response speed of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor chips, and in particular relates to a method for preparing a vertical MOS transistor. Background Art

[0002] In the field of semiconductor technology, with the continuous development of semiconductor device manufacturing technology, vertical MOS transistors (Vertical MOSFET, referred to as VMOS) have an increasingly broad application prospect due to their own excellent device performance.

[0003] Vertical MOS transistors include U-shaped trench MOS transistors and SGT MOS transistors, such as Figures 1a-1d As shown in FIG, the U-shaped trench MOS transistor has a triangular electric field distribution, and the electric field intensity is highest at the bottom corner C of the trench. The dielectric layer breakdown is very likely to occur in this area, that is, the breakdown voltage of the U-shaped trench MOS transistor is low. Figures 2a-2c As shown, the SGT MOS transistor has a trapezoidal electric field distribution, and the electric field intensity is highest at the bottom corner C of the trench. Dielectric layer breakdown is likely to occur in this area, and similarly, the breakdown voltage of the SGT MOS transistor is low. Summary of the Invention

[0004] The object of the present invention is to provide a method for preparing a vertical MOS transistor, which can improve the breakdown voltage of the vertical MOS transistor to avoid dielectric layer breakdown at the bottom corner of the trench.

[0005] In order to solve the above problems, the present invention provides a method for preparing a vertical MOS transistor, comprising the following steps:

[0006] Step S21: providing a semiconductor substrate, wherein a trench is formed in the semiconductor substrate, and the trench has a rounded corner profile;

[0007] Step S22: forming sidewalls on the sidewalls of the trench, and performing ion implantation on the bottom wall of the trench using the sidewalls as a mask;

[0008] Step S23: forming a first insulating film layer on the bottom wall of the trench and removing the sidewalls;

[0009] Step S24: forming a second insulating film layer on the inner wall of the trench.

[0010] Optionally, step S21 includes:

[0011] Providing a semiconductor substrate, the semiconductor substrate comprising a base and an epitaxial layer;

[0012] forming a trench in the epitaxial layer through an etching process, wherein the depth of the trench is less than the thickness of the epitaxial layer; and

[0013] The bottom corner of the groove is rounded so that the groove forms a rounded contour.

[0014] Optionally, after step S21, the method further includes:

[0015] depositing a sacrificial oxide layer on the inner wall of the trench; and

[0016] and removing the sacrificial oxide layer.

[0017] Optionally, step S22 includes:

[0018] Depositing a film structure on the semiconductor substrate, wherein the film structure covers the inner wall of the trench;

[0019] removing the film layer structure on the surface of the semiconductor substrate and the bottom wall of the trench by an etching process, and only retaining the film layer structure on a portion of the sidewall of the trench;

[0020] Using the sidewall as a mask, ion implantation is performed on the bottom wall of the trench; and

[0021] The semiconductor substrate is cleaned through a pre-cleaning process.

[0022] Furthermore, depositing a film structure on the semiconductor substrate, wherein the film structure covers the inner wall of the trench, comprises:

[0023] An oxide film layer and a silicon nitride film layer are sequentially deposited on the semiconductor substrate, wherein the oxide film layer covers the inner wall of the trench, and the silicon nitride film layer covers the oxide film layer.

[0024] Furthermore, the implanted ions are electrically neutral ions.

[0025] Furthermore, the implanted ions include silicon ions and germanium ions.

[0026] Optionally, step S23 includes:

[0027] forming a first insulating film layer with a preset thickness on the surface of the semiconductor substrate and the inner wall of the trench exposed by the sidewall; and

[0028] The sidewall spacer is removed to expose the sidewall of the trench not covered by the first insulating film layer.

[0029] Optionally, the first insulating film layer and the second insulating film layer are both oxide film layers.

[0030] Optionally, the second insulating film layer covers the first insulating film layer on the surface of the semiconductor substrate, the first insulating film layer on the inner wall of the trench, and the sidewall of the trench exposed by the first insulating film layer.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The present invention provides a method for fabricating a vertical MOS transistor, comprising the following steps: Step S21: providing a semiconductor substrate having a trench formed therein, the trench having a rounded corner profile; Step S22: forming sidewalls on the sidewalls of the trench, and performing ion implantation on the bottom wall of the trench using the sidewalls as a mask; Step S23: forming a first insulating film layer on the bottom wall of the trench, and removing the sidewalls; Step S24: forming a second insulating film layer on the inner wall of the trench. The present invention increases the thickness of the insulating layer on the bottom wall of the trench (i.e., by increasing the thickness of the first insulating film layer to the sum of the thicknesses of the first insulating film layer and the second insulating film layer) by adding Step S22 and Step S23. This increases the thickness of the first insulating film layer, improves the breakdown voltage of the vertical MOS transistor, avoids dielectric breakdown at the bottom corners of the trench, and reduces the parasitic capacitance of the vertical MOS transistor, thereby improving the response speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figures 1a-1d Schematic diagram of the structure of a U-shaped trench MOS transistor;

[0034] Figures 2a-2c Schematic diagram of the structure of the SGT MOS transistor;

[0035] Figure 3a-3b is a schematic structural diagram of a vertical MOS transistor during its formation;

[0036] Figure 4 A schematic flow chart of a method for manufacturing a vertical MOS transistor according to an embodiment of the present invention;

[0037] Figures 5a-5f FIG. 1 is a structural diagram of a vertical MOS transistor during the formation process according to an embodiment of the present invention.

[0038] Description of reference numerals:

[0039] Figures 1a-3b middle:

[0040] 10-substrate; 1-base; 2-epitaxial layer; 20-trench; 4-source region; 41-shield electrode; 5-gate electrode; 6-source metal layer; 7-drain metal layer; 51-gate insulating film;

[0041] Figures 5a-5f middle:

[0042] 100 - semiconductor substrate; 200 - trench; 300 - sidewall; 410 - first insulating film layer; 420 - second insulating film layer. DETAILED DESCRIPTION

[0043] The method for forming a vertical MOS transistor in the prior art is:

[0044] like Figure 3a As shown, step S11: providing a substrate 10 and forming a trench 20 in the substrate 10, wherein the bottom corner of the trench 20 is rounded.

[0045] Among them, Figure 1a and 2a As shown, the substrate 10 includes a base 1 and an epitaxial layer 2 formed on the base 1. The base 1 is, for example, an N+ type base, and the epitaxial layer 2 is, for example, an N- type epitaxial layer.

[0046] Please continue reading Figure 3a Step S12: forming a sacrificial oxide layer on the inner wall of the trench 20 and removing the sacrificial oxide layer to remove the damage to the inner wall of the trench 20 caused by the step S11.

[0047] like Figure 3b As shown, step S13: depositing a gate insulating film 51 on the inner wall of the trench 20 .

[0048] Step S14: Figure 1a As shown, a gate electrode 5 is formed in the trench 20, or as Figure 2a As shown, a shield electrode 41 and a gate electrode 5 are stacked and spaced apart and formed in the trench 20 .

[0049] like Figure 1a and Figure 2a As shown, step S15: P- ions are doped into the epitaxial layer 2 on both sides of the trench 20 to form a body region 3, and then N+ ions are doped into the body region 3 to form a source region 4. P+ ions are also doped into the body region 3 outside the source region to form a contact region (not shown in the figure). A source metal layer 6 is then formed on the surface of the epitaxial layer 2, and a drain metal layer 7 is formed on the side of the substrate 1 away from the epitaxial layer 2, thereby forming a vertical MOS transistor. The surface of the epitaxial layer 2 is defined as position A, the interface between the substrate 1 and the epitaxial layer 2 is defined as position B, and the bottom corner of the trench is defined as position C.

[0050] In this step, since the thickness of the gate insulating film 51 on the inner wall of the trench 20 is relatively thin, Figure 1c Graph showing the electric field intensity distribution when the applied voltages are: gate voltage Vg = 0, drain voltage Vd = 5V, and the difference between adjacent electric field lines ΔV = 1V; Figure 1dThe electric field intensity distribution diagram at the position 0.51 μm away from the middle of the trench, i.e., when x=0.51 μm, when the drain voltage Vd is 2V, 5V, 10V, 20V, 30V and 40V respectively. Figure 1c-1d See also Figure 1b , the electric field intensity of the U-shaped trench MOS transistor gradually increases from A to B and reaches a peak at position C, and then gradually decreases, so that the U-shaped trench MOS transistor has a triangular electric field distribution, and also makes the breakdown voltage of the U-shaped trench MOS transistor at the bottom corner of the trench 30 lower. It should be noted that, in Figure 1c In the figure, the dotted lines at the body region 3 and the source region 4 are the potential of the source terminal voltage at 0 V, and △V=1V refers to the five electric field lines below the curve. The difference between each adjacent electric field line is 1 V, and 5 electric field lines indicate that there is a potential difference of 5 V from the source to the drain. Figure 2c The electric field intensity distribution diagram when the applied voltages are: gate voltage Vg = 0, drain voltage Vd = 20V, ΔV = 2V. Figure 2c See also Figure 2b The electric field strength of the SGT MOS transistor gradually increases from A to B and reaches a peak at position C, maintains for a distance, and then gradually decreases, so that the SGT MOS transistor has a trapezoidal electric field distribution and the breakdown voltage of the SGT MOS transistor at the bottom corner of the trench 30 is relatively low.

[0051] Based on the above analysis, the present invention provides a method for preparing a vertical MOS transistor, comprising the following steps: Step S21: providing a semiconductor substrate having a trench formed therein, the trench having a rounded corner profile; Step S22: forming sidewalls on the sidewalls of the trench, and performing ion implantation on the bottom wall of the trench using the sidewalls as a mask; Step S23: forming a first insulating film layer on the bottom wall of the trench, and removing the sidewalls; Step S24: forming a second insulating film layer on the inner wall of the trench. The present invention increases the thickness of the insulating layer on the bottom wall of the trench (i.e., by increasing the thickness of the first insulating film layer to the sum of the thicknesses of the first insulating film layer and the second insulating film layer) by adding Step S22 and Step S23, thereby increasing the thickness of the first insulating film layer, improving the breakdown voltage of the vertical MOS transistor, thereby avoiding dielectric layer breakdown at the bottom corners of the trench, and reducing the parasitic capacitance of the vertical MOS transistor, thereby improving the response speed of the device.

[0052] The following is a further detailed description of a method for fabricating a vertical MOS transistor according to the present invention. The present invention will be described in more detail below with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art may modify the present invention described herein while still achieving the beneficial effects of the present invention. Therefore, the following description should be understood as a general guideline for those skilled in the art and is not intended to limit the present invention.

[0053] For the sake of clarity, not all features of actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would obscure the present invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as adapting from one embodiment to another to accommodate system or business constraints. Furthermore, it should be understood that such development work may be complex and time-consuming, but is nevertheless a routine undertaking for those skilled in the art.

[0054] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific embodiments of the present invention are further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0055] Figure 4 FIG. 1 is a flow chart of a method for preparing a vertical MOS transistor according to the present embodiment. Figure 4 As shown, this embodiment provides a method for preparing a vertical MOS transistor, comprising the following steps:

[0056] Step S21: providing a semiconductor substrate, wherein a trench is formed in the semiconductor substrate, and the trench has a rounded corner profile;

[0057] Step S22: forming sidewalls on the sidewalls of the trench, and performing ion implantation on the bottom wall of the trench using the sidewalls as a mask;

[0058] Step S23: forming a first insulating film layer on the bottom wall of the trench and removing the sidewalls;

[0059] Step S24: forming a second insulating film layer on the inner wall of the trench.

[0060] The following combination Figure 4 as well as Figures 5a-5f A method for manufacturing a vertical MOS transistor of this embodiment is described in detail.

[0061] Figure 5a This is a schematic diagram of the structure of the semiconductor substrate provided in this embodiment. Figure 5aAs shown, step S21 is first performed to provide a semiconductor substrate 100 , wherein a trench 200 is formed in the semiconductor substrate 100 , and the trench 100 has a rounded corner profile.

[0062] This step specifically includes:

[0063] First, a semiconductor substrate 100 is provided, which includes a base (not shown in the figure) and an epitaxial layer (not shown in the figure). The base can be an N+ type base, and the epitaxial layer is formed on the base, and the epitaxial layer can be an N-type epitaxial layer.

[0064] Next, a trench 200 is formed in the epitaxial layer through an etching process, and the depth of the trench 200 is less than the thickness of the epitaxial layer.

[0065] Next, the bottom corner of the groove 200 is rounded to form a rounded profile of the groove 200 .

[0066] Next, a sacrificial oxide layer (not shown in the figure) is deposited on the inner wall of the groove 200 and removed. This step is used to remove the damaged layer that appears on the inner wall of the groove 200 when the groove 200 is formed and rounded. It is beneficial to the normal progress of subsequent processes and the improvement of process quality.

[0067] Figure 5b This is a schematic diagram of the structure after the sidewalls are formed in this embodiment. Figure 5c This is a schematic diagram of the structure of the trench during the ion implantation process in this embodiment. Figures 5b-5c As shown, step S22 is then performed to form a sidewall spacer 300 on the sidewall of the trench 200 , and ion implantation is performed on the bottom wall of the trench 200 using the sidewall spacer 300 as a mask.

[0068] This step specifically includes:

[0069] First, a film structure is deposited on the semiconductor substrate 100, the film structure covering the inner walls (i.e., the sidewalls and bottom wall) of the trench 200. Specifically, an oxide film layer and a silicon nitride film layer are sequentially deposited on the semiconductor substrate 100, the oxide film layer covering the inner walls of the trench 200, and the silicon nitride film layer covering the oxide film layer.

[0070] like Figure 5bAs shown, the film structure on the surface of the semiconductor substrate 100 and the bottom wall of the trench 200 is then removed by an etching process, leaving only the film structure on a portion of the sidewalls of the trench 200, thereby forming a sidewall 300 on the sidewalls of the trench 200. In this step, since the thickness of the film structure deposited in the trench 200 is thinner than that on the surface of the semiconductor substrate 100, especially at the bottom of the trench, the etching process in this step etches the film structure on the bottom of the trench 200 and the sidewalls near the bottom of the trench, thereby exposing the bottom wall of the trench 200 and a portion of the sidewalls near the bottom.

[0071] like Figure 5c As shown, ion implantation is performed on the bottom wall of the trench 200 using the sidewall 300 as a mask. The implanted ions in this step are electrically neutral ions, such as silicon ions or germanium ions. Due to the characteristics of the implanted ions, the ion implantation process physically bombards only the bottom wall of the trench 200, resulting in the exposed portion of the trench 200, particularly the bottom wall, being less porous than other portions due to the ion bombardment.

[0072] Next, the semiconductor substrate 100 is cleaned through a pre-cleaning process.

[0073] Figure 5d This is a schematic structural diagram after the first insulating film layer is formed in this embodiment. Figure 5e This is a schematic diagram of the structure after removing the side walls of this embodiment. Figure 5f Schematic diagram of the structure after the second insulating film layer is formed. Figures 5d-5f As shown, step S23 is then performed to form a first insulating film layer 410 on the bottom wall of the trench 200 and remove the sidewall spacer 300 .

[0074] This step specifically includes:

[0075] like Figure 5d As shown, first, a first insulating film layer 410 of a predetermined thickness is formed on the surface of the semiconductor substrate 100 and on the inner walls (bottom wall and partial length of sidewalls) of the trench 200 exposed by the sidewall spacer 300. The first insulating film layer 410 is, for example, an oxide film layer. Because the ion implantation process loosens the exposed portion of the trench 200, a relatively thick first insulating film layer 410 can be grown in this step.

[0076] like Figure 5e As shown, the sidewall spacer 300 is then removed to expose the sidewall of the trench 200 not covered by the first insulating film layer 410 .

[0077] like Figure 5fAs shown, step S24 is then performed to form a second insulating film layer 420 on the inner wall of the trench 200. The second insulating film layer 420 covers the first insulating film layer 410 on the surface of the semiconductor substrate 100, the first insulating film layer 410 on the inner wall of the trench 200, and the sidewall of the trench 200 exposed by the first insulating film layer 410. The second insulating film layer 420 is, for example, an oxide film layer. When forming the second insulating film layer 420, since the speed of the second insulating film layer 420 growing on the trench sidewall exposed by the first insulating film layer 410 is faster than the speed of the second insulating film layer 420 growing directly on the first insulating film layer 410, the thickness of the second insulating film layer 420 growing on the trench sidewall exposed by the first insulating film layer 410 is greater than the thickness of the second insulating film layer 420 growing directly on the first insulating film layer 410.

[0078] At this time, the thickness of the second insulating film layer 420 on the side wall of the trench 200 has not changed, but the film thickness of the bottom wall of the trench 200 is thicker, that is, the first insulating film layer 410 and the second insulating film layer 420 are grown on the bottom wall of the trench 200, so that the thickness of the insulating film layer on the bottom wall of the trench is the sum of the film thicknesses of the first insulating film layer 410 and the second insulating film layer 420. This does not affect the turn-on of the device, but also increases the breakdown voltage of the vertical MOS transistor to avoid dielectric layer breakdown at the bottom corner of the trench, and can also reduce the parasitic capacitance of the vertical MOS transistor. The parasitic capacitance C = dielectric constant * area / dielectric layer thickness, where the dielectric layer thickness is the sum of the film thicknesses of the first insulating film layer 410 and the second insulating film layer 420. Therefore, the parasitic capacitance is reduced, thereby improving the response speed of the device.

[0079] After this step, a gate electrode is formed in the trench, or a shield electrode and a gate electrode are stacked and spaced apart; then, p-type ions are doped in the epitaxial layer on both sides of the trench to form a body region, the depth of the body region being shallower than the depth of the trench; then, n+ type dopants are implanted into the body region to form n+ type source layers on both sides of the trench; in addition, p+ type ions are implanted into the body region to form a contact region on the outside of the n+ type source layer, thereby forming a vertical MOS transistor.

[0080] In summary, the present invention provides a method for fabricating a vertical MOS transistor, comprising the following steps: Step S21: providing a semiconductor substrate having a trench formed therein, the trench having a rounded corner profile; Step S22: forming sidewalls on the sidewalls of the trench, and performing ion implantation on the bottom wall of the trench using the sidewalls as a mask; Step S23: forming a first insulating film layer on the bottom wall of the trench, and removing the sidewalls; Step S24: forming a second insulating film layer on the inner wall of the trench. The present invention increases the thickness of the insulating layer on the bottom wall of the trench (i.e., by increasing the thickness of the first insulating film layer to the sum of the thicknesses of the first insulating film layer and the second insulating film layer) by adding Step S22 and Step S23. This increases the thickness of the first insulating film layer, improves the breakdown voltage of the vertical MOS transistor, avoids dielectric breakdown at the bottom corners of the trench, and reduces the parasitic capacitance of the vertical MOS transistor, thereby improving the response speed of the device.

[0081] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0082] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a vertical MOS transistor, characterized in that: The following steps are involved: Step S21: providing a semiconductor substrate, wherein a trench is formed in the semiconductor substrate, and the trench has a rounded corner profile; Step S22: forming sidewalls on the sidewalls of the trench, and performing ion implantation on the bottom wall of the trench using the sidewalls as a mask to loosen the exposed portion of the trench; Step S23: forming a first insulating film layer on the bottom wall of the trench and removing the sidewalls; Step S24: forming a second insulating film layer on the inner wall of the trench; The total thickness of the insulating layer at the bottom of the trench is the sum of the thicknesses of the first insulating film layer and the second insulating film layer.

2. The preparation method according to claim 1, wherein Step S21 includes: Providing a semiconductor substrate, the semiconductor substrate comprising a base and an epitaxial layer; forming a trench in the epitaxial layer through an etching process, wherein the depth of the trench is less than the thickness of the epitaxial layer; and The bottom corner of the groove is rounded so that the groove forms a rounded contour.

3. The preparation method according to claim 1, wherein After step S21, the method further includes: depositing a sacrificial oxide layer on the inner wall of the trench; and and removing the sacrificial oxide layer.

4. The preparation method according to claim 1, wherein Step S22 includes: Depositing a film structure on the semiconductor substrate, wherein the film structure covers the inner wall of the trench; removing the film layer structure on the surface of the semiconductor substrate and the bottom wall of the trench by an etching process, and only retaining the film layer structure on a portion of the sidewall of the trench; Using the sidewall as a mask, ion implantation is performed on the bottom wall of the trench; and The semiconductor substrate is cleaned through a pre-cleaning process.

5. The preparation method according to claim 4, wherein Depositing a film structure on the semiconductor substrate, wherein the film structure covers the inner wall of the trench comprises: An oxide film layer and a silicon nitride film layer are sequentially deposited on the semiconductor substrate, wherein the oxide film layer covers the inner wall of the trench, and the silicon nitride film layer covers the oxide film layer.

6. The preparation method according to claim 4, wherein The implanted ions are electrically neutral ions.

7. The preparation method according to claim 6, wherein The implanted ions include silicon ions and germanium ions.

8. The preparation method according to claim 1, wherein Step S23 includes: forming a first insulating film layer with a preset thickness on the surface of the semiconductor substrate and the inner wall of the trench exposed by the sidewall; and The sidewall spacer is removed to expose the sidewall of the trench not covered by the first insulating film layer.

9. The preparation method according to claim 1, wherein The first insulating film layer and the second insulating film layer are both oxide film layers.

10. The preparation method according to claim 1, wherein The second insulating film layer covers the first insulating film layer on the surface of the semiconductor substrate, the first insulating film layer on the inner wall of the trench, and the sidewall of the trench exposed by the first insulating film layer.

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