Monolithic Heterogeneous Integration Structure of Top p-Type Diamond MOSFET and GaN HEMT and Its Preparation Method

Abstract

The present invention discloses a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT and a preparation method thereof. The method includes: providing an epitaxial product, and sequentially growing a SiN dielectric layer and a p-type diamond layer on the surface of the AlGaN barrier layer away from the substrate; after etching away a part of the p-type diamond layer, etching source electrode grooves and drain electrode grooves in the SiN dielectric layer, and fabricating first source and drain electrodes of the HMET device; fabricating second source and drain electrodes of the MOSFET device on the surface of the p-type diamond layer; depositing Al2O3 on the surface of the p-type diamond layer to form a gate dielectric layer; fabricating a second gate electrode on the surface of the gate dielectric layer to form a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT. The present invention is beneficial to reducing the device volume and improving the device integration degree; at the same time, it also modulates the thermal generation distribution of GaN HEMTs and improves the heat dissipation capacity of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and particularly relates to a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT and a preparation method thereof. Background Art

[0002] In recent years, due to the advantages of the third-generation semiconductor material GaN, such as wide bandgap width, high breakdown electric field, and high electron saturation velocity, it has unique advantages in high-frequency high-power fields such as military, aerospace, and communication. However, when the ultra-high semiconductor device integration and GaN-based devices are applied in the high-frequency field, the accompanying high heat generation phenomenon cannot be ignored. The accumulation of the self-heating effect of the device will not only reduce the basic performance of the device such as the saturation current and transconductance, but may even cause the device to fail more seriously.

[0003] The thermal conductivity of GaN itself is only 130 W / (m·K) (watts per meter per Kelvin). The commonly used substrates for current GaN HEMTs mainly include SiC substrates, Si substrates, and sapphire substrates, etc. Among them, even when using a SiC substrate with a relatively high thermal conductivity, its heat dissipation performance far cannot meet the application of GaN FETs in the microwave high-power field. In addition, the highest operating temperature of silicon-based MOSFET devices in current logic circuits is 125 °C. The electrical performance of silicon-based devices above this operating temperature will be greatly degraded or even completely fail, while the operating temperature of devices applied in high-frequency high-power fields is much higher than 125 °C. Therefore, new material systems and device structures are needed to solve the current thermal problems faced by GaN devices and the high-temperature application problems of circuits. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0005] In a first aspect, the present invention provides a preparation method for a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT, including:

[0006] Providing a substrate, and growing an epitaxial structure on the surface of the substrate, the epitaxial structure including a GaN buffer layer and an AlGaN barrier layer grown in sequence on the surface of the substrate;

[0007] Growing a SiN dielectric layer on the surface of the AlGaN barrier layer away from the substrate side, and growing a p-type diamond layer on the surface of the SiN dielectric layer away from the substrate side;

[0008] After etching away a part of the p-type diamond layer, source electrode grooves and drain electrode grooves are etched in the exposed SiN dielectric layer, and a first source electrode of the HEMT device is fabricated in the source electrode groove and a first drain electrode of the HEMT device is fabricated in the drain electrode groove; wherein, the etched p-type diamond layer includes a first sub-part and a second sub-part;

[0009] A second source electrode and a second drain electrode of the MOSFET device are fabricated on the surface of the p-type diamond layer away from the substrate side;

[0010] Al2O3 is deposited on the surface of the p-type diamond layer away from the substrate side to form a gate dielectric layer;

[0011] A first gate electrode of the HEMT device is fabricated on the surface of the exposed SiN dielectric layer away from the substrate side; wherein, the first sub-part is in contact with the first gate electrode, and in the direction perpendicular to the plane where the substrate is located, the orthographic projection of the first sub-part is located between the orthographic projection of the first gate electrode and the orthographic projection of the first drain electrode; the orthographic projections of the second source electrode and the second drain electrode are both located within the orthographic projection of the second sub-part;

[0012] A second gate electrode is fabricated on the surface of the gate dielectric layer away from the substrate side to form the monolithic heterogeneous integration structure of the top p-type diamond MOSFET and GaN HEMT.

[0013] In an embodiment of the present invention, the step of growing the SiN dielectric layer on the surface of the AlGaN barrier layer away from the substrate side includes:

[0014] The SiN dielectric layer is grown on the surface of the AlGaN barrier layer away from the substrate side by using the MOCVD process; wherein, in the direction perpendicular to the plane where the substrate is located, the thickness of the SiN dielectric layer is 5-20 nm.

[0015] In an embodiment of the present invention, the step of growing the p-type diamond layer on the surface of the SiN dielectric layer away from the substrate side includes:

[0016] C source is provided by using CH4 diluted with H2, and B(CH3)3 diluted with H2 is introduced into the gas phase. Under the conditions of B:C being 1000 ppm, the air pressure being 25 torr, the microwave power being 750 W, the substrate temperature being 750-800 °C, and the total gas flow rate being 400 sccm, the p-type diamond layer is deposited on the surface of the SiN dielectric layer away from the substrate side by using the microwave plasma chemical vapor deposition MPCVD process.

[0017] In an embodiment of the present invention, in the direction perpendicular to the plane where the substrate is located, the thickness of the p-type diamond layer is 500-1000 nm.

[0018] In one embodiment of the present invention, the deposition rate of the p-type diamond layer is 0.13 - 0.2 μm / h.

[0019] In one embodiment of the present invention, the step of depositing Al2O3 on the surface of the p-type diamond layer away from the substrate side to form a gate dielectric layer includes:

[0020] Using the atomic layer deposition (ALD) process of the coating process, alternately introducing H2O and TMA in a pulsed manner at 300 °C to grow Al2O3 on the surface of the p-type diamond layer away from the substrate side;

[0021] Etching away the Al2O3 outside the MOSFET active region to form a gate dielectric layer.

[0022] In one embodiment of the present invention, along the direction perpendicular to the plane of the substrate, the thickness of Al2O3 is 5 - 20 nm.

[0023] In a second aspect, the present invention provides a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT, which is obtained by the preparation method of the monolithic heterogeneous integration structure of the top p-type diamond MOSFET and the GaN HEMT described in the first aspect above.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] 1. After heteroepitaxially growing a p-type diamond layer on the top of the epitaxial substrate, patterning and etching away part of the p-type diamond layer, and fabricating a GaN HEMT device based on the epitaxial substrate, the present invention can modulate the thermal field by using the high thermal conductivity of the diamond material, effectively reducing the junction temperature of the GaN HEMT device.

[0026] 2. By heteroepitaxially growing a p-type diamond layer on the top and fabricating a MOSFET device based on the p-type diamond, the present invention realizes the heterogeneous integration of a GaN electron conducting device and a diamond hole conducting device, which can be applied to high-temperature logic circuits, and solves the problem that the logic circuit based on Si devices in the prior art cannot be applied when the temperature is higher than 125 °C.

[0027] The present invention will be further described in detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a flowchart of a preparation method of a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT provided by an embodiment of the present invention;

[0029] Figure 2It is a schematic diagram of a preparation method for a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT provided by an embodiment of the present invention;

[0030] Figure 3 It is another schematic diagram of a preparation method for a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT provided by an embodiment of the present invention;

[0031] Figure 4 It is another schematic diagram of a preparation method for a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT provided by an embodiment of the present invention;

[0032] Figure 5 It is another schematic diagram of a preparation method for a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT provided by an embodiment of the present invention;

[0033] Figure 6 It is another schematic diagram of a preparation method for a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT provided by an embodiment of the present invention;

[0034] Figure 7 It is another schematic diagram of a preparation method for a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT provided by an embodiment of the present invention;

[0035] Figure 8 It is another schematic diagram of a preparation method for a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT provided by an embodiment of the present invention;

[0036] Figure 9 It is another schematic diagram of a preparation method for a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT provided by an embodiment of the present invention. Detailed implementation manners

[0037] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0038] Figure 1 It is a flowchart of a preparation method for a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT provided by an embodiment of the present invention, Figures 2-9 It is a schematic diagram of a preparation method for a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT provided by an embodiment of the present invention. Please refer to Figures 1-9, an embodiment of the present invention provides a method for fabricating a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT, including:

[0039] S1. Provide a substrate, and grow an epitaxial structure on the surface of the substrate. The epitaxial structure includes a GaN buffer layer and an AlGaN barrier layer that are sequentially grown on the surface of the substrate;

[0040] S2. Grow a SiN dielectric layer on the surface of the AlGaN barrier layer away from the substrate, and grow a p-type diamond layer on the surface of the SiN dielectric layer away from the substrate;

[0041] S3. After etching away a part of the p-type diamond layer, etch source electrode grooves and drain electrode grooves in the exposed SiN dielectric layer, and fabricate a first source electrode S1 of the HEMT device in the source electrode groove and a first drain electrode D1 of the HEMT device in the drain electrode groove; wherein, the etched p-type diamond layer includes a first sub-part A1 and a second sub-part A2;

[0042] S4. Fabricate a second source electrode S2 and a second drain electrode D2 of the MOSFET device on the surface of the p-type diamond layer away from the substrate;

[0043] S5. Deposit Al2O3 on the surface of the p-type diamond layer away from the substrate to form a gate dielectric layer;

[0044] S6. Fabricate a first gate electrode G1 of the HEMT device on the surface of the exposed SiN dielectric layer away from the substrate; wherein, the first sub-part is in contact with the first gate electrode, and in a direction perpendicular to the plane where the substrate is located, the orthographic projection of the first sub-part is located between the orthographic projection of the first gate electrode and the orthographic projection of the first drain electrode; the orthographic projections of the second source electrode and the second drain electrode are both within the orthographic projection of the second sub-part;

[0045] S7. Fabricate a second gate electrode G2 on the surface of the gate dielectric layer away from the substrate to form a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT.

[0046] This embodiment takes the AlGaN / GaN epitaxial structure based on a diamond substrate as an example, specifically as Figures 2-3As shown, an epitaxial structure is grown on the surface of a diamond substrate. The epitaxial structure includes a GaN buffer layer on one side of the substrate and an AlGaN barrier layer on the side of the GaN buffer layer away from the substrate. A SiN dielectric layer is sequentially grown on the surface of the AlGaN barrier layer away from the substrate. Then, the surface of the sample is cleaned. Exemplarily, the sample is first ultrasonically cleaned in an acetone solution for 3 minutes with an ultrasonic intensity of 3.0, then the sample is water-bath heated in a stripping solution at a temperature of 60°C for 5 minutes, and then the sample is ultrasonically cleaned in an acetone solution and an ethanol solution for 3 minutes respectively with an ultrasonic intensity of 3.0, rinsed with ultrapure water and dried with nitrogen. After cleaning the surface of the sample, a p-type diamond layer is grown on the SiN dielectric layer.

[0047] As Figure 2 shown, in the above step S2, the step of growing a SiN dielectric layer on the surface of the AlGaN barrier layer away from the substrate includes:

[0048] Growing a SiN dielectric layer on the surface of the AlGaN barrier layer away from the substrate by using the MOCVD process; wherein, along the direction perpendicular to the plane where the substrate is located, the thickness of the SiN dielectric layer is 5 - 20 nm.

[0049] Please continue to refer to Figure 3 , in the above step S2, the step of growing a p-type diamond layer on the surface of the SiN dielectric layer away from the substrate includes:

[0050] Providing a C source by using CH4 diluted with H2 and introducing B(CH3)3 diluted with H2 into the gas phase, and depositing a p-type diamond layer on the surface of the SiN dielectric layer away from the substrate by using the microwave plasma chemical vapor deposition (MPCVD) process.

[0051] Specifically, using 0.3% of CH4 to provide a C source and diluting it with H2, controlling the boron content by adding B(CH3)3 diluted with H2 into the gas phase to make B:C reach 1000 ppm, depositing a p-type diamond layer at a deposition rate of 0.13 - 0.2 μm / h under the conditions of a gas pressure of 25 torr, a microwave power of 750 W, a substrate temperature of 750 - 800°C, and a total gas flow rate of 400 sccm.

[0052] Optionally, along the direction perpendicular to the plane where the substrate is located, the thickness of the p-type diamond layer is 500 - 1000 nm.

[0053] As Figures 4-5 shown, in the above step S3, after etching away a part of the diamond layer, the steps of etching source electrode grooves and drain electrode grooves in the exposed SiN dielectric layer and fabricating a first source electrode of the HEMT device in the source electrode groove and a first drain electrode of the HEMT device in the drain electrode groove include:

[0054] S301. Bake the sample on a hot plate at 200 °C for 5 min, then apply and spin-coat photoresist on the sample, and bake the sample on a hot plate at 90 °C for 1 min. Then, place the sample in a lithography machine to expose the photoresist in the area of the p-type diamond layer that needs to be removed. After the exposure is completed, place the sample in a developer to remove the photoresist on the p-type diamond layer in the exposed area, and rinse it with ultrapure water and dry it with nitrogen.

[0055] Further, etch the p-type diamond layer in the exposed area. Specifically, use the ICP process to etch the p-type diamond layer in the exposed area to expose the underlying SiN dielectric layer, and then place the sample in acetone solution, stripping solution, acetone solution, and ethanol solution in sequence for cleaning, and rinse it with ultrapure water and dry it with nitrogen. As Figure 4 shown, after removing a part of the p-type diamond layer, the remaining p-type diamond layer includes a first sub-part A1 and a second sub-part A2.

[0056] S302. After etching and removing a part of the p-type diamond layer, etch the SiN dielectric layer corresponding to the first source electrode region and the first drain electrode region to the AlGaN barrier layer to form a source electrode groove and a drain electrode groove.

[0057] Exemplarily, first bake the sample on a hot plate at 200 °C for 5 min. Then, apply and spin-coat photoresist on the sample, and bake the sample on a hot plate at 90 °C for 1 min. Then, place the sample in a lithography machine to expose the photoresist in the source electrode and drain electrode regions. Finally, place the sample after the exposure is completed in a developer to remove the photoresist in the source electrode and drain electrode regions, and rinse it with ultrapure water and dry it with nitrogen.

[0058] Use the ICP etching process to remove the SiN dielectric layer in the first source electrode region and the first drain electrode region, etching to the upper surface of the AlGaN barrier layer. The etching conditions are: the reaction gases are CF4 and O2, the reaction chamber pressure is 10 mTorr, and the RF powers of the upper electrode and the lower electrode are 20 - 50 W and 5 - 10 W respectively.

[0059] S303. Place the sample with the source electrode groove and drain electrode groove etched in an electron beam evaporation chamber. After the vacuum degree of the reaction chamber of the electron beam evaporation chamber reaches 2×10 -6 Torr, evaporate ohmic metal on the surface of the sample. In this embodiment, the ohmic metal can be a metal stack structure composed of four layers of metals, Ti, Al, Ni, and Au, from bottom to top in sequence. Then, strip the sample after the ohmic metal evaporation is completed to remove the ohmic metal, photoresist, and stripping glue outside the first source electrode region and the first drain electrode region, rinse the sample with ultrapure water and dry it with nitrogen.

[0060] S304, as Figure 5 shown, place the sample after the ohmic metal evaporation and stripping into a rapid thermal annealing furnace for annealing treatment, so that the ohmic metal in the first source and drain electrode regions sinks to the GaN buffer layer, thereby forming an ohmic contact between the ohmic metal and the heterojunction channel. Optionally, the process conditions for annealing are: the annealing atmosphere is N2, the annealing temperature is 830 °C, and the annealing time is 30 s.

[0061] As Figure 6 shown, in the above step S4, the second source electrode S2 and the second drain electrode D2 of the MOSFET device are fabricated on the surface of the second sub - part A2.

[0062] S401. First, photolithograph the second source and drain electrode regions on the surface of the second sub - part A2 away from the substrate; specifically, place the sample on a hot plate at 200 °C and bake for 5 min, then apply and spin - coat the stripping glue, with the spin - coating thickness of 0.35 μm, and place the sample on a hot plate at 200 °C and bake for 5 min; then, apply and spin - coat the photoresist on the stripping glue, with the spin - coating thickness of 0.77 μm, and place the sample on a hot plate at 90 °C and bake for 1 min; place the sample after the coating and spin - coating into a lithography machine, and expose the photoresist in the second source electrode region and the second drain electrode region on the surface of the second sub - part A2; place the exposed sample into a developer to remove the photoresist and the stripping glue in the second source and drain electrode regions on the surface of the second sub - part A2, and rinse the sample with ultrapure water and dry it with nitrogen.

[0063] S402. Further, evaporate Au metal on the photoresist of the second sub - part A2. Specifically, place the sample into a plasma asher for bottom film treatment for 5 min; place the sample into an electron beam evaporation chamber. After the vacuum degree of the reaction chamber of the electron beam evaporation chamber reaches 2×10 -6 Torr, evaporate Au metal on the surface of the sample; then, strip the sample after the metal evaporation to remove the metal, photoresist and stripping glue outside the second source and drain electrode regions on the surface of the second sub - part A2, and rinse it with ultrapure water and dry it with nitrogen to form the second source electrode S2 and the second drain electrode D2 of the MOSFET device.

[0064] As Figure 7 shown, in the above step S5, after the second source electrode S2 and the second drain electrode D2 are fabricated, use the ALD (Atomic layer deposition) process to prepare Al2O3 in the active region of the MOSFET device to form a gate dielectric layer.

[0065] S501. Grow Al2O3 on the surface of the p-type diamond layer far from the substrate side by using the atomic layer deposition (ALD) process in the coating process. Specifically, when depositing Al2O3, use H2O as the oxidant and trimethylaluminum (TMA) as the aluminum source, and alternately introduce H2O and TMA in a pulsed manner. Among them, the pulse time of both TMA and H2O is 0.3 s, the purge time of TMA is 5 s, and the purge time of H2O is 7 s, and Al2O3 with a thickness of 5 - 20 nm is grown.

[0066] S502. Etch away the Al2O3 outside the MOSFET active region to form a gate dielectric layer. Optionally, first lithograph the region outside the MOSFET active region: Bake the epitaxial wafer on a hot plate at 200 °C for 5 min, then apply and spin-coat photoresist on the Al2O3 dielectric layer, and bake the sample on a hot plate at 90 °C for 1 min; Put the sample with applied and spin-coated photoresist into a lithography machine to expose the photoresist in the region outside the MOSFET active region; Then, put the sample into the developer to remove the photoresist in the region outside the MOSFET active region, rinse it with ultrapure water and dry it with nitrogen; Finally, use the ICP etching process to remove the Al2O3 dielectric layer in the region outside the MOSFET active region.

[0067] Please refer to Figure 8 , in step S6 above, fabricate the gate electrode of the HEMT device on the surface of the exposed SiN dielectric layer far from the substrate side.

[0068] S601. Lithograph the gate trench region on the SiN dielectric layer. Specifically, bake the sample on a hot plate at 200 °C for 5 min, then apply and spin-coat photoresist, and bake the sample on a hot plate at 90 °C for 1 min; Then, put the sample into a lithography machine to expose the photoresist in the gate electrode region; Put the exposed sample into the developer to remove the photoresist in the gate electrode region, and rinse it with ultrapure water and dry it with nitrogen.

[0069] S602. Use the ICP etching process to remove the SiN dielectric layer in the gate trench region, etching to the upper surface of the AlGaN barrier layer. The etching conditions are: use CF4 and O2 as the reaction gases, the reaction chamber pressure is 10 mTorr, and the RF powers of the upper electrode and the lower electrode are 20 - 50 W and 5 - 10 W respectively.

[0070] S603. Evaporate the gate electrode in the gate trench region. Put the sample into an electron beam evaporation chamber. Wait until the vacuum degree of the reaction chamber of the electron beam evaporation chamber reaches 2 × 10 -6After Torr, the gate metal is evaporated on the sample surface. The gate metal can be a metal stack structure composed of two layers of metals, Ni and Au, from bottom to top in sequence; the sample after the gate metal evaporation is stripped to remove the gate metal, photoresist, and stripping glue outside the first gate electrode groove area, and the sample is rinsed with ultrapure water and dried with nitrogen.

[0071] It should be noted that the remaining p-type diamond layer after etching in this embodiment includes two parts, a first sub-part A1 and a second sub-part A2. Along the direction perpendicular to the plane where the substrate is located, the orthographic projection of the first sub-part A1 is located between the orthographic projection of the first gate electrode and the orthographic projection of the first drain electrode, and the orthographic projections of the second source electrode and the second drain electrode are both within the orthographic projection of the second sub-part A2, and the first sub-part A1 is in contact with the first gate electrode; that is to say, the part of the p-type diamond layer that is etched away refers to the p-type diamond layer at the corresponding positions of the first source electrode S1, the first gate electrode G1, and the first drain electrode of the HEMT device.

[0072] Please refer to Figure 9 , in the above step S7, first, the sample is baked on a hot plate at 200 °C for 5 min, then the stripping glue is coated and spun on the gate dielectric layer, and the spin coating thickness is 0.35 μm, and the sample is baked on a hot plate at 200 °C for 5 min; then, the photoresist is coated and spun on the stripping glue, and its spin coating thickness is 0.77 μm, and the sample is baked on a hot plate at 90 °C for 1 min; after that, the sample after the coating and spinning is put into a photolithography machine to expose the photoresist in the second gate electrode area; the exposed sample is put into a developer to remove the photoresist and stripping glue in the second gate electrode area, and it is rinsed with ultrapure water and dried with nitrogen, so as to form the second gate electrode area by photolithography on the gate dielectric layer.

[0073] Furthermore, the sample with the lithography patterns of the active electrode and the drain electrode is put into a plasma asher for the bottom film treatment, and the treatment time is 5 min; then, the sample is put into an electron beam evaporation chamber. When the vacuum degree of the reaction chamber of the electron beam evaporation chamber reaches 2×10 -6 Torr, the gate metal Al is evaporated on the sample surface; the sample after the gate metal evaporation is stripped to remove the metal Al, photoresist, and stripping glue outside the second gate electrode area; finally, it is rinsed with ultrapure water and dried with nitrogen.

[0074] As Figure 9 shown, the embodiment of the present invention provides a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT, which is obtained by the preparation method of the monolithic heterogeneous integration structure of the above top p-type diamond MOSFET and GaN HEMT.

[0075] It can be seen from the above embodiments that the beneficial effects of the present invention are as follows:

[0076] 1. After heteroepitaxially growing a p-type diamond layer on the top of the epitaxial substrate, the present invention patterns and etches to remove part of the p-type diamond layer, and fabricates a GaN HEMT device based on the epitaxial substrate, so that the high thermal conductivity of the diamond material can be effectively utilized to reduce the junction temperature of the GaN HEMT device.

[0077] 2. The present invention heteroepitaxially grows a p-type diamond layer on the top and fabricates a MOSFET device based on the p-type diamond, thereby realizing the hetero-integration of a GaN electron conducting device and a diamond hole conducting device, which can be applied to high-temperature logic circuits and solves the problem that the logic circuits based on Si devices in the prior art cannot be applied when the temperature is higher than 125°C.

[0078] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present invention.

[0079] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0080] In the present invention, unless otherwise clearly specified and limited, the first feature being "above" or "below" the second feature may include direct contact between the first and second features, or may include indirect contact between the first and second features through additional features therebetween. Moreover, the first feature being "above", "over" and "on" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "below", "beneath" and "under" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.

[0081] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0082] Although the present application has been described herein in connection with various embodiments, however, in implementing the claimed present application, those skilled in the art can understand and realize other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processor or other unit can implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0083] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A preparation method of a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT, characterized in that, Comprising: Providing a substrate, and growing an epitaxial structure on the surface of the substrate, the epitaxial structure including a GaN buffer layer and an AlGaN barrier layer that are sequentially grown on the surface of the substrate; Growing a SiN dielectric layer on the surface of the AlGaN barrier layer away from the substrate, and growing a p-type diamond layer on the surface of the SiN dielectric layer away from the substrate; After etching away a part of the p-type diamond layer, etching source electrode grooves and drain electrode grooves in the exposed SiN dielectric layer, and fabricating a first source electrode of the HEMT device in the source electrode groove and a first drain electrode of the HEMT device in the drain electrode groove; wherein, the etched p-type diamond layer includes a first sub-part and a second sub-part; Fabricating a second source electrode and a second drain electrode of the MOSFET device on the surface of the p-type diamond layer away from the substrate; Depositing Al2O3 on the surface of the p-type diamond layer away from the substrate to form a gate dielectric layer; Fabricating a first gate electrode of the HEMT device on the surface of the exposed SiN dielectric layer away from the substrate; wherein, the first sub-part is in contact with the first gate electrode, and in a direction perpendicular to the plane where the substrate is located, the orthographic projection of the first sub-part is located between the orthographic projection of the first gate electrode and the orthographic projection of the first drain electrode; the orthographic projections of the second source electrode and the second drain electrode are both located within the orthographic projection of the second sub-part; Fabricating a second gate electrode on the surface of the gate dielectric layer away from the substrate to form the monolithic heterogeneous integration structure of the top p-type diamond MOSFET and GaN HEMT.

2. The preparation method of the monolithic heterogeneous integration structure of the top p-type diamond MOSFET and the GaN HEMT according to claim 1, characterized in that, The step of growing a SiN dielectric layer on the surface of the AlGaN barrier layer away from the substrate includes: Growing a SiN dielectric layer on the surface of the AlGaN barrier layer away from the substrate by using the MOCVD process; wherein, in a direction perpendicular to the plane where the substrate is located, the thickness of the SiN dielectric layer is 5 - 20 nm.

3. The preparation method of the monolithic heterogeneous integration structure of the top p-type diamond MOSFET and the GaN HEMT according to claim 2, characterized in that, The step of growing a p-type diamond layer on the surface of the SiN dielectric layer away from the substrate includes: Providing a C source by using CH4 diluted with H2, and introducing B(CH3)3 diluted with H2 into the gas phase. Under the conditions that B:C is 1000 ppm, the air pressure is 25 torr, the microwave power is 750 W, the substrate temperature is 750 - 800 °C, and the total gas flow rate is 400 sccm, depositing and forming a p-type diamond layer on the surface of the SiN dielectric layer away from the substrate by using the microwave plasma chemical vapor deposition MPCVD process.

4. The preparation method of the monolithic heterogeneous integration structure of the top p-type diamond MOSFET and the GaN HEMT according to claim 3, characterized in that, In a direction perpendicular to the plane where the substrate is located, the thickness of the p-type diamond layer is 500 - 1000 nm.

5. The preparation method of the monolithic heterogeneous integration structure of the top p-type diamond MOSFET and the GaN HEMT according to claim 3, characterized in that, The deposition rate of the p-type diamond layer is 0.13 - 0.2 μm / h.

6. The preparation method of the monolithic heterogeneous integration structure of the top p-type diamond MOSFET and the GaN HEMT according to claim 1, characterized in that, The step of depositing Al2O3 on the surface of the p-type diamond layer away from the substrate to form a gate dielectric layer includes: Using the atomic layer deposition ALD process of the coating process, alternately introducing H2O and TMA in a pulsed manner at 300 °C to grow Al2O3 on the surface of the p-type diamond layer away from the substrate; Etch away Al2O3 outside the MOSFET active region to form a gate dielectric layer.

7. The preparation method of the monolithic heterogeneous integration structure of the top p-type diamond MOSFET and the GaN HEMT according to claim 6, characterized in that, In the direction perpendicular to the plane where the substrate is located, the thickness of Al2O3 is 5 - 20 nm.

8. A monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT, characterized in that, Prepared by the method for fabricating a monolithic heterogeneous integration structure of a top p-type diamond MOSFET and a GaN HEMT according to any one of claims 1 - 7.

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