potential generating circuit, inverter, delay circuit, and logic gate circuit

Abstract

The application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit comprises a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit, wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generating circuit, and a gate end of the second transistor is connected to a drain end of the second transistor. Thus, the substrate end of the first transistor can output a potential which changes with any one of the supply voltage, the operating temperature and the manufacturing process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a potential generation circuit, an inverter, a delay circuit and a logic gate circuit. BACKGROUND

[0002] At present, delay circuits are often used in semiconductor elements. A delay circuit is a circuit capable of delaying a pulse signal for a certain time. When a delay circuit is applied in a dynamic random access memory (DRAM), it is often necessary to precisely control the delay time of the delay circuit. The delay circuit needs to satisfy the condition that the delay time changes less when the power supply voltage, operating temperature and manufacturing process parameters change.

[0003] Figure 1 Fig. 1 is a schematic diagram of an input signal and an output signal of a delay circuit. After the input signal passes through the delay circuit, the output delay signal is obtained. As shown in Fig. 1, the output signal is the signal after the input signal is delayed for a time T. Figure 1 As shown in Fig. 1, the output signal is the signal after the input signal is delayed for a time T. Figure 1 As shown in Fig. 1, the output signal is the signal after the input signal is delayed for a time T.

[0004] In the existing delay circuit, the delay time T changes greatly (becomes larger or smaller) with the changes of the power supply voltage, operating temperature and manufacturing process, which affects the precision of the delay time. How to reduce the influence of the changes of the above parameters on the delay time T of the delay circuit so that the change of the delay time T is small is a problem to be solved. SUMMARY

[0005] The present application provides a potential generation circuit that can output a potential that changes with the change of any one of the power supply voltage, operating temperature and manufacturing process.

[0006] The present application provides an inverter that can make the change of the rising edge delay time or the falling edge delay time of the inverter smaller, thereby improving the control ability of the inverter on the delay time precision.

[0007] The present application provides a delay circuit to reduce the influence of the manufacturing process, power supply voltage and operating temperature of the delay circuit on the rising edge delay time and / or falling edge delay time of the delay circuit, so that the change of the rising edge delay time and / or falling edge delay time is smaller.

[0008] The application provides a logic gate circuit to reduce the influence of manufacturing process, power supply voltage and working temperature of the logic gate circuit on rising edge delay time and / or falling edge delay time of the logic gate circuit, so that the rising edge delay time and / or the falling edge delay time changes less.

[0009] In a first aspect, the application provides a potential generation circuit, comprising:

[0010] a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a power supply voltage, a working temperature and a manufacturing process of the potential generation circuit;

[0011] wherein a gate end of the first transistor is connected to a drain end of the first transistor, and the substrate end of the first transistor serves as an output end of the potential generation circuit; and a gate end of the second transistor is connected to a drain end of the second transistor.

[0012] The potential generation circuit provided by the application sets the first transistor and the second transistor, the gate end of the first transistor is connected to the drain end of the first transistor, the substrate end of the first transistor serves as the output end of the potential generation circuit, and the gate end of the second transistor is connected to the drain end of the second transistor. Since the potential of the substrate end of the first transistor changes with the first parameter, the output end can output a potential that changes with any one of the power supply voltage, the working temperature and the manufacturing process.

[0013] Optionally, the first parameter is the power supply voltage or the working temperature of the potential generation circuit,

[0014] The potential of the substrate end of the first transistor increases with an increase of the first parameter, and the potential of the substrate end of the first transistor decreases with a decrease of the first parameter.

[0015] Optionally, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

[0016] Optionally, a source end of the first transistor is connected to a first voltage node, a source end of the second transistor is connected to a second voltage node, a drain end of the first transistor is connected to a drain end of the second transistor, and a substrate end of the second transistor is connected to the second voltage node.

[0017] Optionally, the application further comprises:

[0018] a constant current source, a first end of the constant current source is connected to the first voltage node, and a second end of the constant current source is connected to a third voltage node.

[0019] Optionally, the application further comprises:

[0020] An error amplifier, and the first transistor constitutes a feedback loop, and the substrate end of the first transistor is connected to one voltage node of the first feedback loop.

[0021] Optionally, the negative input end of the error amplifier is connected to the first voltage node, the positive input end of the error amplifier is connected to the first reference voltage, and the output end of the error amplifier is connected to the substrate end of the first transistor.

[0022] Optionally, the third voltage node is connected to a power supply end, the first reference voltage is connected to the power supply end, and the potential of the third voltage node is greater than the potential of the first reference voltage.

[0023] Optionally, further comprising:

[0024] A buffer, the buffer is connected to the output end, and outputs a substrate potential, and the value of the substrate potential is equal to the potential value of the substrate end of the first transistor.

[0025] In a second aspect, the present application provides a potential generating circuit, comprising:

[0026] A first transistor and a second transistor, the potential of the substrate end of the second transistor changes with a first parameter, and the first parameter is any one of the supply voltage, the working temperature and the manufacturing process of the potential generating circuit;

[0027] Wherein, the gate end of the first transistor is connected to the drain end of the first transistor, the gate end of the second transistor is connected to the drain end of the second transistor, and the substrate end of the second transistor serves as the output end of the potential generating circuit.

[0028] The potential generating circuit provided by the present application, by setting the first transistor and the second transistor, the gate end of the first transistor is connected to the drain end of the first transistor, the gate end of the second transistor is connected to the drain end of the second transistor, the potential of the substrate end of the second transistor T2 changes with the first parameter, and the substrate end of the second transistor serves as the output end of the potential generating circuit. Since the potential of the substrate end of the second transistor changes with the first parameter, the output end can output a potential that changes with any one of the supply voltage, the working temperature and the manufacturing process.

[0029] Optionally, the first parameter is the supply voltage or the working temperature of the potential generating circuit, the potential of the substrate end of the second transistor decreases as the first parameter increases, and the potential of the substrate end of the second transistor increases as the first parameter decreases.

[0030] Optionally, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

[0031] Optionally, a source terminal of the first transistor is connected to a first voltage node, a source terminal of the second transistor is connected to a second voltage node, a drain terminal of the first transistor is connected to a drain terminal of the second transistor, and a substrate terminal of the first transistor is connected to the first voltage node.

[0032] Optionally, the potential generation circuit further comprises:

[0033] a constant current source, a first terminal of the constant current source being connected to a third voltage node, and a second terminal of the constant current source being connected to the second voltage node.

[0034] Optionally, the potential generation circuit further comprises:

[0035] an error amplifier, the error amplifier and the second transistor forming a feedback loop, and a substrate terminal of the second transistor being connected to a voltage node of the first feedback loop.

[0036] Optionally, a negative input terminal of the error amplifier is connected to the second voltage node, a positive input terminal of the error amplifier is connected to a first reference voltage, and an output terminal of the error amplifier is connected to the substrate terminal of the second transistor.

[0037] Optionally, the first voltage node is connected to a power supply terminal, the first reference voltage is connected to a ground terminal, and a potential of the third voltage node is less than a potential of the first reference voltage.

[0038] Optionally, the potential generation circuit further comprises:

[0039] a buffer, the buffer being connected to the output terminal and outputting a substrate potential, a value of the substrate potential being equal to a potential value of the substrate terminal of the second transistor.

[0040] In a third aspect, the present application provides a delay circuit, comprising:

[0041] the potential generation circuit as claimed in the first aspect or any one of the embodiments of the first aspect;

[0042] a delay unit, the delay unit comprising a first inverter, the first inverter comprising a fourth transistor and a fifth transistor, a substrate terminal of the fourth transistor being connected to a potential of the substrate terminal of the first transistor, a substrate terminal of the fifth transistor being connected to a ground terminal, the fourth transistor being a P-type transistor, and the fifth transistor being an N-type transistor.

[0043] Optionally, a ratio of a channel length of the first transistor to a channel length of the fourth transistor is denoted as H, a ratio of a channel length of the second transistor to a channel length of the fifth transistor is denoted as L, a ratio of a channel width of the first transistor to a channel width of the fourth transistor is denoted as M, and a ratio of a channel width of the second transistor to a channel width of the fifth transistor is denoted as N, the H is equal to the L, and the M is equal to the N.

[0044] The delay circuit provided in the application can adjust the current flowing through the P-type transistor in the inverter, compensate the change value of the current flowing through the P-type transistor in the inverter, so that the change of the rising edge delay time T of the delay circuit is smaller, and the control ability of the delay circuit on the rising edge delay time precision is improved.

[0045] In a fourth aspect, the application provides a delay circuit, comprising:

[0046] The potential generating circuit as claimed in the second aspect or any one of the embodiments of the second aspect;

[0047] The delay unit comprises a first inverter, the first inverter comprises a fourth transistor and a fifth transistor, a substrate end of the fourth transistor is connected to the potential of the substrate end of the first transistor, a substrate end of the fifth transistor is connected to the power supply end, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0048] The delay circuit provided in the application can adjust the current flowing through the P-type transistor in the inverter, compensate the change value of the current flowing through the P-type transistor in the inverter, so that the change of the rising edge delay time T of the delay circuit is smaller, and the control ability of the delay circuit on the rising edge delay time precision is improved.

[0049] Optionally, a ratio of a channel length of the first transistor to a channel length of the fourth transistor is denoted as H, a ratio of a channel length of the second transistor to a channel length of the fifth transistor is denoted as L, a ratio of a channel width of the first transistor to a channel width of the fourth transistor is denoted as M, and a ratio of a channel width of the second transistor to a channel width of the fifth transistor is denoted as N, the H is equal to the L, and the M is equal to the N.

[0050] In a fifth aspect, the present application provides a delay circuit, comprising:

[0051] a first potential generating circuit, which is the potential generating circuit as described in any one of the first aspect and the implementation manners of the first aspect;

[0052] a second potential generating circuit, which is the potential generating circuit as described in any one of the second aspect and the implementation manners of the second aspect;

[0053] a delay unit, which comprises a first inverter, the first inverter comprises a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the potential of the substrate end of the first transistor in the first potential generating circuit, the substrate end of the fifth transistor is connected to the potential of the substrate end of the second transistor in the second potential generating circuit, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0054] The delay circuit provided by the present application can compensate the influence of any one of the power supply voltage, the working temperature and the manufacturing process on the rising edge delay time and the falling edge delay time, so that the changes of the rising edge delay time T and the falling edge delay time T are small, and the control ability of the delay circuit on the rising edge delay time and the falling edge delay time precision is improved.

[0055] Optionally, the ratio of the channel length of the first transistor in the first potential generating circuit to the channel length of the fourth transistor is H1, the ratio of the channel length of the second transistor in the first potential generating circuit to the channel length of the fifth transistor is L1, the ratio of the channel width of the first transistor in the first potential generating circuit to the channel width of the fourth transistor is M1, the ratio of the channel width of the second transistor in the first potential generating circuit to the channel width of the fifth transistor is N1, the H1 is equal to the L1, and the M1 is equal to the N1.

[0056] The ratio of the channel length of the first transistor in the second potential generating circuit to the channel length of the fourth transistor is H2, the ratio of the channel length of the second transistor in the second potential generating circuit to the channel length of the fifth transistor is L2, the ratio of the channel width of the first transistor in the second potential generating circuit to the channel width of the fourth transistor is M2, the ratio of the channel width of the second transistor in the second potential generating circuit to the channel width of the fifth transistor is N2, the H2 is equal to the L2, and the M2 is equal to the N2.

[0057] In a sixth aspect, the present application provides an inverter, comprising:

[0058] a P-type transistor and an N-type transistor, a source terminal of the P-type transistor is connected to a power supply terminal, a drain terminal of the P-type transistor is connected to a drain terminal of the N-type transistor, a source terminal of the N-type transistor is connected to a ground terminal, a gate terminal of the P-type transistor is connected to a gate terminal of the N-type transistor and serves as an input terminal of the inverter, and a drain terminal of the P-type transistor serves as an output terminal of the inverter.

[0059] a substrate terminal of the P-type transistor is connected to a substrate potential, a substrate terminal of the N-type transistor is connected to the ground terminal, and the substrate potential changes with a first parameter, the first parameter being any one of a power supply voltage, an operating temperature and a manufacturing process of the inverter.

[0060] optionally, the first parameter is the power supply voltage or the operating temperature of the inverter,

[0061] the substrate potential increases with an increase of the first parameter, and the substrate potential decreases with an increase of the first parameter.

[0062] The inverter provided by the application can provide the substrate potential of the P-type transistor TP2 to change with any one of the power supply voltage, the operating temperature and the manufacturing process, so as to adjust the current flowing through the P-type transistor TP2 of the inverter, compensate the change value of the current flowing through the P-type transistor TP2, and make the change of the rising edge delay time T of the inverter smaller, thereby improving the control ability of the inverter on the rising edge delay time precision.

[0063] In a seventh aspect, the application provides an inverter, comprising:

[0064] a P-type transistor and an N-type transistor, a source terminal of the P-type transistor is connected to a power supply terminal, a drain terminal of the P-type transistor is connected to a drain terminal of the N-type transistor, a source terminal of the N-type transistor is connected to a ground terminal, a gate terminal of the P-type transistor is connected to a gate terminal of the N-type transistor and serves as an input terminal of the inverter, and a drain terminal of the P-type transistor serves as an output terminal of the inverter;

[0065] a substrate terminal of the N-type transistor is connected to a substrate potential, a substrate terminal of the P-type transistor is connected to the power supply terminal, and the substrate potential changes with a first parameter, the first parameter being any one of a power supply voltage, an operating temperature and a manufacturing process of the inverter.

[0066] The inverter provided by the application can provide a substrate potential of the N-type transistor TN2 that changes with the first parameter, thereby adjusting the current of the N-type transistor TN2 passing through the inverter, compensating the change value of the current of the N-type transistor TN2, making the change of the falling edge delay time T of the inverter smaller, and improving the control ability of the inverter on the precision of the falling edge delay time.

[0067] Optionally, the first parameter is a supply voltage or a working temperature of the inverter.

[0068] The first substrate potential decreases with the decrease of the first parameter, and the second substrate potential increases with the decrease of the first parameter.

[0069] In an eighth aspect, the application provides a delay circuit, comprising:

[0070] The inverter as claimed in any one of the fifth aspect and the implementation manners of the fifth aspect, and the sixth aspect and the implementation manners of the sixth aspect;

[0071] A capacitor, one end of which is connected to the output end of the inverter, and the other end of which is connected to the power supply end or the ground end.

[0072] Optionally, the capacitor is a capacitor array.

[0073] The delay circuit provided by the application can compensate the change value of the current of the P-type transistor TP2 passing through the inverter, make the change of the rising edge delay time T of the inverter smaller, and further make the change of the rising edge delay time T of the delay circuit smaller, thereby improving the control ability of the delay circuit on the precision of the rising edge delay time.

[0074] In a ninth aspect, the application provides a logic gate circuit, comprising:

[0075] A P-type transistor and an N-type transistor, a substrate end of the P-type transistor being connected to a substrate potential, a substrate end of the N-type transistor being connected to a ground end, the substrate potential changing with a first parameter, so that the delay time of the logic gate circuit from an input end to an output end changes within a first range with the change value of the first parameter, the first parameter including any one of a supply voltage, a working temperature and a manufacturing process of the logic gate circuit.

[0076] The logic gate circuit provided by the application can make the rising edge delay time of the logic gate circuit from the input end to the output end change smaller when any one of the supply voltage, the working temperature and the manufacturing process changes, thereby improving the control ability of the logic gate circuit on the precision of the rising edge delay time.

[0077] In a tenth aspect, the present application provides a logic gate circuit, comprising:

[0078] a P-type transistor and an N-type transistor, a substrate end of the N-type transistor being connected to a substrate potential, a substrate end of the P-type transistor being connected to a power supply end, the substrate potential being changed with a first parameter, so that a delay time of the logic gate circuit from an input end to an output end is changed within a first range with a change value of the first parameter, the first parameter including any one of a supply voltage, an operating temperature and a manufacturing process of the logic gate circuit.

[0079] The logic gate circuit provided by the present application can make the falling edge delay time of the logic gate circuit from the input end to the output end change less when any one of the supply voltage, the operating temperature and the manufacturing process changes, and improve the control ability of the logic gate circuit on the falling edge delay time precision. BRIEF DESCRIPTION OF DRAWINGS

[0080] In order to more clearly illustrate the technical solutions in the present application or prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative labor under the premise of the drawings.

[0081] Figure 1 is a schematic diagram of an input signal and an output signal through a delay circuit;

[0082] Figure 2 is a schematic diagram of an input signal and an output signal through a delay circuit;

[0083] Figure 3 is a schematic diagram of an input signal and an output signal through a delay circuit;

[0084] Figure 4 is a structural schematic diagram of a potential generating circuit provided by an embodiment of the present application;

[0085] Figure 5 is a structural schematic diagram of a potential generating circuit provided by an embodiment of the present application;

[0086] Figure 6 is a structural schematic diagram of a potential generating circuit provided by an embodiment of the present application;

[0087] Figure 7 is a structural schematic diagram of a potential generating circuit provided by an embodiment of the present application;

[0088] Figure 8 is a structural schematic diagram of a potential generating circuit provided by an embodiment of the present application;

[0089] Figure 9 A structure diagram of a potential generation circuit provided for an embodiment of the present application;

[0090] Figure 10 A structure diagram of a potential generation circuit provided for an embodiment of the present application;

[0091] Figure 11 A structure diagram of a potential generation circuit provided for an embodiment of the present application;

[0092] Figure 12 A structure diagram of a potential generation circuit provided for an embodiment of the present application;

[0093] Figure 13 A structure diagram of a delay circuit provided for an embodiment of the present application;

[0094] Figure 14 A structure diagram of a delay circuit provided for an embodiment of the present application;

[0095] Figure 15 A structure diagram of a delay circuit provided for an embodiment of the present application;

[0096] Figure 16 A structure diagram of an inverter provided for an embodiment of the present application;

[0097] Figure 17 A structure diagram of a delay circuit provided for an embodiment of the present application;

[0098] Figure 18 A structure diagram of a potential generation circuit provided for an embodiment of the present application;

[0099] Figure 19 A structure diagram of a potential generation circuit provided for an embodiment of the present application;

[0100] Figure 20 A structure diagram of a potential generation circuit provided for an embodiment of the present application;

[0101] Figure 21 A structure diagram of a potential generation circuit provided for an embodiment of the present application;

[0102] Figure 22 A structure diagram of a potential generation circuit provided for an embodiment of the present application;

[0103] Figure 23 A structure diagram of a potential generation circuit provided for an embodiment of the present application;

[0104] Figure 24 A structure diagram of a potential generation circuit provided for an embodiment of the present application;

[0105] Figure 25 A structure diagram of a potential generation circuit provided for an embodiment of the present application is shown in FIG. 1;

[0106] Figure 26 A structure diagram of a potential generation circuit provided for an embodiment of the present application is shown in FIG. 1;

[0107] Figure 27 A structure diagram of a potential generation circuit provided for an embodiment of the present application is shown in FIG. 1;

[0108] Figure 28 A structure diagram of a delay circuit provided for an embodiment of the present application is shown in FIG. 2;

[0109] Figure 29 A structure diagram of a delay circuit provided for an embodiment of the present application is shown in FIG. 2;

[0110] Figure 30 A structure diagram of a delay circuit provided for an embodiment of the present application is shown in FIG. 2;

[0111] Figure 31 A structure diagram of an inverter provided for an embodiment of the present application is shown in FIG. 3;

[0112] Figure 32 A structure diagram of an inverter provided for an embodiment of the present application is shown in FIG. 3;

[0113] Figure 33 A structure diagram of a delay circuit provided for an embodiment of the present application is shown in FIG. 2;

[0114] Figure 34 A structure diagram of a delay circuit provided for an embodiment of the present application is shown in FIG. 2;

[0115] Figure 35 A structure diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 4;

[0116] Figure 36 A structure diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 4;

[0117] Figure 37 A structure diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 4;

[0118] Figure 38 A structure diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 4;

[0119] Figure 39 A structure diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 4;

[0120] Figure 40 A structure diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 4;

[0121] Figure 41 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0122] Figure 42 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0123] Figure 43 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0124] Figure 44 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0125] Figure 45 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0126] Figure 46 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0127] Figure 47 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0128] Figure 48 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0129] Figure 49 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0130] Figure 50 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0131] Figure 51 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0132] Figure 52 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0133] Figure 53 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1.

[0134] Figure 54 A structural schematic diagram of a control circuit provided for an embodiment of the present application is shown in FIG. 1. DETAILED DESCRIPTION

[0135] In order to make the purposes, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below in conjunction with the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0136] Firstly, the rising edge delay time and the falling edge delay time involved in the present application are explained so as to facilitate understanding.

[0137] 1. The rising edge delay time, as shown in FIG. 1, the delay time T between the rising edge of the output signal and the rising edge of the input signal is the rising edge delay time. Figure 1 FIG. 1 is a schematic diagram of an input signal and an output signal after passing through a delay circuit. Figure 1 The delay time T between the rising edge of the output signal and the rising edge of the input signal is the rising edge delay time.

[0138] 2. The falling edge delay time, as shown in FIG. 2, the delay time T between the falling edge of the output signal and the falling edge of the input signal is the falling edge delay time. Figure 1

[0139] The delay circuit provided by the present application can delay the rising edge and the falling edge of the input signal by the delay time T, and the width of the pulse signal remains unchanged, as shown in FIG. 3. Figure 1 The delay circuit provided by the present application can delay the rising edge of the input signal by the delay time T, and can also delay the falling edge of the input signal by the delay time T. Figure 2 FIG. 4 is a schematic diagram of an input signal and an output signal after passing through a delay circuit. Figure 2 The rising edge of the input signal is delayed by the delay time T to obtain the output signal, and the width of the pulse signal is shortened by the time T. Figure 3 FIG. 5 is a schematic diagram of an input signal and an output signal after passing through a delay circuit. Figure 3 The falling edge of the input signal is delayed by the delay time T to obtain the output signal, and the width of the pulse signal is lengthened by the time T. It should be noted that, Figures 1-3 FIG. 5 only shows one period of the pulse signal.

[0140] The delay circuit provided by the present application can be applied to a scene in which the delay time of the delay circuit needs to be controlled accurately, for example, can be applied to DRAM, and can compensate the influence of any one of the power supply voltage, the working temperature and the manufacturing process on the delay time, so that the change of the delay time T is small, and the control ability of the delay circuit on the delay time precision is improved.

[0141] ​The delay unit in the existing delay circuit includes an inverter composed of two transistors (a P-type transistor and an N-type transistor), and the delay time T of an output signal passing through the delay circuit will change greatly with changes in the power supply voltage, working temperature and manufacturing process, which will affect the precision of the delay time. To solve this problem, the present application starts from the structure of the delay unit. Since the current flowing through the two transistors of the inverter will change when the power supply voltage, working temperature and manufacturing process change, which will cause the delay time to change, the present application provides a delay circuit, which includes a potential generating circuit and a delay unit. The potential generating circuit includes a first transistor and a second transistor. The potential at the substrate end of the first transistor changes with a first parameter, and the potential at the substrate end of the second transistor changes with the first parameter. The first parameter is any one of the power supply voltage, working temperature and manufacturing process of the potential generating circuit. The delay unit includes a first inverter, and the first inverter includes a fourth transistor and a fifth transistor. The substrate end of the fourth transistor is connected to the potential at the substrate end of the first transistor, and the substrate end of the fifth transistor is connected to the potential at the substrate end of the second transistor.

[0142] Since the potential at the substrate end of the first transistor can change with any one of the power supply voltage, working temperature and manufacturing process, the substrate potential that changes with the first parameter can be provided to the substrate end of the fourth transistor, and the potential at the substrate end of the second transistor can change with any one of the power supply voltage, working temperature and manufacturing process, so that the substrate potential that changes with the first parameter can be provided to the substrate end of the fifth transistor. Therefore, the current flowing through the two transistors of the first inverter can be adjusted, the change value of the current flowing through the two transistors of the inverter is compensated, the change of the delay time T of the delay circuit is small, and the control ability of the delay circuit on the delay time precision is improved.

[0143] The specific structure of the potential generating circuit, the inverter, the delay circuit and the logic gate circuit provided by the present application will be described in detail below through specific embodiments.

[0144] Embodiment one

[0145] Figure 4 The structure diagram of a potential generating circuit provided by the present application is shown in Figure 4 The potential generating circuit of the present embodiment can include a first transistor T1 and a second transistor T2. The potential at the substrate end of the first transistor T1 changes with a first parameter, and the first parameter is any one of the power supply voltage, working temperature and manufacturing process of the potential generating circuit. The potential at the substrate end of the second transistor T2 changes with the first parameter.

[0146] The gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the substrate terminal of the first transistor T1 is the first output terminal of the potential generating circuit, the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2, and the substrate terminal of the second transistor T2 is the second output terminal of the potential generating circuit.

[0147] Specifically, the potential of the substrate terminal of the first transistor T1 is the potential output by the first output terminal, and the potential of the substrate terminal of the second transistor T2 is the potential output by the second output terminal. The potential of the substrate terminal of the first transistor T1 changes with the first parameter, and the potential of the substrate terminal of the second transistor T2 changes with the first parameter. Therefore, the potential generating circuit provided in the embodiment can output a potential that changes with any one of the supply voltage, the working temperature, and the manufacturing process.

[0148] Specifically, if the first parameter is the supply voltage or the working temperature of the potential generating circuit, the potential of the substrate terminal of the first transistor T1 changes with the first parameter, and the potential of the substrate terminal of the second transistor T2 changes with the first parameter. Specifically, the potential of the substrate terminal of the first transistor T1 increases with the increase of the first parameter, and the potential of the substrate terminal of the first transistor T1 decreases with the decrease of the first parameter, that is, the two are in a proportional relationship. The potential of the substrate terminal of the second transistor T2 decreases with the increase of the first parameter, and the potential of the substrate terminal of the second transistor T2 increases with the decrease of the first parameter.

[0149] In an implementable manner, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor.

[0150] In an implementable manner, the source terminal of the first transistor T1 is connected to the first voltage node, the source terminal of the second transistor T2 is connected to the second voltage node, and the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2.

[0151] In this embodiment, Figure 5 A structural schematic diagram of a potential generating circuit provided in the embodiment is shown in FIG. 1. The potential generating circuit in the embodiment is based on the circuit shown in FIG. 1, and further includes a constant current source 11. Figure 5 The constant current source 11 has a first terminal connected to the second voltage node and a second terminal connected to a third voltage node. Figure 4

[0152] Figure 6 A structural schematic diagram of a potential generating circuit provided in the embodiment is shown in FIG. 1. The potential generating circuit in the embodiment is based on the circuit shown in FIG. 1, and further includes a constant current source 11. Figure 6 The constant current source 11 has a first terminal connected to the second voltage node and a second terminal connected to a third voltage node. Figure 5 ​Based on the circuit shown, it may further include: a first error amplifier 12, a second error amplifier 13, and a third transistor T3, wherein,

[0153] The first error amplifier 12 and the second transistor T2 form a first feedback loop, and the substrate of the second transistor T2 is connected to a voltage node of the first feedback loop.

[0154] The second error amplifier 13 and the third transistor T3 constitute the second feedback loop, and the substrate of the first transistor is connected to a voltage node of the second feedback loop.

[0155] like Figure 6 As shown, optionally, the negative input terminal of the first error amplifier 12 is connected to the second voltage node, the positive input terminal of the first error amplifier 12 is connected to the first reference voltage V1, and the output terminal of the first error amplifier 12 is connected to the substrate terminal of the second transistor T2.

[0156] The negative input terminal of the second error amplifier 13 is connected to the second reference voltage V2, the positive input terminal of the second error amplifier 13 is connected to the fourth voltage node, the output terminal of the second error amplifier 13 is connected to the gate terminal of the third transistor T3, the source terminal of the third transistor T3 is connected to the first voltage node, the drain terminal of the third transistor T3 is coupled to the fourth voltage node through the first resistor R1, and the output terminal of the first error amplifier 12 is coupled to the fourth voltage node through the second resistor R2.

[0157] In this embodiment, the first voltage node can be connected to the power supply terminal, the first reference voltage V1 can be connected to the ground terminal, and the potential of the third voltage node is less than the potential of the first reference voltage V1.

[0158] Figure 6 In the potential generation circuit shown, the first voltage node is connected to the power supply terminal, the first reference voltage V1 is connected to the ground terminal, and the potential of the third voltage node is less than the potential of V1, that is, the potential of the third voltage node is less than 0. The potential of the first voltage node is greater than the potential of the third voltage node.

[0159] The following is combined Figure 7 and Figure 8 Another potential generation circuit is shown below, in conjunction with... Figure 7 and Figure 8 Please provide a detailed explanation.

[0160] Figure 7 This is a schematic diagram of a potential generation circuit provided in an embodiment of this application, as shown below. Figure 7 As shown, the potential generation circuit in this embodiment is... Figure 4On the basis of the circuit shown, further, can include: constant current source 11, the first end of constant current source 11 connects the third voltage node, the second end of constant current source 11 connects the first voltage node.

[0161] Figure 8 For the structure schematic diagram of potential generation circuit provided by the embodiment of the application, as Figure 8 Shown, the potential generation circuit of the embodiment can further include, on the basis of the circuit shown: Figure 7 Shown, the potential generation circuit of the embodiment can further include, on the basis of the circuit shown:

[0162] Second error amplifier 13 and third transistor T3, second error amplifier 13 and third transistor T3 constitute a second feedback loop, the substrate end of the second transistor T2 is connected to one voltage node of the second feedback loop.

[0163] As Figure 8 Shown, optionally, the negative input end of the first error amplifier 12 is connected to the first voltage node, the positive input end of the first error amplifier is connected to the first reference voltage V1, and the output end of the first error amplifier 12 is connected to the substrate end of the first transistor T1.

[0164] The negative input end of the second error amplifier 13 is connected to the second reference voltage V2, the positive input end of the second error amplifier 13 is connected to the fourth voltage node, the output end of the second error amplifier 13 is connected to the gate end of the third transistor T3, the source end of the third transistor T3 is connected to the second voltage node, the drain end of the third transistor T3 is coupled to the fourth voltage node through the second resistance R2, and the output end of the first error amplifier 12 is coupled to the fourth voltage node through the first resistance R1.

[0165] In the embodiment, the second voltage node can be connected to the ground end, the first reference voltage V1 can be connected to the power supply end, and the potential of the third voltage node is greater than the potential of the first reference voltage V1.

[0166] Figure 8 In the potential generation circuit shown, the second voltage node is connected to the ground end, the first reference voltage V1 is connected to the power supply end, and the potential of the third voltage node is greater than the potential of V1, that is, the potential of the third voltage node is greater than the potential of the power supply end. The potential of the first voltage node is less than the potential of the third voltage node.

[0167] Figures 4-8Any of the potential generating circuits, by setting a first transistor and a second transistor, a gate terminal of the first transistor is connected to a drain terminal of the first transistor, a substrate terminal of the first transistor is as a first output terminal of the potential generating circuit, a gate terminal of the second transistor is connected to a drain terminal of the second transistor, a substrate terminal of the second transistor is as a second output terminal of the potential generating circuit, since the potential of the substrate terminal of the first transistor changes with the first parameter, the potential of the substrate terminal of the second transistor changes with the first parameter, so that the first output terminal and the second output terminal can output the potential which changes with any of the power supply voltage, the working temperature and the manufacturing process, respectively.

[0168] Further, in Figures 4-8 Any of the potential generating circuits, by setting a first transistor and a second transistor, a gate terminal of the first transistor is connected to a drain terminal of the first transistor, a substrate terminal of the first transistor is as a first output terminal of the potential generating circuit, a gate terminal of the second transistor is connected to a drain terminal of the second transistor, a substrate terminal of the second transistor is as a second output terminal of the potential generating circuit, since the potential of the substrate terminal of the first transistor changes with the first parameter, the potential of the substrate terminal of the second transistor changes with the first parameter, so that the first output terminal and the second output terminal can output the potential which changes with any of the power supply voltage, the working temperature and the manufacturing process, respectively. Figure 9 A structure schematic diagram of a potential generating circuit provided by the embodiment of the present application, Figure 10 A structure schematic diagram of a potential generating circuit provided by the embodiment of the present application, Figure 9 The potential generating circuit shown in Figure 6 Any of the potential generating circuits, by setting a first transistor and a second transistor, a gate terminal of the first transistor is connected to a drain terminal of the first transistor, a substrate terminal of the first transistor is as a first output terminal of the potential generating circuit, a gate terminal of the second transistor is connected to a drain terminal of the second transistor, a substrate terminal of the second transistor is as a second output terminal of the potential generating circuit, since the potential of the substrate terminal of the first transistor changes with the first parameter, the potential of the substrate terminal of the second transistor changes with the first parameter, so that the first output terminal and the second output terminal can output the potential which changes with any of the power supply voltage, the working temperature and the manufacturing process, respectively. Figure 10 The potential generating circuit shown in Figure 8 Any of the potential generating circuits, by setting a first transistor and a second transistor, a gate terminal of the first transistor is connected to a drain terminal of the first transistor, a substrate terminal of the first transistor is as a first output terminal of the potential generating circuit, a gate terminal of the second transistor is connected to a drain terminal of the second transistor, a substrate terminal of the second transistor is as a second output terminal of the potential generating circuit, since the potential of the substrate terminal of the first transistor changes with the first parameter, the potential of the substrate terminal of the second transistor changes with the first parameter, so that the first output terminal and the second output terminal can output the potential which changes with any of the power supply voltage, the working temperature and the manufacturing process, respectively.

[0169] Referring to Figure 9 And Figure 10 The first buffer 14 is connected to the first output terminal and outputs a first substrate potential, the value of the first substrate potential is equal to the potential value of the substrate terminal of the first transistor T1. The input potential and the output potential of the first buffer 14 are the same, the first buffer 14 is used to enhance the driving ability of the potential of the substrate terminal of the first transistor T1, and can also isolate the substrate terminal of the first transistor T1 to avoid the potential of the substrate terminal of the first transistor T1 being disturbed.

[0170] The second buffer 15 is connected to the second output terminal and outputs a second substrate potential, the value of the second substrate potential is equal to the potential value of the substrate terminal of the second transistor T2. The input potential and the output potential of the second buffer 15 are the same, the second buffer 15 is used to enhance the driving ability of the potential of the substrate terminal of the second transistor T2, and can also isolate the substrate terminal of the second transistor T2 to avoid the potential of the substrate terminal of the second transistor T2 being disturbed.

[0171] The structure of the potential generating circuit of the present application will be described below in combination with specific embodiments, and the specific structure of the potential generating circuit of the present application is not limited to any of the following structures.

[0172] Figure 11A structure diagram of a potential generation circuit is provided in the embodiment of the present application. The potential generation circuit can include a first transistor T1, a second transistor T2, a constant current source 11, a first error amplifier 12, a second error amplifier 13, a first resistor R1, a second resistor R2, a third transistor T3, a first buffer 14, and a second buffer 15.

[0173] In the embodiment, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2, the source terminal of the first transistor T1 is connected to a power supply terminal Vcc, the source terminal of the second transistor T2 is connected to the first terminal of the constant current source 11, and the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2. The second terminal of the constant current source 11 is connected to Vkb, and the potential of Vkb is less than 0.

[0174] The first error amplifier 12 and the second transistor T2 form a first feedback loop. The negative input terminal of the first error amplifier 12 is connected to the source terminal of the second transistor T2 and the first terminal of the constant current source 11, the positive input terminal of the first error amplifier 12 is connected to a ground terminal, and the output terminal of the first error amplifier 12 is connected to the substrate terminal of the second transistor T2.

[0175] The negative input terminal of the second error amplifier 13 is connected to a power supply terminal (for example, Vcc / 2), the positive input terminal of the second error amplifier 13 is connected to a fourth voltage node, the output terminal of the second error amplifier 13 is connected to the gate terminal of the third transistor T3, the source terminal of the third transistor T3 is connected to the power supply terminal Vcc, the drain terminal of the third transistor T3 is coupled to the fourth voltage node through the first resistor R1, and the output terminal of the first error amplifier 12 is coupled to the fourth voltage node through the second resistor R2.

[0176] The first buffer 14 is connected to the substrate terminal of the first transistor and outputs a first substrate potential, and the value of the first substrate potential is equal to the potential value of the substrate terminal of the first transistor T1. The second buffer 15 is connected to the substrate terminal of the second transistor and outputs a second substrate potential, and the value of the second substrate potential is equal to the potential value of the substrate terminal of the second transistor T2.

[0177] Optionally, the resistance values of the first resistor R1 and the second resistor R2 can be set to be large, for example, 100MΩ. By setting the resistance values of the first resistor R1 and the second resistor R2 to be large, the output of the first error amplifier 12 only slowly affects the input of the second error amplifier 13, and has little effect on the first substrate potential.

[0178] In this embodiment, the potential of the substrate end of the first transistor T1 increases with the increase of the first parameter, and the potential of the substrate end of the first transistor T1 decreases with the decrease of the first parameter; the potential of the substrate end of the second transistor T2 decreases with the increase of the first parameter, and the potential of the substrate end of the second transistor T2 increases with the decrease of the first parameter, the first parameter being any one of the supply voltage, the working temperature and the manufacturing process of the potential generating circuit.

[0179] Taking the working temperature as the first parameter, the principle that the potential of the substrate end of the first transistor T1 changes with the change of the first parameter, and the principle that the potential of the substrate end of the second transistor T2 changes with the change of the first parameter are described in detail below.

[0180] The current Id flowing through the first transistor T1 is μ*Cox*(W / L)*(Vgs-Vth) 2 Wherein, μ is the electron mobility, Cox is the gate capacitance, Vgs is the voltage difference between the gate and the source, and Vth is the threshold voltage. For example, when the working temperature increases, the electron mobility μ decreases, which will cause the current Id flowing through the first transistor T1 to decrease, and the delay time of the corresponding inverter to become longer. At this time, if Vgs-Vth is adjusted to be larger, the change of the current caused by the decrease of the electron mobility μ can be compensated. The specific adjustment value can be set according to actual needs. Figure 11 In the potential generating circuit shown, if the temperature increases, the electron mobility μ decreases, and the current Id flowing through the first transistor T1 decreases. In order to keep the current of the constant current source unchanged, the first substrate potential needs to be increased, for example, to Vcc+100mV, and the second substrate potential needs to be decreased, for example, to -100mV. When the temperature increases, the current Id flowing through the first transistor T1 and the second transistor T2 decreases. For the constant current source 11, the current provided from the upper side decreases, while the current flowing to the lower side remains unchanged, so that the negative input end potential of the first error amplifier 12 decreases, and then the second substrate potential decreases. At this time, it will cause the output of the first error amplifier 12 to gradually become -100mV, and then the positive input end of the second error amplifier 13 decreases, causing the output voltage of the second error amplifier 13 to decrease, and then causing the pull-up ability of the third transistor T3 to increase, and then causing the voltage of the first substrate potential to increase. The first substrate potential gradually becomes Vcc+100mV.

[0181] When the first parameter is the supply voltage and the manufacturing process, the change of the supply voltage and the manufacturing process will cause the current Id flowing through the first transistor T1 to change, and then cause the delay time to change. The compensation principle is similar to the above principle, which is not described here.

[0182] Figure 12A structure diagram of a potential generation circuit is provided in the embodiment, and the potential generation circuit can include: a first transistor T1, a second transistor T2, a constant current source 11, a first error amplifier 12, a second error amplifier 13, a first resistor R1, a second resistor R2, a third transistor T3, a first buffer 14, and a second buffer 15.

[0183] In the embodiment, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2, the source terminal of the first transistor T1 is connected to the first terminal of the constant current source 11, the source terminal of the second transistor T2 is connected to a ground terminal, and the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2. The second terminal of the constant current source 11 is connected to a power supply terminal Vdd.

[0184] The first error amplifier 12 and the first transistor T1 form a first feedback loop, the negative input terminal of the first error amplifier 12 is connected to the first terminal of the constant current source 11, the positive input terminal of the first error amplifier is connected to a power supply terminal Vcc, and the output terminal of the first error amplifier 12 is connected to the substrate terminal of the first transistor T1.

[0185] Vdd is greater than Vcc.

[0186] The negative input terminal of the second error amplifier 13 is connected to a power supply terminal (for example, Vcc / 2), the positive input terminal of the second error amplifier 13 is connected to a fourth voltage node, the output terminal of the second error amplifier 13 is connected to the gate terminal of the third transistor T3, the source terminal of the third transistor T3 is connected to a ground terminal, the drain terminal of the third transistor T3 is coupled to the fourth voltage node through the second resistor R2, and the output terminal of the first error amplifier 12 is coupled to the fourth voltage node through the first resistor R1.

[0187] The first buffer 14 is connected to the substrate terminal of the first transistor and outputs a first substrate potential, and the value of the first substrate potential is equal to the potential value of the substrate terminal of the first transistor T1. The second buffer 15 is connected to the substrate terminal of the second transistor and outputs a second substrate potential, and the value of the second substrate potential is equal to the potential value of the substrate terminal of the second transistor T2.

[0188] In the embodiment, the potential of the substrate terminal of the first transistor T1 increases as the first parameter increases, and the potential of the substrate terminal of the first transistor T1 decreases as the first parameter decreases; the potential of the substrate terminal of the second transistor T2 decreases as the first parameter increases, and the potential of the substrate terminal of the second transistor T2 increases as the first parameter decreases, and the first parameter is any one of the power supply voltage, the working temperature, and the manufacturing process of the potential generation circuit.

[0189] Taking the first parameter as the working temperature as an example, the principle that the potential at the substrate end of the first transistor T1 changes with the first parameter, and the principle that the potential at the substrate end of the second transistor T2 changes with the first parameter are described in detail below.

[0190] The current flowing through the first transistor T1 is Id=μ*Cox*(W / L)*(Vgs-Vth) 2 Wherein, μ is the electron mobility, Vth is the threshold voltage, for example, when the working temperature rises, the electron mobility μ decreases, which will cause the current Id flowing through the first transistor T1 to decrease, and the delay time of the corresponding inverter will become longer, at this time, if Vgs-Vth is adjusted to be larger, the current change caused by the decrease of the electron mobility μ can be compensated, and the specific adjustment value can be set according to actual needs. Figure 12 In the potential generating circuit shown, if the temperature rises, the electron mobility μ decreases, and the current Id flowing through the first transistor T1 decreases, in order to keep the current of the constant current source unchanged, the second substrate potential needs to be reduced, for example, to-100mV, and at the same time, the first substrate potential needs to be increased, for example, to Vcc+100mV. If the temperature rises, the current provided above the constant current source does not change, the current flowing downward from the constant current source is equal to the current Id flowing through the first transistor T1 and the second transistor T2, and Id decreases, so the negative input end potential of the first error amplifier 12 increases, and the first substrate potential increases, which will cause the output of the first error amplifier 12 to gradually become Vcc+100mV, and then the positive input end of the second error amplifier 13 increases, causing the output voltage of the second error amplifier 13 to increase, and then causing the pull-down ability of the third transistor T3 to increase, so that the voltage of the second substrate potential decreases.

[0191] When the first parameter is the supply voltage and the manufacturing process, the change of the supply voltage and the manufacturing process will cause the change of the current Id flowing through the first transistor T1, and then cause the change of the delay time, and the compensation principle is similar to the above principle, which is not described here.

[0192] The embodiment of the application also provides a delay circuit, comprising Figures 4-12 Any of the potential generating circuits and delay units, the delay unit comprises a first inverter, the first inverter comprises a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the potential at the substrate end of the first transistor T1, and the substrate end of the fifth transistor is connected to the potential at the substrate end of the second transistor T2.

[0193] The delay circuit provided by the embodiment can adjust the current flowing through the two transistors of the first inverter, compensate the change value of the current flowing through the two transistors of the inverter, and make the change of the delay time T of the delay circuit smaller, thereby improving the control ability of the delay circuit on the delay time precision.

[0194] When the first transistor is a P-type transistor, the second transistor is an N-type transistor, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor, the change value of the rising delay time of the delay circuit can be adjusted by providing the first substrate end of the P-type transistor with the first substrate potential changing with the first parameter, so that the change of the rising delay time of the delay circuit is smaller, and the change value of the falling delay time of the delay circuit can be adjusted by providing the second substrate end of the N-type transistor with the second substrate potential changing with the first parameter, so that the change of the falling delay time of the delay circuit is smaller.

[0195] It should be noted that, in the embodiment of the present application, the connection relationship between the potential generating circuit and the inverter can be set according to the number of inverters included in the delay circuit and the requirement of delay time compensation, for example, two inverters are connected in series, the substrate end of the P-type transistor in the inverter is connected to the substrate end of the P-type transistor in the potential generating circuit, the change value of the rising delay time of the delay circuit can be adjusted, the substrate end of the N-type transistor in the inverter is connected to the substrate end of the N-type transistor in the potential generating circuit, and the change value of the falling delay time of the delay circuit can be adjusted. The connection relationship between the potential generating circuit and the inverter can be set according to the change value of the rising delay time and / or the falling delay time to be adjusted. The potential generating circuit provided by the embodiment of the present application can be applied to a delay circuit in which the rising delay time and / or the falling delay time is delayed, can reduce the influence of the manufacturing process, the power supply voltage and the working temperature of the delay circuit on the delay time T of the delay circuit, so that the change of the delay time T (including the rising delay time and / or the falling delay time) is smaller, and the control ability of the delay circuit on the delay time precision is improved.

[0196] The following will be described in combination with Figures 13-15 Examples of three delay circuits are given, Figure 13 The structure schematic diagram of a delay circuit provided by the embodiment of the present application is shown in Figure 13 The delay circuit of the embodiment includes a potential generating circuit 1 and a delay unit 2, the potential generating circuit 1 is Figure 11The circuit shown, specific structural description can be seen in Figure 11 In the embodiment shown, the description, here will not be described, potential generating circuit 1 output first substrate potential BP and second substrate potential BN, delay unit 2 includes inverter and capacitor C1, the inverter includes P type transistor TP1 and N type transistor TN1, the substrate end of P type transistor TP1 is connected with first substrate potential BP, the substrate end of N type transistor TN1 is connected with second substrate potential BN. In the delay circuit of the embodiment, potential generating circuit 1 provides the substrate end of P type transistor in delay unit 2 with first substrate potential that changes with the first parameter, when the input end of delay unit 2 is falling edge, first substrate potential BP can adjust the change value of the rising edge delay time of delay circuit, so that the change of the rising edge delay time of delay circuit is smaller, potential generating circuit 1 provides the substrate end of N type transistor in delay unit 2 with second substrate potential that changes with the first parameter, when the input end of delay unit 2 is rising edge, second substrate potential BN can adjust the change value of the falling edge delay time of delay circuit, so that the change of the falling edge delay time of delay circuit is smaller, thereby, the influence of manufacturing process, power supply voltage and working temperature of delay circuit on delay time T of delay circuit can be reduced, so that the change of delay time T (including rising edge and falling edge) is smaller, the control ability of delay circuit to delay time precision is improved. Figure 14 The structure diagram of a delay circuit provided by the embodiment of the application is shown in Figure 14 The delay circuit of the embodiment includes potential generating circuit 1 and delay unit 2, potential generating circuit 1 provides the substrate end of P type transistor in delay unit 2 with first substrate potential that changes with the first parameter, when the input end of delay unit 2 is falling edge, first substrate potential BP can adjust the change value of the rising edge delay time of delay circuit, so that the change of the rising edge delay time of delay circuit is smaller, potential generating circuit 1 provides the substrate end of N type transistor in delay unit 2 with second substrate potential that changes with the first parameter, when the input end of delay unit 2 is rising edge, second substrate potential BN can adjust the change value of the falling edge delay time of delay circuit, so that the change of the falling edge delay time of delay circuit is smaller, thereby, the influence of manufacturing process, power supply voltage and working temperature of delay circuit on delay time T of delay circuit can be reduced, so that the change of delay time T (including rising edge and falling edge) is smaller, the control ability of delay circuit to delay time precision is improved. Figure 11 The circuit shown, specific structural description can be seen in Figure 11 In the embodiment shown, the description, here will not be described, potential generating circuit 1 output first substrate potential BP and second substrate potential BN, delay unit 2 includes first inverter, second inverter and capacitor C1, the first inverter includes P type transistor TP1 and N type transistor TN1, the second inverter includes P type transistor TP2 and N type transistor TN2. Wherein, the substrate end of N type transistor TN1 in delay unit 2 is connected with second substrate potential BN, the substrate end of N type transistor TN2 is connected with second substrate potential BN. In the delay circuit of the embodiment, potential generating circuit 1 provides the substrate end of N type transistor TN1 and N type transistor TN2 in delay unit 2 with second substrate potential BN that changes with the first parameter, when the input end of delay unit 2 is rising edge, can adjust the change value of the falling edge delay time of delay circuit, so that the change of the rising edge delay time of delay circuit is smaller, thereby, the influence of manufacturing process, power supply voltage and working temperature of delay circuit on the rising edge delay time T of delay circuit can be reduced, so that the change of rising edge delay time T is smaller, the control ability of delay circuit to delay time precision is improved.

[0197] It is understandable that in another type of delay circuit, the substrate end of the P-type transistor TP1 in delay unit 2 can be connected to the first substrate potential BP, and the substrate end of the P-type transistor TP2 can be connected to the first substrate potential BP. This can adjust the change value of the falling edge delay time of the delay circuit, so that the change of the falling edge delay time of the delay circuit is small.

[0198] Figure 15 This is a schematic diagram of a delay circuit provided in an embodiment of this application, as shown below. Figure 15 As shown, the delay circuit and in this embodiment Figure 13 The difference in the delay circuit shown is that the potential generation circuit 1 in this embodiment is... Figure 12 The circuit shown is identical in all other aspects and achieves the same effect, so it will not be described in detail here.

[0199] This application embodiment also provides a delay circuit, including Figures 9-12 Any of the potential generation circuits and delay units shown herein, wherein the delay unit includes a first inverter, the first inverter includes a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to a first substrate potential, and the substrate end of the fifth transistor is connected to a second substrate potential.

[0200] The delay circuit provided in this embodiment can provide a first substrate potential that varies with the supply voltage, operating temperature, and manufacturing process to the substrate of the fourth transistor, since the first substrate potential in the potential generation circuit can vary with any of the supply voltage, operating temperature, and manufacturing process. The second substrate potential can also vary with the supply voltage, operating temperature, and manufacturing process, thus providing a second substrate potential that varies with the first parameter to the substrate of the fifth transistor. Therefore, the current flowing through the two transistors of the first inverter can be adjusted to compensate for the change in the current flowing through the two transistors of the inverter, so that the change in the delay time T of the delay circuit is small, thereby improving the control capability of the delay circuit on the delay time accuracy.

[0201] In the two delay circuits described above, let H be the ratio of the channel length of the first transistor T1 to the channel length of the fourth transistor, L be the ratio of the channel length of the second transistor T2 to the channel length of the fifth transistor, M be the ratio of the channel width of the first transistor T1 to the channel width of the fourth transistor, and N be the ratio of the channel width of the second transistor T2 to the channel width of the fifth transistor. H equals L, M equals N, and optionally, H, L, M, and N can all be 1. Optionally, the first and fourth transistors can be of the same type, and the second and fifth transistors can be of the same type.

[0202] This application also provides an inverter. Figure 16 This is a schematic diagram of an inverter provided in an embodiment of this application, as shown below. Figure 16As shown, the inverter includes:

[0203] The P-type transistor TP1 has a source end connected to a power supply end, a drain end connected to a drain end of the N-type transistor TN1, a gate end connected to a gate end of the N-type transistor TN1 and serving as an input end of the inverter, and a drain end serving as an output end of the inverter.

[0204] The substrate end of the P-type transistor TP1 is connected to a first substrate potential, and the substrate end of the N-type transistor TN1 is connected to a second substrate potential. The first substrate potential changes with a first parameter, and the second substrate potential changes with the first parameter. The first parameter is any one of a supply voltage, an operating temperature, and a manufacturing process of the inverter.

[0205] When the first parameter is the supply voltage or the operating temperature, the first substrate potential increases with an increase of the first parameter and decreases with a decrease of the first parameter, and the second substrate potential decreases with the increase of the first parameter and increases with the decrease of the first parameter.

[0206] The inverter provided by the embodiment can provide the first substrate potential changing with the first parameter to the substrate end of the P-type transistor TP1, and can provide the second substrate potential changing with the first parameter to the substrate end of the N-type transistor TN1. Therefore, the current flowing through the P-type transistor TP1 and the N-type transistor TN1 of the inverter can be adjusted, the change value of the current flowing through the two transistors of the inverter can be compensated, the change of the delay time T of the inverter is small, and the control ability of the inverter on the delay time precision is improved.

[0207] The embodiment of the present application further provides a delay circuit, Figure 17 The structure diagram of the delay circuit provided by the embodiment of the present application is shown in Figure 17 As shown, the delay circuit of the embodiment can include Figure 16 As shown, the inverter and the capacitor C1, one end of the capacitor C1 is connected to the ground end. In an implementable manner, the capacitor C1 can be a capacitor array.

[0208] The delay circuit provided by the embodiment can compensate the change value of the current flowing through the two transistors of the inverter, so that the change of the delay time T of the inverter is small, and the change of the delay time T of the delay circuit is small, and the control ability of the delay circuit on the delay time precision is improved.

[0209] This application embodiment also provides a logic gate circuit, including: a P-type transistor and an N-type transistor, the substrate end of the P-type transistor is connected to a first substrate potential, the substrate end of the N-type transistor is connected to a second substrate potential, the first substrate potential and the second substrate potential change with a first parameter, such that the delay time of the logic gate circuit from the input end to the output end changes with the first parameter within a first range, the first parameter including any one of the power supply voltage, operating temperature and manufacturing process of the logic gate circuit.

[0210] Specifically, the first range is a small range, such as a range close to 0. For example, if the first range is 1%, 3%, or 5%, it can make the delay time from the input to the output of the logic gate circuit change less when any of the power supply voltage, operating temperature, and manufacturing process changes, thereby improving the logic gate circuit's ability to control the delay time accuracy.

[0211] Example 2

[0212] Figure 18 This is a schematic diagram of a potential generation circuit provided in an embodiment of this application, as shown below. Figure 18 As shown, the potential generation circuit of this embodiment may include: a first transistor T1 and a second transistor T2, wherein the potential at the substrate end of the first transistor T1 changes with a first parameter, the first parameter being any one of the power supply voltage, operating temperature and manufacturing process of the potential generation circuit.

[0213] In this circuit, the gate terminal of the first transistor T1 is connected to the drain terminal of the first transistor T1, the substrate terminal of the first transistor T1 serves as the output terminal of the potential generation circuit, and the gate terminal of the second transistor T2 is connected to the drain terminal of the second transistor T2.

[0214] Specifically, the potential at the substrate end of the first transistor T1 is the potential output at the output end. The potential at the substrate end of the first transistor T1 changes with the first parameter. Therefore, the potential generation circuit provided in this embodiment can output a potential that changes with any of the following: power supply voltage, operating temperature, and manufacturing process.

[0215] Specifically, if the first parameter is the power supply voltage or operating temperature of the potential generation circuit, the potential at the substrate of the first transistor T1 changes with the first parameter. Specifically, the potential at the substrate of the first transistor T1 increases as the first parameter increases, and decreases as the first parameter decreases, that is, the two are directly proportional.

[0216] In one feasible embodiment, the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor.

[0217] In one feasible embodiment, the source terminal of the first transistor T1 is connected to a first voltage node, the source terminal of the second transistor T2 is connected to a second voltage node, the drain terminal of the first transistor T1 is connected to the drain terminal of the second transistor T2, and the substrate terminal of the second transistor T2 is connected to the second voltage node.

[0218] In this embodiment, Figure 19 This is a schematic diagram of a potential generation circuit provided in an embodiment of this application, as shown below. Figure 19 As shown, the potential generation circuit in this embodiment is... Figure 18 Based on the circuit shown, it may further include: a constant current source 21, the first end of which is connected to the first voltage node, and the second end of which is connected to the third voltage node.

[0219] Figure 20 This is a schematic diagram of a potential generation circuit provided in an embodiment of this application, as shown below. Figure 20 As shown, the potential generation circuit in this embodiment is... Figure 19 Based on the circuit shown, it may further include: an error amplifier 22, which forms a feedback loop with the first transistor T1, wherein the substrate of the first transistor T1 is connected to a voltage node of the first feedback loop.

[0220] like Figure 20 As shown, optionally, the negative input terminal of the error amplifier 22 is connected to the first voltage node, the positive input terminal of the error amplifier 22 is connected to the first reference voltage V1, and the output terminal of the error amplifier 22 is connected to the substrate terminal of the first transistor T1.

[0221] In this embodiment, the first reference voltage V1 can be connected to the power supply terminal, and the potential of the third voltage node is greater than the potential of the first reference voltage V1.

[0222] Figure 20 In the potential generation circuit shown, the potential of the third voltage node is greater than the potential of the first reference voltage V1, and the potential of the first voltage node is less than the potential of the third voltage node. For example, the voltage of the third voltage node can be Vdd, the first reference voltage V1 can be equal to Vcc, and Vdd is greater than Vcc.

[0223] Figures 18-20 Any of the potential generation circuits shown herein, by setting a first transistor and a second transistor, wherein the gate terminal of the first transistor is connected to the drain terminal of the first transistor, the substrate terminal of the first transistor serves as the output terminal of the potential generation circuit, and the gate terminal of the second transistor is connected to the drain terminal of the second transistor, since the potential of the substrate terminal of the first transistor changes with the first parameter, the output terminal can output a potential that changes with any of the following: supply voltage, operating temperature, and manufacturing process.

[0224] Figure 21 A structure diagram of a potential generation circuit provided by an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the potential generation circuit can include a first transistor T1 and a second transistor T2. Figure 21 As shown in FIG. 1, the potential generation circuit can further include a buffer 23 connected to the output end and outputting a substrate potential, the value of the substrate potential being equal to the potential value of the substrate end of the first transistor T1. The input potential and the output potential of the buffer 23 are the same, and the buffer 23 is used to enhance the driving capability of the potential of the substrate end of the first transistor T1, and can also isolate the substrate end of the first transistor T1 to avoid the potential of the substrate end of the first transistor T1 being disturbed. Figure 20 As shown in FIG. 1, the potential generation circuit can further include a buffer 23 connected to the output end and outputting a substrate potential, the value of the substrate potential being equal to the potential value of the substrate end of the first transistor T1. The input potential and the output potential of the buffer 23 are the same, and the buffer 23 is used to enhance the driving capability of the potential of the substrate end of the first transistor T1, and can also isolate the substrate end of the first transistor T1 to avoid the potential of the substrate end of the first transistor T1 being disturbed.

[0225] Another potential generation circuit is shown in FIG. 2. Figures 22-25 A structure diagram of a potential generation circuit provided by an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the potential generation circuit can include a first transistor T1 and a second transistor T2. Figure 22 As shown in FIG. 1, the potential generation circuit can further include a buffer 23 connected to the output end and outputting a substrate potential, the value of the substrate potential being equal to the potential value of the substrate end of the first transistor T1. The input potential and the output potential of the buffer 23 are the same, and the buffer 23 is used to enhance the driving capability of the potential of the substrate end of the first transistor T1, and can also isolate the substrate end of the first transistor T1 to avoid the potential of the substrate end of the first transistor T1 being disturbed. Figure 22 As shown in FIG. 1, the potential generation circuit can further include a buffer 23 connected to the output end and outputting a substrate potential, the value of the substrate potential being equal to the potential value of the substrate end of the first transistor T1. The input potential and the output potential of the buffer 23 are the same, and the buffer 23 is used to enhance the driving capability of the potential of the substrate end of the first transistor T1, and can also isolate the substrate end of the first transistor T1 to avoid the potential of the substrate end of the first transistor T1 being disturbed.

[0226] As shown in FIG. 1, the potential generation circuit can further include a buffer 23 connected to the output end and outputting a substrate potential, the value of the substrate potential being equal to the potential value of the substrate end of the first transistor T1. The input potential and the output potential of the buffer 23 are the same, and the buffer 23 is used to enhance the driving capability of the potential of the substrate end of the first transistor T1, and can also isolate the substrate end of the first transistor T1 to avoid the potential of the substrate end of the first transistor T1 being disturbed.

[0227] Specifically, the potential of the substrate end of the second transistor T2 is the potential output by the output end, and the potential of the substrate end of the second transistor T2 changes with the first parameter, so the potential generation circuit provided by the embodiment can output a potential that changes with any one of the supply voltage, the working temperature and the manufacturing process.

[0228] Specifically, if the first parameter is the supply voltage or the working temperature of the potential generation circuit, the potential of the substrate end of the second transistor T2 changes with the first parameter, and specifically, the potential of the substrate end of the second transistor T2 decreases with the increase of the first parameter, and the potential of the substrate end of the second transistor T2 increases with the decrease of the first parameter.

[0229] In an implementable manner, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor.

[0230] In an implementable manner, the source end of the first transistor T1 is connected to a first voltage node, the source end of the second transistor T2 is connected to a second voltage node, the drain end of the first transistor T1 is connected to the drain end of the second transistor T2, and the substrate end of the first transistor T1 is connected to the first voltage node.

[0231] In this embodiment, Figure 23 This is a schematic diagram of a potential generation circuit provided in an embodiment of this application, as shown below. Figure 23 As shown, the potential generation circuit in this embodiment is... Figure 22 Based on the circuit shown, it may further include: a constant current source 21, the first end of which is connected to a third voltage node, and the second end of which is connected to a second voltage node.

[0232] Figure 24 This is a schematic diagram of a potential generation circuit provided in an embodiment of this application, as shown below. Figure 24 As shown, the potential generation circuit in this embodiment is... Figure 23 Based on the circuit shown, it may further include: an error amplifier 22, which forms a feedback loop with the second transistor T2, wherein the substrate of the second transistor T2 is connected to a voltage node of the first feedback loop.

[0233] like Figure 24 As shown, optionally, the negative input terminal of the error amplifier 22 is connected to the second voltage node, the positive input terminal of the error amplifier 22 is connected to the first reference voltage V1, and the output terminal of the error amplifier 22 is connected to the substrate terminal of the second transistor T2.

[0234] In this embodiment, the first voltage node can be connected to the power supply terminal Vcc, the first reference voltage V1 can be connected to the ground terminal Vss, and the potential of the third voltage node is less than the potential of the first reference voltage V1.

[0235] Figure 24 In the potential generation circuit shown, the first voltage node is connected to the power supply terminal Vcc, the first reference voltage V1 is connected to the ground terminal Vss, the potential of the third voltage node is less than the potential of V1, for example, the potential of the third voltage node is less than 0, and the potential of the second voltage node is greater than the potential of the third voltage node.

[0236] Figures 22-24 Any of the potential generation circuits shown herein includes a first transistor and a second transistor. The gate of the first transistor is connected to its drain, and the gate of the second transistor is connected to its drain. The potential at the substrate of the second transistor T2 changes with a first parameter. The substrate of the second transistor serves as the output of the potential generation circuit. Since the potential at the substrate of the second transistor changes with the first parameter, the output can output a potential that varies with any of the following: supply voltage, operating temperature, and manufacturing process.

[0237] Figure 25 This is a schematic diagram of a potential generation circuit provided in an embodiment of this application, as shown below. Figure 25 As shown, in Figure 24Further, based on the potential generation circuit shown, a buffer 23 can be further included, the buffer 23 is connected to the output end and outputs a substrate potential, the value of the substrate potential is equal to the potential value of the substrate end of the second transistor T2. The input potential and the output potential of the buffer 23 are the same, the buffer 23 is used to enhance the driving capability of the potential of the substrate end of the second transistor T2, and the substrate end of the second transistor T2 can also be isolated to avoid the potential of the substrate end of the second transistor T2 being disturbed.

[0238] The structure of the potential generation circuit of the present application will be described below in combination with specific embodiments, and the specific structure of the potential generation circuit of the present application is not limited to any one of the following structures.

[0239] Figure 26 A structure diagram of a potential generation circuit provided by an embodiment of the present application is shown in the figure, Figure 26 The potential generation circuit of the present embodiment can include a first transistor T1, a second transistor T2, a constant current source 21, an error amplifier 22 and a buffer 23.

[0240] In the present embodiment, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The gate end of the first transistor T1 is connected to the drain end of the first transistor T1, the gate end of the second transistor T2 is connected to the drain end of the second transistor T2, the source end of the first transistor T1 is connected to the power supply end Vcc, the source end of the second transistor T2 is connected to the first end of the constant current source 21, and the drain end of the first transistor T1 is connected to the drain end of the second transistor T2. The second end of the constant current source 21 is connected to Vkb, and the potential of Vkb is less than 0.

[0241] The error amplifier 22 and the second transistor T2 form a first feedback loop, the negative input end of the error amplifier 22 is connected to the source end of the second transistor T2 and the first end of the constant current source 21, the positive input end of the error amplifier 22 is connected to the ground end, and the output end of the error amplifier 22 is connected to the substrate end of the second transistor T2.

[0242] The buffer 23 is connected to the substrate end of the second transistor T2 and outputs a substrate potential, and the value of the substrate potential is equal to the potential value of the substrate end of the second transistor T2.

[0243] In the present embodiment, the potential of the substrate end of the second transistor T2 changes with the first parameter, specifically, the potential of the substrate end of the second transistor T2 decreases as the first parameter increases, the potential of the substrate end of the second transistor T2 increases as the first parameter decreases, and the first parameter is any one of the power supply voltage, the working temperature and the manufacturing process of the potential generation circuit.

[0244] Taking the first parameter as the working temperature as an example, the principle that the potential at the substrate end of the second transistor T2 changes with the first parameter is described in detail below.

[0245] The current flowing through the second transistor T2 is Id = μ*Cox*(W / L)*(Vgs-Vth) 2 Wherein, μ is the electron mobility, Vth is the threshold voltage, for example, when the working temperature rises, the electron mobility μ decreases, which will cause the current Id flowing through the second transistor T2 to decrease, and the delay time of the corresponding inverter will become longer. At this time, if Vgs-Vth is adjusted to be larger, the current change caused by the decrease of the electron mobility μ can be compensated. The specific adjustment value can be set according to actual needs. Figure 26 In the potential generating circuit shown, if the temperature rises, the electron mobility μ decreases, and the current Id flowing through the second transistor T2 decreases. In order to keep the current of the constant current source unchanged, the substrate potential of the second transistor T2 needs to be reduced. At this time, the substrate potential decreases with the increase of the temperature.

[0246] When the first parameter is the supply voltage and the manufacturing process, the change of the supply voltage and the manufacturing process will cause the change of the current Id flowing through the second transistor T2, and then cause the change of the delay time. The compensation principle is similar to the above principle, which is not described here.

[0247] Figure 27 A structure diagram of a potential generating circuit provided by the embodiment of the present application is shown in the figure. Figure 27 As shown in the figure, the potential generating circuit of the embodiment can include a first transistor T1, a second transistor T2, a constant current source 21, an error amplifier 22, and a buffer 23.

[0248] In the embodiment, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The gate end of the first transistor T1 is connected to the drain end of the first transistor T1, the gate end of the second transistor T2 is connected to the drain end of the second transistor T2, the source end of the first transistor T1 is connected to the first end of the constant current source 21, the source end of the second transistor T2 is connected to the ground end, and the drain end of the first transistor T1 is connected to the drain end of the second transistor T2. The second end of the constant current source 21 is connected to Vdd.

[0249] The error amplifier 22 and the first transistor T1 form a first feedback loop, the negative input end of the error amplifier 22 is connected to the source end of the first transistor T1 and the first end of the constant current source 21, the positive input end of the error amplifier 22 is connected to the power supply end Vcc, and the output end of the error amplifier 22 is connected to the substrate end of the first transistor T1.

[0250] Wherein, Vdd is greater than Vcc.

[0251] The buffer 23 is connected to the substrate end of the first transistor T1 and outputs a substrate potential, and the value of the substrate potential is equal to the potential value of the substrate end of the first transistor T1.

[0252] In the embodiment, the potential of the substrate end of the first transistor T1 changes with the first parameter, specifically, the potential of the substrate end of the first transistor T1 increases with the increase of the first parameter, the potential of the substrate end of the first transistor T1 decreases with the decrease of the first parameter, and the first parameter is any one of the supply voltage, the working temperature and the manufacturing process of the potential generation circuit.

[0253] Taking the working temperature as the first parameter, the principle that the potential of the substrate end of the first transistor T1 changes with the first parameter is described in detail below.

[0254] The current Id flowing through the first transistor T1 is μ*Cox*(W / L)*(Vgs-Vth) 2 Wherein, μ is the electron mobility, Vth is the threshold voltage, for example, when the working temperature increases, the electron mobility μ decreases, which will cause the current Id flowing through the first transistor T1 to decrease, and the delay time of the corresponding inverter will become longer, at this time, if Vgs-Vth is adjusted to be larger, the current change caused by the decrease of the electron mobility μ can be compensated, and the specific adjustment value can be set according to the actual demand. Figure 26 In the potential generation circuit shown, if the temperature increases, the electron mobility μ decreases, and the current Id flowing through the first transistor T1 decreases, in order to keep the current of the constant current source unchanged, the substrate potential of the first transistor T1 needs to be reduced, at this time, the substrate potential decreases with the increase of the temperature.

[0255] When the first parameter is the supply voltage and the manufacturing process, the changes of the supply voltage and the manufacturing process will cause the current Id flowing through the second transistor T2 to change, and then cause the delay time to change, the compensation principle is similar to the above principle, which is not described here.

[0256] The embodiment of the application also provides a delay circuit, which comprises Figure 18 Or Figure 19 Or Figure 20 Figure 21 Or Figure 27 The potential generation circuit and the delay unit shown, the delay unit comprises a first inverter, the first inverter comprises a fourth transistor and a fifth transistor, the substrate end of the fourth transistor is connected to the potential of the substrate end of the first transistor, the substrate end of the fifth transistor is connected to the ground end, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0257] Optionally, a ratio of the channel length of the first transistor to the channel length of the fourth transistor is denoted as H, a ratio of the channel length of the second transistor to the channel length of the fifth transistor is denoted as L, a ratio of the channel width of the first transistor to the channel width of the fourth transistor is denoted as M, a ratio of the channel width of the second transistor to the channel width of the fifth transistor is denoted as N, H is equal to L, and M is equal to N. Optionally, H, L, M, and N can be 1. Optionally, the first transistor and the fourth transistor can be of the same type, and the second transistor and the fifth transistor can be of the same type.

[0258] The delay circuit provided in the embodiment can adjust the current flowing through the P-type transistor in the inverter, compensate the change value of the current flowing through the P-type transistor in the inverter, so that the change of the rising edge delay time T of the delay circuit is small, and the control ability of the delay circuit on the rising edge delay time precision is improved.

[0259] The delay circuit provided in the embodiment can be applied to a scene in which the rising edge delay time of the delay circuit needs to be accurately controlled, for example, can be applied to DRAM, and can compensate the influence of the change of any one of the power supply voltage, the working temperature, and the manufacturing process on the rising edge delay time, so that the change of the rising edge delay time T is small, and the control ability of the delay circuit on the rising edge delay time precision is improved.

[0260] The embodiment of the present application further provides a delay circuit, comprising Figures 22-26 Any one of the potential generating circuits and the delay unit, the delay unit comprising a first inverter, the first inverter comprising a fourth transistor and a fifth transistor, a substrate end of the fourth transistor being connected to the potential of the substrate end of the first transistor, a substrate end of the fifth transistor being connected to a power supply end, the fourth transistor being a P-type transistor, and the fifth transistor being an N-type transistor.

[0261] Optionally, a ratio of the channel length of the first transistor to the channel length of the fourth transistor is denoted as H, a ratio of the channel length of the second transistor to the channel length of the fifth transistor is denoted as L, a ratio of the channel width of the first transistor to the channel width of the fourth transistor is denoted as M, a ratio of the channel width of the second transistor to the channel width of the fifth transistor is denoted as N, H is equal to L, and M is equal to N. Optionally, H, L, M, and N can be 1. Optionally, the first transistor and the fourth transistor can be of the same type, and the second transistor and the fifth transistor can be of the same type.

[0262] The delay circuit provided in the embodiment can be applied to a scene in which the falling edge delay time of the delay circuit needs to be accurately controlled, for example, can be applied to DRAM, and can compensate the influence of any one of the power supply voltage, the working temperature and the manufacturing process on the falling edge delay time, so that the change of the falling edge delay time T is small, and the control ability of the delay circuit on the falling edge delay time precision is improved.

[0263] The delay circuit provided in the embodiment can be applied to a scene in which the falling edge delay time of the delay circuit needs to be accurately controlled, for example, can be applied to DRAM, and can compensate the influence of any one of the power supply voltage, the working temperature and the manufacturing process on the falling edge delay time, so that the change of the falling edge delay time T is small, and the control ability of the delay circuit on the falling edge delay time precision is improved.

[0264] The delay circuit provided in the embodiment can be applied to a scene in which the falling edge delay time of the delay circuit needs to be accurately controlled, for example, can be applied to DRAM, and can compensate the influence of any one of the power supply voltage, the working temperature and the manufacturing process on the falling edge delay time, so that the change of the falling edge delay time T is small, and the control ability of the delay circuit on the falling edge delay time precision is improved.

[0265] The first potential generating circuit is a potential generating circuit as shown in any one of Figure 18 or Figure 19 or 20 or Figure 21 or Figure 27 .

[0266] The second potential generating circuit is a potential generating circuit as shown in any one of Figures 22-26 .

[0267] The delay unit comprises a first inverter, and the first inverter comprises a fourth transistor and a fifth transistor. The substrate end of the fourth transistor is connected to the potential of the substrate end of the first transistor in the first potential generating circuit, and the substrate end of the fifth transistor is connected to the potential of the substrate end of the second transistor in the second potential generating circuit. The fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0268] Optionally, the ratio of the channel length of the first transistor in the first potential generating circuit to the channel length of the fourth transistor is H1, the ratio of the channel length of the second transistor in the first potential generating circuit to the channel length of the fifth transistor is L1, the ratio of the channel width of the first transistor in the first potential generating circuit to the channel width of the fourth transistor is M1, and the ratio of the channel width of the second transistor in the first potential generating circuit to the channel width of the fifth transistor is N1. H1 is equal to L1, and M1 is equal to N1. Optionally, H1, L1, M1 and N1 can be 1.

[0269] A ratio of a channel length of the first transistor in the second potential generation circuit to a channel length of the fourth transistor is H2, a ratio of a channel length of the second transistor in the second potential generation circuit to a channel length of the fifth transistor is L2, a ratio of a channel width of the first transistor in the second potential generation circuit to a channel width of the fourth transistor is M2, and a ratio of a channel width of the second transistor in the second potential generation circuit to a channel width of the fifth transistor is N2. H2 is equal to L2, and M2 is equal to N2. Alternatively, H2, L2, M2, and N2 can be 1.

[0270] The delay circuit provided by the embodiment can be applied to a scene in which the rising edge delay time and the falling edge delay time of the delay circuit need to be accurately controlled, for example, can be applied to a DRAM, and can simultaneously compensate for the influence of changes in any one of a power supply voltage, a working temperature, and a manufacturing process on the rising edge delay time and the falling edge delay time, so that the rising edge delay time T and the falling edge delay time T change less, and the control ability of the delay circuit on the rising edge delay time and the falling edge delay time precision is improved.

[0271] It should be noted that the delay circuit provided in this application embodiment can be configured to set the connection relationship between the potential generation circuit and the inverter in the delay unit as shown in the above two embodiments, according to the rising edge delay and / or falling edge delay implemented by the delay unit. For example, if a certain delay circuit implements a rising edge delay and includes an inverter, which includes a P-type transistor and an N-type transistor, then a first potential generation circuit is provided in the delay circuit. The first potential generation circuit can provide a substrate potential that varies with the first parameter to the substrate terminal of the P-type transistor in the inverter, thereby adjusting the current flowing through the P-type transistor in the inverter and compensating for the change in the current flowing through the P-type transistor in the inverter, so that the change in the rising edge delay time T of the delay circuit is small. For example, a delay circuit implements a falling edge delay. This delay circuit includes an inverter, which includes a P-type transistor and an N-type transistor. In this delay circuit, a second potential generation circuit is set. The second potential generation circuit can provide a substrate potential that varies with the first parameter to the substrate terminal of the N-type transistor in the inverter. This allows adjustment of the current flowing through the N-type transistor in the inverter, compensating for the change in the current flowing through the N-type transistor in the inverter, so that the change in the falling edge delay time T of the delay circuit is small. For example, a delay circuit that delays both the rising and falling edges includes an inverter comprising a P-type transistor and an N-type transistor. This delay circuit incorporates a first potential generation circuit and a second potential generation circuit. The first potential generation circuit provides a substrate potential to the substrate of the P-type transistor in the inverter that varies with a first parameter, thereby adjusting the current flowing through the P-type transistor and compensating for changes in the current flowing through it. This minimizes the variation in the rising edge delay time T. Similarly, the second potential generation circuit provides a substrate potential to the substrate of the N-type transistor in the inverter that varies with the first parameter, thereby adjusting the current flowing through the N-type transistor and compensating for changes in the current flowing through it. This minimizes the variation in the falling edge delay time T. Thus, the variations in both the rising and falling edge delay times are minimized, improving the delay circuit's control over the accuracy of delay times (including both rising and falling edge delay times).

[0272] The following is combined Figures 28-30 Three examples of delay circuits are given. Figure 28 This is a schematic diagram of a delay circuit provided in an embodiment of this application, as shown below. Figure 28 As shown, the delay circuit in this embodiment includes a potential generation circuit 1 and a delay unit 2. The potential generation circuit 1 is... Figure 26 For a detailed structural description of the circuit shown, please refer to [link / reference needed]. Figure 26In the embodiment shown, the potential generating circuit 1 outputs a substrate potential BN, the delay unit 2 includes an inverter and a capacitor C1, the inverter includes a P-type transistor TP1 and an N-type transistor TN1, the substrate end of the P-type transistor TP1 is connected to a power supply end Vcc, and the substrate end of the N-type transistor TN1 is connected to the substrate potential BN. In the delay circuit of the embodiment, the potential generating circuit 1 provides the substrate end of the N-type transistor in the delay unit 2 with a substrate potential that changes with the first parameter, the change value of the falling edge delay time of the delay circuit is adjusted, the change of the falling edge delay time of the delay circuit is small, the influence of the manufacturing process, the power supply voltage and the working temperature of the delay circuit on the falling edge delay time T of the delay circuit is reduced, the change of the falling edge delay time T is small, and the control ability of the delay circuit on the falling edge delay time precision is improved.

[0273] Figure 29 A structural schematic diagram of a delay circuit provided by the embodiment of the application is shown in FIG. 1. The delay circuit of the embodiment includes a potential generating circuit 1 and a delay unit 2. Figure 29 The potential generating circuit 1 is a circuit shown in FIG. 2, and the specific structural description can be referred to the description in the embodiment shown in FIG. 2. Figure 27 In the embodiment shown, the potential generating circuit 1 outputs a substrate potential BN. The second potential generating circuit 3 is a circuit shown in FIG. 3, and the specific structural description can be referred to the description in the embodiment shown in FIG. 3. Figure 27 In the embodiment shown, the potential generating circuit 1 outputs a substrate potential BN. The second potential generating circuit 3 is a circuit shown in FIG. 3, and the specific structural description can be referred to the description in the embodiment shown in FIG. 3.

[0274] Figure 30 A structural schematic diagram of a delay circuit provided by the embodiment of the application is shown in FIG. 1. The delay circuit of the embodiment includes a potential generating circuit 1 and a delay unit 2. Figure 30 The potential generating circuit 1 is a circuit shown in FIG. 2, and the specific structural description can be referred to the description in the embodiment shown in FIG. 2. Figure 27 In the embodiment shown, the potential generating circuit 1 outputs a substrate potential BN. The second potential generating circuit 3 is a circuit shown in FIG. 3, and the specific structural description can be referred to the description in the embodiment shown in FIG. 3. Figure 27 In the embodiment shown, the potential generating circuit 1 outputs a substrate potential BN. The second potential generating circuit 3 is a circuit shown in FIG. 3, and the specific structural description can be referred to the description in the embodiment shown in FIG. 3. Figure 28 In the embodiment shown, the potential generating circuit 1 outputs a substrate potential BN. The second potential generating circuit 3 is a circuit shown in FIG. 3, and the specific structural description can be referred to the description in the embodiment shown in FIG. 3. Figure 28The second potential generating circuit 3 outputs the substrate potential BP in the embodiment shown. The delay unit 2 includes an inverter and a capacitor C1, and the inverter includes a P-type transistor TP1 and an N-type transistor TN1. The substrate end of the P-type transistor TP1 is connected to the substrate potential BP output by the second potential generating circuit 3, and the substrate end of the N-type transistor TN1 is connected to the substrate potential BN output by the first potential generating circuit 1. In the delay circuit of the embodiment, the first potential generating circuit 1 provides the substrate end of the N-type transistor in the delay unit 2 with a substrate potential that changes with the first parameter, so as to adjust the change value of the rising delay time of the delay circuit, and make the change of the rising delay time of the delay circuit smaller. The third potential generating circuit 3 provides the substrate end of the P-type transistor in the delay unit 2 with a substrate potential that changes with the first parameter, so as to adjust the change value of the falling delay time of the delay circuit, and make the change of the falling delay time of the delay circuit smaller. Therefore, the influence of the manufacturing process, the supply voltage and the working temperature of the delay circuit on the delay time T (including the rising delay time and the falling delay time) of the delay circuit can be reduced, the change of the delay time T is smaller, and the control ability of the delay circuit on the delay time precision is improved.

[0275] The application further provides a kind of inverter, Figure 31 The application provides a kind of inverter structure diagram, as Figure 31 The application provides a kind of inverter structure diagram, as

[0276] The application provides a kind of inverter structure diagram, as

[0277] The application provides a kind of inverter structure diagram, as

[0278] The application provides a kind of inverter structure diagram, as

[0279] The inverter provided by the embodiment can provide the substrate potential of the P-type transistor TP2 with the change of the first parameter, thereby adjusting the current of the P-type transistor TP2 of the inverter, compensating the change value of the current of the P-type transistor TP2, and reducing the change of the rising edge delay time T of the inverter, thereby improving the control ability of the inverter on the rising edge delay time precision.

[0280] Figure 32 As shown in a structural schematic diagram of the inverter provided by the embodiment of the present application, Figure 32 the inverter comprises a P-type transistor TP2 and an N-type transistor TN2, the source end of the P-type transistor TP2 is connected to a power supply end, the drain end of the P-type transistor TP2 is connected to the drain end of the N-type transistor TN2, the source end of the N-type transistor TN2 is connected to a ground end, the gate end of the P-type transistor TP2 is connected to the gate end of the N-type transistor TN2 and serves as an input end of the inverter, and the drain end of the P-type transistor TP2 serves as an output end of the inverter.

[0281] The substrate end of the N-type transistor TN2 is connected to a substrate potential, the substrate end of the P-type transistor TP2 is connected to the power supply end, and the substrate potential changes with the first parameter, the first parameter being any one of the power supply voltage, the working temperature and the manufacturing process of the inverter.

[0282] If the first parameter is the power supply voltage or the working temperature of the inverter, the substrate potential decreases with the increase of the first parameter and increases with the decrease of the first parameter.

[0283] The inverter provided by the embodiment can provide the substrate potential of the P-type transistor TP2 with the change of the first parameter, thereby adjusting the current of the P-type transistor TP2 of the inverter, compensating the change value of the current of the P-type transistor TP2, and reducing the change of the rising edge delay time T of the inverter, thereby improving the control ability of the inverter on the rising edge delay time precision.

[0284] The embodiment of the present application further provides a delay circuit, Figure 33 As shown in a structural schematic diagram of the delay circuit provided by the embodiment of the present application, Figure 33 the delay circuit of the embodiment can comprise Figure 31 the inverter and a capacitor C1, one end of the capacitor C1 being connected to the ground end. In an implementable manner, the capacitor C1 can be a capacitor array.

[0285] The delay circuit provided by the embodiment can compensate the change value of the current flowing through the P-type transistor TP2 of the inverter, so that the change of the rising edge delay time T of the inverter is small, and the change of the rising edge delay time T of the delay circuit is small, and the control ability of the delay circuit on the rising edge delay time precision is improved.

[0286] The embodiment of the application further provides a delay circuit, Figure 34 The structure diagram of the delay circuit provided by the embodiment of the application is shown in the figure, Figure 34 The delay circuit of the embodiment can include Figure 32 The inverter and the capacitor C1 shown in the figure, one end of the capacitor C1 is connected to the ground. In an implementable manner, the capacitor C1 can be a capacitor array.

[0287] The delay circuit provided by the embodiment can compensate the change value of the current flowing through the N-type transistor TN2 of the inverter, so that the change of the falling edge delay time T of the inverter is small, and the change of the falling edge delay time T of the delay circuit is small, and the control ability of the delay circuit on the falling edge delay time precision is improved.

[0288] The embodiment of the application further provides a logic gate circuit, comprising: a P-type transistor and an N-type transistor, a substrate end of the P-type transistor is connected to a substrate potential, a substrate end of the N-type transistor is connected to a ground, the substrate potential changes with a first parameter, so that the delay time of the logic gate circuit from an input end to an output end changes within a first range with the change of the first parameter, and the first parameter includes any one of a supply voltage, a working temperature and a manufacturing process of the logic gate circuit.

[0289] Specifically, the first range is a small range, for example, a range close to 0, for example, the first range is 1%, or 3%, or 5%, so that the rising edge delay time of the logic gate circuit from the input end to the output end changes less when any one of the supply voltage, the working temperature and the manufacturing process changes, and the control ability of the logic gate circuit on the rising edge delay time precision is improved.

[0290] The embodiment of the application further provides a logic gate circuit, comprising: a P-type transistor and an N-type transistor, a substrate end of the N-type transistor is connected to a substrate potential, a substrate end of the P-type transistor is connected to a power supply, the substrate potential changes with a first parameter, so that the delay time of the logic gate circuit from an input end to an output end changes within a first range with the change of the first parameter, and the first parameter includes any one of a supply voltage, a working temperature and a manufacturing process of the logic gate circuit.

[0291] Specifically, the first range is a small range, such as a range close to 0. For example, if the first range is 1%, 3%, or 5%, it can make the change in the falling edge delay time of the logic gate circuit from the input to the output terminal smaller when any of the power supply voltage, operating temperature, and manufacturing process changes, thereby improving the logic gate circuit's ability to control the accuracy of the falling edge delay time.

[0292] Example 3

[0293] Figure 35 This is a schematic diagram of a control circuit provided in an embodiment of this application, such as... Figure 35 As shown, the control circuit of this embodiment may include: a control unit 41, a first feedback unit 42, and a second feedback unit 43. The first feedback unit 42 is used to output a first feedback signal according to the voltage of the control unit 41 and a first reference voltage. The first end of the first feedback unit 42 is connected to the first end of the control unit, the second end of the first feedback unit 42 is the input end of the first reference voltage, and the output end of the first feedback unit 42 is connected to the second end of the control unit 41 and the first end of the second feedback unit 43.

[0294] The second feedback unit 43 is used to output a second feedback signal based on the voltage output by the first feedback unit 42 and the second reference voltage. The second terminal of the second feedback unit 43 is the input terminal of the second reference voltage, and the output terminal of the second feedback unit 43 is connected to the third terminal of the control unit 41.

[0295] The control unit 41 is used to adjust the voltage at its second terminal according to a first feedback signal, and to adjust the voltage at its third terminal according to a second feedback signal, so that the change in the current of the control unit 41 with respect to a first parameter is within a first range. The first parameter includes at least one of the manufacturing process of the control circuit, the supply voltage, and the operating temperature. The fourth terminal of the control unit 41 is connected to a first power supply terminal, and the fifth terminal of the control unit 41 is connected to a negative power supply terminal. Specifically, the first range is a small range, for example, a range close to 0, such as 1%, 3%, or 5%, thereby making the change in the current of the control unit 41 with respect to the first parameter relatively small.

[0296] Figure 36 This is a schematic diagram of a control circuit provided in an embodiment of this application, such as... Figure 36 As shown, this embodiment is similar to Figure 35 The difference in the illustrated embodiment is that the fourth terminal of the control unit 41 is connected to the second power supply terminal, and the fifth terminal of the control unit 41 is connected to the ground terminal Vgg.

[0297] Figure 35 and Figure 36The control circuit shown, by setting the control unit, the first feedback unit and the second feedback unit, the first end of the first feedback unit is connected with the first end of the control unit, the second end of the first feedback unit is the input end of the first reference voltage, the output end of the first feedback unit is connected with the second end of the control unit and the first end of the second feedback unit, the second end of the second feedback unit is the input end of the second reference voltage, and the output end of the second feedback unit is connected with the third end of the control unit. The first feedback unit is used for outputting a first feedback signal according to the voltage of the control unit and the first reference voltage, the second feedback unit is used for outputting a second feedback signal according to the voltage output by the first feedback unit and the second reference voltage, and the control unit is used for adjusting the voltage of the second end of the control unit according to the first feedback signal and adjusting the voltage of the third end of the control unit according to the second feedback signal, so that the current of the control unit changes within a first range with the change value of the first parameter, the first parameter being any one of the supply voltage, the working temperature and the manufacturing process. Therefore, the second end of the control unit and the third end of the control unit can respectively output the voltage changing with any one of the supply voltage, the working temperature and the manufacturing process.

[0298] Figure 37 A structural schematic diagram of a control circuit provided by the embodiment of the application is shown in the figure, Figure 37 The control circuit of the embodiment is based on the circuit shown in the figure, Figure 35 The control unit 41 can further include an inverter 411 and a constant current source 412, wherein the first end of the inverter 411 is connected with the first power supply end;

[0299] The first end of the constant current source 412 is connected with the second end of the inverter 411, and the second end of the constant current source 412 is connected with the negative power supply end.

[0300] The input end of the inverter 411 is short-circuited with the output end of the inverter 411.

[0301] Figure 38 A structural schematic diagram of a control circuit provided by the embodiment of the application is shown in the figure, Figure 38 The control circuit of the embodiment is based on the circuit shown in the figure, Figure 37 The inverter 411 further includes a first transistor T1 and a second transistor T2, the substrate end of the first transistor T1 is connected with the output end of the second feedback unit 43, and the substrate end of the second transistor T2 is connected with the output end of the first feedback unit 42;

[0302] The first end of the first transistor T1 is connected with the first power supply end, the second end of the first transistor T1 is connected with the first end of the second transistor T2, the control end of the first transistor T1 and the control end of the second transistor T2 are connected, and the second end of the second transistor T2 is connected with the first end of the constant current source 412.

[0303] In the embodiment, the control unit 41 is configured to adjust the voltage at the substrate end of the second transistor T2 according to the first feedback signal, and adjust the voltage at the substrate end of the first transistor T1 according to the second feedback signal.

[0304] The control circuit provided by the embodiment is configured to adjust the voltage at the substrate end of the second transistor according to the first feedback signal, and adjust the voltage at the substrate end of the first transistor according to the second feedback signal, so that the current of the control unit changes within a first range when the first parameter changes, the first parameter being any one of the supply voltage, the working temperature and the manufacturing process, thereby the substrate end of the first transistor and the substrate end of the second transistor can output voltages changing with any one of the supply voltage, the working temperature and the manufacturing process.

[0305] Figure 39 A structural schematic diagram of the control circuit provided by the embodiment is shown in FIG. 4, and the control circuit of the embodiment is based on the circuit shown in FIG. 3. Figure 39 As shown in FIG. 4, the control unit 41 of the embodiment can further include an inverter 411 and a constant current source 412. Figure 36

[0306] The first end of the constant current source 412 is connected with the second end of the inverter 411, and the second end of the constant current source 412 is connected with the second power supply end.

[0307] The input end of the inverter 411 is short-circuited with the output end of the inverter 411.

[0308] Figure 40 A structural schematic diagram of the control circuit provided by the embodiment is shown in FIG. 4, and the control circuit of the embodiment is based on the circuit shown in FIG. 3. Figure 40 As shown in FIG. 4, the control unit 41 of the embodiment can further include an inverter 411 and a constant current source 412. Figure 39 The first end of the first transistor T1 is connected with the first end of the constant current source, the second end of the first transistor T1 is connected with the first end of the second transistor T2, the control end of the first transistor T1 and the control end of the second transistor T2 are connected, and the second end of the second transistor T2 is connected with the ground end.

[0309] In the embodiment, the control unit 41 is configured to adjust the voltage at the substrate end of the second transistor T2 according to the first feedback signal, and adjust the voltage at the substrate end of the first transistor T1 according to the second feedback signal.

[0310]

[0311] ​​The control circuit provided by the embodiment controls the control unit to adjust the voltage at the substrate end of the second transistor according to the first feedback signal and adjust the voltage at the substrate end of the first transistor according to the second feedback signal, so that the current of the control unit changes within a first range when the first parameter changes, the first parameter being any one of the supply voltage, the working temperature and the manufacturing process, thereby the substrate end of the first transistor and the substrate end of the second transistor can respectively output the voltage changing with any one of the supply voltage, the working temperature and the manufacturing process.

[0312] In Figure 38 and Figure 40 the control circuit, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0313] The specific implementable structure of the first feedback unit and the second feedback unit will be described in detail below with reference to the accompanying drawings.

[0314] Figure 41 The structural schematic diagram of the control circuit provided by the embodiment is shown in Figure 41 the control circuit of the embodiment is based on the circuit shown in Figure 38 further, the first feedback unit 42 comprises a first error amplifier 421, the negative input end of the first error amplifier 421 is connected with the first end of the control unit 41, the positive input end of the first error amplifier 421 is the input end of the first reference voltage, and the output end of the first error amplifier 421 is connected with the second end of the control unit 41 and the first end of the second feedback unit 43.

[0315] As shown in Figure 41 further, the second feedback unit 43 comprises a second error amplifier 431, a first resistor R1, a second resistor R2 and a third transistor T3, wherein the negative input end of the second error amplifier 431 is the input end of the second reference voltage, the positive input end of the second error amplifier 431 is connected with the first end of the first resistor R1 and the first end of the second resistor R2, and the output end of the second error amplifier 431 is connected with the control end of the third transistor T3.

[0316] the second end of the first resistor R1 is connected with the first end of the third transistor T3 and the third end of the control unit 41;

[0317] the second end of the second resistor R2 is connected with the output end of the first feedback unit and the second end of the control unit 41;

[0318] the second end of the third transistor is connected with the first power supply end.

[0319] Figure 42 The structural schematic diagram of the control circuit provided by the embodiment is shown in Figure 42 the control circuit of the embodiment is based on the circuit shown inFigure 40 Further, the first feedback unit 42 comprises a first error amplifier 421, a negative input terminal of the first error amplifier 421 is connected with the first terminal of the control unit 41, a positive input terminal of the first error amplifier 421 is the input terminal of the first reference voltage, and an output terminal of the first error amplifier 421 is connected with the second terminal of the control unit 41 and the first terminal of the second feedback unit 43.

[0320] As shown in Figure 42 Further, the second feedback unit 43 comprises a second error amplifier 431, a first resistor R1, a second resistor R2 and a third transistor T3, wherein a negative input terminal of the second error amplifier 431 is the input terminal of the second reference voltage, a positive input terminal of the second error amplifier 431 is connected with the first terminal of the first resistor R1 and the first terminal of the second resistor R2, and an output terminal of the second error amplifier 431 is connected with a control terminal of the third transistor T3.

[0321] A second terminal of the first resistor R1 is connected with the output terminal of the first feedback unit and the second terminal of the control unit 41.

[0322] A second terminal of the second resistor R2 is connected with the first terminal of the third transistor T3 and the third terminal of the control unit 41.

[0323] A second terminal of the third transistor is connected with a ground terminal.

[0324] In Figure 41 or Figure 42 Further, the control circuit can further comprise a first buffer and a second buffer. Figure 43 A structure schematic diagram of a control circuit provided by the embodiment of the present application, Figure 44 A structure schematic diagram of a control circuit provided by the embodiment of the present application, as shown in Figure 43 and Figure 44 As shown in Figure 41 or Figure 42 Further, the control circuit can further comprise a first buffer 44 and a second buffer 45, wherein the first buffer 44 is connected with the substrate terminal of the first transistor T1 and outputs a first substrate voltage, the value of the first substrate voltage is equal to the voltage value of the substrate terminal of the first transistor T1, the input voltage and the output voltage of the first buffer 44 are the same, the first buffer 44 is used to enhance the driving capability of the potential of the substrate terminal of the first transistor T1, and can also isolate the substrate terminal of the first transistor T1 to avoid the potential of the substrate terminal of the first transistor T1 from being disturbed.

[0325] The second buffer 45 is connected to the substrate end of the second transistor T2 and outputs a second substrate voltage, the value of the second substrate voltage is equal to the voltage value of the substrate end of the first transistor T1, the second buffer 45 is used to enhance the driving capability of the potential of the substrate end of the second transistor T2, and the substrate end of the second transistor T2 can be isolated to avoid the potential of the substrate end of the second transistor T2 being disturbed.

[0326] It should be noted that, in the control circuit shown in Figures 35-44 The voltage of the first power supply end is, for example, Vcc, the second reference voltage can be Vcc / 2, the voltage of the negative power supply end can be a voltage value less than 0, and the first reference voltage can be 0.

[0327] The voltage of the second power supply end is greater than the voltage of the first reference voltage, and the value of the second reference voltage can be half of the first reference voltage, for example, the voltage of the second power supply end is Vdd, the first reference voltage is Vcc, Vdd is greater than Vcc, and the value of the second reference voltage can be Vcc / 2.

[0328] The structure of the control circuit of the present application will be described below in conjunction with specific embodiments, and the specific structure of the control circuit of the present application is not limited to any one of the following structures.

[0329] Specifically, the specific structure of the control circuit of the present embodiment can be seen from Figure 11 and Figure 12 the circuit structure shown in Figure 11 and Figure 12 the potential generating circuit shown in Figure 11 and Figure 12 the description of the embodiments shown in

[0330] The application embodiment also provides a delay circuit, which comprises Figures 35-44 Any one of the control circuit and the delay unit shown, wherein the second end of the control unit in the control circuit is connected to the first end of the delay unit, the third end of the control unit is connected to the second end of the delay unit, and the control circuit is used to control the change value of the rising edge delay time and / or the falling edge delay time of the delay unit to change with the first parameter in the first range.

[0331] Optionally, the delay unit comprises an inverter, the inverter comprises a fourth transistor and a fifth transistor, the third end of the control unit is connected to the substrate end of the fourth transistor, and the second end of the control unit is connected to the substrate end of the fifth transistor.

[0332] Optionally, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0333] In the present embodiment, optionally, the control circuit in the delay circuit isFigure 38 or Figures 41-44 or Figures 13-15 When any of the control circuits is used, the ratio of the channel length of the first transistor to the channel length of the fourth transistor is H, the ratio of the channel length of the second transistor to the channel length of the fifth transistor is L, the ratio of the channel width of the first transistor to the channel width of the fourth transistor is M, and the ratio of the channel width of the second transistor to the channel width of the fifth transistor is N. H is equal to L, and M is equal to N.

[0334] The delay circuit provided in the embodiment can output a voltage that changes with the first parameter (any of the supply voltage, the working temperature, and the manufacturing process) at the second end of the control unit and the third end of the control unit. Thus, the first substrate voltage that changes with the first parameter can be provided at the substrate end of the fourth transistor, and the second substrate voltage that changes with the first parameter can be provided at the substrate end of the fifth transistor. Therefore, the change value of the current flowing through the two transistors of the inverter with the first parameter can be adjusted within a first range, the change value of the current flowing through the two transistors of the inverter is compensated, and the change of the delay time T of the delay circuit is small, and the control ability of the delay circuit on the delay time precision is improved.

[0335] It should be noted that the connection relationship between the control circuit and the inverter can be set according to the number of inverter included in the delay circuit and the requirement of delay time compensation in the embodiment of the present application. The substrate end of the P-type transistor in the inverter is connected to the substrate end of the P-type transistor in the control circuit, and the change value of the rising delay time of the delay circuit can be adjusted. The substrate end of the N-type transistor in the inverter is connected to the substrate end of the N-type transistor in the control circuit, and the change value of the falling delay time of the delay circuit can be adjusted. Specifically, the connection relationship between the control circuit and the inverter can be set according to the change value of the rising delay time and / or the falling delay time to be adjusted. The control circuit provided in the embodiment of the present application can be applied to the delay circuit in which the rising delay and / or the falling delay are delayed. The influence of the manufacturing process, the supply voltage, and the working temperature of the delay circuit on the delay time T of the delay circuit can be reduced, the change of the delay time T (including the rising delay and / or the falling delay) is small, and the control ability of the delay circuit on the delay time precision is improved.

[0336] Figures 13-15 The examples of the two delay circuits are also applicable to the embodiment, Figures 13-15 The potential generating circuit shown in the embodiment is the specific control circuit in the embodiment, and specific description can be made with reference to Figure 45 the embodiment, which will not be described herein.

[0337] Embodiment Four

[0338] Figure 45 A structure schematic diagram of a control circuit provided in the embodiment of the present application is shown in FIG. 4.Figure 46 As shown in the control circuit of the embodiment, the control circuit can comprise a control unit 51 and a feedback unit 52, wherein,

[0339] The feedback unit 52 is configured to output a feedback signal according to a voltage of the control unit 51 and a reference voltage, a first end of the feedback unit 52 is connected to a first end of the control unit 51, a second end of the feedback unit 52 is an input end of the reference voltage, and an output end of the feedback unit 52 is connected to a second end of the control unit 51.

[0340] The control unit 51 is configured to adjust the voltage at the second end of the control unit 51 according to the feedback signal, so that the variation of the current of the control unit 51 with respect to the variation of the first parameter is within a first range, the first parameter comprises at least one of a manufacturing process of the control circuit, a supply voltage and an operating temperature, a third end of the control unit 51 is connected to a first power supply end, and a fourth end of the control unit 51 is connected to a negative power supply end.

[0341] Specifically, the first range is a small range, for example, a range close to 0, such as 1% or 3% or 5%, so that the variation of the current of the control unit 41 with respect to the variation of the first parameter is small.

[0342] Figure 46 As shown in the control circuit of the embodiment, the control circuit can comprise a control unit 51 and a feedback unit 52, wherein, Figure 45 The difference between the embodiment and the embodiment shown in Figure 45 lies in that a third end of the control unit 51 is connected to a second power supply end, and a fourth end of the control unit 51 is connected to a ground end Vgg.

[0343] Figure 46 and Figure 47 As shown in the control circuit, by setting the control unit and the feedback unit, the feedback unit is configured to output a feedback signal according to a voltage of the control unit and a reference voltage, and the control unit is configured to adjust the voltage at the second end of the control unit according to the feedback signal, so that the variation of the current of the control unit with respect to the variation of the first parameter is within a first range, the first parameter is any one of the supply voltage, the operating temperature and the manufacturing process, so that the second end of the control unit can output a voltage that varies with any one of the supply voltage, the operating temperature and the manufacturing process.

[0344] Figure 47 As shown in the control circuit of the embodiment, the control circuit of the embodiment can comprise a control unit 51 and a feedback unit 52, wherein, Figure 45 As shown in the control circuit of the embodiment, the control circuit of the embodiment can comprise a control unit 51 and a feedback unit 52, wherein, Figure 48 Further, the control unit 51 can comprise an inverter 511 and a constant current source 512, a first end of the inverter 511 is connected to the first power supply end, a first end of the constant current source 512 is connected to a second end of the inverter 511, a second end of the constant current source 512 is connected to the negative power supply end, and an input end of the inverter 511 is shorted to an output end of the inverter 511.

[0345] Figure 48 This is a schematic diagram of a control circuit provided in an embodiment of this application, such as... Figure 47 As shown, the control circuit of this embodiment is in Figure 49 Based on the circuit shown, the inverter 411 further includes a first transistor T1 and a second transistor T2. The substrate of the first transistor T1 is connected to the first power supply terminal, and the substrate of the second transistor T2 is connected to the output terminal of the feedback unit 52.

[0346] The first terminal of the first transistor T1 is connected to the first power supply terminal, the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2, the control terminal of the first transistor T1 and the control terminal of the second transistor T2 are connected, and the second terminal of the second transistor T2 is connected to the first terminal of the constant current source.

[0347] In this embodiment, the control unit 41 is used to adjust the voltage at the substrate end of the second transistor T2 according to the feedback signal.

[0348] The control circuit provided in this embodiment is used to adjust the voltage at the substrate of the second transistor according to the feedback signal, so that the change value of the current of the control unit with the change of the first parameter is within a first range. The first parameter is any one of the power supply voltage, operating temperature and manufacturing process. Thus, the substrate of the second transistor can output a voltage that changes with any one of the power supply voltage, operating temperature and manufacturing process.

[0349] Figure 49 This is a schematic diagram of a control circuit provided in an embodiment of this application, such as... Figure 46 As shown, the control circuit of this embodiment is in Figure 50 Based on the circuit shown, the control unit 51 may further include an inverter 511 and a constant current source 512, wherein the first end of the inverter 511 is connected to the ground terminal, the first end of the constant current source 512 is connected to the second end of the inverter 511, the second end of the constant current source 512 is connected to the second power supply terminal, and the input terminal of the inverter 511 is short-circuited to the output terminal of the inverter 511.

[0350] Figure 50 This is a schematic diagram of a control circuit provided in an embodiment of this application, such as... Figure 49 As shown, the control circuit of this embodiment is in Figure 48 Based on the circuit shown, the inverter 511 further includes a first transistor T1 and a second transistor T2. The substrate end of the first transistor T1 is connected to the output end of the feedback unit, and the substrate end of the second transistor is connected to the ground end.

[0351] The first end of the first transistor T1 is connected to the first end of the constant current source, the second end of the first transistor T1 is connected to the first end of the second transistor T2, the control end of the first transistor T1 and the control end of the second transistor T2 are connected, and the second end of the second transistor T2 is connected to the ground end.

[0352] In the embodiment, the control unit 51 is configured to adjust the voltage at the substrate end of the first transistor T1 according to the feedback signal.

[0353] The control circuit provided by the embodiment is configured to adjust the voltage at the substrate end of the first transistor according to the feedback signal, so that the variation of the current of the control unit with the variation of the first parameter is within the first range, the first parameter being any one of the power supply voltage, the working temperature and the manufacturing process, thereby the substrate end of the first transistor can output the voltage varying with any one of the power supply voltage, the working temperature and the manufacturing process.

[0354] In Figure 50 and Figure 51 The first transistor is a P-type transistor and the second transistor is an N-type transistor in the control circuit shown in the figure.

[0355] The specific implementable structure of the feedback unit will be described in detail below with reference to the accompanying drawings.

[0356] Figure 51 A structural schematic diagram of the control circuit provided by the embodiment of the application is shown in the figure. Figure 48 The control circuit of the embodiment is based on the circuit shown in the figure. Figure 52 The feedback unit 52 further includes an error amplifier 521, the negative input end of the error amplifier 521 is connected to the first end of the constant current source 512 and the second end of the second transistor T2, the positive input end of the error amplifier 521 is a reference voltage input end, and the output end of the error amplifier 521 is connected to the substrate end of the second transistor T2.

[0357] Figure 52 A structural schematic diagram of the control circuit provided by the embodiment of the application is shown in the figure. Figure 51 The control circuit of the embodiment is based on the circuit shown in the figure. Figure 53 The control circuit of the embodiment can further include:

[0358] The buffer 53 is connected to the substrate end of the second transistor T2 and outputs a first substrate voltage, the value of the first substrate voltage being equal to the voltage value at the substrate end of the second transistor T2.

[0359] Figure 53 A structural schematic diagram of the control circuit provided by the embodiment of the application is shown in the figure. Figure 50 The control circuit of the embodiment is based on the circuit shown in the figure. Figure 54Further, the feedback unit 52 comprises an error amplifier 521, a negative input terminal of the error amplifier 521 is connected with the first terminal of the constant current source 512 and the first terminal of the first transistor T1, the negative input terminal of the error amplifier 521 is a reference voltage input terminal, and an output terminal of the error amplifier 521 is connected with the substrate terminal of the first transistor T1.

[0360] Figure 54 A structural schematic diagram of a control circuit provided by the embodiment of the application is shown in Figure 53 The control circuit of the embodiment can be based on the circuit shown in Figures 45-54 Further, the control circuit can further comprise a buffer 53, the buffer 53 is connected with the substrate terminal of the first transistor T1 and outputs a second substrate voltage, a value of the second substrate voltage is equal to a voltage value of the substrate terminal of the first transistor T1.

[0361] It should be noted that, in the control circuit shown in Figure 26 The voltage of the first power supply terminal is, for example, Vcc, the second reference voltage can be Vcc / 2, the voltage of the negative power supply terminal can be 0 or less than 0, and the first reference voltage can be 0.

[0362] The voltage of the second power supply terminal is greater than the voltage of the first reference voltage, and the value of the second reference voltage can be half of the first reference voltage, for example, the voltage of the second power supply terminal is Vdd, the first reference voltage is Vcc, Vdd is greater than Vcc, and the value of the second reference voltage can be Vcc / 2.

[0363] The structure of the control circuit of the application will be described below in combination with specific embodiments, and the specific structure of the control circuit of the application is not limited to any of the following structures.

[0364] Specifically, the specific structure of the control circuit of the embodiment can refer to the circuit structures shown in Figure 27 and Figure 26 The potential generating circuit shown in Figure 27 and Figure 26 is the control circuit in the embodiment, and the working principle is the same, and the details can refer to the descriptions of the embodiments shown in Figure 27 and Figures 45-54 Here, no further description is given.

[0365] The embodiment of the application further provides a delay circuit, which comprises Figure 48 any of the control circuits and the delay unit, wherein the second terminal of the control unit is connected with the first terminal of the delay unit, and the control circuit is used to control the change value of the rising edge delay time and / or the falling edge delay time of the delay unit to change with the first parameter within the first range.

[0366] Optionally, the delay unit comprises an inverter, the inverter comprises a fourth transistor and a fifth transistor, the second end of the control unit is connected to a substrate end of the fourth transistor or a substrate end of the fifth transistor.

[0367] Optionally, the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0368] When the fifth end of the control unit is connected to the negative power supply end, the second end of the control unit is connected to the substrate end of the fifth transistor.

[0369] When the third end of the control unit is connected to the second power supply end, and the fourth end of the control unit is connected to the ground end, the second end of the control unit is connected to the substrate end of the fourth transistor.

[0370] In the embodiment, optionally, the control circuit in the delay circuit is Figures 51-54 or Figures 28-30 or Figures 28-30 When the control circuit is any of the control circuits shown in the embodiments, the ratio of the channel length of the first transistor to the channel length of the fourth transistor is H, the ratio of the channel length of the second transistor to the channel length of the fifth transistor is L, the ratio of the channel width of the first transistor to the channel width of the fourth transistor is M, the ratio of the channel width of the second transistor to the channel width of the fifth transistor is N, H is equal to L, and M is equal to N.

[0371] The delay circuit provided by the embodiment can output a voltage that changes with a first parameter (any of a supply voltage, an operating temperature, and a manufacturing process) at the second end of the control unit. Thus, a first substrate voltage that changes with the first parameter can be provided at the substrate end of the fourth transistor, so that the change value of the current flowing through the fourth transistor of the inverter with the first parameter can be adjusted to be within a first range, the change value of the current flowing through the fourth transistor of the inverter is compensated, so that the change of the rising delay time T of the delay circuit is smaller, and the control ability of the delay circuit on the rising delay time precision is improved.

[0372] Or a first substrate voltage that changes with the first parameter can be provided at the substrate end of the fifth transistor, so that the change value of the current flowing through the fifth transistor of the inverter with the first parameter can be adjusted to be within a first range, the change value of the current flowing through the fifth transistor of the inverter is compensated, so that the change of the falling delay time T of the delay circuit is smaller, and the control ability of the delay circuit on the falling delay time precision is improved.

[0373] It should be noted that the delay circuit provided in the embodiments of the present application can set the connection relationship between the control circuit and the inverter in the delay unit shown in the above two embodiments according to the rising edge delay and / or falling edge delay realized by the delay unit. For example, a certain delay circuit realizes rising edge delay, the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor. In this case, the first control circuit is arranged in the delay circuit, the first control circuit can adjust the voltage at the substrate end of the P-type transistor in the inverter, thereby adjusting the current flowing through the P-type transistor in the inverter, so that the change value of the current flowing through the P-type transistor in the inverter with the change of the first parameter is within the first range, and the change value of the current flowing through the P-type transistor in the inverter is compensated, so that the change of the rising edge delay time T of the delay circuit is smaller. For another example, a certain delay circuit realizes falling edge delay, the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor. In this case, the second control circuit is arranged in the delay circuit, the second control circuit can adjust the voltage at the substrate end of the N-type transistor in the inverter, thereby adjusting the current flowing through the N-type transistor in the inverter, so that the change value of the current flowing through the N-type transistor in the inverter with the change of the first parameter is within the first range, and the change value of the current flowing through the N-type transistor in the inverter is compensated, so that the change of the falling edge delay time T of the delay circuit is smaller. For another example, a certain delay circuit realizes rising edge delay and falling edge delay, the delay circuit includes an inverter, and the inverter includes a P-type transistor and an N-type transistor. In this case, the first control circuit and the second control circuit are arranged in the delay circuit, the first control circuit can adjust the voltage at the substrate end of the P-type transistor in the inverter, thereby adjusting the current flowing through the P-type transistor in the inverter, so that the change value of the current flowing through the P-type transistor in the inverter with the change of the first parameter is within the first range, and the change value of the current flowing through the P-type transistor in the inverter is compensated, so that the change of the rising edge delay time T of the delay circuit is smaller, and the second control circuit can adjust the voltage at the substrate end of the N-type transistor in the inverter, thereby adjusting the current flowing through the N-type transistor in the inverter, so that the change value of the current flowing through the N-type transistor in the inverter with the change of the first parameter is within the first range, and the change value of the current flowing through the N-type transistor in the inverter is compensated, so that the change of the falling edge delay time T of the delay circuit is smaller. In this way, the change of the rising edge delay time T and the falling edge delay time T of the delay circuit can be smaller. The control ability of the delay circuit on the delay time (including the rising edge delay time and the falling edge delay time) precision is improved.

[0374] Figures 28-30 The examples of the two delay circuits are also applicable to the control circuit shown in the embodiments of the present application, ​ The potential generation circuit shown in the embodiments of the present application is a specific control circuit, which can be referred to in the prior art, ​In particular, the above description is not exhaustive.

[0375] The constant current source in the above embodiments can be, for example, a mirror current source, and the current at the mirror end can be a current independent of temperature coefficient, or a current independent of temperature, voltage, etc. The constant current source in the above embodiments can also be implemented in other ways.

[0376] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A potential generating circuit, characterized by comprising: Comprising: a first transistor and a second transistor, a potential of a substrate end of the first transistor varies with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generation circuit; wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generation circuit; a gate end of the second transistor is connected to a drain end of the second transistor; the first transistor is a P-type transistor, and the second transistor is an N-type transistor; a source end of the first transistor is connected to a first voltage node, a source end of the second transistor is connected to a second voltage node, a drain end of the first transistor is connected to a drain end of the second transistor, and a substrate end of the second transistor is connected to the second voltage node; the potential generation circuit further comprises: a constant current source, a first end of the constant current source is connected to the first voltage node, and a second end of the constant current source is connected to a third voltage node; an error amplifier, the first transistor and the error amplifier constitute a feedback loop, and the substrate end of the first transistor is connected to a voltage node of the feedback loop; a negative input end of the error amplifier is connected to the first voltage node, a positive input end of the error amplifier is connected to a first reference voltage, and an output end of the error amplifier is connected to the substrate end of the first transistor.

2. The potential generating circuit according to claim 1, characterized by the first parameter is the supply voltage or the operating temperature of the potential generation circuit, the potential of the substrate end of the first transistor increases as the first parameter increases, and the potential of the substrate end of the first transistor decreases as the first parameter decreases.

3. The potential generating circuit according to claim 1, wherein the third voltage node is connected to a power supply end, the first reference voltage is connected to the power supply end, and the potential of the third voltage node is greater than the potential of the first reference voltage.

4. The potential generating circuit according to any one of claims 1 to 3, characterized by Further comprising: a buffer, the buffer is connected to the output end and outputs a substrate potential, a value of the substrate potential is equal to a value of the potential of the substrate end of the first transistor.

5. A potential generating circuit, characterized by comprising: Comprising: a first transistor and a second transistor, a potential of a substrate end of the second transistor varies with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generation circuit; wherein a gate end of the first transistor is connected to a drain end of the first transistor, a gate end of the second transistor is connected to a drain end of the second transistor, and a substrate end of the second transistor serves as an output end of the potential generation circuit; the first transistor is a P-type transistor, and the second transistor is an N-type transistor; a source end of the first transistor is connected to a first voltage node, a source end of the second transistor is connected to a second voltage node, a drain end of the first transistor is connected to a drain end of the second transistor, and a substrate end of the first transistor is connected to the first voltage node; the potential generation circuit further comprises: a constant current source, a first end of the constant current source is connected to a third voltage node, and a second end of the constant current source is connected to the second voltage node; An error amplifier forms a feedback loop with the second transistor, and a substrate end of the second transistor is connected to one voltage node of the feedback loop; a negative input end of the error amplifier is connected to the second voltage node, a positive input end of the error amplifier is connected to a first reference voltage, and an output end of the error amplifier is connected to the substrate end of the second transistor.

6. The potential generating circuit according to claim 5, wherein The first parameter is a supply voltage or an operating temperature of the potential generation circuit, the potential of the substrate end of the second transistor decreases as the first parameter increases, and the potential of the substrate end of the second transistor increases as the first parameter decreases.

7. The potential generating circuit according to claim 5, wherein The first voltage node is connected to a power supply end, the first reference voltage is connected to a ground end, and the potential of the third voltage node is less than the potential of the first reference voltage.

8. The potential generating circuit according to any one of claims 5 to 7, characterized in that, Further comprising: a buffer connected to the output end and outputting a substrate potential, a value of the substrate potential being equal to a value of the potential of the substrate end of the second transistor.

9. A delay circuit, characterized by comprising: Comprising: the potential generation circuit according to any one of claims 1-4; a delay unit including a first inverter, the first inverter including a fourth transistor and a fifth transistor, a substrate end of the fourth transistor being connected to the potential of the substrate end of the first transistor, and a substrate end of the fifth transistor being connected to a ground end, the fourth transistor being a P-type transistor, and the fifth transistor being an N-type transistor.

10. The delay circuit of claim 9, wherein, Let H be a ratio of a channel length of the first transistor to a channel length of the fourth transistor, let L be a ratio of a channel length of the second transistor to a channel length of the fifth transistor, let M be a ratio of a channel width of the first transistor to a channel width of the fourth transistor, and let N be a ratio of a channel width of the second transistor to a channel width of the fifth transistor, the H being equal to the L, and the M being equal to the N.

11. A delay circuit, characterized by comprising: Comprising: the potential generation circuit according to any one of claims 5-8; a delay unit including a first inverter, the first inverter including a fourth transistor and a fifth transistor, a substrate end of the fourth transistor being connected to the potential of the substrate end of the first transistor, and a substrate end of the fifth transistor being connected to a power supply end, the fourth transistor being a P-type transistor, and the fifth transistor being an N-type transistor.

12. The delay circuit of claim 11, wherein, Let H be a ratio of a channel length of the first transistor to a channel length of the fourth transistor, let L be a ratio of a channel length of the second transistor to a channel length of the fifth transistor, let M be a ratio of a channel width of the first transistor to a channel width of the fourth transistor, and let N be a ratio of a channel width of the second transistor to a channel width of the fifth transistor, the H being equal to the L, and the M being equal to the N.

13. A delay circuit, characterized by Comprising: a first potential generation circuit, the first potential generation circuit being the potential generation circuit according to any one of claims 1-4; a second potential generation circuit, the second potential generation circuit being the potential generation circuit according to any one of claims 5-8; a delay unit including a first inverter including a fourth transistor and a fifth transistor, a substrate terminal of the fourth transistor being connected to a potential of a substrate terminal of a first transistor in the first potential generation circuit, a substrate terminal of the fifth transistor being connected to a potential of a substrate terminal of a second transistor in the second potential generation circuit, the fourth transistor being a P-type transistor, and the fifth transistor being an N-type transistor.

14. The delay circuit of claim 13, wherein, Let the ratio of the channel length of the first transistor in the first potential generation circuit to the channel length of the fourth transistor be H1, let the ratio of the channel length of the second transistor in the first potential generation circuit to the channel length of the fifth transistor be L1, let the ratio of the channel width of the first transistor in the first potential generation circuit to the channel width of the fourth transistor be M1, and let the ratio of the channel width of the second transistor in the first potential generation circuit to the channel width of the fifth transistor be N1, the H1 being equal to the L1, and the M1 being equal to the N1; Let the ratio of the channel length of the first transistor in the second potential generation circuit to the channel length of the fourth transistor be H2, let the ratio of the channel length of the second transistor in the second potential generation circuit to the channel length of the fifth transistor be L2, let the ratio of the channel width of the first transistor in the second potential generation circuit to the channel width of the fourth transistor be M2, and let the ratio of the channel width of the second transistor in the second potential generation circuit to the channel width of the fifth transistor be N2, the H2 being equal to the L2, and the M2 being equal to the N2.

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