Timing calibration device and method for multi-channel group

Abstract

The present invention discloses a timing calibration device and method for a multi-channel group. The timing calibration device for a multi-channel group includes multiple channel inputs, at least one relay switch, at least one comparator, at least one first multiplexer, and a measuring time chip. The at least one comparator is connected to the at least one relay switch and to a reference voltage, or the reference voltage is replaced by a digital-to-analog converter. The at least one first multiplexer inputs signals from different channel groups and outputs a signal of a designated channel. The measuring time chip calculates the timing signal difference of each channel in the multiple channel inputs as a basis for timing signal delay. The present invention can achieve a timing waveform with consistent alignment on the channel terminal, complete accurate timing error calibration, avoid signal time difference, and use only a single circuit board, significantly reducing the cost of the circuit board.

Description

Technical Field

[0001] The present invention relates to a timing calibration device and method for a multi-channel group, and more particularly to a timing calibration device and method for a multi-channel group that can be used on a large number of channels and can effectively calibrate the timing differences between the channels using a single calibration device. Background Art

[0002] In the prior art, regarding the transmission of multi-channel signals, due to individual differences between components, there will be differences in the timing of each channel, such as Figure 1 As shown. Figure 1 The left side mainly shows that there are timing differences between channels 1 to 4 compared to the reference. The arrows indicate that after timing calibration, we hope to achieve the following Figure 1 The timing diagram on the right side shows that the timing of each channel is consistent. It is expected that the timing of each channel from channel 1 to channel 4 is synchronized without error. Figure 2 Disclosed is a basic circuit architecture for a single channel. The architecture includes a driving data element connected to a delay circuit and then to a driver. The driver's output serves as a channel terminal. The channel terminal is then fed back to one input of a comparator. The other input of the comparator is connected to a reference voltage. The comparator then outputs a comparison data element, which serves as a reference for comparing timing differences.

[0003] like Figure 2 As shown in the circuit architecture, due to differences in driver characteristics and comparator characteristics, and even differences in line length, etc., there will be differences in timing comparison between multiple channels. However, when there are differences in channel timing, such as Figure 1 As shown in the timing diagram on the left side of the middle, these timing differences cannot produce aligned waveforms at the channel terminals, and there will also be different time differences between the comparison data from the channel terminals to the comparison results. The current common solution is to use a "short-circuit device interface board". This traditional architecture uses a short-circuit device interface board to calibrate the comparator path first and then the driver path. However, this calibration method often requires the configuration of a second or third calibration board when there are a large number of channels or a large number of channels. Figure 3 shown. Figure 3 In order to be applied to a large number of channels, the existing technology in the present invention sets the device interface board as two calibration boards, namely device interface board 1 and device interface board 2. Generally speaking, the device interface board is called a calibration board (or calibration board). The gathering point on the right side of device interface board 1 and the gathering point on the right side of device interface board 2 are both regarded as signal sources. However, Figure 3The disclosed prior art requires two calibration boards, or in other words, two circuit boards, to perform multi-channel timing calibration. Adding more input channels requires additional circuit boards. This not only complicates the calibration process, increasing costs, but also reduces calibration efficiency. Summary of the Invention

[0004] The present invention is a timing calibration device and method for a multi-channel group, including an innovative design of a calibration board architecture for timing calibration and its corresponding calibration method. It can be effectively used in timing calibration operations involving a large number of channels, and a single calibration device (i.e., a single calibration board) can be used to effectively detect the timing differences between each channel. The timing differences between each channel are then calibrated to achieve a consistent and aligned waveform at the channel terminal, thereby completing accurate calibration of timing errors and avoiding the generation of signal time differences. Only a single circuit board is used, which greatly reduces the cost of the circuit board and effectively improves the defects of the prior art.

[0005] The timing calibration device for a multi-channel group of the present invention comprises: a plurality of channel inputs, each of the plurality of channel inputs carrying a timing signal; at least one relay switch, an input of the at least one relay switch connected to the plurality of channel inputs; at least one comparator, a first input of the at least one comparator connected to an output of the at least one relay switch, a second input of the at least one comparator connected to a reference voltage, and an output of the at least one comparator outputting a first channel group; at least one first multiplexer having a plurality of inputs and an output; one of the plurality of inputs of the at least one first multiplexer connected to the first channel group; the plurality of inputs of the at least one first multiplexer further connected to a plurality of channel groups; an output of the at least one first multiplexer providing a first channel group; and a time measurement chip having a synchronization signal input and at least one event terminal, the at least one event terminal connected to the first channel group, the synchronization signal input terminal connected to a reference signal; the time measurement chip calculating a timing signal difference for each of the plurality of channel inputs as a basis for timing signal delay.

[0006] The beneficial effect of the present invention is that the timing calibration device and method for a multi-channel group of the present invention not only develops a timing calibration device for a multi-channel group of a single circuit board device, significantly reducing the cost of the circuit board, but also can be expanded to be used for timing signal correction with multiple multi-channel groups. It is effectively applied in the technical field of timing difference correction for a large number of channel groups or a large number of channels, saving the area and volume of the entire calibration device and facilitating connection with the multi-channel group to be calibrated.

[0007] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and illustration and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram for the purpose of prior art multi-channel timing calibration;

[0009] Figure 2 A schematic diagram of a basic channel architecture of the prior art;

[0010] Figure 3 A schematic diagram of solving multi-channel timing problems in the prior art;

[0011] Figure 4 is a circuit diagram of a first embodiment of the present invention;

[0012] Figure 5 is a circuit diagram of a second embodiment of the present invention;

[0013] Figure 6 FIG. 4 is a circuit diagram of another state in the second embodiment of the present invention. DETAILED DESCRIPTION

[0014] The present invention discloses a timing calibration device and method for a multi-channel group. The present invention can be effectively applied to timing calibration operations involving a large number of channels. A single calibration device can effectively detect the timing differences between the channels, thereby facilitating subsequent calibration operations based on the timing differences between the channels, thereby effectively achieving consistent alignment of the timing waveforms at the terminals of each channel.

[0015] Hereinafter, various exemplary embodiments will be described more fully with reference to the accompanying drawings, and some exemplary embodiments will be shown in the accompanying drawings. However, the concept of the present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Specifically, these exemplary embodiments are provided so that the present invention will be detailed and specific, and will fully convey the scope of the concept of the present invention to those skilled in the art. In the accompanying drawings, the size and relative position distances of the number or size of multi-channel input, channel group, multiplexer, and measurement time chip can be shown for clarity, wherein similar or similar English labels or numbers are always indicated to indicate similar or related elements.

[0016] It should be understood that although the terms "first," "second," "third," etc. may be used herein, these terms are used to clearly distinguish one element from another and do not necessarily have a numerical order. That is, a description may include a first and a third, but no second; or there may be multiple firsts but only a single second. For example, the terms "upper side" or "lower side," "left end" or "right end," "left side" or "right side," etc., used herein, are used to clearly distinguish one side or endpoint of an element from the other side or endpoint of the corresponding element, or to distinguish the corresponding connection position relationship between one element and another element, or the different positions between one side and another side. They are not used to limit the order or position relationship presented by the text numbers, and do not necessarily have a numerically continuous relationship. That is, from another perspective, the upper side (or lower side) of an element can be renamed the lower side (or upper side) without affecting the essence of the technology. Furthermore, the term "at least one" may be used herein to describe a technology implemented by one or more elements. In addition, the term "plurality" may also be used herein to describe a plurality of elements or a plurality of components, but such plurality is not limited to the implementation of the technology implemented by two, three, four or more numbers.

[0017] See Figure 4 FIG. 1 is a circuit block diagram of a first embodiment of a timing calibration device for a multi-channel group according to the present invention. The timing calibration device according to the present invention can also be referred to as a “calibration board” or a “correction board” in practical operation. The present invention does not impose any restrictions on such names, and the name is determined based on the actual business needs of the user. Figure 1 The disclosed embodiment includes a plurality of channel inputs 10, a plurality of relays 20, a plurality of comparators 30, a plurality of first multiplexers 40 and a measuring time chip 50. It should be stated that in the application of the embodiment of the present invention, if the number of channels of the user is not large, the present invention can also use only a single relay 20, a single comparator 30 and a single first multiplexer 40; that is, the embodiment of the present invention includes one or more relays 20, comparators 30 and a first multiplexer 40 in operation; in other words, the present invention includes at least one relay switch 20, at least one comparator 30 and at least one first multiplexer 40. Each channel of the plurality of channel inputs 10 carries a timing signal, and the timing signal can be, for example, as follows Figure 1 The channel timing signal shown; furthermore, the gathering point of multiple channel inputs 10 can be regarded as a signal source. When there are multiple groups of multiple channel inputs 10, there will be multiple gathering points, that is, there are multiple signal sources. However, the present invention is not limited to one signal source or multiple signal sources.

[0018] The input end of the relay switch 20 (as mentioned above, it can be one or more relay switches 20) is connected to the multiple channel inputs 10. If there are multiple groups of multiple channel inputs 10, they are respectively connected to multiple relay switches 20. The relay switch 20 is a switch or gate for the timing signals of the multiple channel inputs 10 to enter the timing calibration device of the entire multi-channel group. When the relay switch 20 is disconnected or cut off, the signals of the multiple channel inputs 10 will not enter the timing calibration device of the multi-channel group; when the relay switch 20 is turned on or connected, the signals of the multiple channel inputs 10 enter the timing calibration device of the multi-channel group. The comparator 30 described above can be implemented by one or more comparators 30 in the present invention. The first input end of the comparator 30 (for example, Figure 4 The upper input of the comparator 30 shown in FIG. 1 is connected to the output of the relay switch 20 , and the second input of the comparator 30 (eg, Figure 4 The lower input of the comparator 30 shown in FIG3 is connected to a reference voltage; the output of the comparator 30 is then output to the first channel group (ie Figure 4 The channel group 1 shown in FIG. 1 ). The first multiplexer 40 can also be implemented as one or more first multiplexers 40, wherein the first multiplexer 40 has multiple input terminals (such as Figure 4 The left side of the first multiplexer 40 is shown) and an output terminal (as shown Figure 4 One of the plurality of input terminals of the first multiplexer 40 is connected to the first channel group (ie, channel group 1). Figure 4 The plurality of input terminals of the first multiplexer 40 are further connected to a plurality of channel groups including the second, third, fourth, fifth, sixth, seventh to eighth channel groups (channel group 2 to channel group 8, as shown in FIG. Figure 4 After the multiplexing selection by the first multiplexer 40, the output of the first multiplexer 40 is a timing signal of the channel group 1-8. In practice, the timing signal of the channel group 1-8 can be a designated channel signal or a designated channel group signal.

[0019] Figure 4 The measuring time chip 50 shown in the figure has a synchronous signal input terminal S and at least one event terminal. In actual operation, it can meet the needs of the user. The measuring time chip 50 can have only a single event terminal or multiple event terminals as the input terminal of the timing signal. Figure 4In an embodiment, the first, second, third, and fourth event terminals (A, B, C, and D) are provided, wherein the first event terminal A is connected to the timing signals of channel groups 1-8 output by the first multiplexer 40. Furthermore, the synchronization signal input terminal S is connected to a reference signal, which serves as a time reference for measuring the timing signals of different channels. The timing measurement chip 50 calculates the timing signal differences for each channel within the plurality of channel inputs 10, which can be used as a basis for timing signal delay control. In another embodiment, when multiple groups of channel inputs 10 are coupled with multiple relay switches 20, multiple comparators 30, and multiple first multiplexers 40, the first event terminal A of the timing measurement chip 50 is input to channel groups 1-8 (the first channel group), the second event terminal B is input to channel groups 9-16 (the second channel group), the third event terminal C is input to channel groups 17-24 (the third channel group), and the fourth event terminal D is input to channel groups 25-32 (the fourth channel group).

[0020] See Figure 5 FIG. 1 is a circuit diagram of a second embodiment of the present invention. In addition to the aforementioned multiple channel inputs 10 (which can also be implemented as multiple groups of multiple channel inputs 10), multiple relays 20 (which can also be implemented as a single relay 20), multiple comparators 30 (which can also be implemented as a single comparator 30), multiple first multiplexers 40 (which can also be implemented as a single first multiplexer 40), and a time measurement chip 50, the circuit also includes a digital-to-analog converter (DAC) 70 and a controller 80. The DAC 70 replaces the aforementioned reference voltage. In the second embodiment, the DAC 70 can generate a user-defined reference voltage waveform signal as a signal for the second input terminal (the upper input terminal of the comparator 30) of the comparator 30. Furthermore, the DAC 70 can function as a waveform generator, generating a reference timing waveform that serves as a reference value for timing calibration.

[0021] Figure 5 The controller 80 shown is connected to the relay switch 20 (can be one or more relay switches 20), the digital-to-analog converter 70, the first multiplexer 40 (can be one or more first multiplexers 40, and Figure 4The controller 80 receives the output signal of the timing chip 50 as a timing signal feedback reference, facilitating subsequent overall control of the calibration board of the present invention. After calculating the delay state of each timing signal, the controller 80 further controls the digital-to-analog converter 70 and the aforementioned first multiplexer 40 to perform the necessary timing adjustment operations and processes, adjusting the timing delays of channels with timing differences, thereby ensuring consistent and aligned timing outputs from each channel in the calibration board of the present invention.

[0022] exist Figure 5 Another embodiment is also disclosed, which includes a second multiplexer 60. This is another reference embodiment of the second embodiment of the present invention. The function of this reference embodiment is to be able to calibrate the timing error of the timing calibration device of the entire multi-channel group of the present invention. In other words, it can be used to calibrate the timing error of the calibration board itself. For the calibration board or correction board, it is also important to be able to calibrate the timing error of the device itself. Figure 5 In order to correct the timing error of the correction board of the device of the present invention, Figure 6 This is the state correction after the general channel timing signal comes in after the device of the present invention is corrected. The second multiplexer 60 has an input terminal (such as Figure 5 The left side of the second multiplexer 60 in the circuit is connected to a reference signal at its input, which serves as a reference for the timing error of the calibration circuit itself. The right side of the second multiplexer 60 has a first output and a second output, and the second output is connected to the synchronization signal input S in the measurement time chip 50. In another embodiment of the second embodiment, the timing calibration device for a multi-channel group of the present invention further includes a first coaxial RF connector (SMA connector) 22 and a second coaxial RF connector (SMA connector) 62. The first coaxial RF connector 22 is connected between the relay switch 20 and the first input of the comparator 30; the second coaxial RF connector 62 is connected to the first output of the second multiplexer 60. When actually needed, in addition to directly connecting the second output of the second multiplexer 60 to the first input of the at least one comparator 30 with a jumper connection, a pair of coaxial RF connectors can also be provided as a jumper connection medium to measure the timing error of the calibration circuit itself.

[0023] Likewise, Figure 5 In the embodiment of the measuring time chip 50, at least one event terminal is provided. In actual operation, the measuring time chip 50 can be adapted to the needs of the user. The measuring time chip 50 can have only one event terminal or multiple event terminals as the input terminals of the timing signal. Figure 5In the embodiment, the first, second, third, and fourth event terminals (A, B, C, and D) are provided. The first event terminal A is connected to the timing signals of channel groups 1-8 output by the first multiplexer 40. The timing chip 50 calculates the timing signal differences for each channel in the plurality of channel inputs 10, which can be used as a basis for controlling the timing signal delay. After the timing chip 50 calculates the delay states of each timing signal, the controller further controls the digital-to-analog converter 70 and the first multiplexer 40 to adjust the delays of channels with timing differences, thereby aligning the timing of each channel in the calibration board of the present invention. Furthermore, when multiple sets of channel inputs 10 are combined with multiple relay switches 20, multiple comparators 30, and multiple first multiplexers 40, the first event terminal A of the timing chip 50 is connected to channel groups 1-8, the second event terminal B is connected to channel groups 9-16, the third event terminal C is connected to channel groups 17-24, and the fourth event terminal D is connected to channel groups 25-32.

[0024] Combine Figure 5 and Figure 6 As shown in FIG, the timing calibration method of the multi-channel group proposed in the embodiment of the present invention can be further explained. It should be noted that the timing calibration method of the multi-channel group described in the present invention is mainly used in the following embodiments. Figure 4 or Figure 5 In a timing calibration device for a multi-channel group, the timing calibration method for the multi-channel group includes: first calibrating a general comparator path; then calibrating a general driver path; and then calibrating the timing error of the timing calibration device for the multi-channel group: first, the relay switch 20 is turned off, as shown in FIG. Figure 5 The second output of the second multiplexer 60 is connected to the first input terminal of the at least one comparator 30, as shown Figure 5 As shown; and the timing difference of multiple channel groups is measured by the measuring time chip 50; the controller 20 then uses the timing difference as the basis for timing calibration to calibrate the timing of each channel. After calibrating the timing of each channel group, please refer to Figure 6 As shown: first disconnect the second output of the second multiplexer 60 and the first input of the at least one comparator 30; at the same time, connect the relay switch 20 (on), as shown Figure 6 to measure the timing difference of multiple channel groups using the measuring time chip 50; the controller 80 then uses the timing difference as the basis for timing calibration to calibrate the timing of each channel.

[0025] In summary, the multi-channel timing calibration device and method of the present invention not only develops a multi-channel timing calibration device for a single circuit board, significantly reducing circuit board costs, but also expands its application to timing signal calibration for multiple multi-channel groups. This effectively applies to the technical field of timing discrepancy correction for large numbers of channels or complex channels, saving the overall calibration device area and volume, and facilitating integration with the multi-channel group to be calibrated. Clearly, the technical content of the present invention meets the requirements for a strong patent application.

[0026] The contents disclosed above are only preferred feasible embodiments of the present invention and do not limit the claims of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention description and drawings are included in the claims of the present invention.

Claims

1. A timing calibration device for a multi-channel group, characterized in that: The timing calibration device of the multi-channel group includes: A plurality of channel inputs, each channel of the plurality of channel inputs carrying a timing signal; at least one relay switch, wherein an input end of the at least one relay switch is connected to the plurality of channel inputs; at least one comparator, wherein a first input terminal of the at least one comparator is connected to the output terminal of the relay switch, and an output terminal of the at least one comparator outputs a first channel group; At least one first multiplexer has a plurality of input terminals and an output terminal; one of the plurality of input terminals of the at least one first multiplexer is connected to the first channel group; the plurality of input terminals of the at least one first multiplexer are further connected to the plurality of channel groups; the output terminal of the at least one first multiplexer is a first channel group; a second multiplexer having an input terminal connected to a reference signal; the second multiplexer having a first output and a second output; a timing measurement chip having a synchronization signal input terminal and at least one event terminal; the synchronization signal input terminal is connected to the second output of the second multiplexer; the at least one event terminal is connected to the first channel group; the timing measurement chip calculates the timing signal difference of each channel among the plurality of channel inputs as a basis for timing signal delay; a digital-to-analog converter, wherein an output terminal of the digital-to-analog converter is connected to the second input terminal of the at least one comparator; A controller is simultaneously connected to the relay switch, the digital-to-analog converter, the at least one first multiplexer, and the measuring time chip, and the controller receives the output signal of the measuring time chip; after the measuring time chip calculates the delay status of each timing signal, the controller controls the digital-to-analog converter and the at least one first multiplexer to adjust the delay of channels with timing differences so that the timing of each channel is consistent.

2. The timing calibration device for a multi-channel group according to claim 1, wherein: The timing calibration device of the multi-channel group, wherein the digital-to-analog converter can generate a reference voltage waveform signal required by the user in accordance with the user's needs as the second input terminal signal of the at least one comparator.

3. The timing calibration device for a multi-channel group as claimed in claim 1, wherein: in, The at least one event terminal in the time measurement chip includes: a first event terminal, a second event terminal, a third event terminal, and a fourth event terminal; the first event terminal inputs the first channel group; the second event terminal inputs the second channel group; the third event terminal inputs the third channel group; and the fourth event terminal inputs the fourth channel group. The plurality of channel groups connected to the plurality of input terminals of the at least one first multiplexer include different channel groups from the second channel group to the eighth channel group.

4. A timing calibration method for a multi-channel group, characterized in that: The timing calibration method for a multi-channel group is used in the timing calibration device for a multi-channel group as claimed in claim 1 , and the timing calibration method for a multi-channel group comprises: First calibrate a comparator path; recalibrating a drive path; Then, calibrating the timing error of the timing calibration device of the multi-channel group; Cut off the relay switch; connecting the second output of the second multiplexer to the first input of the at least one comparator; Use the timing chip to measure the timing differences of multiple channel groups; The controller then uses the timing difference as a basis for timing calibration to calibrate the timing of each channel; Then calibrate the timing of each channel group; disconnecting the second output of the second multiplexer from the first input of the at least one comparator; Connect the relay switch; Use the timing chip to measure the timing differences of multiple channel groups; The controller then uses the timing difference as a basis for timing calibration to calibrate the timing of each channel.

Images