Resistor Geometry

Abstract

A thin film resistor and a method for manufacturing the thin film resistor are provided. The thin film resistor includes a first terminal, a second terminal, and a resistor body, the resistor body providing a resistive current path between the first terminal and the second terminal, and the method includes: depositing a first layer of conductive material onto at least one of a support structure and the resistor body, applying a first photolithography mask to the first layer, and etching the first layer to form a first terminal; and depositing a second layer of conductive material onto at least one of the support structure and the resistor body, applying a second photolithography mask to the second layer, and etching the second layer to form a second terminal, wherein the first photolithography mask is different from the second photolithography mask, and the lateral spacing between the first terminal and the second terminal is less than the in-plane minimum feature size of the first photolithography mask and the second photolithography mask.

Description

Technical Field

[0001] The present disclosure relates to resistor geometries and methods for forming resistors having different geometries. Background Art

[0002] In thin film electronics, resistors are often oriented laterally so that the conductive terminals are arranged in the same plane and / or formed from the same deposited layer of material, and the resistor body is arranged between the terminals. Figure 1 , where the resistor 100 has a first conductive terminal 102 and a second conductive terminal 104 in the same plane and / or deposition layer, and a resistor body 106 formed of a resistive material (e.g., a resistive film) connects the two conductive terminals 102 and 104. However, this geometry and the associated manufacturing sequence result in limitations on the size and value of the resistor that can be provided.

[0003] More specifically, refer to Figure 2 In a plan view, the resistance of the resistor body 106 providing a current path between the terminals 102 and 104 is proportional to the path length / spacing L between the terminals (i.e., the length of the resistor body / spacing of the interface between the terminals and the resistor body), and inversely proportional to the width W of the resistor body, assuming uniform thickness. Therefore, in order to provide a large resistance without occupying a large area of ​​lateral space, a high resistivity film, such as a high resistivity film having a resistivity greater than 1 MΩ / sq, can be used. However, by using a film having a high resistivity, for example, the geometry and size of low and medium value (such as 20 kΩ) resistors are affected.

[0004] In thin film resistors, the minimum width W and length L of the film forming the resistor body are primarily determined by the spatial resolution, i.e., the minimum in-plane feature size of the photolithography process used to pattern the relevant thin film layers. For example, using a 1MΩ / sq resistor film and a minimum width of 4μm, a 10MΩ resistor requires a 40μm spacing between the terminals, resulting in a 160μm 2 However, while this resistive film area is feasible, problems may arise when considering smaller value resistors. For example, when the goal is to provide a 20kΩ resistor using the same 1MΩ / sq resistive film with the same width of 4μm, a terminal spacing of 80nm will be required, which is beyond the resolution of many lithographic processes (such as conventional thin film optical lithography, for example). Alternatively, if the terminal spacing is increased to the minimum resolution of the lithographic technology used, for example 0.5μm, a resistive film width of 25μm will be required, yielding a 12.5μm 2Therefore, although the value of a 20kΩ thin film resistor is 3 orders of magnitude lower than that of a 10MΩ thin film resistor, the lateral space (i.e., the area occupied by the 20kΩ resistor) is only one order of magnitude smaller than that of the 10MΩ resistor.

[0005] Thin film electronics can be used in flexible IC (FlexIC) architectures; however, the above-mentioned resistor size limitations may prevent further miniaturization of FlexIC architectures, for example, when thin film transistors require a load to form an inverter. Although an inverter can be provided via a diode or transistor load transistor in some cases, these transistors typically suffer from high power consumption and slow switching speeds given the unipolar nature of FlexIC semiconductors, and may therefore be a suboptimal solution in many cases.

[0006] Conventional lateral thin-film resistor geometries also impose restrictions on the placement and use of resistors in thin-film electronics, as there is less flexibility in how they can be placed and manufactured in thin-film and FlexIC architectures.

[0007]

[0006] It would be desirable, therefore, if thin film resistor geometries and methods for forming thin film resistors could be provided that overcome the above-mentioned limitations in lithographic resolution, lateral space requirements, and geometric flexibility. Summary of the invention

[0008] It is an object of certain examples of the present disclosure to provide a thin film resistor and a method of manufacturing a thin film resistor having a terminal pitch that is less than a minimum in-plane feature size of a lithography tool used to pattern the thin film resistor layer. By achieving a terminal pitch that is less than the minimum in-plane feature size, a thin film resistor with reduced lateral dimensions can be achieved at a lower cost, and improved scaling between resistor value and lateral dimension can also be achieved.

[0009] According to a first aspect of the present disclosure, a method for manufacturing a thin film resistor on a support structure is provided, the thin film resistor comprising a first terminal, a second terminal and a resistor body, the resistor body providing a resistive current path between the first terminal and the second terminal, the method comprising: depositing a first layer of conductive material onto at least one of the support structure and the resistor body, applying a first photolithography mask to the first layer, and etching the first layer to form a first terminal; and depositing a second layer of conductive material onto at least one of the support structure and the resistor body, applying a second photolithography mask to the second layer, and etching the second layer to form a second terminal, wherein the first photolithography mask is different from the second photolithography mask, and a lateral spacing between the first terminal and the second terminal is smaller than the minimum feature size within the plane of the first photolithography mask and the second photolithography mask.

[0010] In one example, the lithography mask is an optical lithography mask.

[0011] In another example, at least a portion of the second terminal is located outside of a lateral plane defined by a vertical extent of the first terminal.

[0012] In another example, the resistor body is non-planar.

[0013] In another example, the resistor body includes a first planar region located in a first transverse plane and a second planar region located in a second transverse plane, and a third planar region located in a third plane substantially perpendicular to the first transverse plane and the second transverse plane and connecting the first planar region and the second planar region, and wherein the first transverse plane and the second transverse plane are separated by a distance in a direction parallel to the third plane.

[0014] In another example, the first planar region of the resistor body laterally overlaps at least a portion of the first terminal.

[0015] In another example, the second planar region of the resistor body laterally overlaps at least a portion of the second terminal.

[0016] In another example, the second terminal is located completely outside of a lateral plane defined by the vertical extent of the first terminal.

[0017] In another example, the resistor includes a third terminal electrically connected to the first terminal, and wherein the resistor body provides a resistance path between the second terminal and the third terminal that is different from the resistance path between the first terminal and the second terminal, and wherein the method includes forming the third terminal at a time separate from at least one of the first terminal and the second terminal.

[0018] In another example, a spacing between the second terminal and the third terminal is smaller than an in-plane minimum feature size of the first photolithography mask and the second photolithography mask.

[0019] In another example, the third terminal is at least partially located outside of a lateral plane defined by a vertical extent of the first terminal and a lateral plane defined by a vertical extent of the second terminal.

[0020] In another example, a lateral spacing between any two terminals is less than 500 nm.

[0021] In another example, the first terminal, the second terminal, and the resistor body are formed from separate thin film layers of material.

[0022] In another example, the first terminal and the second terminal do not vertically overlap.

[0023] In another example, applying the first photolithography mask and the second photolithography mask each includes depositing an unillustrated photoresist layer onto the corresponding conductive material layer, applying the photolithography mask to the photoresist layer, and developing the photoresist layer to produce a patterned photoresist layer.

[0024] According to a second aspect of the present disclosure, a thin film resistor is provided, comprising a first terminal formed by a first thin film layer of a conductive material, a second terminal formed by a second thin film layer of a conductive material, and a resistor body formed by a thin film layer of a resistive material, the resistor body providing a resistive current path between the first terminal and the second terminal, wherein a lateral spacing between the first terminal and the second terminal is smaller than a minimum in-plane lateral characteristic dimension of the thin film resistor.

[0025] In one example, a lateral spacing between the first terminal and the second terminal is at least an order of magnitude smaller than a minimum in-plane lateral feature size of the thin film resistor.

[0026] In another example, the thin film resistor includes a third terminal electrically connected to the first terminal, and wherein the resistor body provides a resistance path between the second terminal and the third terminal that is different from a resistance path between the first terminal and the second terminal.

[0027] In another example, the third terminal is at least partially located outside of a lateral plane defined by the first terminal and a lateral plane defined by the second terminal.

[0028] In another example, the first terminal and the second terminal are in separate deposition layers.

[0029] In another example, a lateral spacing between any two terminals is less than 500 nm.

[0030] In another example, the first terminal and the second terminal do not vertically overlap.

[0031] In another example, a lateral spacing between any two terminals of the thin film resistor is smaller than a minimum in-plane feature size of the thin film integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The following further describes embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 A schematic diagram of a conventional thin film resistor is provided;

[0034] Figure 2 A schematic diagram of a conventional thin film resistor is provided;

[0035] Figure 3a A schematic diagram of a thin film resistor according to an example of the present disclosure is provided;

[0036] Figure 3b A schematic diagram of a thin film resistor according to an example of the present disclosure is provided;

[0037] Figure 4 A schematic diagram of a thin film resistor according to an example of the present disclosure is provided;

[0038] Figure 5 A schematic diagram of a thin film resistor according to an example of the present disclosure is provided;

[0039] Figure 6 A schematic diagram of a thin film resistor according to an example of the present disclosure is provided;

[0040] Figure 7 A schematic diagram of a thin film resistor according to an example of the present disclosure is provided;

[0041] Figure 8 A schematic diagram of a thin film resistor according to an example of the present disclosure is provided;

[0042] Fig. 9 A schematic diagram of a thin film resistor according to an example of the present disclosure is provided;

[0043] Fig.10 A schematic diagram of a thin film resistor according to an example of the present disclosure is provided;

[0044] Fig.11 A schematic diagram of a thin film resistor according to an example of the present disclosure is provided;

[0045] Fig.12 A schematic diagram of a thin film resistor according to an example of the present disclosure is provided;

[0046] Figures 13a to 13i Provides a schematic diagram of stages in the manufacture of a thin film resistor according to an example of the present disclosure;

[0047] Figures 14a to 14d Provides a schematic diagram of stages in the manufacture of a thin film resistor according to an example of the present disclosure;

[0048] Fig.15 A schematic diagram of a thin film resistor according to an example of the present disclosure is provided; and

[0049] Figures 16a to 16g Schematic diagrams of stages in the manufacture of a thin film resistor according to examples of the present disclosure are provided. DETAILED DESCRIPTION

[0050] According to the present disclosure, at least some of the limitations discussed above can be solved by using two different layers to form the conductive terminals / contacts of the thin film resistor, i.e., depositing the conductive material forming each terminal separately from each other at different points in time and / or independently applying the photolithography mask used to pattern the layer forming the terminal. For example, a resistive film layer can be formed during a first deposition, photolithography patterning, and etching step, and the resistor body is formed by the resistive film layer; a first terminal is formed during a second deposition, photolithography patterning, and etching step; and a second terminal is formed during a third deposition, photolithography patterning, and etching step. However, this order can be changed as needed to achieve any desired geometry. For example, the material forming the first terminal can be deposited first, followed by the material forming the resistive film, and then the material forming the second terminal can be deposited.

[0051] Advantageously, forming the terminals via two separate deposited layers enables the spacing of the terminals (i.e., the spacing between the interfaces between the terminals and the resistor body) to be smaller than the resolution of the lithography method used, i.e., the length L can be greater than zero but less than the minimum resolution of the lithography mask / tool. In particular, the minimum spacing can be determined by the overlay error of the lithography technique and the mask rather than its in-plane resolution, without being limited by the in-plane resolution of the lithography tool used. For example, with respect to optical lithography, the overlay error (i.e., the positioning error of the two masks defining two different layers) can be approximately 30nm, while the minimum in-plane optical resolution of the lithography tool can be 500nm. Therefore, even with an error of + / -5%, this overlay error will be sufficient to achieve the exemplary terminal spacing of 80nm discussed above. In addition to effectively achieving increased patterning resolution, patterning resolution typically associated with higher cost lithography tools can also be achieved using lower cost lithography tools by following the currently disclosed technology.

[0052] Furthermore, in addition to enabling small terminal pitches, new resistor geometries can be formed by separating the deposition / patterning / etching steps used to form the terminals of the thin film resistor. For example, by forming the terminals separately, the terminals can only partially overlap or not overlap at all in the spatial layer / planar layer / lateral plane, so that the resistor no longer has a purely lateral structure.

[0053] Finally, some limitations associated with traditional lateral thin film resistor architectures may be addressed by the novel (eg, 3D) thin film resistor architectures set forth by the present disclosure.

[0054] Figure 3a -b to Fig.12Schematics are provided of many different resistor geometries that can be formed by the described two-step lithography process (i.e., when the terminal pitch is less than the minimum resolution of the lithography tool, or when the material for the terminals cannot be deposited in a single layer) or via conventional thin film fabrication techniques. Thus, while described with reference to two-step lithography processes and their ability to achieve low resistor values ​​in a space efficient manner, they are not limited to terminals formed in this manner.

[0055] Figure 3a , Figure 3b , Figure 4 and Figure 5 Alternative thin film resistor geometries according to the present disclosure are shown, wherein the resulting terminal pitch may be smaller than the resolution of the photolithography tool used.

[0056] exist Figure 3a , the lateral planes P1 and P2 defined by the vertical extent of the terminals 302a and 304a, respectively, only partially overlap, and therefore the terminals no longer have a purely lateral spatial geometry. In addition, in this particular example, the terminal 302a is partially located on the top of the resistor body 306a and partially located on the surface below the resistor body and the terminal 302a. Although this geometry may not be formed solely by the separation of the deposition stages of the two terminals, a reduced terminal spacing can be achieved by doing so. For example, the material forming the resistor body 306a is first deposited and may be patterned and etched. Subsequently, the material forming the first terminal 302a is deposited, photolithographically patterned using a first mask, and etched to form the first terminal. Finally, the material forming the second terminal 304a is deposited, photolithographically patterned using a second mask, and etched to form the second terminal. Reference Fig.13a -i, Fig.14a -d and Fig.16a -g discusses these processes in more detail. In other variant embodiments of the method, both terminals 302a and 304a can be deposited completely on top of resistor body 306a, giving them a substantially planar and lateral spatial geometry. The thickness of terminals 302a and 304a can be substantially the same, so that their lateral planes substantially overlap. Alternatively, the thickness of terminals 302a and 304a can be different, so that their lateral planes partially overlap. Figure 3a The described TFT geometries and variations may use different conductive materials for each terminal to reduce etching process requirements. In addition, different etching processes may be used in the formation of one or more first terminals, second terminals, and resistor bodies so that, for example, the formation of the second terminal does not adversely affect the first terminal, and / or different arrangements of etch stop layers may be used.

[0057] Although Figure 3aThe structure of the resistor is shown as including surfaces in only perpendicular horizontal and vertical planes, but this is for illustration only, and in reality, the material forming terminal 302a may conform to the resistor body 306a when deposited, and therefore may not have a purely horizontal and vertical planar structure. In other words, the thickness of the material forming terminal 302a will be approximately the same, whether it is deposited on the resistor body or on the underlying substrate, so that the shape of the material forming terminal 302a will generally conform to the shape of the surface deposited thereon.

[0058] Figure 3b 3 shows a structure of a resistor according to the present disclosure, wherein the material forming one of the terminals 302b at least partially conforms to the shape of the resistor body 306b, and the material has been at least partially deposited on the resistor body 306b. Figure 3b The order of deposition is similar to that of reference Figure 3a The sequence described is the same, but the terminal 302b has a non-vertical / horizontal portion (such as 308b) that is produced by the deposition of the material forming the terminal 302b covering the edge of the resistor body 306b. Figure 3b As shown, planes P1 and P2 refer to the vertical extents of terminals 302b and 304b, respectively.

[0059] More generally, although Figures 4 to 16a The resistor structures of FIG. 1-g primarily show idealized structures having vertical and horizontal planar structures, but in each of the structures shown, the layers may at least partially conform to them to correspond to Figure 3b The terminals 302b in the embodiment of the present invention are similar to the layers on which the layers are deposited. In addition, the specific shape of the conforming layer may vary depending on the material deposition technique used, and may therefore be straight or curved.

[0060] By following Figure 3a and Figure 3b The invention provides a method for manufacturing resistor geometries that can achieve L values ​​that are less than the in-plane optical resolution of the lithography tool used, which in turn enables a wider range of resistor values ​​and scalable dimensions in thin film ICs. More specifically, because separate lithography masks are used to form the first and second terminals, it is the alignment accuracy of these masks that limits the terminal spacing, as relative to the in-plane resolution / minimum feature size of any particular lithography mask, where the alignment accuracy is generally higher than the absolute resolution of the mask. In addition, because each terminal is defined in a single exposure, this method is lower in cost and complexity and higher in yield than existing multiple exposure techniques for high-resolution lithography, such as LELE (exposure-etch-exposure-etch).

[0061] Furthermore, as explained in more detail below, when designing thin films and / or FlexICs, Figure 3a and Figure 3b Novel geometries and fabrications of the resistor of and yet other exemplary resistors may be used to provide additional design / architecture flexibility.

[0062] refer to Figure 4 , in which the transverse planes (P1 and P2) defined by the vertical extent of the terminals partially overlap, as Figure 3a and Figure 3b As shown in , the resistor includes a non-planar resistor body that includes planar regions located in different planes. More specifically, the resistor body includes a first planar region 408 located in a first transverse plane, a second planar region 410 located in a second transverse plane, and a third planar region 412 located in a third (vertical) plane that is substantially perpendicular to the first transverse plane and the second transverse plane, such that the first planar region and the second planar region are separated by a distance in a direction parallel to the third plane. As described with respect to Figure 3a and Figure 3b As stated, Figure 4 The structure in represents an idealized case, and in general the third plane / third plane region 412 may be oriented away from vertical, depending on the patterning and etching techniques used to create the structure.

[0063] exist Figure 4 In terms of manufacturing the resistor, the material for the first terminal 402 can be deposited in a first layer, which is then patterned and etched by photolithography; then the material for the resistor body 406 is deposited in a second layer, which is then patterned and etched by photolithography; then the material for the second terminal 404 is deposited in a third layer, which is then patterned and etched by photolithography. The resistor body 406 can be patterned to extend over any number of locations on the first terminal 402 as desired, such as over none, part, or all of the upper surface of the first terminal 402. Figure 3a , a terminal pitch L smaller than the resolution of the lithography tool can be achieved by applying separate lithography masks for the first terminal and the second terminal.

[0064] exist Figure 5 In the case of Figure 4 however, the manufacturing process can be simplified because only the layer forming the resistor body 506 may need to act as an etch stop since it can cover all of the upper surface of the first terminal 502, thereby preventing etching of the first terminal while the second terminal is being etched.

[0065] exist Figure 6In the embodiment, the first terminal 602 and the second terminal 604 are deposited, patterned and etched in separate layers around the additional support or substrate layer 608 to achieve separation of L, where L may be smaller than the resolution of the photolithography mask. Subsequently, a resistive film layer is deposited to form the resistor body 606. Figure 6 The layer forming terminal 602 can be patterned and etched down to the second terminal 604 and the additional layer 608 according to the etching required for the geometry of the first terminal 602. In some examples, the second terminal 604 and the resistor film can be etch stops to simplify the manufacturing process. For example, by selecting different materials and / or different etching processes for the first terminal 602 and the second terminal 604, the additional layer 608 can be omitted. In this case, the first terminal and the second terminal are deposited, patterned and etched in separate layers, and the structure of the first deposited terminal is substantially unaffected by the etching process of the second deposited terminal. The resistor body is deposited on top of the first terminal and the second terminal.

[0066] Alternatively, if the spacing L does not need to be smaller than the resolution of the photolithography tool / mask used, the first and second terminals may be deposited, patterned and etched together.

[0067] With respect to when using high resistivity resistive films, by enabling terminal spacings smaller than the lithographic resolution, scaling of the lateral space required for lower value thin film resistors compared to high value thin film resistors can achieve improvements in scalability using the above described geometry and manufacturing sequence. For example, a 20 kΩ resistor formed from a resistive film having a resistivity of 1 MΩ / sq, a width of 4 μm, and having a terminal spacing of 80 nm can occupy 0.32 μm 2 Instead of 12.5μm 2 , thus achieving a reduction in lateral space of the same order of magnitude as the reduction in resistance from 10MΩ to 20kΩ.

[0068] While a reduction in the minimum spacing between resistor terminals can be achieved by depositing material layers, patterning and / or etching the terminals separately, the tolerance of the resulting resistor may be adversely affected by variations in alignment between layers and, therefore, between terminals, particularly given the small terminal spacing and high resistivity of the resistive film layers. However, this effect can be reduced by forming the desired resistor from two parallel resistors so that variations in layer alignment have less impact on the overall resistance.

[0069] Figure 7 shows a thin film resistor geometry in which at least two of the terminals have been formed in separate layers and in which the total resistance is formed by two parallel resistors, such as Figure 4 The resistors shown in , although other resistor geometries may be used.

[0070] In particular, Figure 7In the embodiment, the first terminals 702a and 702b are electrically connected to each other so that the first resistor R a is formed between the terminals 702a and 704, separated by a distance L by the resistor film 706. a ; and the second resistor R b is formed between the terminals 702b and 704, separated by a distance L by the resistor film 706. b . From R = R a R b / (R a +R b ) gives a total resistance R between the terminals 702a, 702b and 704. Therefore, the total resistance of the resistor is less sensitive to changes in the relative position of the terminals, and in particular changes in the relative position of the second terminal 704 relative to the terminals 702a and 702b.

[0071] Can be manufactured in many different ways Figure 7 resistor. For example, if the total distance between terminals 702a and 702b and the width of terminal 704 are greater than the minimum resolution of the photolithography tool, the terminals can be deposited, patterned, and etched together. Alternatively, if the spacing between all terminals is less than the minimum resolution of the photolithography tool, each of the terminals can be deposited, patterned, and etched separately to take advantage of the relatively high coverage accuracy of the photolithography mask. Alternatively, if Figure 7 If the size of the resistor is not limited by the minimum in-plane resolution of the photolithography tool used, it may be necessary to have a central terminal 704 with a width less than the minimum in-plane resolution of the photolithography mask. In this case, it may be necessary to pattern the terminal 704 in two stages so that its width is limited by the overlay error of the photolithography mask rather than the in-plane resolution of the mask. Therefore, Figure 7 The structure may require at least three separate photolithography steps.

[0072] exist Figure 8 , a vertical resistor geometry is shown, where the terminals are in the same vertical plane and the current path is in that vertical plane. Figure 3a -b to Figure 7 The geometry is different compared to , but the geometry is still based on forming the terminals from separate layers.

[0073] exist Figure 8 In FIG. 8 , a resistor is formed by a first (lower) terminal 802, a resistor body 806, and a second (upper) terminal 804, wherein these elements may be surrounded by a dielectric / insulator 808. Figure 3a -b to Figure 7 Compared with the resistor geometry shown in Figure 8The value of the resistor may be about 10 nm, thus allowing a compact but high value resistor to be formed. For example, a resistor having a thickness of about 0.005 μm may be formed. 2 The resistive film of the area forms a resistor having the same width / length ratio as the previous 20 kΩ resistor (W / L=50).

[0074] although Figure 8 The resistor geometry may allow for the formation of compact and / or low value resistors, but small geometries may be difficult to achieve and alignment errors may have a greater impact on the final value of the resistor.

[0075] Fig. 9 A further resistor geometry is provided, but in which the current path between the terminals (i.e., the current path between the interface between the terminals and the resistor body) is in both the lateral plane and in the vertical plane, which is different from the previous geometry in which the current path is substantially confined to the vertical plane or the lateral plane. More specifically, the horizontal spacing d between the terminals 902 and 904 is horiz and their vertical spacing d vert The two define a current path 910 (i.e., equivalent to Figures 1 to 8 In addition, the thickness of the insulating layer 908 provides a spacing L in the middle. vert , thus allowing fine control of the distance d vert , and may be Figure 8 The vertical geometry of d is easier to implement. This geometry can also allow the use of distance d horiz to provide most of the resistance and use distance d vert To provide a finer tuning of the resistors, finer control of the total resistance of the resistors is provided, thus allowing smaller resistance increments to be obtained than may be given by the overlay error of the photolithography tool used. Figure 3a In a manner of geometric shape, after depositing the insulating layer 908, the resistive layer 906 may be deposited and optionally patterned, followed by the deposition / patterning and etching of the materials for the first terminal 902 and the second terminal 904, respectively, so as to precisely control the distance d horiz .

[0076] Fig.10 An alternative structure is shown in which the resistive film 1006 is disposed on the lower terminal 1002 but below the second terminal 1004, and in which the distance d vert Still defined by the insulator 1008, and the length of the current path 1010 is determined by d horiz and d vert Since the order of the terminals and the resistor body is different, the material forming the resistor film 1006 will be deposited between the deposition of the material forming the first terminal and the second terminal. Fig. 9The distance d can be precisely controlled, if necessary, via the alignment of the photolithographic masks used to pattern the layers forming the first and second terminals. horiz .exist Fig.10 In a variant embodiment of the structure, the second terminal 1004 may be deposited and patterned before the resistive film 1006 is deposited.

[0077] Fig.11 Shows Figure 7 The alternative method of resistor geometry shown in FIG. 1104 allows the placement of the second terminal 1104 and also the change in the height of the insulating layer 1108 to have a reduced effect on the overall resistance of the resistor. Figure 7 In a geometrically equivalent manner, the first terminals 1102a and 1102b are electrically connected; the first resistor R a The second resistor R is formed by the first terminal 1102a, the resistance film 1106 and the second terminal 1104; b The first terminal 1102b, the resistor film 1106 and the second terminal 1104 are formed; and the total resistance between the first terminal and the second terminal is R=R a R b / (R a +R b ).

[0078] Fig.12 An alternative resistor geometry is shown, where the current path is defined by the horizontal and vertical dimensions of the resistive film. Fig.12 , the horizontal distance d between the first terminal 1202 and the terminal 1204 horiz A current path 1210 is defined through the resistive film 1206 , and a vertical distance d between the first terminal 1202 and the second terminal 1204 is defined by the thickness of the resistive film 1206 . vert .

[0079] Fig.13a -i, Fig.14a -d and Fig.16a -g provides the reference for making the above Figure 3a -b to Fig.12 An exemplary process for one or more of the various resistor geometries described. Figure 3a and Figure 3b As stated, Fig.13a -i and Fig.16a The structure shown in -g is an idealized structure, which does not show the conformal nature of certain material layers deposited during the manufacturing process, and therefore the surfaces of the various layers may not only be vertical and horizontal.

[0080] Figures 13a to 13i shows the method for making a reference Figure 3a-b describes the steps of an exemplary process for making the resistor geometry.

[0081] exist Fig.13a In the present invention, the substrate 1302 first has a resistive film 1304 deposited thereon. The resistive film may be a material that is inherently resistive and therefore does not require any further processing to achieve the desired resistivity. Alternatively, the resistive film may initially be a semiconductor layer that requires processing to achieve the desired resistive behavior at a certain point during the manufacturing process. For example, a metal oxide material may be deposited in an environment with or without the presence of oxygen using PVD techniques. Alternatively, the characteristics of the resistive film may be achieved by processing after the initial formation / deposition stage. For example, the initially deposited material may be selectively exposed to electromagnetic radiation in order to anneal it and increase its conductivity so that it provides a resistive rather than a semiconducting path. It should be understood that this selective exposure is only one method and that changes in characteristics may be achieved in a variety of ways. Further techniques suitable for use in certain embodiments to increase the conductivity of one or more bodies are described in US10204683B2. In another example, the semiconductor forming the resistive film is deposited on a doped surface that acts as a dopant source so that the semiconductor characteristics change once the semiconductor has been deposited.

[0082] exist Fig.13b In the embodiment of the present invention, photolithography has been used to pattern the photoresist. Specifically, the photoresist is applied to the resistive film 1304, and then a photomask and a light source are used to develop the photoresist to leave the patterned photoresist 1306.

[0083] exist Fig.13c 13, etching has been performed to remove the portion of the resistor film not covered by the patterned photoresist 1306 to leave the resistor body 1304a. Although the desired size of the resistor body 1304a has been described as being achieved by etching, it can also be achieved via selective deposition or other means to achieve a resistor body of a desired geometry. The etching process can be a wet etching process or a plasma etching process, however, any suitable etching process can be used.

[0084] exist Fig.13d In FIG. 1 , a conductive layer 1308 has been deposited to form a first terminal of the resistor.

[0085] exist Fig.13e , photoresist has been applied to conductive layer 1308 , and then a photomask and light source are used to develop the photoresist to leave patterned photoresist 1310 .

[0086] exist Fig.13f , etching has been performed to remove portions of the conductive layer 1308 not covered by the patterned photoresist 1310 to leave a first terminal 1308a of the resistor.

[0087] exist Figure 13g 13, a second conductive layer 1312 has been deposited to form a second terminal of the resistor. The second conductive layer may be composed of the same material as the first conductive layer 1308. Alternatively, the second conductive layer may be composed of a material different from that of the first conductive layer 1308.

[0088] exist Fig.13h , photoresist has been applied to conductive layer 1312 , and then a photomask and light source are used to develop the photoresist to leave patterned photoresist 1314 .

[0089] exist Fig.13i , etching has been performed to remove portions of the conductive layer 1312 not covered by the patterned photoresist 1314 to leave a second terminal 1312a of the resistor. Fig.13f The step of forming the first terminal 1308a using a different etching process is facilitated so that the formation of the second terminal 1312a does not adversely affect the first terminal 1308a.

[0090] like Figures 13d to 13i As shown, the first terminal 1308a and the second terminal 1312a of the resistor are formed by two different conductive material layers. Therefore, it is the alignment of the two photomasks and the patterned photoresists 1310 and 1314 that enable the spacing of the terminals to be smaller than the in-plane resolution of the photolithography process, thereby allowing the formation of smaller and more variable value resistors.

[0091] Although about Figures 13a to 13i It is not specifically described, but one or more of the different layers may be configured as an etch stop to simplify the manufacturing process.

[0092] Figures 14a to 14d Explains the Fig.13a -i. In particular, additional layers may be introduced and may be simply manufactured. For example, after depositing and patterning the resistor body 1402 and the first terminal 1404, the dielectric layer 1406 may be deposited, such as Fig.14a shown.

[0093] After the dielectric layer 1406 is deposited, the dielectric layer 1406 may be patterned and etched to form a layer 1406a that defines a spacing L between the resistor terminals, such as Fig.14b shown.

[0094] Then, a subsequent conductive material layer 1408 for forming a second terminal 1408a may be deposited on the exposed resistor body 1402 and the patterned dielectric layer 1406a, such as Fig.14c shown.

[0095] Finally, if Fig.14d As shown, the conductive material layer 1408 may be patterned and etched to form a second terminal 1408a. The patterned dielectric layer 1406a provides an etch stop.

[0096] About Figures 14a to 14d A similar approach to the method shown can be applied to make Figure 7 The resistor structure shown here produces Fig.15 More specifically, layer 1508, which may be a dielectric layer, is used to define a spacing L between terminals 1502a and 1504. a , and the distance L between terminals 1504 and 1502b b , and thus the effective length of the two resistor bodies of the resistive layer 1506 forming a parallel resistor, which reduces the sensitivity of the resulting resistor value to alignment variations between the layers forming the resistor terminals.

[0097] As for other exemplary resistor structures and manufacturing processes, Figures 14a to 14d and Fig.15 The structure and process can enable the pitch of the resistor terminals, and therefore the effective length of the resistor body, to be smaller than the in-plane resolution of the photolithography tool used, because it is the overlay error of the photolithography mask that limits the minimum reproducible pitch of the resistor terminals. Therefore, the pitch of the terminals may be smaller than the minimum in-plane feature size of the photolithography tool, and therefore smaller than the resistor / IC in which the terminals are included.

[0098] Fig.16a -g provides a manufacturing reference Figure 3a -b to Fig.12 Another exemplary method of one or more resistor geometries described herein, wherein the deposition order of materials for the first terminal, the resistor body, and the second terminal is as follows: Fig.13a -i shows the difference. In addition, for Fig.13a -i, Fig.16a The structure shown in -g is an idealized structure, which does not illustrate the possible conformal nature of certain material layers deposited during the manufacturing process, such as conductive layer 1610 forming terminal 1610a.

[0099] exist Fig.16a In FIG. 1 , a conductive layer 1604 for forming a first terminal has been deposited on a substrate or other supporting structure 1602 .

[0100] exist Fig.16b , photoresist has been applied to conductive layer 1604 , and then a photomask and light source are used to develop the photoresist to leave patterned photoresist 1606 .

[0101] exist Fig.16c , etching has been performed to remove portions of the conductive layer 1604 not covered by the patterned photoresist 1606 to leave a first terminal 1604a of the resistor.

[0102] exist Fig.16d In the embodiment of the present invention, a resistive film 1608 is deposited on the first terminal 1604a and the substrate 1602 to form the body of the resistor. The resistive film may have the desired characteristics without further processing, or may require further processing to achieve the desired resistance characteristics as described above.

[0103] exist Fig.16e In the embodiment, a second conductive layer 1610 is deposited to form a second terminal of the resistor.

[0104] exist Fig.16f , photoresist has been applied to conductive layer 1610 , and then a photomask and light source are used to develop the photoresist to leave patterned photoresist 1612 .

[0105] exist Figure 16g , etching has been performed to remove portions of the conductive layer 1610 not covered by the patterned photoresist 1612 to leave a second terminal 1610a of the resistor.

[0106] Fig.16a The order of -g and the resulting geometry may be Fig.13a -i has some advantages. For example, in Fig.16a In FIG. 1-g, the resistive film layer 1608 may only be needed as an etch stop layer because it covers the first terminal 1604a, and thus the first terminal 1604a will not be exposed during etching.

[0107] Although optical lithography has been described Fig.13a -i, Fig.14a -d and Fig.16a -g, but any suitable lithography and / or any combination of lithography and etching techniques may be used. For example, it should be understood that patterning may be performed using a variety of techniques, such as techniques involving one or more of the following: lithography, photolithography, imprinting, nanoimprinting.

[0108] Fig.13a -i, Fig.14a -d and Fig.16a -g are used to form Figure 3a -b to Fig.12 and Fig.15The deposition of various layers of any geometry shown can be performed using a technique selected from the following list, including: vapor deposition (physical, such as sputtering; chemical, such as PECVD); vacuum deposition (such as thermal evaporation or electron beam evaporation); coating (spin, dip, doctor blade, rod, spray, slot die); printing (inkjet, gravure, offset, screen, flexo); pulsed laser deposition (PLD); atomic layer deposition (ALD) coating.

[0109] also, Fig.13a -i, Fig.14a -d and Fig.16a -g is intended to illustrate the sequence of fabrication process steps and is not drawn to scale so that the shapes of layers, photoresist terminals, etc. may vary depending on the techniques used for deposition, etching, lithography, etc.

[0110] exist Figure 3a -b to Fig.16a -g, each conductive layer can be a metal (such as Au, Ti, Al, Mo, Pt, Pd, Ag, Cu, Ni, Cr, Ta, W); a metal alloy (such as MoNi, MoCr, AlSi); a transparent conductive oxide (such as ITO, IZO, AZO); a metal nitride (such as TiN); a carbon material (such as carbon black, carbon nanotubes, graphene); a conductive polymer (such as polyaniline, PEDOT:PSS); or a semiconductor material.

[0111] If a semiconductor is used to form the resistive film, the semiconductor material can be selected from the following list, including: compound semiconductors (such as GaAs, GaN, InP, CdSe, InGaAs, InGaAsSb); metal oxides (such as ZnO, SnO2, NiO, SnO, Cu2O, In2O3, LiZnO, ZnSnO, InSnO (ITO), InZnO (IZO), HfInZnO (HIZO), InGaZnO (IGZO)); metal oxynitrides (such as Z nxOyNz); inorganic semiconductors (such as amorphous, microcrystalline or nanocrystalline Si); organic semiconductors (such as CuPc, pentacene, PTCDA, methylene blue, orange G, rubrene); polymer semiconductors (such as PEDOT:PSS, POT, P3OT, P3HT, polyaniline, polycarbazole); 2D materials (such as graphene); chalcogenides (such as MoS2, GeSbTe); and perovskites (SrTiO3, CH3NH3PbCl3, H2NCHNH2PbCl3, CsSnI3). Alternatively, the resistive film can be formed of a non-semiconductor metal oxide.

[0112] It should also be understood that although various resistor geometries have been described separately, the resistors may be formed together with one or more components on a substrate. For example, the resistors may be manufactured together with transistors, as set forth in GB1912025.2, where the resistors may act as loads for the transistors. Alternatively, multiple resistors may be formed simultaneously using the described manufacturing techniques.

[0113] Throughout the description and claims of this specification, the words "comprise" and "comprising" and their variations mean "including but not limited to", and they are not intended to (and do not) exclude other parts, additional parts, components, integers or steps. Throughout the description and claims of this specification, the singular encompasses the plural, unless the context requires otherwise. In particular, where the indefinite article is used, the specification will be understood to contemplate the plural as well as the singular, unless the context requires otherwise.

[0114] Features, integers, characteristics, compounds, chemical moieties or groups described in conjunction with a particular aspect, embodiment or example of the invention will be understood to be applicable to any other aspect, embodiment or example described herein unless they are incompatible therewith. All features disclosed in this specification (including any accompanying claims, abstracts and drawings), and / or all steps of any method or process so disclosed may be combined in any combination, except combinations in which at least some of such features and / or steps are mutually exclusive. The invention is not limited to the details of any foregoing embodiments. The invention extends to any novel one or any novel combination of the features disclosed in this specification (including any accompanying claims, abstracts and drawings), or to any novel one or any novel combination of the steps of any method or process so disclosed.

Claims

1. A method for manufacturing a thin film resistor on a support structure, the thin film resistor comprising a first terminal, a second terminal and a resistor body, the resistor body providing a resistive current path between the first terminal and the second terminal, the method comprising: depositing a first layer of conductive material onto at least one of the support structure and the resistor body, applying a first photolithography process to the first layer, and etching the first layer to form the first terminal; and depositing a second layer of conductive material onto at least one of the support structure and the resistor body, applying a second photolithography process to the second layer, and etching the second layer to form the second terminal, The first photolithography process is different from the second photolithography process, and a lateral spacing between the first terminal and the second terminal is smaller than a minimum feature size in a plane of the first photolithography process and the second photolithography process. wherein the lateral spacing between the first terminal and the second terminal is non-zero, and The first terminal and the second terminal are formed by respective independent thin film layers.

2. The method according to claim 1, wherein: The photolithography process is an optical photolithography process.

3. The method according to claim 1, wherein: At least a portion of the second terminal is located outside of a transverse plane defined by the vertical extent of the first terminal.

4. The method according to claim 1, wherein: The resistor body is non-planar.

5. The method according to claim 1, wherein: The resistor body includes a first transverse plane region and a second transverse plane region, and a third vertical plane region that is substantially perpendicular to the first transverse plane region and the second transverse plane region and connects the first transverse plane region and the second transverse plane region, and wherein the first transverse plane region and the second transverse plane region are separated by a vertical distance in a direction parallel to the third vertical plane region.

6. The method according to claim 5, wherein: The first lateral planar region of the resistor laterally overlaps at least a portion of the first terminal.

7. The method according to claim 5, wherein: The second lateral planar region of the resistor laterally overlaps at least a portion of the second terminal.

8. The method according to claim 5, wherein: The second terminal is located completely outside of a transverse plane defined by the vertical extent of the first terminal.

9. The method according to claim 1, wherein: The resistor includes a third terminal electrically connected to the first terminal, and wherein the resistor body provides a resistance path between the second terminal and the third terminal, the resistance path being different from the resistance path between the first terminal and the second terminal, and wherein the method includes forming the third terminal at a time separate from at least one of the first terminal and the second terminal.

10. The method according to claim 9, wherein: A distance between the second terminal and the third terminal is smaller than a minimum feature size in a plane of the first photolithography process and the second photolithography process.

11. The method according to claim 9, wherein: The third terminal is at least partially located outside of a transverse plane defined by a vertical extent of the first terminal and a transverse plane defined by a vertical extent of the second terminal.

12. The method according to claim 1, wherein: The lateral spacing between any two terminals is less than 500nm.

13. The method of claim 1, further comprising depositing a layer of resistive material onto at least one of the support structure, the first terminal, and the second terminal to form the resistive body.

14. The method according to claim 1, wherein: The first terminal and the second terminal do not vertically overlap.

15. The method according to claim 1, wherein: Applying the first and second photolithography processes each includes depositing an unillustrated photoresist layer onto the corresponding conductive material layer, applying a photolithography process to the photoresist layer, and developing the photoresist layer to produce a patterned photoresist layer.

16. A thin film resistor manufactured by the method of any one of claims 1 to 15, the thin film resistor comprising a first terminal formed by a first thin film layer of conductive material, a second terminal formed by a second thin film layer of conductive material, and a resistor body formed by a thin film layer of resistive material, the resistor body providing a resistive current path between the first terminal and the second terminal, wherein: The lateral spacing between the first terminal and the second terminal is less than the minimum in-plane lateral feature size of the thin film resistor, and wherein the lateral spacing between the first terminal and the second terminal is non-zero, and wherein the first terminal and the second terminal are in respective independent deposition layers.

17. The thin film resistor according to claim 16, wherein: A lateral distance between the first terminal and the second terminal is at least one order of magnitude smaller than a minimum feature size in a plane of the first photolithography process and the second photolithography process.

18. The thin film resistor according to claim 16, wherein The thin film resistor includes a third terminal electrically connected to the first terminal, and wherein the resistor body provides a resistance path between the second terminal and the third terminal that is different from the resistance path between the first terminal and the second terminal.

19. The thin film resistor according to claim 18, wherein: The third terminal is at least partially located outside of a transverse plane defined by a vertical extent of the first terminal and a transverse plane defined by a vertical extent of the second terminal.

20. The thin film resistor according to claim 16, wherein The lateral distance between any two of the terminals is less than 500 nm.

21. The thin film resistor according to claim 16, wherein The first terminal and the second terminal do not vertically overlap.

22. A thin film integrated circuit comprising the thin film resistor according to any one of claims 16 to 21.

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