Method for forming a high resistivity processing support for a composite substrate

Abstract

The present invention relates to a method of forming a high resistivity processing substrate for a composite substrate, the method comprising: - providing a base substrate made of silicon; - exposing the base substrate to a carbon single precursor at a pressure below atmospheric pressure to form a polycrystalline silicon carbide layer of at least 10 nm on the surface of the base substrate; and then - growing a polycrystalline charge trapping layer on the carbon-containing layer.

Description

BACKGROUND OF THE INVENTION

[0002] WO2017144821 describes a high resistivity processed substrate for a composite substrate, which includes a charge trapping layer disposed on a base substrate. For example, the composite substrate may be a silicon-on-insulator substrate, which includes a silicon thin film transferred onto the processed substrate.

[0003] In one embodiment described in the above-mentioned document, the charge trapping layer is made of an intermediate layer and a polycrystalline main layer. The intermediate layer is composed of a silicon and carbon alloy (or carbon) and is directly disposed on the base substrate. The main layer is disposed on and in contact with the intermediate layer.

[0004] The multi-layer structure of the charge trapping layer enables prevention of the recrystallization phenomenon of the main polycrystalline layer when the substrate is exposed to high temperatures, such as during its manufacture or during the manufacture of integrated devices on the composite substrate. When the trapping layer recrystallizes, even partially, the RF (radio frequency) performance of the substrate and the integrated devices to be formed thereon will be affected, which is of course undesirable.

[0005] To prepare the high resistivity processed substrate, the document proposes placing the base substrate in a conventional deposition chamber. A first precursor gas stream passes through the chamber. The first precursor gas may be a silicon-containing precursor, such as SiH4, to grow the main polycrystalline layer. A second precursor gas containing carbon is introduced into the chamber to form the intermediate layer. Such precursor gases may consist of methane (CH4), ethane (C2H6), propane (C3H8), acetylene (C2H2), ethylene (C2H4)...

[0006] When two precursor gases flow into the chamber simultaneously to grow the intermediate silicon and carbon alloy layer, there is a risk of forming deposits on the chamber walls and the susceptor on which the base substrate is located. Such deposits require extensive cleaning of the chamber, for example, by etching, which is both time-consuming and reduces the manufacturing yield. Such problems are recorded, for example, in the publication WO2019002376. Moreover, deposits of silicon and carbon substances may generate particles, which may be transported onto the surface of the base substrate or the processed substrate and render the substrate unsuitable for further use.

[0007] It has also been observed that doping substances (such as boron) may be incorporated into the intermediate layer and / or the main layer, especially when the base substrate is a standard CZ silicon substrate (i.e., not designed to exhibit high resistivity characteristics). Such a CZ silicon substrate includes some residual concentrations of boron and other dopants, which may migrate towards the surface of the base wafer during the growth of the charge trapping layer. When present in the charge trapping layer, the dopants reduce the resistivity of the layer and the overall RF performance of the processed substrate.

[0008] SUBJECT MATTER OF THE INVENTION

[0009] The present invention aims to overcome all or part of the above-mentioned drawbacks. In particular, the present invention aims to provide a method for forming a processed substrate that exhibits high resistivity characteristics and is easy to manufacture. Summary of the Invention

[0010] To achieve this purpose, the subject matter of the present invention proposes a method for forming a high-resistivity processed substrate for a composite substrate, the method comprising the following steps:

[0011] - Providing a base substrate made of single-crystalline silicon;

[0012] - Exposing the base substrate to a carbon single precursor under a pressure below atmospheric pressure to form a polycrystalline silicon carbide layer of at least 10 nm on the surface of the base substrate; and then

[0013] - Growing a polycrystalline charge trapping layer on the polycrystalline silicon carbide layer.

[0014] According to other advantageous and non-limiting features of the present invention, individually or in any technically feasible combination:

[0015] - The base substrate has a resistivity greater than 1000 ohm.cm;

[0016] - The base substrate has a resistivity less than 1000 ohm.cm;

[0017] - The method further comprises: directly forming an intrinsic silicon epitaxial layer on the base substrate before exposing the base substrate to the carbon single precursor;

[0018] - The charge trapping layer has a thickness greater than 5 microns or 10 microns;

[0019] - The charge trapping layer is made of polycrystalline silicon;

[0020] - The carbon single precursor has a temperature between 700 °C and 1200 °C;

[0021] - The method further comprises: exposing the base substrate to a reducing atmosphere at a temperature of at least 900 °C before exposing the base substrate to the carbon single precursor to remove the native oxide layer from the base substrate;

[0022] - The polycrystalline silicon carbide layer is stoichiometric.

[0023] According to another aspect, the present invention also relates to a high-resistivity processed substrate for a composite substrate, the high-resistivity processed substrate comprising:

[0024] - A base substrate made of single-crystalline silicon;

[0025] - A polycrystalline silicon carbide layer having a thickness of at least 10 nm directly on the surface of the base substrate;

[0026] - A polycrystalline charge trapping layer on the polycrystalline silicon carbide layer.

[0027] Optionally, the polycrystalline silicon carbide layer may include dopants at a concentration less than 10^14 at / cm^3, and the high resistivity treated substrate may further include an intrinsic silicon epitaxial layer in contact with the base substrate and the polycrystalline silicon carbide layer. The polycrystalline silicon carbide layer is stoichiometric.

[0028] Finally, the present invention also relates to a composite substrate comprising the high resistivity treated substrate as described above and a thin film made of a crystalline material on top of the treated substrate.

[0029] Advantageously, the composite substrate further includes a dielectric layer disposed between the treated substrate and the thin film. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other features and advantages of the present invention will become apparent from the following detailed description of the invention with reference to the accompanying drawings, in which:

[0031] Figure 1 Schematically shows a treated substrate for a semiconductor structure according to the present invention;

[0032] Figure 2 Schematically shows a composite substrate using the treated substrate according to the present invention;

[0033] Figure 3 and Figure 4 Are respectively the SRP measurement results of two treated substrates. DETAILED DESCRIPTION

[0034] Figure 1 Schematically shows a high resistivity treated support for a composite substrate according to an embodiment of the present disclosure. The treated substrate 1 may be in the form of a circular wafer having a standardized size, for example, a diameter of 200 mm or 300 mm or even 450 mm. However, the present invention is in no way limited to these sizes or this form.

[0035] The treated substrate 1 includes a single crystal silicon base substrate 3 typically several hundred microns thick. The silicon base substrate presents a smooth surface with a roughness below 0.5 nm RMS. Preferably, the silicon base substrate has a high resistivity greater than 1000 ohm.cm, more preferably greater than 3000 ohm.cm. In this way, the density of charges, holes or electrons that are easily mobile in the base substrate is limited. For example, the treated substrate may be a CZ substrate with a low interstitial oxygen content, and it is well known that the resistivity of such a CZ substrate may be greater than 500 ohm.cm or greater than 1000 ohm.cm.

[0036] However, the present invention is not limited to silicon-based substrates having such a resistivity, and when the base substrate has a more common resistivity (on the order of a few hundred ohm.cm or less, e.g., less than 1000 ohm.cm or less than 500 ohm.cm or even less than or equal to 10 ohm.cm), the present invention also obtains advantages in terms of RF performance.

[0037] When the base substrate 3 has a more common resistivity of less than 1000 ohm.cm or 500 ohm.cm, it may be advantageous to provide a silicon intrinsic epitaxial layer directly on top of the base substrate 3. "Intrinsic" means that the layer is not deliberately doped. In this case, the silicon epitaxial layer is grown to exhibit a resistivity higher than 2000 ohm.cm, preferably between 2000 ohm.cm and 20000 ohm.cm. The thickness of the epitaxial layer 2 is typically in the range of 2 to 100 microns. This method is particularly advantageous when the base substrate is made of silicon, as it provides a substrate with an appropriate surface resistivity without the cost and availability drawbacks associated with a base substrate that exhibits a high resistivity across its total thickness.

[0038] Processing the substrate 1 further includes a polycrystalline charge trapping layer 2 on the base substrate 3. The function of the charge trapping layer is to trap any charge carriers that may be present in the processing substrate 1 and limit their migration.

[0039] For reasons of availability and cost, the charge trapping layer 2 is preferably made of polycrystalline silicon. However, it may be formed of another semiconductor and polycrystalline material, or include portions made of another semiconductor and polycrystalline material. This may be the case for example with germanium, silicon germanium, etc.

[0040] In all cases, the polycrystalline charge trapping layer 2 has a high resistivity, typically higher than 3000 ohm.cm. For this purpose, the layer is not deliberately doped, that is, the dopant concentration of the layer is less than 10E14 atoms per cubic centimeter. The polycrystalline charge trapping layer may be nitrogen- or carbon-rich in order to improve its resistivity characteristics.

[0041] The high resistivity processing substrate 1 further includes a polycrystalline silicon carbide layer 4 at least 10 nm thick inserted between the base substrate 3 and the polycrystalline charge trapping layer 2. Such a silicon carbide thickness forms an effective barrier against the diffusion of dopants (e.g., boron) that may be contained in the base substrate 3. The layer typically exhibits a resistivity higher than 1000 ohm.cm. "Silicon carbide layer" means that the silicon and carbon species forming the layer are present in the layer in a stoichiometric or near-stoichiometric ratio.

[0042] Thus, the highly resistive treated substrate 1 is composed of a base substrate 3 (optionally including a top silicon intrinsic epitaxial layer), a polycrystalline silicon carbide layer 4 in direct contact with the base substrate 3, and a polycrystalline charge trapping layer 2 on and in direct contact with the polycrystalline silicon carbide layer 4. In this particular embodiment, no additional layers are provided, especially an electrically insulating layer in or under the polycrystalline charge trapping layer 2, as this may change the nature of the proposed structure.

[0043] The thickness of the polycrystalline charge trapping layer 2 can be greater than 1 micron, or greater than 5 microns, or even greater than 10 microns. Regardless of whether its thickness is greater or less than these limits, the charge trapping layer 2 can be composed of grains with sizes between 100 and 1000 nanometers.

[0044] Finally, as Figure 1 shown, the treated substrate 1 can optionally have a dielectric layer 5 directly on the trapping layer 2. This dielectric layer 5 (which is optional) can facilitate the assembly of the treated substrate 1 with another substrate. The dielectric layer 5 can be made of, for example, silicon oxide or silicon nitride.

[0045] For completeness, Figure 2 a composite substrate including the treated substrate 1 according to the present disclosure is shown. It can be clearly seen from this figure that the composite substrate includes a thin film 6 preferably made of a crystalline material on top of the treated substrate 1. By way of example but not limitation, the thin film 6 can be made of a semiconductor material such as silicon, or a piezoelectric material such as lithium tantalate (LiTaO3), lithium niobate (LiNbO3), lithium aluminate (LiAlO3), barium titanate (BaTiO3), lead zirconate titanate (PbZrTiO3), potassium niobate (KNbO3), barium zirconate (BaZrO3), calcium titanate (CaTiO3), lead titanate (PbTiO3), potassium tantalate (KTaO3), etc.

[0046] Figure 2 The structure of can be formed by the treated substrate 1 in various ways, but advantageously, this formation includes the step of transferring the thin film 6 onto the treated substrate 1. As is well known, this transfer is typically carried out by assembling the face of the donor substrate on the treated substrate 1. This can be performed in the presence or absence of the dielectric layer 5.

[0047] When the film 6 is made of a piezoelectric material, its crystal orientation is selected according to the intended application. For a SAW filter made of LiTaO3 material, an orientation between 30° and 60° XY or between 40° and 50° XY is typically selected. For LiNbO3 material, an orientation of about 128° XY is typically selected. However, the present invention is in no way limited to a specific crystal orientation of the piezoelectric film. The donor substrate can be taken from a ferroelectric material ingot such that the donor substrate presents a selected crystal orientation. Alternatively, the donor substrate can include a thick ferroelectric material layer assembled to a support substrate.

[0048] After this assembly step, the thickness of the donor substrate is reduced in order to form the film 6. This reduction step can be carried out by mechanical or chemical thinning. It can also be carried out by breaking, for example, according to the principle of the Smart Cut TM technique at a fragile region previously introduced into the donor substrate.

[0049] The step of finishing the film 6 (for example, a polishing step, a heat treatment in a reducing or neutral atmosphere, or a sacrificial oxidation) can be linked to the step of reducing the thickness.

[0050] When the donor substrate is a simple substrate (i.e., does not include any integrated devices), a composite substrate of the "semiconductor-on-insulator" type including the processing substrate 1 of the present invention is formed, where the film 6 is a blank semiconductor layer. Then, this composite substrate can be used to form integrated devices.

[0051] When the donor substrate has been pre-treated to form integrated devices on its surface, at the end of the method, a film 6 including these devices can be obtained.

[0052] The manufacture of the processing substrate 1 of the present disclosure is particularly simple and can be achieved using industrial standard deposition equipment.

[0053] A base substrate 3 is provided and placed in a conventional deposition chamber. As is well known, the base substrate 3 can be prepared before deposition, for example, in order to eliminate the native oxide layer from its surface. This can be carried out by exposing the base substrate in the chamber to a reducing atmosphere at a temperature of at least 900 °C. However, this step is not mandatory and the oxide can be retained. In fact, from 1 nm to 2 nm is already thin enough without creating any insulating effect (conduction through the layer due to tunneling effect), as long as future heat treatments do not cause it to completely disappear by dissolution.

[0054] Then, the flat surface of the silicon-based substrate 3 is exposed to a single carbon precursor gas at a pressure below atmospheric pressure (e.g., between 0.01 Torr and 760 Torr). The carbon precursor gas can consist of methane (CH4), ethane (C2H6), propane (C3H8), acetylene (C2H2), ethylene (C2H4),... The precursor gas can flow into the chamber (or be heated into the chamber) at a temperature between 700 °C and 1200 °C, such that carbon species nucleate onto the surface of the base substrate. A carrier gas flow (e.g., H2) can also be introduced into the chamber simultaneously, but no other precursor gases other than the carbon precursor gas flow over the substrate 3. By avoiding the reaction of carbon species with other species of a second precursor, the deposition of carbon compounds on the chamber walls is limited, and the generation of particles is avoided.

[0055] Surprisingly, it has been observed that when this deposition step is carried out at a reduced carbon partial pressure (i.e., below atmospheric pressure), this nucleation of carbon species occurs on isolated islands on the surface. Then, silicon atoms from the base wafer diffuse into the carbon islands, forming stoichiometric or near-stoichiometric 3C / 6H and 4H-type silicon carbide islands. These islands merge to form a relatively thick polycrystalline silicon carbide layer having a stoichiometric or near-stoichiometric ratio. When the flow of the carbon precursor gas is maintained for a few minutes, the thickness of the polycrystalline layer grows to a few nanometers.

[0056] In a specific example, a carbon precursor gas of C3H8 mixed with H2 in a ratio of 180 sccm / 5 slm is introduced and flows in the chamber at a pressure of 10 Torr for 5 minutes and is heated at 1000 °C. Then, a polycrystalline layer 4 of silicon carbide with a thickness of 10 nm is observed on the surface of the silicon-based substrate 3.

[0057] When the deposition step is carried out at atmospheric pressure or above atmospheric pressure, as described, for example, in WO2019002376 cited in the introduction, a completely different phenomenon occurs on the surface of the base substrate 3. Carbon species nucleate on the surface of the base wafer at a high density and prevent silicon atoms from diffusing from this surface. Then, a crystalline or partially crystalline carbon layer slowly grows on the surface in alignment with the silicon lattice in a 3C structure. Such a layer typically exhibits a thickness of 2 nm after 10 minutes of deposition.

[0058] Therefore, flowing a single carbon precursor gas over the substrate 3 under reduced pressure seems to be a very effective way to form a relatively thick (greater than or equal to 10 nm) polycrystalline silicon carbide layer. Such a layer is advantageous because due to its polycrystalline nature, it allows the subsequent preparation and maintenance of the polycrystalline nature of the charge trapping layer grown on top of it. Moreover, a relatively thick polycrystalline silicon carbide layer is formed quite rapidly and constitutes an effective diffusion barrier to prevent dopant species from migrating from the base wafer 3 to the charge trapping layer.

[0059] In addition, it has been observed that this growth method under reduced pressure incorporates very little dopant (such as boron) into the silicon carbide intermediate layer. Measurements indicate that the boron concentration in this silicon carbide layer is below 10^14 at / cm^3. It is believed that the dopant substance (which may be present on the surface of the base wafer or incorporated into the base wafer) diffuses out of the silicon carbide layer during the formation of the silicon carbide layer and is discharged from the deposition chamber together with the precursor and the transport gas.

[0060] After the silicon carbide polycrystalline layer has been grown on the base substrate, the chamber passes a second precursor gas stream (e.g., SiH4) through the chamber at a temperature of about 1000 °C to form a polycrystalline charge trapping layer in a conventional manner. The circulation duration of the second precursor gas determines the thickness of the polycrystalline layer 2, and this duration can be selected such that layers of 5 μm, 10 μm or more are grown.

[0061] Advantageously, the silicon carbide polycrystalline layer and the polycrystalline charge trapping layer are formed in situ in the same deposition chamber. This avoids contamination of the stack by dopants or contaminants from the atmosphere and maintains the high resistivity characteristics of the processed substrate 1.

[0062] For completeness, the processed substrate 1 may be provided with a conventionally deposited dielectric layer 5, e.g., silicon oxide or silicon nitride. The insulator 4 may also be polished.

[0063] When the base substrate 3 is provided with a silicon intrinsic epitaxial layer, the formation of this layer can be achieved in situ with the formation of the silicon carbide polycrystalline layer. This method avoids breaking the vacuum in the deposition chamber, thereby improving the original processing time and the overall method efficiency. It also prevents the processed substrate from capturing contaminants from the ambient atmosphere, such as particles or boron residues that may be present in a clean room. These two layers can also be formed in separate deposition chambers, but these chambers share a common transfer module. In addition to the advantages already mentioned, this method of using separate chambers allows for better management of the required chamber cleaning. Obviously, these two layers can also be formed in completely separate chambers.

[0064] To illustrate the benefits of this manufacturing method, Figure 3 shows the SRP measurement results (spread resistance profile) along the depth of a processed wafer according to the present invention. In this particular measurement, the base wafer is a high resistivity silicon wafer (3500 ohm.cm) on which a 10 nm thick silicon carbide polycrystalline layer and a 2 μm thick silicon polycrystalline charge trapping layer are successively grown. As can be seen from this figure, the resistivity of the layer grown on top of the base substrate is greater than 3500 ohm.cm for its entire depth profile.

[0065] Figure 4SRP measurements are shown for a processed wafer made from a base substrate that exhibits a resistivity of 4000 ohm.cm in this case. A 2 nm carbon layer and a 2 micron thick polycrystalline silicon charge trapping layer are successively grown on top of this substrate. The carbon layer is formed at atmospheric pressure and is thus mostly crystalline. This time it is very apparent from Figure 4 that the resistivity of the layer grown on top of the base substrate reaches low values (less than 10 ohm.cm) at and near the interface with the base substrate. Such a low resistivity forms a conductive plane in the processed substrate, which can affect the performance of the device.

[0066] This comparative example clearly shows the advantage of exposing the base substrate to a carbon single precursor at a pressure below atmospheric pressure.

[0067] Of course, the present invention is not limited to the described embodiments, and variations of the implementation can be made without exceeding the scope of the present invention defined by the claims.

Claims

1. A method of forming a high resistivity processed substrate (1) for a composite substrate, the method comprising the steps of: - providing a base substrate (3) made of single crystal silicon; - exposing the base substrate (3) to a carbon single precursor under a pressure below atmospheric pressure to form a polycrystalline silicon carbide layer (4) of at least 10 nm on the surface of the base substrate; and then - growing a polycrystalline charge trapping layer (2) on the polycrystalline silicon carbide layer.

2. The method according to claim 1, wherein, The base substrate (3) has a resistivity greater than 1000 ohm.cm.

3. The method according to claim 1, wherein The base substrate (3) has a resistivity less than 1000 ohm.cm.

4. The method according to claim 3, wherein, The method further comprises the step of: directly forming a silicon intrinsic epitaxial layer on the base substrate (3) before exposing the base substrate (3) to the carbon single precursor.

5. The method according to any one of claims 1 to 4, wherein The polycrystalline charge trapping layer (2) has a thickness greater than 5 microns or 10 microns.

6. The method according to any one of claims 1 to 4, wherein, The polycrystalline charge trapping layer (2) is made of polycrystalline silicon.

7. The method according to any one of claims 1 to 4, wherein The carbon single precursor has a temperature between 700 °C and 1200 °C.

8. The method according to any one of claims 1 to 4, the method further comprising the steps of: Before exposing the base substrate (3) to the carbon single precursor, the base substrate is exposed to a reducing atmosphere at a temperature of at least 900 °C to remove the native oxide layer from the base substrate (3).

9. The method according to any one of claims 1 to 4, wherein The polycrystalline silicon carbide layer is stoichiometric.

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