Semiconductor wafer and method for manufacturing the same

Abstract

The manufacturing method of the semiconductor chip involved in the invention of the present application comprises: a first step of forming a gallium nitride growth layer divided into a plurality of small blocks on the upper surface of a silicon substrate; and a second step of filling the spaces between the plurality of small blocks with an insulating film, wherein the insulating film applies stress to the silicon substrate in the opposite direction to the stress applied by the gallium nitride growth layer to the silicon substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor wafer and a method for manufacturing the same. Background Art

[0002] Patent Document 1 discloses a method for growing a semiconductor layer having a lattice constant different from that of a substrate on a sapphire or silicon carbide substrate. In this method, a layer having an opening for selectively growing a semiconductor layer is formed at a predetermined position on the substrate, and a predetermined position of the substrate is exposed through the opening. Next, a semiconductor layer is selectively heteroepitaxially grown on the surface of the substrate exposed through the opening.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 10-135140

[0004] When growing gallium nitride on a silicon substrate, there is a possibility that the substrate warps due to the difference in lattice constants between the two. In the method of Patent Document 1, the substrate warping can be reduced by dividing the semiconductor layer. However, in the method of Patent Document 1, the warping may not be fully suppressed. As a result, subsequent processes such as the exposure process may become difficult. Summary of the invention

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor wafer capable of suppressing warping of a substrate and a method for manufacturing the same.

[0006] The method for manufacturing a semiconductor chip involved in the invention of the present application comprises: a first step of forming a gallium nitride growth layer divided into a plurality of small blocks on the upper surface of a silicon substrate; and a second step of filling the spaces between the plurality of small blocks with an insulating film, wherein the insulating film applies stress to the silicon substrate in a direction opposite to the stress applied by the gallium nitride growth layer to the silicon substrate.

[0007] The semiconductor chip involved in the invention of the present application comprises: a silicon substrate; a gallium nitride growth layer, which is arranged on the upper surface of the silicon substrate and is divided into a plurality of small blocks; and an insulating layer, which is arranged on the upper surface of the silicon substrate and fills the space between the plurality of small blocks, and the insulating layer applies stress to the silicon substrate in the opposite direction to the stress applied to the silicon substrate by the gallium nitride growth layer.

[0008] In the method for manufacturing a semiconductor wafer according to the present invention, the insulating film can suppress the warping of the silicon substrate.

[0009] In the semiconductor wafer according to the present invention, the insulating layer can suppress the warping of the silicon substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a cross-sectional view of the semiconductor wafer according to the first embodiment.

[0011] Figure 2 It is a plan view showing a state where a thermal oxide film is formed on a silicon substrate.

[0012] Figure 3 It is a top view showing a state where the thermal oxide film has been removed.

[0013] Figure 4 It is a cross-sectional view showing a state where the thermal oxide film has been removed.

[0014] Figure 5 It is a cross-sectional view showing a state where an insulating film is formed.

[0015] Figure 6 This is a cross-sectional view of a semiconductor wafer according to the second embodiment.

[0016] Figure 7 It is a cross-sectional view for explaining the method for manufacturing a semiconductor wafer according to the second embodiment.

[0017] Figure 8 It is a cross-sectional view showing a state in which the upper surfaces of a plurality of small blocks are exposed.

[0018] Fig. 9 This is a cross-sectional view of a semiconductor wafer according to the third embodiment.

[0019] Fig.10 This is a cross-sectional view of a semiconductor wafer according to a fourth embodiment. DETAILED DESCRIPTION

[0020] A semiconductor wafer and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to the accompanying drawings. The same or corresponding components may be denoted by the same reference numerals to omit repeated description.

[0021] Implementation Method 1

[0022] Figure 1 1 is a cross-sectional view of a semiconductor wafer 100 according to Embodiment 1. The semiconductor wafer 100 includes a silicon substrate 10. A gallium nitride growth layer 12 is provided on the upper surface of the silicon substrate 10. The gallium nitride growth layer 12 is divided into a plurality of small blocks 13. The plurality of small blocks 13 are separated from each other. The gallium nitride growth layer 12 may include, for example, In 1－x－y Ga x Al y A multilayer film of N layers. Here, 0≤x≤1, 0≤y≤1.

[0023] An insulating film 14 is provided on the upper surface of the silicon substrate 10. The insulating film 14 fills the gaps between the plurality of small blocks 13. The thickness of the insulating film 14 is, for example, 1 μm or more and is less than the thickness of the gallium nitride growth layer 12. The insulating film 14 is, for example, a silicon nitride film. The insulating film 14 is connected from one end of the silicon substrate 10 to the other end.

[0024] Next, a method for manufacturing the semiconductor wafer 100 will be described. First, a thermal oxide film 16 is formed on the upper surface of the silicon substrate 10 . Figure 2 1 is a top view showing a state where a thermal oxide film 16 is formed on a silicon substrate 10. A grid-shaped pattern is formed on the thermal oxide film 16 by photolithography. Thus, a grid-shaped oxide film is formed. The upper surface of the silicon substrate 10 is divided into a plurality of regions 11 by the thermal oxide film 16.

[0025] Next, a gallium nitride growth layer 12 is formed on the silicon substrate 10. The gallium nitride growth layer 12 is formed, for example, by an organic metal vapor phase epitaxy method or a molecular beam epitaxy method. Thus, the gallium nitride growth layer 12 is formed on the portion of the silicon substrate 10 that is not covered by the thermal oxide film 16. That is, a plurality of small blocks 13 are grown in each of the plurality of regions 11. The gallium nitride growth layer 12 is configured to include a buffer layer for epitaxial growth of gallium nitride.

[0026] Thereafter, the thermal oxide film 16 is removed. For example, hydrofluoric acid is used for the removal. Figure 3 It is a plan view showing a state where the thermal oxide film 16 has been removed. Figure 4 1 is a cross-sectional view showing a state where the thermal oxide film 16 has been removed. The above is the first step of forming the gallium nitride growth layer 12 divided into a plurality of small blocks 13 on the upper surface of the silicon substrate 10 .

[0027] Next, a second step of filling spaces between the plurality of small blocks 13 with the insulating film 14 is performed. Figure 5 1 is a cross-sectional view showing a state where the insulating film 14 is formed. The insulating film 14 is deposited on the silicon substrate 10 by, for example, CVD (Chemical Vapor Deposition). The insulating film 14 is formed so as to be in close contact with the silicon substrate 10 .

[0028] The insulating film 14 applies stress to the silicon substrate 10 in the opposite direction to the stress applied to the silicon substrate 10 by the gallium nitride growth layer 12. The insulating film 14 is formed of a material that applies stress to the silicon substrate 10 in the opposite direction to the gallium nitride growth layer 12. The insulating film 14 is, for example, a silicon nitride film or a silicon oxide film. Preferably, the insulating film 14 is formed of a material that applies a large stress to the silicon substrate 10.

[0029] Generally, a silicon nitride film can generate tensile stress or compressive stress of about several GPa depending on the film forming conditions. Although it depends on the manufacturing device, a film stress of about 300 MPa can be obtained in a silicon nitride film formed by plasma CVD, and a film stress of about 1 GPa can be obtained in a silicon nitride film formed by thermal CVD. In addition, the insulating film 14 can also be formed by ECR (Electron Cyclotron Resonance) sputtering. In a silicon nitride film formed by ECR sputtering, a film stress of about 3 GPa can be obtained.

[0030] For example, SiH4 and NH3 may be used as process gases to form the insulating film 14 by plasma CVD. In this case, by changing the ratio of SiH4 to NH3 between 0.5 and 2, the film stress can be changed to a tensile stress of about 100 MPa to a compressive stress of about 300 MPa. Therefore, for example, by setting the ratio of SiH4 to NH3 to 0.5 or less, a tensile stress can be applied from the insulating film 14 to the silicon substrate 10. In addition, by setting the ratio of SiH4 to NH3 to 2 or more, a tensile stress can be applied from the insulating film 14 to the silicon substrate 10.

[0031] Next, if Figure 1 As shown, the insulating film 14 is removed until the gallium nitride growth layer 12 is exposed. The insulating film 14 is removed by etching such as dry etching. At this time, the thickness of the insulating film 14 is adjusted by adjusting the etching time. Generally, the thicker the insulating film 14, the greater the stress applied to the silicon substrate 10. Therefore, by adjusting the etching time, the magnitude of the stress applied by the insulating film 14 to the silicon substrate 10 can be adjusted.

[0032] In addition, the warpage that can be corrected increases in proportion to the thickness of the insulating film 14. The thickness of the insulating film 14 may be determined by the amount of warpage of the silicon substrate 10 in a state where the gallium nitride growth layer 12 is formed and before the insulating film 14 is formed. The thickness of the insulating film 14 may be set so that the silicon substrate 10 becomes flat in a state where the insulating film 14 is formed.

[0033] Generally, the thickness of the insulating film required to alleviate the warping of the substrate depends on the size of the area between the gallium nitride growth layers or the size of the film stress of the insulating film. For example, if an insulating film 14 with a film stress of 1 GPa is deposited with a thickness of 1 μm, the warping of the silicon substrate 10 of about several μm to 10 μm can be corrected compared to the case where the insulating film 14 is not provided. Here, the width of the insulating film 14 sandwiched between adjacent small blocks 13 is set to 1 / 10 relative to the width of the small block 13. In addition, the thickness of the silicon substrate 10 is set to 625 μm. Based on the above, by, for example, setting the thickness of the insulating film 14 to more than 1 μm, the warping of the silicon substrate 10 can be fully suppressed.

[0034] According to the above, the insulating film 14 is formed. Figure 3 As shown, the insulating film 14 is formed in the portion where the gallium nitride growth layer 12 is removed and the silicon substrate 10 is exposed in a lattice shape. That is, the insulating film 14 is formed in a lattice shape.

[0035] Next, electrodes and the like are formed on the surface of the gallium nitride growth layer 12 exposed from the insulating film 14. Thus, a device is formed.

[0036] Generally, heterostructures can be fabricated by using nitride-based semiconductor materials such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), and aluminum nitride (AlN). Therefore, these materials are sometimes used in the manufacture of high-frequency devices, optical devices, or power devices.

[0037] Nitride-based semiconductor structures are usually made by epitaxial growth on silicon carbide, sapphire or silicon substrates. In particular, silicon substrates are cheaper than silicon carbide, etc. Therefore, material costs can be reduced.

[0038] Here, generally, when gallium nitride is grown on a silicon substrate, the substrate may be warped, which may cause problems in the process such as conveyance or exposure.

[0039] The lattice constant of silicon is 0.5431nm. Therefore, the atomic spacing on the (111) plane of silicon is 0.5431 / √2=0.3840nm. In contrast, the lattice constant of gallium nitride is 0.3819nm. The lattice spacing of gallium nitride is narrower than that of silicon. Therefore, the silicon substrate is subjected to compressive stress from the gallium nitride heteroepitaxially grown on the (111) plane.

[0040] In addition, the linear expansion coefficient of silicon is 2.6×10 －6 K －1 In contrast, the linear expansion coefficient of gallium nitride is 5.6×10 －6 K －1 Generally, gallium nitride is grown at a high temperature of 800°C or more. Therefore, when the growth temperature is lowered to room temperature, gallium nitride shrinks more than silicon. Therefore, the silicon substrate receives compressive stress from the gallium nitride growth layer.

[0041] As described above, when a gallium nitride growth layer is formed on a silicon substrate, warping occurs so that the gallium nitride growth layer is located inside. In fact, the direction of the warping varies depending on the conditions of epitaxial growth or the configuration of the buffer layer.

[0042] In addition, it is conceivable to reduce substrate warpage by dividing the gallium nitride growth layer into small blocks to disperse the stress. However, in such a method, it is usually difficult to completely eliminate the warpage of the substrate. For example, in a 4-inch substrate, there may be a wafer warpage of about several μm to 10 μm. Such warpage is particularly problematic in gate exposure processes that require the formation of micro-patterns.

[0043] In contrast, the insulating film 14 of the present embodiment applies stress to the silicon substrate 10 in the opposite direction to the stress applied to the silicon substrate 10 by the gallium nitride growth layer 12. That is, when the gallium nitride growth layer 12 applies compressive stress to the silicon substrate 10, a film that applies tensile stress to the silicon substrate is used as the insulating film 14. Alternatively, when the gallium nitride growth layer 12 applies tensile stress to the silicon substrate 10, a film that applies compressive stress to the silicon substrate is used as the insulating film 14.

[0044] Thus, the stress applied to the silicon substrate 10 by the gallium nitride growth layer 12 can be offset by the insulating film 14. Therefore, the warping of the silicon substrate 10 can be alleviated. In this embodiment, both the effect of dispersing the stress by dividing the gallium nitride growth layer 12 into small blocks 13 and the effect of offsetting the stress by the insulating film 14 can be obtained. Therefore, the warping of the wafer can be suppressed, and the exposure process can be easily performed.

[0045] In addition, the stress applied to the silicon substrate 10 can be adjusted by the thickness of the insulating film 14. The thickness of the insulating film 14 can be adjusted by the etching time. Therefore, the silicon substrate 10 can be easily flattened.

[0046] In addition, Figure 2 It is difficult to suppress the warping by forming the thermal oxide film 16 thickly. In this case, a thick thermal oxide film 16 is formed on the silicon substrate 10 before epitaxial growth. At this time, since the film stress of the thermal oxide film 16 is large, the wafer may be greatly warped at the beginning of epitaxial growth. Therefore, the epitaxial growth process may become difficult.

[0047] Therefore, the thermal oxide film 16 needs to be formed thin to suppress a large warping of the silicon substrate 10 . On the other hand, the insulating film 14 is formed thicker than the thermal oxide film 16 to apply a large stress to the silicon substrate 10 .

[0048] As a modification of this embodiment, Figure 3 The region where the gallium nitride growth layer 12 is removed is not limited to a lattice shape. The region where the gallium nitride growth layer 12 is removed may be in other shapes as long as the gallium nitride growth layer 12 can be divided into a plurality of small blocks 13. Considering that stress is applied to the silicon substrate 10 by forming the insulating film 14, the region where the gallium nitride growth layer 12 is removed preferably penetrates from one end of the silicon substrate 10 to the other end in the longitudinal and transverse directions.

[0049] Alternatively, the first step may be performed as follows. First, a gallium nitride growth layer 12 is formed on the entire upper surface of the silicon substrate 10 by an organic metal vapor phase epitaxy method or a molecular beam epitaxy method. Thereafter, a mask layer such as a photoresist is formed on the gallium nitride growth layer 12. Next, the gallium nitride growth layer 12 is etched using the mask layer until the silicon substrate 10 is exposed. As a result, the silicon substrate 10 is exposed in a lattice shape, and the gallium nitride growth layer 12 is divided into a plurality of small blocks 13. Next, the mask layer is removed.

[0050] These modifications can be appropriately applied to the semiconductor wafer and the manufacturing method thereof according to the following embodiments. In addition, since the semiconductor wafer and the manufacturing method thereof according to the following embodiments have many common points with the first embodiment, the description will be centered on the differences from the first embodiment.

[0051] Implementation Method 2

[0052] Figure 6 2 is a cross-sectional view of a semiconductor wafer 200 according to Embodiment 2. The semiconductor wafer 200 is different from the semiconductor wafer 100 in the structure of the insulating film 214. A recess 215 is formed in the insulating film 214 between a pair of small blocks 13 adjacent to each other among the plurality of small blocks 13.

[0053] Next, a method for manufacturing the semiconductor wafer 200 will be described. The first step is the same as that of Embodiment 1. Next, the second step is performed. Figure 7 It is a cross-sectional view for explaining the method for manufacturing a semiconductor wafer according to Embodiment 2. First, the upper surface of the silicon substrate 10 and the side surfaces and upper surfaces of the plurality of small blocks 13 are covered with the insulating film 214 .

[0054] The insulating film 214 is formed along the silicon substrate 10 and the plurality of small blocks 13. The surface of the insulating film 214 is formed with projections and depressions reflecting the shapes of the plurality of small blocks 13. At this time, a recess 215 is formed in a portion between a pair of small blocks 13 adjacent to each other in the insulating film 214. The thickness of the portion of the insulating film 214 covering the side surface of the small block 13 is less than 1 / 2 of the width of the region sandwiched by the adjacent small blocks 13.

[0055] Next, a resist 218 is applied. The resist 218 is provided on the insulating film 214 so as to fill the recessed portion 215. The upper surface of the resist 218 is flat. The resist 218 has a thickness such that the upper surface of the resist 218 does not reflect the surface irregularities of the insulating film 214.

[0056] Next, an etching step is performed, thereby exposing the upper surfaces of the plurality of small blocks 13 from the insulating film 214 . Figure 82 is a cross-sectional view showing a state where the upper surfaces of the plurality of small blocks 13 are exposed. In the etching step, the insulating film 214 is removed together with the resist 218 by dry etching until the gallium nitride growth layer 12 is exposed. Thus, the portion of the resist 218 disposed above the upper surfaces of the plurality of small blocks 13 and the portion of the insulating film 214 disposed above the upper surfaces of the plurality of small blocks 13 are removed.

[0057] At this time, it is preferable to use etching conditions that make the etching rates of the resist 218 and the insulating film 214 equal. Generally, in silicon oxide films and silicon nitride films, etching conditions that make the etching rate equal to that of the resist can be found. In this way, the upper surfaces of the plurality of small blocks 13 can be exposed with high precision.

[0058] After the etching step, the portion of the resist 218 that fills the recess 215 is removed. As described above, the insulating film 214 is formed.

[0059] If the insulating film 214 is provided in a manner covering a plurality of small blocks 13, Figure 7 As shown in FIG. 2 , grid-like projections and depressions may be formed on the surface of the insulating film 214. If the insulating film 214 is etched only until the gallium nitride growth layer 12 is exposed as in Embodiment 1 without applying the resist 218, the insulating film 214 on the silicon substrate 10 is also etched. Therefore, there is a possibility that the insulating film 214 will hardly remain on the silicon substrate 10.

[0060] In an extreme example where a film having zero coverage is used as the insulating film 214, the thickness of the insulating film 214 becomes the same on the gallium nitride growth layer 12 and on the silicon substrate 10. Therefore, if the insulating film 214 is etched until the gallium nitride growth layer 12 is exposed, the insulating film 214 on the silicon substrate 10 is also completely removed.

[0061] In contrast, in this embodiment, even when the surface of the insulating film 214 is uneven, the insulating film 214 can remain thick on the silicon substrate 10. Therefore, the insulating film 214 can sufficiently suppress the warping of the silicon substrate 10.

[0062] Implementation 3

[0063] Fig. 9 2 is a cross-sectional view of a semiconductor wafer 300 according to Embodiment 3. The structure of a silicon substrate 310 of the semiconductor wafer 300 is different from that of the semiconductor wafer 100. A plurality of protrusions 310a are formed on the upper surface of the silicon substrate 310. A plurality of small blocks 13 are respectively provided on the plurality of protrusions 310a.

[0064] Next, a method for manufacturing the semiconductor wafer 300 is described. First, a gallium nitride growth layer 12 is formed on the upper surface of the silicon substrate 310 . In this state, the upper surface of the silicon substrate 310 is flat. In addition, the gallium nitride growth layer 12 is formed on the entire upper surface of the silicon substrate 310 .

[0065] Next, an etching process is performed. In the etching process, first, a mask layer such as a photoresist is formed on the gallium nitride growth layer 12. Next, a portion of the gallium nitride growth layer 12 is removed by etching using the mask layer. The etching is, for example, dry etching. As a result, the gallium nitride growth layer 12 is removed in a grid shape, and the silicon substrate 310 is exposed. Through the etching process, the gallium nitride growth layer 12 is divided into a plurality of small blocks 13.

[0066] Furthermore, etching is continued even after the silicon substrate 310 is exposed. Thus, the silicon substrate 310 is etched, and grooves are formed in the silicon substrate 310. That is, a plurality of protrusions 310a are formed on the upper surface side of the silicon substrate 310.

[0067] Next, the insulating film 14 is formed. The insulating film 14 fills the space between the adjacent protrusions 310a. The subsequent steps are the same as those in the first embodiment.

[0068] In this embodiment, the insulating film 14 can be thickened according to the depth of the groove formed in the silicon substrate 310. Therefore, a greater stress can be applied to the silicon substrate 310 through the insulating film 14 than in the first embodiment. In addition, even when the thickness of the gallium nitride growth layer 12 is thinner than the thickness of the insulating film 14 required to suppress warping, the thickness of the insulating film 14 can be ensured.

[0069] Implementation 4

[0070] Fig.10 4 is a cross-sectional view of a semiconductor wafer 400 according to Embodiment 4. In this embodiment, a thermal oxide film 16 is provided on the upper surface of a silicon substrate 10. An insulating film 14 is provided on the thermal oxide film 16. The thermal oxide film 16 and the insulating film 14 form an insulating layer.

[0071] Next, a method for manufacturing the semiconductor wafer 400 is described. The steps up to the step of growing the gallium nitride growth layer 12 are the same as those of the first embodiment. In this embodiment, the thermal oxide film 16 is not removed. Next, the insulating film 14 is formed on the thermal oxide film 16. The subsequent steps are the same as those of the first embodiment.

[0072] In this embodiment, the manufacturing process can be simplified because the thermal oxide film 16 is not removed. In addition, when the thermal oxide film 16 applies stress for correcting the warping of the silicon substrate 10, the thermal oxide film 16 can be effectively used to suppress the warping.

[0073] Furthermore, the technical features described in each embodiment may be used in combination as appropriate.

[0074] Description of Reference Numerals

[0075] 10...silicon substrate; 11...region; 12...gallium nitride growth layer; 13...small block; 14...insulating film; 16...thermal oxide film; 100, 200...semiconductor wafer; 214...insulating film; 215...concave portion; 218...resist; 300...semiconductor wafer; 310...silicon substrate; 310a...convex portion; 400...semiconductor wafer.

Claims

1. A semiconductor wafer, characterized in that: The semiconductor wafer comprises: Silicon substrate; A gallium nitride growth layer is disposed on the upper surface of the silicon substrate and is divided into a plurality of small blocks; and An insulating layer is disposed on the upper surface of the silicon substrate and fills the gaps between the plurality of small blocks. The insulating layer applies stress to the silicon substrate in a direction opposite to the stress applied to the silicon substrate by the gallium nitride growth layer. The insulating layer includes a silicon nitride film, The insulating layer has a recessed portion formed between a pair of small blocks adjacent to each other among the plurality of small blocks.

2. The semiconductor wafer according to claim 1, characterized in that The thickness of the insulating layer is greater than 1 μm and less than the thickness of the gallium nitride growth layer.

3. The semiconductor wafer according to claim 1 or 2, characterized in that A plurality of convex portions are formed on the upper surface side of the silicon substrate, The plurality of small blocks are respectively disposed on the plurality of convex portions.

4. The semiconductor wafer according to claim 1 or 2, characterized in that The insulating layer includes a thermal oxide film provided on the upper surface of the silicon substrate and an insulating film provided on the thermal oxide film.

5. The semiconductor wafer according to claim 4, characterized in that The insulating film is thicker than the thermal oxide film.

6. The semiconductor wafer according to claim 1 or 2, characterized in that: The insulating layer is connected from one end to the other end of the silicon substrate.

7. A semiconductor wafer, characterized in that: The semiconductor wafer comprises: Silicon substrate; A gallium nitride growth layer is disposed on the upper surface of the silicon substrate and is divided into a plurality of small blocks; and An insulating layer is disposed on the upper surface of the silicon substrate and fills the gaps between the plurality of small blocks. The insulating layer applies stress to the silicon substrate in a direction opposite to the stress applied to the silicon substrate by the gallium nitride growth layer. The insulating layer includes a silicon nitride film, A plurality of convex portions are formed on the upper surface side of the silicon substrate, The plurality of small blocks are respectively disposed on the plurality of convex portions.

8. The semiconductor wafer according to claim 7, characterized in that The insulating layer is connected from one end to the other end of the silicon substrate.

9. A method for manufacturing a semiconductor wafer, characterized in that: The method for manufacturing a semiconductor wafer comprises: In a first step, a gallium nitride growth layer divided into a plurality of small blocks is formed on the upper surface of a silicon substrate; and In the second step, an insulating film is used to fill the gaps between the plurality of small blocks. The insulating film applies stress to the silicon substrate in a direction opposite to the stress applied to the silicon substrate by the gallium nitride growth layer. The insulating film is a silicon nitride film.

10. The method for manufacturing a semiconductor wafer according to claim 9, wherein: The gallium nitride growth layer applies compressive stress to the silicon substrate, In the second step, SiH 4 and NH 3 are used as process gases, and the ratio of SiH 4 to NH 3 is set to 0.5 or less, and the insulating film is formed by plasma CVD.

11. The method for manufacturing a semiconductor wafer according to claim 9 or 10, characterized in that: The cross-sections of the plurality of small blocks perpendicular to the upper surface of the silicon substrate are rectangular.

12. The method for manufacturing a semiconductor wafer according to claim 9 or 10, characterized in that: The thickness of the insulating film is greater than or equal to 1 μm and less than or equal to the thickness of the gallium nitride growth layer.

13. The method for manufacturing a semiconductor wafer according to claim 9 or 10, characterized in that: The first step includes the following steps: forming a thermal oxide film on the upper surface of the silicon substrate, and dividing the upper surface of the silicon substrate into a plurality of regions by the thermal oxide film; and The step of growing the plurality of small blocks in the plurality of regions, respectively.

14. The method for manufacturing a semiconductor wafer according to claim 13, wherein: In the first step, the thermal oxide film is removed after the plurality of small blocks are grown.

15. The method for manufacturing a semiconductor wafer according to claim 13, wherein: In the second step, the insulating film is formed on the thermal oxide film.

16. The method for manufacturing a semiconductor wafer according to claim 13, wherein: The insulating film is thicker than the thermal oxide film.

17. The method for manufacturing a semiconductor wafer according to claim 9 or 10, characterized in that: The first step includes the following steps: forming the gallium nitride growth layer on the upper surface of the silicon substrate; and an etching step of removing a portion of the gallium nitride growth layer by etching to expose the silicon substrate, thereby dividing the gallium nitride growth layer into the plurality of small blocks; In the etching step, etching is continued even after the silicon substrate is exposed, thereby forming a groove in the silicon substrate.

18. The method for manufacturing a semiconductor wafer according to claim 9 or 10, characterized in that: The insulating film is connected from one end to the other end of the silicon substrate.

19. A method for manufacturing a semiconductor wafer, characterized in that: The method for manufacturing a semiconductor wafer comprises: In a first step, a gallium nitride growth layer divided into a plurality of small blocks is formed on the upper surface of a silicon substrate; and In the second step, an insulating film is used to fill the gaps between the plurality of small blocks. The insulating film applies stress to the silicon substrate in a direction opposite to the stress applied to the silicon substrate by the gallium nitride growth layer. The second step includes the following steps: A step of covering the upper surface of the silicon substrate and the side surfaces and upper surfaces of the plurality of small blocks with the insulating film, and forming a recessed portion between a pair of small blocks adjacent to each other in the insulating film; a step of providing a resist on the insulating film so as to fill the recess; An etching step of removing portions of the resist disposed above the upper surfaces of the plurality of small blocks and portions of the insulating film disposed above the upper surfaces of the plurality of small blocks by etching, thereby exposing the upper surfaces of the plurality of small blocks from the insulating film; as well as After the etching step, a step of removing the portion of the resist that fills the recess.

20. The method for manufacturing a semiconductor wafer according to claim 19, wherein: The cross-sections of the plurality of small blocks perpendicular to the upper surface of the silicon substrate are rectangular.

21. The method for manufacturing a semiconductor wafer according to claim 19 or 20, characterized in that: The thickness of the insulating film is greater than or equal to 1 μm and less than or equal to the thickness of the gallium nitride growth layer.

22. The method for manufacturing a semiconductor wafer according to claim 19 or 20, characterized in that: The first step includes the following steps: forming a thermal oxide film on the upper surface of the silicon substrate, and dividing the upper surface of the silicon substrate into a plurality of regions by the thermal oxide film; and The step of growing the plurality of small blocks in the plurality of regions, respectively.

23. The method for manufacturing a semiconductor wafer according to claim 22, wherein: In the first step, the thermal oxide film is removed after the plurality of small blocks are grown.

24. The method for manufacturing a semiconductor wafer according to claim 22, wherein: In the second step, the insulating film is formed on the thermal oxide film.

25. The method for manufacturing a semiconductor wafer according to claim 22, wherein: The insulating film is thicker than the thermal oxide film.

26. The method for manufacturing a semiconductor wafer according to claim 19 or 20, characterized in that: The first step includes the following steps: forming the gallium nitride growth layer on the upper surface of the silicon substrate; and an etching step of removing a portion of the gallium nitride growth layer by etching to expose the silicon substrate, thereby dividing the gallium nitride growth layer into the plurality of small blocks; In the etching step, etching is continued even after the silicon substrate is exposed, thereby forming a groove in the silicon substrate.

27. The method for manufacturing a semiconductor wafer according to claim 19 or 20, characterized in that: The insulating film is connected from one end to the other end of the silicon substrate.

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