MOS device for electrostatic protection and preparation method thereof

Abstract

The present invention provides a MOS device for electrostatic protection and a preparation method thereof, wherein the MOS device includes a stacked first substrate, a buried oxide layer, and a second substrate, a well region located in the second substrate, a gate, a lightly doped drain region, a drain terminal, and a source terminal. The drain terminal includes: a first body and a first tooth portion; the source terminal includes: a second body and a second tooth portion, and the adjacent first tooth portions and second tooth portions are arranged opposite to each other and staggered. The present application improves the electrostatic protection capability of the device by designing the first tooth portion of the drain terminal and the second tooth portion of the source terminal to be staggered, and the lightly doped drain region between the drain terminal and the source terminal can ensure the electrical connection between the two, so that the shapes of the drain terminal and the source terminal on both sides can form a complementary shape, and greatly increases the contact area between the source terminal and the drain terminal and the well region on both sides, that is, increases the junction area of ​​the PN junction, increases the ESD flow area, and thus improves the electrostatic protection capability of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a MOS device for electrostatic protection and a preparation method thereof. Background Art

[0002] In SOI-structured MOS devices used for ESD protection, the active silicon region above the buried oxide layer is made extremely thin, typically 50nm to 60nm, to achieve better RF (radio frequency) characteristics. Taking SOI-structured NMOS devices as an example, the drain (N+ heavily doped region) and source (N+ heavily doped region) directly contact the buried oxide layer. Compared to bulk silicon NMOS devices, SOI-structured NMOS devices lack the PN junction between the bottom of the N+ heavily doped region and the P-type well (PW). This reduces the ESD flow area, making the ESD protection capabilities of MOS devices in SOI processes extremely weak. Summary of the Invention

[0003] The present application provides a MOS device for electrostatic protection and a preparation method thereof, which can solve the problem that the ESD protection capability of the MOS device in the SOI process is extremely weak due to the small ESD flow area.

[0004] On the one hand, an embodiment of the present application provides a MOS device for electrostatic protection, comprising:

[0005] a first substrate, on which a buried oxide layer and a second substrate are stacked;

[0006] a well region, the well region being located in the second substrate;

[0007] a plurality of gates, the gates being spaced apart and located on the surface of the well region;

[0008] a plurality of lightly doped drain regions, each of the lightly doped drain regions being located in the well region on both sides of each of the gates;

[0009] a drain terminal, the drain terminal being located in the well region between the lightly doped drain regions; and

[0010] a source terminal, the source terminal being located in the well region on a side of the lightly doped drain region away from the drain terminal;

[0011] Wherein, the drain end includes: a first body and first teeth located on both sides of the first body; the source end includes: a second body and second teeth located on both sides of the second body, and adjacent first teeth are arranged opposite to the second teeth and staggered.

[0012] Optionally, in the MOS device for electrostatic protection, a ratio of a size of the first tooth portion in the transverse direction to a size of the first tooth portion in the longitudinal direction is 1-3.

[0013] Optionally, in the MOS device for electrostatic protection, a ratio of a size of the second tooth portion in a lateral direction to a size of the second tooth portion in a longitudinal direction is 1-3.

[0014] Optionally, in the MOS device for electrostatic protection, the number of the source terminals is one more than the number of the drain terminals, and the source terminals and the drain terminals are arranged alternately.

[0015] Optionally, in the MOS device for electrostatic protection, each of the lightly doped drain regions extends laterally into the well region at the bottom of the adjacent gate, and the lightly doped drain regions do not contact each other.

[0016] Optionally, in the MOS device for electrostatic protection, the conductivity type of the well region is P-type, and the conductivity types of the lightly doped drain region, the source terminal, and the drain terminal are all N-type.

[0017] Optionally, in the MOS device for electrostatic protection, the drain terminal is connected to an external IO terminal, and the source terminal and the gate terminal are connected to a ground terminal of an external power supply.

[0018] Optionally, in the MOS device for electrostatic protection, the conductivity type of the well region is N-type, and the conductivity types of the lightly doped drain region, the source terminal, and the drain terminal are all P-type.

[0019] Optionally, in the MOS device for electrostatic protection, the drain terminal is connected to an external IO terminal, and the source terminal and the gate terminal are connected to a positive terminal of an external power supply.

[0020] On the other hand, an embodiment of the present application further provides a method for preparing a MOS device, comprising:

[0021] Providing a first substrate, on which a buried oxide layer and a second substrate are stacked;

[0022] forming a well region, wherein the well region is located in the second substrate;

[0023] forming a plurality of gates, the gates being spaced apart and located on the surface of the well region;

[0024] forming a plurality of lightly doped drain regions, each of the lightly doped drain regions being located in the well regions on both sides of each of the gates; and

[0025] A drain terminal and a source terminal are formed, wherein the drain terminal is located in the well region between the lightly doped drain regions, and the source terminal is located in the well region on the side of the lightly doped drain region away from the drain terminal; wherein the drain terminal includes: a first body portion and first teeth portions located on both sides of the first body portion; the source terminal includes: a second body portion and second teeth portions located on both sides of the second body portion, and adjacent first teeth portions are arranged opposite to each other and are staggered.

[0026] The technical solution of this application has at least the following advantages:

[0027] The present application designs the first tooth portion of the drain end and the second tooth portion of the source end to be staggered, and the lightly doped drain region between the drain end and the source end can ensure the electrical connection between the two, so that the shapes of the drain end and the source end on both sides can complement each other, and greatly increases the contact area between the source end and the drain end and the well region on both sides, that is, increases the junction area of ​​the PN junction, increases the ESD flow area, and thus improves the electrostatic protection capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] FIG1( a ) is a schematic top view of a semiconductor structure having a gate formed thereon according to an embodiment of the present invention;

[0030] FIG1( b ) is a cross-sectional view of FIG1( a ) taken along line AA according to an embodiment of the present invention;

[0031] FIG2( a ) is a schematic top view of a semiconductor structure forming a lightly doped drain region according to an embodiment of the present invention;

[0032] FIG2( b ) is a cross-sectional view of FIG2( a ) taken along line AA according to an embodiment of the present invention;

[0033] FIG3( a ) is a schematic top view of a semiconductor structure forming a source terminal and a drain terminal according to an embodiment of the present invention;

[0034] FIG3( b ) is a cross-sectional view of FIG3( a ) taken along line AA according to an embodiment of the present invention;

[0035] Figure 4 is a cross-sectional view of an NMOS device for electrostatic protection according to an embodiment of the present invention, with section AA as the cross-section;

[0036] Figure 5is a cross-sectional view of a PMOS device for electrostatic protection according to an embodiment of the present invention, with section AA as the cross section;

[0037] The description of the accompanying drawings is as follows:

[0038] 11-first substrate, 12-second substrate, 20-buried oxide layer, 30-well region, 40-gate, 50-lightly doped drain region, 61-drain terminal, 611-first body, 612-first comb portion, 62-source terminal, 621-second body, 622-second comb portion, 70-silicide barrier layer;

[0039] a1 is the dimension of the first tooth portion in the transverse direction, b1 is the dimension of the first tooth portion 612 in the longitudinal direction, a2 is the dimension of the second tooth portion in the transverse direction, and b2 is the dimension of the second tooth portion in the longitudinal direction. DETAILED DESCRIPTION

[0040] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0041] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0042] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0043] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0044] The present invention provides a MOS device for electrostatic protection. Figure 4 and Figure 5 , Figure 4 is a cross-sectional view of an NMOS device for electrostatic protection according to an embodiment of the present invention, with AA as the cross-section. Figure 5 is a cross-sectional view of a PMOS device for electrostatic protection according to an embodiment of the present invention, wherein the MOS device includes a plurality of Figure 4 or Figure 5 The structure shown, Figure 4 or Figure 5 The structures shown are all units of a MOS device. The MOS device can be composed of a plurality of such units to form an array structure.

[0045] The MOS device provided in the embodiment of the present application includes: a first substrate 11, a well region 30, multiple gates 40, multiple lightly doped drain regions 50, a drain terminal 61 and a source terminal 62, wherein a stacked buried oxide layer 20 and a second substrate 12 are formed on the first substrate 11; the well region 30 is located in the second substrate 12; the gates 40 are located at intervals on the surface of the well region 30; each of the lightly doped drain regions 50 is located in the well region 30 on both sides of each of the gates 40; the drain terminal 61 is located in the well region 30 between the lightly doped drain regions 50; and the source terminal 62 is located in the well region 30 on the side of the lightly doped drain region 50 away from the drain terminal 61. Furthermore, the drain end 61 includes: a first body 611 and first teeth 612 located on both sides of the first body 611; the source end 62 includes: a second body 621 and second teeth 622 located on both sides of the second body 621, and the adjacent first teeth 612 and second teeth 622 are arranged opposite to each other and staggered.

[0046] In this embodiment, each of the lightly doped drain regions 50 extends into the well region 30 at the bottom of the adjacent gate 40 in the lateral direction, and the lightly doped drain regions 50 do not contact each other.

[0047] Based on the same inventive concept, an embodiment of the present application further provides a method for preparing a MOS device. Next, taking an NMOS device as an example, the method for preparing a MOS device is described in detail.

[0048] First, please refer to Figure 1(a) and Figure 1(b). Figure 1(a) is a top view schematic diagram of a semiconductor structure forming a gate according to an embodiment of the present invention, and Figure 1(b) is a cross-sectional view of Figure 1(a) taken along AA according to an embodiment of the present invention. A first substrate 11 is provided, on which a stacked buried oxide layer 20 and a second substrate 12 are formed.

[0049] Step 2: As shown in FIG1( a ) and FIG1( b ), a well region 30 is formed, and the well region 30 is located in the second substrate 12. Specifically, the conductivity type of the well region 30 is P type.

[0050] The third step: as shown in FIG. 1( a ) and FIG. 1 ( b ), a plurality of gates 40 are formed. The gates 40 are spaced apart and located on the surface of the well region 30 .

[0051] Step 4: Please refer to Figures 2(a) and 2(b). Figure 2(a) is a schematic top view of a semiconductor structure forming a lightly doped drain region according to an embodiment of the present invention, and Figure 2(b) is a cross-sectional view of Figure 2(a) taken along line AA according to an embodiment of the present invention, to form a plurality of lightly doped drain regions 50. Specifically, in this embodiment, one of the lightly doped drain regions 50 is located in the well region 30 between two adjacent gates 40, and the remaining lightly doped drain regions 50 are located in the well region 30 on both sides of each gate 40. Furthermore, each of the lightly doped drain regions 50 extends laterally into the well region 30 at the bottom of the adjacent gate 40, and the lightly doped drain regions 50 do not contact each other. The conductivity type of the lightly doped drain regions 50 is all N-type.

[0052] Step 5: Please refer to Figures 3(a) and 3(b), Figure 3(a) is a top view schematic diagram of a semiconductor structure forming a source terminal and a drain terminal according to an embodiment of the present invention, and Figure 3(b) is a cross-sectional view of Figure 3(a) according to an embodiment of the present invention with AA as the cross-sectional view, forming a drain terminal 61 and a source terminal 62, wherein the drain terminal 61 is located in the well region 30 between the lightly doped drain regions 50, and the source terminal 62 is located in the well region 30 on the side of the lightly doped drain region 50 away from the drain terminal 61; wherein the drain terminal 61 includes: a first body portion 611 and a first tooth portion 612 located on both sides of the first body portion 611; the source terminal 62 includes: a second body portion 621 and a second tooth portion 622 located on both sides of the second body portion 621, and adjacent first tooth portions 612 and second tooth portions 613 are arranged opposite to each other and staggered.

[0053] Preferably, the ratio of the horizontal dimension a1 of the first tooth portion 612 to the vertical dimension b1 of the first tooth portion 612 can be 1 to 3. The ratio of the horizontal dimension a2 of the second tooth portion 622 to the vertical dimension b2 of the second tooth portion 622 can be 1 to 3. Thus, it can be seen that the first tooth portion 612 of the drain terminal 61 is alternatingly concave and convex, and is arranged alternately with the second tooth portion 622, which is also alternatingly concave and convex. The first tooth portion 612 increases the side area of ​​the drain terminal 61, and the second tooth portion 622 increases the side area of ​​the source terminal 62, thereby greatly increasing the contact area between the source terminal 61 and the drain terminal 62 and the well region 30, that is, increasing the junction area of ​​the PN junction, increasing the ESD flow area, and thus improving the electrostatic protection capability of the device.

[0054] Furthermore, the number of the source terminals 62 can be one more than the number of the drain terminals 61, and the source terminals 62 and the drain terminals 61 are arranged alternately. As shown in FIG3(b), in one unit, the number of the source terminals 62 can be two, and the number of the drain terminal 61 can be one, forming a source-drain-source structure.

[0055] Better, such as Figure 4 As shown, after forming the drain terminal 61 and the source terminal 62, the preparation method of the MOS device may further include: forming a silicide blocking layer 70, the material of the silicide blocking layer 70 may be silicon dioxide, the silicide blocking layer 70 covers the surface of the lightly doped drain region 50 between the gate 40 and the drain terminal 61, the silicide blocking layer 70 also covers part of the surface of the drain terminal 61 and part of the surface of the gate 40, and the remaining surface of the gate 40 and the remaining surface of the drain terminal 61 not covered by the silicide blocking layer can be subsequently electrically connected (lead out) to the peripheral circuit.

[0056] In this embodiment, if Figure 4 As shown, the conductivity type of the source terminal 62 and the drain terminal 61 are both N-type. The drain terminal 61 is connected to an external IO terminal, and the source terminal 62 and the gate 40 are connected to the ground terminal of an external power supply.

[0057] In addition, the MOS device provided by the present invention may also be a PMOS device, such as Figure 5 As shown, the conductivity type of the well region 30 is N-type, and the conductivity type of the lightly doped drain region 50, the source terminal 62, and the drain terminal 61 are all P-type. The drain terminal 61 is connected to an external IO terminal, and the source terminal 62 and the gate 40 are connected to the positive terminal of an external power supply. The positional relationship between the various film layers and the various doped regions of the PMOS device is the same as the positional relationship between the various film layers and the various doped regions of the NMOS device described above, and will not be repeated in this application.

[0058] In summary, the present invention provides a MOS device for electrostatic protection and a method for manufacturing the same. The MOS device comprises a stacked first substrate 11, a buried oxide layer 20, and a second substrate 12, a well region 30 located in the second substrate 12, a gate 40, a lightly doped drain region 50, a drain terminal 62, and a source terminal 61. The drain terminal 61 comprises a first body 611 and a first tooth 612; the source terminal 62 comprises a second body 621 and a second tooth 622, with adjacent first teeth 612 and second teeth 622 disposed opposite each other and arranged in an alternating pattern. The present application designs the first tooth portion 622 of the drain terminal 62 and the second tooth portion 612 of the source terminal 61 to be staggered, and the lightly doped drain region 50 between the drain terminal 62 and the source terminal 61 can ensure the electrical connection between the two, so that the shapes of the drain terminal 62 and the source terminal 61 on both sides can form a complementary shape, and greatly increase the contact area between the source terminal 61 and the drain terminal 62 and the well region 30 on both sides, that is, increase the junction area of ​​the PN junction, increase the ESD flow area, thereby improving the electrostatic protection capability of the device.

[0059] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A MOS device for electrostatic protection, characterized in that: include: a first substrate, on which a buried oxide layer and a second substrate are stacked; a well region, the well region being located in the second substrate; a plurality of gates, the gates being spaced apart and located on the surface of the well region; a plurality of lightly doped drain regions, each of the lightly doped drain regions being located in the well region on both sides of each of the gates, wherein each of the lightly doped drain regions laterally extends into the well region at the bottom of an adjacent gate, and the lightly doped drain regions do not contact each other; a drain terminal, the drain terminal being located in the well region between the lightly doped drain regions; and a source terminal, the source terminal being located in the well region on the side of the lightly doped drain region away from the drain terminal, wherein the drain terminal is connected to an external IO terminal, and the source terminal and the gate terminal are both connected to a ground terminal of an external power supply or a positive terminal of an external power supply; Wherein, the drain end includes: a first body and first teeth located on both sides of the first body; the source end includes: a second body and second teeth located on both sides of the second body, and adjacent first teeth are arranged opposite to the second teeth and staggered.

2. The MOS device for electrostatic protection according to claim 1, characterized in that: The ratio of the size of the first tooth portion in the transverse direction to the size of the first tooth portion in the longitudinal direction is 1-3.

3. The MOS device for electrostatic protection according to claim 1, characterized in that: The ratio of the size of the second tooth portion in the transverse direction to the size of the second tooth portion in the longitudinal direction is 1-3.

4. The MOS device for electrostatic protection according to claim 1, wherein: The number of the source terminals is one more than the number of the drain terminals, and the source terminals and the drain terminals are arranged alternately.

5. The MOS device for electrostatic protection according to claim 1, characterized in that: The conductivity type of the well region is P-type, and the conductivity types of the lightly doped drain region, the source terminal, and the drain terminal are all N-type.

6. The MOS device for electrostatic protection according to claim 5, characterized in that: The drain terminal is connected to an external IO terminal, and the source terminal and the gate terminal are connected to a ground terminal of an external power supply.

7. The MOS device for electrostatic protection according to claim 1, characterized in that: The conductivity type of the well region is N-type, and the conductivity types of the lightly doped drain region, the source terminal, and the drain terminal are all P-type.

8. The MOS device for electrostatic protection according to claim 7, characterized in that: The drain terminal is connected to an external IO terminal, and the source terminal and the gate terminal are connected to a positive terminal of an external power supply.

9. A method for preparing a MOS device, characterized in that: include: Providing a first substrate, on which a buried oxide layer and a second substrate are stacked; forming a well region, wherein the well region is located in the second substrate; forming a plurality of gates, the gates being spaced apart and located on the surface of the well region; forming a plurality of lightly doped drain regions, each of the lightly doped drain regions being located in the well region on both sides of each of the gates, wherein each of the lightly doped drain regions laterally extends into the well region at the bottom of the adjacent gate, and the lightly doped drain regions do not contact each other; and A drain terminal and a source terminal are formed, wherein the drain terminal is located in the well region between the lightly doped drain regions, and the source terminal is located in the well region on the side of the lightly doped drain region away from the drain terminal; wherein the drain terminal includes: a first body portion and first teeth located on both sides of the first body portion; and the source terminal includes: a second body portion and second teeth located on both sides of the second body portion, wherein adjacent first teeth and second teeth are disposed opposite each other and are arranged in a staggered manner. The drain terminal is connected to an external IO terminal, and the source terminal and the gate terminal are both connected to a ground terminal of an external power supply or a positive terminal of an external power supply.

Images