Transfer status output device, time-to-digital converter and A / D conversion circuit

Abstract

This invention provides a transition state output device, a time-to-digital converter, and an A / D conversion circuit. The transition state output device includes: a ring oscillating circuit; a state machine that changes state according to state changes of the ring oscillating circuit; a transition state acquisition unit that acquires and maintains state information, including a signal output from the ring oscillating circuit and a signal output from the state machine, synchronously with a reference signal; and an internal state calculation unit that calculates an internal state corresponding to the number of state changes of the ring oscillating circuit based on the state information maintained by the transition state acquisition unit, wherein the time from the internal state transitioning from a first internal state to a second internal state until it transitions back to the first internal state is longer than the interval for updating the state information maintained by the transition state acquisition unit.

Description

TECHNICAL FIELD

[0001] The present application relates to a transition state output device, a time-to-digital converter, and an A / D conversion circuit. BACKGROUND

[0002] In Patent Literature 1, a time-to-digital converter is described, which has a multi-stage delay line to which a plurality of delay elements are connected, a logic circuit, and a state machine, and which is provided with a state transition section that starts state transition based on a trigger signal, a transition state acquisition section that acquires and holds state information indicating an internal state from the state transition section in synchronization with a reference signal, and a calculation section that calculates a time-to-digital value corresponding to the number of times of transition of the internal state based on the state information.

[0003] Patent Literature 1: Japanese Patent Application Publication No. 2020-178153

[0004] The time-to-digital converter described in Patent Literature 1 is caused by the fact that the delay time and the operation speed differ for each structural element of the multi-stage delay line, the logic circuit, the state machine, and the like included in the state transition section, and thus there is a relatively large difference in the time during which each internal state continues. Therefore, in order to improve the linearity of the time-to-digital value with respect to the number of times of transition of the internal state, correction information obtained by measuring the duration of each internal state in advance is stored in a storage section, and the number of times of transition of the internal state is corrected by numerical operation using the correction information. Therefore, in the time-to-digital converter described in Patent Literature 1, a correction circuit for improving linearity is required, and effort is required to create the correction information required for the operation of the correction circuit. SUMMARY

[0005] One embodiment of the transition state output device of the present application is provided with a ring-shaped oscillation circuit that starts oscillation based on a trigger signal, a state machine whose state changes in accordance with a change in the state of the ring-shaped oscillation circuit, a transition state acquisition section that acquires and holds state information including a signal output from the ring-shaped oscillation circuit and a signal output from the state machine in synchronization with a reference signal, and an internal state calculation section that calculates an internal state corresponding to the number of times of change in the state of the ring-shaped oscillation circuit based on the state information held by the transition state acquisition section, the time from when the internal state transitions from a first internal state to a second internal state to when it transitions again to the first internal state being longer than the interval of the times at which the state information held by the transition state acquisition section is updated.

[0006] One embodiment of the time-to-digital converter of the present application is provided with one embodiment of the transition state output device and a calculation section that calculates the number of times of transition of the internal state and calculates a time-to-digital value corresponding to a time event of the trigger signal based on the number of times of transition.

[0007] An A / D conversion circuit according to an embodiment of the present application is an A / D conversion circuit that converts an input analog signal into a digital signal and outputs the digital signal, and includes: a time-to-digital converter according to an embodiment of the present application; a reference waveform signal generation circuit that generates a reference waveform signal based on a reference signal; and a comparator that compares a voltage of the analog signal with a voltage of the reference waveform signal and outputs a trigger signal, the A / D conversion circuit outputting the digital signal based on a time-to-digital value calculated by the time-to-digital converter.

[0008] An A / D conversion circuit according to an embodiment of the present application is an A / D conversion circuit that converts an input analog signal into a digital signal and outputs the digital signal, and includes: a time-to-digital converter according to an embodiment of the present application; a sample-and-hold circuit that samples and holds a voltage of the analog signal; a reference waveform signal generation circuit that generates a reference waveform signal based on a reference signal; and a comparator that compares a voltage held by the sample-and-hold circuit with a voltage of the reference waveform signal and outputs a trigger signal, the A / D conversion circuit outputting the digital signal based on a time-to-digital value calculated by the time-to-digital converter. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 FIG. 1 is a diagram showing a functional structure of a time-to-digital converter according to a first embodiment.

[0010] Figure 2 FIG. 2 is a diagram showing a structure example of a transition state output device according to the first embodiment.

[0011] Figure 3 FIG. 3 is a diagram showing an example of a truth table of a decoder.

[0012] Figure 4 FIG. 4 is a diagram showing another example of a truth table of a decoder.

[0013] Figure 5 FIG. 5 is a timing chart showing an example of an operation of the transition state output device.

[0014] Figure 6 FIG. 6 is a diagram showing a structure example of an arithmetic unit.

[0015] Figure 7 FIG. 7 is a diagram showing a structure example of a counter.

[0016] Figure 8 FIG. 8 is a diagram showing a structure example of a count value holding unit and an accumulation unit.

[0017] Figure 9 FIG. 9 is a diagram showing a relationship between a phase difference PD and a time-to-digital value TD.

[0018] Figure 10is a graph showing a relationship between a phase difference PD and a time digital value TD.

[0019] Figure 11 is a functional block diagram of a time-to-digital converter of the second embodiment.

[0020] Figure 12 is a graph showing a structure example of the transfer state output device in the second embodiment.

[0021] Figure 13 is a graph showing an example of a truth table of the decoder.

[0022] Figure 14 is a graph showing an example of a truth table of the decoder.

[0023] Figure 15 is a timing chart showing an example of the action of the transfer state output device.

[0024] Figure 16 is a timing chart showing an example of the action of the transfer state output device.

[0025] Figure 17 is a graph showing another example of a truth table of the decoder.

[0026] Figure 18 is a graph showing another example of a truth table of the decoder.

[0027] Figure 19 is a timing chart showing an example of the action of the transfer state output device.

[0028] Figure 20 is a graph showing another example of a truth table of the decoder.

[0029] Figure 21 is a graph showing another example of a truth table of the decoder.

[0030] Figure 22 is a timing chart showing an example of the action of the transfer state output device.

[0031] Figure 23 is a graph showing a structure example of the transfer state output device in the third embodiment.

[0032] Figure 24 is a timing chart showing an example of the action of the transfer state output device.

[0033] Figure 25 is a graph showing a structure example of the counting section.

[0034] Figure 26 is a graph showing a relationship between a phase difference PD and a time digital value TD.

[0035] Figure 27Fig. 1 is a diagram showing a configuration example of a transfer state output apparatus in the fourth embodiment.

[0036] Figure 28 Fig. 2 is a timing chart showing an example of the operation of the transfer state output apparatus.

[0037] Figure 29 Fig. 3 is a functional block diagram of a time-to-digital converter of the fifth embodiment.

[0038] Figure 30 Fig. 4 is another functional block diagram of the time-to-digital converter of the fifth embodiment.

[0039] Figure 31 Fig. 5 is a diagram showing a configuration example of an arithmetic unit.

[0040] Figure 32 Fig. 6 is a diagram showing a configuration of an A / D conversion circuit of the first embodiment.

[0041] Figure 33 Fig. 7 is a diagram showing an example of waveforms of various signals.

[0042] Figure 34 Fig. 8 is a diagram showing a configuration of an A / D conversion circuit of the second embodiment.

[0043] Figure 35 Fig. 9 is a diagram showing an example of waveforms of various signals.

[0044] BRIEF DESCRIPTION OF THE DRAWINGS

[0045] 1... transfer state output apparatus, 10... ring oscillator circuit, 11... logical AND circuit; 12... logical inversion circuit, 13... traveling wave counter, 14... stop control circuit, 15... XOR circuit, 20... state machine, 21... Gray code counter, 30... transfer state acquisition section, 31, 31-0 to 31-q... D flip-flop, 32... register, 40... internal state calculation section, 41... decoder, 42... decoder, 50... arithmetic unit, 60... counting section, 61... register, 62... subtracter, 63... accumulator, 64... multiplier, 65... virtualization section, 70... count value holding section, 71... register, 80... accumulation section, 81... adder, 82... register, 90... conversion section, 92... time-to-digital value generation section, 100... time-to-digital converter, 101... sample-and-hold circuit, 102... reference waveform signal generation circuit, 103... comparator, 200... multi-stage delay line, 201-1 to 201-q... delay element, 300... A / D conversion circuit. DETAILED DESCRIPTION

[0046] Hereinafter, preferred embodiments of the present application will be described in detail with reference to the accompanying drawings. In addition, the embodiments described below do not unduly limit the scope of the application described in the claims. Furthermore, all the structures described below are not necessarily essential to the application.

[0047] 1. Time-to-digital converter

[0048] 1-1. First embodiment

[0049] 1-1-1. Structure of time-to-digital converter

[0050] Figure 1 is a functional block diagram of the time-to-digital converter of the first embodiment. As shown in Figure 1 , the time-to-digital converter 100 of the first embodiment is provided with a transition state output device 1 and an arithmetic unit 50. The transition state output device 1 is provided with a ring oscillator circuit 10, a state machine 20, a transition state acquisition unit 30, and an internal state calculation unit 40.

[0051] The ring oscillator circuit 10 starts oscillation based on a trigger signal TRG.

[0052] The state machine 20 changes state in accordance with a change in state of the ring oscillator circuit 10.

[0053] The transition state acquisition unit 30 acquires and holds state information including a signal output from the ring oscillator circuit 10 and a signal output from the state machine 20 in synchronization with a reference signal CLK.

[0054] The internal state calculation unit 40 calculates an internal state corresponding to the number of changes in state of the ring oscillator circuit 10 based on the state information held by the transition state acquisition unit 30.

[0055] The transition state output device 1 outputs a state signal OUT[n:0] of n+1 bits representing the internal state calculated by the internal state calculation unit 40. n is an arbitrary integer of 0 or greater.

[0056] The operation section 50 operates the number of times of transition of the internal state based on the state signal OUT[n:0] and calculates the time digital value TD corresponding to the time event of the trigger signal TRG based on the number of times of transition. The operation section 50 is constituted by, for example, an MPU, an FPGA, or the like. The MPU is an abbreviation of Micro Processing Unit. Further, the FPGA is an abbreviation of Field Programmable Gate Array. As will be described later, in the present embodiment, the operation section 50 weights the number of times of state transition based on the passage of time and accumulates the weighted number of times of state transition, thereby generating the time digital value TD corresponding to the phase difference between the time event of the reference signal CLK and the time event of the trigger signal TRG.

[0057] The time event of the trigger signal TRG refers to the timing at which the trigger signal TRG changes, and can be, for example, the rising edge or the falling edge of the trigger signal TRG, or the rising edge and the falling edge of the trigger signal TRG. Similarly, the time event of the reference signal CLK refers to the timing at which the reference signal CLK changes, and can be, for example, the rising edge or the falling edge of the reference signal CLK, or the rising edge and the falling edge of the reference signal CLK.

[0058] In the following, it is assumed that the time event of the trigger signal TRG is the rising edge and the falling edge, and the time event of the reference signal CLK is the rising edge.

[0059] 1-1-2. Structure of transition state output apparatus 1

[0060] Figure 2 is a diagram showing an example of the structure of the transition state output apparatus 1. In Figure 2 In the example of FIG. 1, the transition state output apparatus 1 includes a logical AND circuit 11, a logical inversion circuit 12, a ripple counter 13, a stop control circuit 14, an exclusive OR circuit 15, a Gray code counter 21, a D flip-flop 31, a register 32, and a decoder 41.

[0061] The logical AND circuit 11 outputs a logical AND signal of the enable signal EN output from the exclusive OR circuit 15 and the signal output from the logical inversion circuit 12. The signal output from the logical AND circuit 11 becomes a low level when the enable signal EN is a low level, and becomes the same logical level as the signal output from the logical inversion circuit 12 when the enable signal EN is a high level.

[0062] The logic inversion circuit 12 outputs a signal obtained by inverting the logic level of the signal output from the logic AND circuit 11. Therefore, when the enable signal EN is high, the logic level of the signal output from the logic AND circuit 11 alternates between low and high levels. That is, the logic AND circuit 11 and the logic inversion circuit 12 constitute a ring oscillation circuit 10, and the ring oscillation circuit 10 outputs the signal output from the logic AND circuit 11 as the oscillation signal D0. It can be considered that the change in the logic level of the oscillation circuit D0 is equivalent to the change in the state of the ring oscillation circuit 10.

[0063] Gray code counter 21 counts the two edges of the oscillation signal D0 output from the ring oscillator circuit 10, and outputs a Gray code signal G[k:0] of bits k+1 corresponding to the count value. The Gray code signal G[k:0] is a signal whose two or more bits do not change simultaneously. Since the change in the value of the Gray code signal G[k:0] at regular intervals can be considered equivalent to a change in the state of the Gray code counter 21, the Gray code counter 21 forms the state machine 20. When the state machine 20, formed by the Gray code counter 21, transitions from any state to the next state, only one bit of the Gray code signal G[k:0] changes in the k+1 bits. That is, the Hamming distance before and after the state transition of the state machine 20 is 1.

[0064] The ripple counter 13 counts the number of rising edges of the signal G[1], which is bit 1 of the Gray code signal G[k:0] output from the Gray code counter 21, and outputs a count signal C[m:0] of bit m+1. m is any integer greater than or equal to 0. Additionally, the ripple counter 13 can count the number of falling edges of the signal G[1], and also count the number of logic level inversions of the signal G[1]. Furthermore, the ripple counter 13 can count the number of rising or falling edges of the oscillation signal D0, and also count the number of logic level inversions of the oscillation signal D0.

[0065] The stop control circuit 14 outputs the following stop control signal PS: a stop control signal PS that is reversed whenever the increment of the value of the counting signal C[m:0] output from the traveling wave counter 13 matches the value of the stop setting signal TN[m:0] at bit m+1.

[0066] The XOR signal EX, generated by the XOR circuit 15, is the trigger signal TRG and the stop control signal PS output from the stop control circuit 14. The enable signal EN is high when the logic level of the trigger signal TRG differs from that of the stop control signal PS, and low when they are the same.

[0067] The D flip-flop 31 acquires the oscillation signal D0 synchronously with the rising edge of the reference signal CLK, and holds the signal S0 corresponding to the value of the oscillation signal D0.

[0068] Register 32 is a k+1 bit register composed of k+1 D flip-flops. It acquires the Gray code signal G[k:0] synchronously with the rising edge of the reference signal CLK and holds the signal g[k:0] corresponding to the value of the Gray code signal G[k:0].

[0069] Since the oscillation signal D0 represents the state of the ring oscillation circuit 10 and the Gray code signal G[k:0] represents the state of the Gray code counter 21 that constitutes the state machine 20, the transition state acquisition unit 30 is constituted by the D flip-flop 31 and the register 32.

[0070] Decoder 41 decodes the k+2-bit signal consisting of signal S0 held by D flip-flop 31 and signal g[k:0] held by register 32, and outputs the n+1-bit decoded signal dec[n:0]. n is any integer greater than or equal to 1.

[0071] Since signal S0 represents the state of the ring oscillator circuit 10 at the timing of the rising edge of the reference signal CLK, and signal g[k:0] represents the state of the state machine 20 at the timing of the rising edge of the reference signal CLK, it can be considered that the decoded signal dec[n:0] obtained by decoding the signal composed of signal S0 and signal g[k:0] is equivalent to the signal representing the internal state of the transition state output device 1 at the timing of the rising edge of the reference signal CLK. That is, the decoder 41 constitutes the internal state calculation unit 40.

[0072] Furthermore, the transition state output device 1 outputs the decoded signal dec[n:0] as the state signal OUT[n:0].

[0073] Figure 3 This is a diagram illustrating an example of the truth table of decoder 41. Figure 3 In the example, k = 2 and n = 3. Figure 3 In this context, 0 represents a low level and 1 represents a high level. Since the decoding signal dec[3:0] is equivalent to the signal representing the internal state of the rising edge of the reference signal CLK, therefore... Figure 3 In the example, whenever the state of state machine 20 changes, the value of the internal state increases sequentially from 0 to 15, and the value of the internal state returns to 0 after 15. That is, in Figure 3In the example, sixteen internal states are defined. Furthermore, these sixteen internal states transition sequentially at either the timing of a change in the logic level of the oscillation signal D0 or the timing of a change in the value of the decoded signal dec[n:0]. Since the period of the oscillation signal D0 is approximately constant, and the delay time of the decoder 41 is approximately constant regardless of the value of the decoded signal dec[n:0], the difference in the duration of the sixteen internal states can be reduced. However, when the delay time of the decoder 41 is greater than 1 / 4 of the period of the oscillation signal D0, the duration of the eight internal states with odd-numbered values ​​of the decoded signal dec[n:0] becomes relatively long, making them easier to acquire by the transition state acquisition unit 30. On the other hand, the duration of the eight internal states with even-numbered values ​​of the decoded signal dec[n:0] becomes relatively short, making them harder to acquire by the transition state acquisition unit 30. Therefore, it is desirable to make the delay time of the decoder 41 consistent with 1 / 4 of the period of the oscillation signal D0, but this is difficult to achieve. Figure 3 In the example, the frequency of the internal state acquired by the transition state acquisition unit 30 will deviate. In contrast, if the timing of the internal state being reversed with the logic level of the oscillation signal D0, i.e., the timing of the state change of the ring oscillation circuit 10, is changed synchronously, the difference in duration of each internal state can be greatly reduced regardless of the delay time of the decoder 41.

[0074] Figure 4 This is a diagram illustrating an example of the truth table of decoder 41 that defines such internal states. Figure 4 In the example, k=2, n=2. In Figure 4 In this context, 0 represents a low voltage level, and 1 represents a high voltage level. Figure 4 In the example, whenever the state of the ring oscillator circuit 10 changes, the value of the internal state increases sequentially from 0 to 7, and the value of the internal state returns to 0 after the next value of 7. That is, in Figure 4 In the example, eight internal states are defined. Furthermore, since the internal states necessarily transition at the timing of the logic level reversal of the oscillation signal D0, the duration of the eight internal states coincides with half the period of the oscillation signal D0, with an extremely small difference. Therefore, in Figure 4 In the example, although the number of defined internal states is greater than Figure 3 There are few examples, but the frequency of the internal states acquired by the transition state acquisition unit 30 will not deviate.

[0075] Figure 5 This is a timing diagram illustrating an example of the operation of the transition state output device 1. Figure 5In the example, whenever the logic level of the trigger signal TRG reverses, the enable signal EN transitions from low to high, and the oscillation of the ring oscillator circuit 10 begins. After this, whenever the increment of the count signal C[m:0] matches the value of the stop setting signal TN[m:0] (i.e., 2), the enable signal EN transitions from high to low, and the oscillation of the ring oscillator circuit 10 stops. Specifically, during the first period when the enable signal EN is high, the oscillation of the ring oscillator circuit 10 stops after twenty internal state transitions. During subsequent periods when the enable signal EN is high, the oscillation of the ring oscillator circuit 10 stops after thirty-two internal state transitions. That is, during subsequent periods when the enable signal EN is high, the state transition stops when the number of state transitions of the transition state output device 1 reaches the upper limit of 32.

[0076] The truth table of decoder 41 is as follows: Figure 3 In this case, the status signal OUT[3:0] of Case (Event) 1 is output, and the truth table of decoder 41 is... Figure 4 In this case, the status signal OUT[2:0] for Case2 is output. Figure 5 In the example, the period of the reference signal CLK is 2.5 times the period of the oscillation signal D0. Furthermore, in Figure 3 In the example, since the internal state transitions four times during one cycle of the oscillation signal D0, the internal state transitions ten times during one cycle of the reference signal CLK. Therefore, during the period when the enable signal EN is high, the value of the state signal OUT[3:0] of Case1 changes ten times at the rising edge of the reference signal CLK. Furthermore, in Figure 4 In the example, since the internal state transitions twice during one cycle of the oscillation signal D0, the internal state transitions five times during one cycle of the reference signal CLK. Therefore, during the period when the enable signal EN is high, the value of the state signal OUT[2:0] of Case2 changes five times at the rising edge of the reference signal CLK.

[0077] In this embodiment, the time from transitioning from any first internal state to a second internal state to transitioning back to the first internal state is longer than the time interval for updating the state information held by the transition state acquisition unit 30. The time until transitioning back to the first internal state can also be referred to as the time until the first internal state reappears. For example, in... Figure 3 In the example, when the state where the oscillation signal D0 is low and all bits of the Gray code signal G[2:0] are low is taken as the first internal state, the state where the oscillation signal D0 is high and all bits of the Gray code signal G[2:0] are low is the second internal state. Furthermore, inFigure 4 In the example, when the state where the oscillation signal D0 is low and all bits 1 and 0 of the Gray code signals G[2:0] are low is taken as the first internal state, the state where the oscillation signal D0 is high and bits 2 and 1 of the Gray code signals G[2:0] are low is the second internal state. Furthermore, the interval between updating the state information held by the transition state acquisition unit 30 is one cycle of the reference signal CLK. Therefore, in Figure 3 In the example, since there are sixteen internal states, the time required for fifteen internal state transitions is longer than the time of one cycle of the reference signal CLK. Figure 4 In the example, since there are eight internal states, the time required for seven internal state transitions is longer than the time of one cycle of the reference signal CLK.

[0078] By satisfying the condition that the time between transitioning from any first internal state to a second internal state and then back to the first internal state is longer than the time interval for updating the state information held by the transition state acquisition unit 30, the arithmetic unit 50 of the next stage of the transition state output device 1 can easily calculate the number of internal state transitions during one cycle of the reference signal CLK. Conversely, if this condition is not met, the arithmetic unit 50 needs to determine the number of times the internal state cycles once and calculate the number of internal state transitions during one cycle of the reference signal CLK using a predetermined formula.

[0079] 1-1-3. Structure of the arithmetic unit

[0080] Figure 6 This is a diagram showing an example of the structure of the arithmetic unit 50. (Example) Figure 6 As shown, the arithmetic unit 50 includes a counting unit 60, a count value holding unit 70, an accumulation unit 80, and a conversion unit 90.

[0081] The counting unit 60 outputs the count value CNT corresponding to the trigger signal TRG based on the status signal OUT[n:0].

[0082] The count value holding unit 70 reads the count value CNT output from the count unit 60 synchronously with the reference signal CLK, and holds it as the count value DCNT.

[0083] The accumulator 80 accumulates the count value DCNT held in the count value holding unit 70 in sync with the reference signal CLK, thereby generating a digital time value TD corresponding to the phase difference between the time events of the reference signal CLK and the respective time events of the trigger signal TRG. Furthermore, the count value holding unit 70 and the accumulator 80 are initialized, for example, by inputting a reset signal (not shown).

[0084] The conversion unit 90 converts the digital time value TD output from the accumulator 80 into a digital time value TDX. For example, the conversion unit 90 can convert the digital time value TD into a digital time value TDX by performing a prescribed scaling, or it can convert the digital time value TD into a digital time value TDX according to a prescribed conversion formula or table information. Alternatively, the calculation unit 50 may not include the conversion unit 90.

[0085] Furthermore, the time digital value TD or time digital value TDX calculated by the arithmetic unit 50 is output to the outside from the time digital converter 100 via a terminal not shown.

[0086] Figure 7 This is a diagram showing an example of the structure of the counting unit 60. The counting unit 60 includes a register 61, a subtractor 62, an accumulator 63, and a multiplier 64.

[0087] Register 61 consists of n+1 D flip-flops, which are read in synchronously with the rising edge of the reference signal CLK and hold the status signal OUT[n:0].

[0088] Subtractor 62 subtracts the value of the signal held by register 61 from the value of the status signal OUT[n:0]. Here, the value of signal C1 output from subtractor 62 corresponds to the number of internal state transitions of the status output device 1 during the most recent cycle of the reference signal CLK.

[0089] Accumulator 63 accumulates the constant value 'a' synchronously with the rising edge of the reference signal CLK. Therefore, accumulator 63 outputs a weighting coefficient signal WC, which has a value that is 'a' times the value obtained by counting the rising edges of the reference signal CLK. The value of the weighting coefficient signal WC monotonically increases or decreases with the elapsed time following the rising or falling edge of the trigger signal TRG. Specifically, if the constant value 'a' is positive, the value of the weighting coefficient signal WC monotonically increases with the elapsed time; if the constant value 'a' is negative, the value of the weighting coefficient signal WC monotonically decreases with the elapsed time.

[0090] Multiplier 64 multiplies the value of signal C1 with the value of weighting coefficient signal WC to calculate the count value CNT. The count value CNT is output from the counting unit 60.

[0091] exist Figure 7 The illustrations and explanations are omitted, but when the state transition of the state output device 1 stops, a reset signal to initialize the value to 0 can be input to the register 61 and the accumulator 63.

[0092] In addition, in this embodiment, the count value CNT is calculated by multiplying the number of internal state transitions of the transition state output device 1 within the most recent period of the reference signal CLK by the value of the weighting coefficient signal WC. However, the count value CNT can also be calculated by multiplying the number of internal state transitions of the transition state output device 1 within the period from the input of the trigger signal TRG to the time-to-digital converter 100 to the output of the state signal OUT[n:0] of the transition state output device 1 by the value of the weighting coefficient signal WC.

[0093] Figure 8 This is a diagram showing an example of the structure of the count value holding unit 70 and the accumulation unit 80. (See diagram for details.) Figure 8 As shown, the count value holding unit 70 includes a register 71 composed of multiple D flip-flops. The register 71 acquires the count value CNT output from the counting unit 60 synchronously with the rising edge of the reference signal CLK, and holds it as the count value DCNT.

[0094] The accumulator 80 includes an adder 81 and a register 82 composed of multiple D flip-flops. The adder 81 adds the count value DCNT held in register 71 to the value output from register 82. Register 82 reads the value output from adder 81 synchronously with the rising edge of the reference signal CLK and holds it as the digital time value TD.

[0095] In addition, Figure 8 The diagram is omitted, but a reset signal that initializes the retained value to 0 can also be input to registers 71 and 82 respectively. Thus, the digital time value TD is also initialized to 0.

[0096] In this embodiment, the time events of the reference signal CLK and the trigger signal TRG are set independently. That is, the time events of the reference signal CLK and the trigger signal TRG are asynchronous. Furthermore, the digital time value TD corresponds to the phase difference PD between the time events of the reference signal CLK and the trigger signal TRG. For example, the digital time value TD or the digital time value TDX is used as a timestamp for the time event of the trigger signal TRG, which is based on the time event of the reference signal CLK.

[0097] 1-1-4. Relationship between the phase difference between the reference signal and the trigger signal and the digital value of time.

[0098] Figure 9 This is a graph showing the relationship between the phase difference PD of the time events of the reference signal CLK and the trigger signal TRG, and the digital value TD of the time. Figure 9 The values ​​of the status signal OUT, C1, weighting coefficient signal WC, count value CNT, and count value DCNT are also shown. Furthermore, in Figure 9In this example, the upper limit of the number of state transitions for the state transition output device 1 is 64, and the constant value a is 1. Furthermore, T is the time of one cycle of the reference signal CLK.

[0099] like Figure 9 As shown, whenever a time event of the reference signal CLK is generated, a count value CNT is generated based on the status signal OUT, signal C1, and weighting coefficient signal WC. The count value DCNT, which holds the count value CNT, is accumulated, while the digital time value TD increases. When the time event of the reference signal CLK is taken as the 0th rising edge, with a phase difference PD of T×1.5, at the tenth rising edge, the value of the status signal OUT, which indicates the number of transitions of the internal state of the transition state output device 1 after the time event of the trigger signal TRG, reaches the upper limit value of 64. Moreover, after the twelfth rising edge of the reference signal CLK, the digital time value TD becomes 377.

[0100] Furthermore, when the phase difference PD is T×1.7, the value of the status signal OUT reaches the upper limit of 64 at the tenth rising edge of the reference signal CLK, and the digital value of time TD becomes 391 after the twelfth rising edge of the reference signal CLK.

[0101] Furthermore, when the phase difference PD is T×2.7, the value of the status signal OUT reaches the upper limit of 64 at the eleventh rising edge of the reference signal CLK, and the digital value of time TD becomes 455 after the thirteenth rising edge of the reference signal CLK.

[0102] Furthermore, when the phase difference PD is T×3.7, the value of the status signal OUT reaches the upper limit of 64 at the twelfth rising edge of the reference signal CLK, and the digital value of time TD becomes 519 after the fourteenth rising edge of the reference signal CLK.

[0103] Figure 10 It is shown in Figure 9 A graph showing the relationship between the phase difference PD and the digital time TD after the number of state transitions in the transition state output device 1 reaches the upper limit. (See figure) Figure 10 As shown, the digital time values ​​TD for phase differences PD of T×1.5, T×1.7, T×2.7, and T×3.7 are 377, 391, 455, and 519, respectively, and the differences ΔTD between the digital time values ​​TD are +14, +64, and +64, respectively. Figure 9In the example, since the constant value a is positive, the value of the weighting coefficient signal WC increases as time goes by. Moreover, since the phase difference PD is larger, the time when the number of state transitions of the transition state output device 1 reaches the upper limit of 64 is later. Therefore, when the phase difference PD only increases by one cycle of the reference signal CLK time T, the time digital value TD only increases by the upper limit of the number of state transitions, i.e., 64.

[0104] 1-1-5. Effects

[0105] In the time-to-digital converter 100 of the first embodiment described above, in the transition state output device 1, since the ring oscillator circuit 10 has an extremely simple structure, the period of state change is approximately constant. Furthermore, since the state machine 20 is not included in the oscillation ring of the ring oscillator circuit 10, and its state changes according to the state change of the ring oscillator circuit 10, the period of state change of the state machine 20 is also approximately constant. Therefore, the duration of each state of the ring oscillator circuit 10 and the state machine 20 is approximately constant. Therefore, according to the time-to-digital converter 100 of the first embodiment, in the transition state output device 1, since the difference in the duration of each internal state obtained from the state information including the signal output from the ring oscillator circuit 10 and the signal output from the state machine 20 can be reduced, the arithmetic unit 50 does not perform calculations to correct the number of transitions of the internal states, and can calculate a time digital value TD with higher accuracy. Furthermore, since the arithmetic unit 50 does not need to perform correction calculations, the time from the input trigger signal TRG to the calculation of the time digital value TD is shortened, and the effort required to generate correction information for correction calculations is not expended.

[0106] Furthermore, in the time-to-digital converter 100 of the first embodiment, in the transition state output device 1, if the internal state changes synchronously with the timing of the state change of the ring oscillating circuit 10, the timing of the state change of the ring oscillating circuit 10 corresponds one-to-one with the timing of the internal state change. Therefore, according to the time-to-digital converter 100 of the first embodiment, in the transition state output device 1, since the period of the state change of the ring oscillating circuit 10 is approximately constant, the duration of each internal state is approximately constant, and the difference in the duration of each internal state can be further reduced.

[0107] Furthermore, in the time-to-digital converter 100 of the first embodiment, in the transition state output device 1, since the time from transitioning from the first internal state to the second internal state to transitioning back to the first internal state is longer than the time interval for updating the state information held by the transition state acquisition unit 30, the transition state acquisition unit 30 can acquire the state information before the state transition cycle is completed once. Therefore, according to the time-to-digital converter 100 of the first embodiment, the calculation unit 50 does not need to determine the number of times the internal state cycles once during the period from acquiring the state information from the transition state acquisition unit 30 to acquiring the next state information, thus simplifying the processing of the calculation unit 50.

[0108] Furthermore, in the time-to-digital converter 100 of the first embodiment, in the transition state output device 1, since the Hamming distance between the state information before and after the internal state transition is 1, the transition state acquisition unit 30 can acquire state information corresponding to either of the two states before and after the state transition. Therefore, according to the time-to-digital converter 100 of the first embodiment, in the transition state output device 1, the possibility of acquiring incorrect state information is reduced, and the calculation unit 50 can calculate the time digital value TD with high accuracy.

[0109] Furthermore, in the time-to-digital converter 100 of the first embodiment, whenever a time event triggering the signal TRG is generated, the counting unit 60, the count value holding unit 70, and the accumulator 80 in the arithmetic unit 50 can operate without dead time because they are not reset, thus achieving a higher noise reduction effect based on Δ∑ modulation. Therefore, according to the time-to-digital converter 100 of the first embodiment, in the transition state output device 1, since the noise component caused by small differences in the duration of each internal state is shifted to the high-frequency side by the noise reduction effect, the arithmetic unit 50 can calculate a higher time digital value TD with a S / N ratio.

[0110] 1-2. Second Implementation Method

[0111] Hereinafter, the time-to-digital converter of the second embodiment will be described using the same reference numerals as the first embodiment, and descriptions that are repeated in the first embodiment will be omitted or simplified. The descriptions will mainly focus on the differences from the first embodiment.

[0112] Figure 11 This is a functional block diagram illustrating the time-to-digital converter 100 according to the second embodiment. (As shown...) Figure 11 As shown, similar to the first embodiment, the time-to-digital converter 100 of the second embodiment includes a transition state output device 1 and an arithmetic unit 50, and generates a time digital value TD corresponding to the phase difference between the time event of the reference signal CLK and the time event of the trigger signal TRG.

[0113] The transition state output device 1 includes a ring oscillation circuit 10, a state machine 20, a transition state acquisition unit 30, an internal state calculation unit 40, and a multi-stage delay line 200. Since the functions of the ring oscillation circuit 10 and the state machine 20 are the same as in the first embodiment, their description is omitted.

[0114] Similar to the first embodiment, the ring oscillation circuit 10 starts oscillating based on the trigger signal TRG, and the state machine 20 changes state according to the state changes of the ring oscillation circuit 10.

[0115] The multi-stage delay line 200 is configured to connect multiple delay elements. A signal output from the ring oscillator circuit 10 is input to the multi-stage delay line 200. The signal input to the multi-stage delay line 200 is transmitted through the multiple delay elements.

[0116] The transition state acquisition unit 30 acquires and maintains state information, including signals output from the ring oscillator circuit 10, signals output from the state machine 20, and signals output from the multi-stage delay line 200, in sync with the reference signal CLK.

[0117] Similar to the first embodiment, the internal state calculation unit 40 calculates the internal state corresponding to the number of state changes of the ring oscillation circuit 10 based on the state information held by the transition state acquisition unit 30. Furthermore, the transition state output device 1 outputs n+1 bits of state information OUT[n: 0] representing the internal state calculated by the internal state calculation unit 40. n is any integer greater than or equal to 0.

[0118] Similar to the first embodiment, the arithmetic unit 50 calculates the number of transitions of the internal state based on the state signal OUT[n: 0], and calculates the digital time value TD corresponding to the time event of the trigger signal TRG based on the number of transitions. Furthermore, since the structure of the arithmetic unit 50 is the same as in the first embodiment, its illustrations and descriptions are omitted.

[0119] Figure 12 This is a diagram illustrating a structural example of the transfer state output device 1 included in the time-to-digital converter 100 of the second embodiment. Figure 12 In the example, the transition state output device 1 includes a logic AND circuit 11, a logic inversion circuit 12, a traveling wave counter 13, a stop control circuit 14, an XOR circuit 15, a Gray code counter 21, q+1 D flip-flops 31-0 to 31-q, a register 32, a decoder 41, a decoder 42, and q delay elements 201-1 to 201-q. q is an integer greater than 2.

[0120] Since the functions of the AND circuit 11, the inverted logic circuit 12, the ripple counter 13, the stop control circuit 14, the XOR circuit 15, the Gray code counter 21, the register 32, and the decoder 41 are the same as those in the first embodiment, their descriptions are omitted.

[0121] q delay elements 201-1 to 201-q are chained together to form a multi-stage delay line 200. The multi-stage delay line 200 has one input and q outputs. Such a multi-stage delay line 200 is also called a tapped delay line. Delay elements 201-1 to 201-q are respectively buffer elements and logic inversion elements. Since the delay times of delay elements 201-1 to 201-q are expected to be approximately equal, the same type of element is used as delay elements 201-1 to 201-q. In the following description, all delay elements 201-1 to 201-q will be explained as buffer elements.

[0122] The input terminal of the first delay element 201-1 of the multi-stage delay line 200 becomes the input terminal of the multi-stage delay line 200. Furthermore, the output terminals of each of the delay elements 201-1 to 201-q become the q output terminals of the multi-stage delay line 200. Signals D1 to Dq are output sequentially from the input terminal side of the multi-stage delay line 200 from the q output terminals of the multi-stage delay line 200.

[0123] An oscillation signal D0 is input to the input terminal of the multi-stage delay line 200. The oscillation signal D0 changes from a low level to a high level, and the high-level signal D0 is transmitted in the delay element 201-1, thereby causing the signal D1 to change from a low level to a high level. Furthermore, for each integer i greater than 1 and less than q, the high-level signal Di-1 is transmitted in the delay element 201-i, thereby causing the signal Di to change from a low level to a high level. That is, the high-level signal is transmitted sequentially in the delay elements 201-1 to 201-q, and the signals D1 to Dq sequentially change from a low level to a high level.

[0124] Similarly, the oscillation signal D0 changes from a high level to a low level, and the low-level signal D0 is transmitted in the delay element 201-1, thereby causing the signal D1 to change from a high level to a low level. Furthermore, for each integer i above 1 and below q, the low-level signal Di-1 is transmitted in the delay element 201-i, thereby causing the signal Di to change from a high level to a low level. That is, the low-level signals are transmitted sequentially in the delay elements 201-1 to 201-q, and the signals D1 to Dq sequentially change from a high level to a low level.

[0125] D flip-flops 31-0 acquire the oscillation signal D0 synchronously with the rising edge of the reference signal CLK, and hold the signal S0 corresponding to the value of the oscillation signal D0. Furthermore, for each integer i greater than 1 and less than q, D flip-flops 31-i acquire the signal Di output from the delay element 201-i synchronously with the rising edge of the reference signal CLK, and hold the signal Si corresponding to the value of signal Di. Since the oscillation signal D0 represents the state of the ring oscillation circuit 10, the q signals D1 to Dq represent the state of the multi-stage delay line 200, and the Gray code signal G[k:0] represents the state of the Gray code counter 21 constituting the state machine 20, the transition state acquisition unit 30 is constructed by D flip-flops 31-0 to 31-q and register 32.

[0126] Decoder 42 decodes the p+q+2-bit signal consisting of the signals S0 to Sq held by q+1 D flip-flops 31-0 to 31-q respectively and the p+1-bit decoded signal dec[p:0] output from decoder 41, and outputs the n+1-bit decoded signal dec2[n:0]. p and n are any integers greater than or equal to 1.

[0127] Since signal S0 represents the state of the ring oscillator circuit 10 at the rising edge of the reference signal CLK, and signal g[k:0] represents the state of the state machine 20 at the rising edge of the reference signal CLK, the decoded signal dec2[n:0] obtained by decoding the signal composed of signal S0 and decoded signal dec[p:0] is equivalent to the signal representing the internal state of the transition state output device 1 at the rising edge of the reference signal CLK. That is, the internal state calculation unit 40 is composed of decoder 41 and decoder 42.

[0128] Furthermore, the transition state output device 1 outputs the decoded signal dec2[n:0] as the state signal OUT[n:0].

[0129] Figure 13 as well as Figure 14 This is a diagram illustrating an example of the truth table of decoder 42. Figure 13 as well as Figure 14 In the example, p = 2, q = 7, and n = 5. Figure 13 It is a truth table of the decoded signal dec2[5:0] with values ​​from 0 to 31. Figure 14 This is a truth table of values ​​from 32 to 63 for the decoded signal dec2[5:0]. Figure 13 as well as Figure 14 In this context, 0 represents a low level and 1 represents a high level. Furthermore, the values ​​of the decoding signal dec[2:0] are set according to... Figure 4The truth table shown is used to obtain the values. In addition, P0 is a function that returns the number of signals among signals S1 to S7 whose logic level is consistent with signal S0. Let's say that the value of the decoded signal dec0[2:0] is obtained by function P0.

[0130] exist Figure 13 as well as Figure 14 In the example, the value of the decoding signal dec2[5:0] is the value obtained by multiplying the value of the decoding signal dec[2:0] by eight times and adding the value of the decoding signal dec0[2:0]. The decoding signal dec2[5:0] is equivalent to the signal representing the internal state of the rising edge of the reference signal CLK. Whenever the state of the ring oscillator circuit 10 or the state of the multi-stage delay line 200 changes, the value of the internal state increases from 0 to 63, and the value of the internal state returns to 0 after the next 63. That is, in Figure 13 as well as Figure 14 In the example, relative to Figure 4 For example, define eight times the sixty-four internal states.

[0131] Moreover, in Figure 13 as well as Figure 14 In the example, the sixty-four internal states transition sequentially at either the timing of a change in the logic level of the oscillation signal D0 or the timing of a change in the logic level of the signals D1 to D7 output from the multi-stage delay line 200. Since the period of the oscillation signal D0 is approximately constant, the delay times of the q delay elements 201-1 to 201-q are approximately equal, thus reducing the difference in the duration of the sixty-four internal states. However, when the time from the change in the logic level of the delay element 201-q of the last stage of the multi-stage delay line 200 to the transition of the ring oscillation circuit 10 to the next state is long, the duration of the eight internal states with the values ​​7, 15, 23, 31, 39, 47, 55, and 63 of the decoded signal dec2[n:0] is longer than that of the other fifty-six internal states. Therefore, the frequency of the internal states acquired by the transition state acquisition unit 30 will deviate. Therefore, the time from the state transition of the last stage delay element 201-q of the multi-stage delay line 200 to the transition of the ring oscillation circuit 10 to the next state is preferably less than the average value of the delay times of the plurality of delay elements 201-1 to 201-q included in the multi-stage delay line 200. When the delay times of delay elements 201-1 to 201-q are equal, the average value is equal to the individual delay times of delay elements 201-1 to 201-q. In particular, when this time coincides with the average value of the delay times of the plurality of delay elements 201-1 to 201-q, the measurement times of the sixty-four internal states are approximately equal, and the frequencies of the internal states acquired by the transition state acquisition unit 30 hardly deviate.

[0132] in addition,Figure 13 as well as Figure 14 The truth table is valid on the condition that the delay time of the multi-stage delay line 200 is less than half the period of the oscillation signal D0. The delay time of the multi-stage delay line 200 is the time from when the logic level of the oscillation signal D0 changes until the logic level of the signal Dq output from the last stage delay element 201-q changes according to the change in the logic level of the oscillation signal D0.

[0133] Figure 15 as well as Figure 16 It is shown Figure 13 as well as Figure 14 A timing diagram of an example of the operation of the transition state output device 1 when the truth table is true. Figure 15 An example is the ideal case where the time until the ring oscillator circuit 10 transitions to the next state coincides with the average delay time of the delay elements 201-1 to 201-q. Furthermore, Figure 16 An example is the case where the time until the ring oscillator circuit 10 transitions to the next state is greater than the average delay time of the delay elements 201-1 to 201-q. Figure 15 as well as Figure 16 In the example, the period of the reference signal CLK is 2.5 times the period of the oscillation signal D0. Furthermore, since the internal state transitions sixteen times during one period of the oscillation signal D0, the internal state transitions forty times during one period of the reference signal CLK. Therefore, in Figure 15 Examples and Figure 16 In the example, although the values ​​of the status signals OUT[5:0] are different, during the period when the enable signal EN is high, the value of the status signals OUT[5:0] changes forty times at the rising edge of the reference signal CLK.

[0134] Thus, in Figure 15 as well as Figure 16 In the context, the change in the value of the state signal OUT[5:0] is relative to... Figure 5 The example becomes eight times, or 40. Therefore, the resolution of the time digital value TD generated by the arithmetic unit 50 is increased by eight times. Generally speaking, the multi-stage delay line 200 includes q delay elements 201-1 to 201-q, so the resolution of the time digital value TD becomes q+1 times that of the case excluding the multi-stage delay line 200.

[0135] However, if the condition that the delay time of the multi-stage delay line 200 is less than half the period of the oscillation signal D0 is not met, that is, if the delay time of the multi-stage delay line 200 is more than half the period of the oscillation signal D0, the logic level of the oscillation signal D0 changes again before the logic level of the signal Dq output from the last stage delay element 201-q changes according to the change in the logic level of the oscillation signal D0.

[0136] Figure 17 as well as Figure 18 This is a diagram illustrating an example of the truth table of decoder 42 that defines such internal states. Figure 17 as well as Figure 18 In the example, p = 2, q = 7, and n = 6. Figure 17 It is a truth table of values ​​from 1 to 32 for the decoded signal dec2[6:0]. Figure 18 This is a truth table of values ​​from 33 to 64 for the decoded signal dec2[5:0]. Figure 17 as well as Figure 18 In this context, 0 represents a low level and 1 represents a high level. Furthermore, the values ​​of the decoding signal dec[2:0] are set according to... Figure 4 The truth table shown is used to obtain the values. Furthermore, P0 is a function that returns the number of signals S1-S3 whose logic level matches that of signal S0; P4 is a function that returns the number of signals S5-S7 whose logic level matches that of signal S4; and x4 is a function that returns 4 when the logic levels of signals S0 and S4 match, and 0 when they do not. Moreover, the value of the decoded signal dec0[3:0] is assumed to be obtained by the sum of functions P0, P4, and x4.

[0137] exist Figure 17 as well as Figure 18 In the example, the value of the decoding signal dec2[6:0] is the value obtained by multiplying the value of the decoding signal dec[2:0] by eight times and adding the value of the decoding signal dec0[3:0]. The decoding signal dec2[6:0] is equivalent to the signal representing the internal state of the rising edge of the reference signal CLK. Whenever the state of the ring oscillator circuit 10 or the state of the multi-stage delay line 200 changes, the value of the internal state increases from 0 to 64, and the value of the internal state returns to 0 after 63. That is, in Figure 17 as well as Figure 18 In the example, also with Figure 13 as well as Figure 14 Similarly, sixty-four internal states are defined.

[0138] Furthermore, during the period from the change in the logic level of signal D5 output from delay element 201-5 based on the change in the logic level of oscillation signal D0 until the change in the logic level of signal D6 output from delay element 201-6, Figure 17 as well as Figure 18 The truth table is valid only if the logic level of the oscillation signal D0 changes again.

[0139] Figure 19 It is shown Figure 17 as well as Figure 18 A timing diagram illustrating an example of the operation of the transition state output device 1 when the truth table is true. Figure 19 In the example, the period of the reference signal CLK is 2.5 times the period of the oscillation signal D0. Furthermore, since the internal state transitions sixteen times during one period of the oscillation signal D0, it transitions forty times during one period of the reference signal CLK. Therefore, during the period when the enable signal EN is high, the value of the state signal OUT[6:0] changes forty times at the rising edge of the reference signal CLK.

[0140] However, since the ring oscillation circuit 10 and the multi-stage delay line 200 have temperature characteristics, the period of the oscillation signal D0 and the delay time of the delay elements 201-1 to 201-q change according to the temperature. Therefore, while ensuring a wide operating temperature range for the time-to-digital converter 100, the condition that the logic level of the oscillation signal D0 changes again according to the temperature during the period from the change in the logic level of signal D5 to the change in the logic level of signal D6 is not satisfied. Figure 17 as well as Figure 18 The truth table is invalid.

[0141] For example, at a certain temperature, the period of the oscillation signal D0 and the delay time of the delay elements 201-1 to 201-7 become shorter. In the internal state where signals D0 to D5 are low and signals D6 and D7 are high, when signal D6 changes to low before signal D0 changes to high, the system transitions to the internal state where signals D0 to D6 are low and signal D7 is high. Figure 17 as well as Figure 18 The truth table does not include the internal state after the transition. However, as Figure 17 as well as Figure 18As in the example, if the value of the decoded signal dec2[6:0] is eight times the value of the decoded signal dec[2:0] plus the value of the decoded signal dec0[2:0] obtained by summing the functions P0, P4, and x4, then there will be no problem. For example, in the internal state where the value of the decoded signal dec[2:0] is 0, signals D0-D5 are low, and signals D6 and D7 are high, the value of the decoded signal dec2[6:0] becomes 8 when the rising edge of the reference signal CLK arrives. Furthermore, in the next internal state where the value of the decoded signal dec[2:0] is 0, signals D0-D6 are low, and signal D7 is high, the value of the decoded signal dec2[6:0] becomes 9 when the rising edge of the reference signal CLK arrives. Furthermore, in the next internal state where the value of the decoding signal dec[2:0] is 0, signal D0 is high, signals D1 to D6 are low, and signal D7 is high, the value of the decoding signal dec2[6:0] becomes 10 when the rising edge of the reference signal CLK arrives. Therefore, when the transition state acquisition unit 30 acquires the internal state before or after the transition, since the difference in the value of the decoding signal dec2[6:0] is always 1, the arithmetic unit 50 can correctly perform the state transition number calculation, and therefore no problem occurs. Even if the period of the oscillation signal D0 and the delay time of the delay elements 201-1 to 201-7 are further shortened, no problem will occur either.

[0142] Thus, regardless of the timing before the state transition of the delay element 201-q in the last stage of the multi-stage delay line 200, even if the ring oscillator circuit 10 transitions to the next state, no problem will occur, depending on the temperature change. Furthermore, if the ring oscillator circuit 10 transitions to the next state before the state transition of the delay element 201-q, the frequency deviation of the internal state acquired by the transition state acquisition unit 30 will also be small. Therefore, even if a temperature change occurs, it is desirable that the ring oscillator circuit 10 will necessarily transition to the next state before the state transition of the delay element 201-q in the last stage of the multi-stage delay line 200.

[0143] Furthermore, when the period of the oscillation signal D0 and the delay times of the delay elements 201-1 to 201-7 become even shorter, the logic level of the oscillation signal D0 changes again after the logic level of signal D7 changes, based on the change in the logic level of the oscillation signal D0. In other words, the delay time of the multi-stage delay line 200 is smaller than half the period of the oscillation signal D0. In this case, instead of Figure 17 as well as Figure 18 The truth table is defined as follows: Figure 20 as well as Figure 21 The truth table. In Figure 20 as well as Figure 21In the example, whenever the state of the ring oscillator circuit 10 or the state of the multi-stage delay line 200 changes, the value of the internal state increases sequentially from 3 to 66, and the value of the internal state returns to 3 after reaching 66. That is, in Figure 20 as well as Figure 21 In the example, also with Figure 17 as well as Figure 18 Similarly, sixty-four internal states are defined, and since the value of the decoded signal dec2[6:0] increases by one when an internal state makes a transition, there is no problem even if the ring oscillator circuit 10 moves to the next state after the state transition of the delay element 201-7 of the last stage of the multi-stage delay line 200.

[0144] Figure 22 It is shown Figure 20 as well as Figure 21 A timing diagram illustrating an example of the operation of the transition state output device 1 when the truth table is true. Figure 22 In the example, the period of the reference signal CLK is 2.5 times the period of the oscillation signal D0. Furthermore, since the internal state transitions sixteen times during one period of the oscillation signal D0, it transitions forty times during one period of the reference signal CLK. Therefore, during the period when the enable signal EN is high, the value of the state signal OUT[6:0] changes forty times at the rising edge of the reference signal CLK.

[0145] However, problems may arise when the period of the oscillation signal D0 and the delay time of the delay elements 201-1 to 201-q increase according to temperature changes. At a certain temperature, the period of the oscillation signal D0 and the delay time of the delay elements 201-1 to 201-7 increase. In the internal state where signals D0 to D4 are low and signals D5 to D7 are high, when signal D0 changes to a high level before signal D5 changes to a low level, the system transitions to an internal state where signals D1 to D4 are low and signals D0, D5, and D7 are high. For example, when the value of the decoded signal dec[2:0] is 0, in the internal state before the transition, when the rising edge of the reference signal CLK arrives, the value of the decoded signal dec2[6:0] becomes 7. In the internal state after the transition, when the rising edge of the reference signal CLK arrives, the value of the decoded signal dec2[6:0] becomes 8. Since the difference is 1, no problem occurs. However, at a certain temperature, the period of the oscillation signal D0 and the delay time of the delay elements 201-1 to 201-7 become longer. In the internal state where signals D0 to D3 are low and signals D4 to D7 are high, when signal D0 changes to a high level before signal D4 changes to a low level, the system transitions to an internal state where signals D1 to D3 are low and signals D0, D4, and D7 are high. For example, in the internal state before the transition, when the value of the decoding signal dec[2:0] is 0, the value of the decoding signal dec2[6:0] becomes 6 when the rising edge of the reference signal CLK arrives. In the internal state after the transition, the value of the decoding signal dec[2:0] becomes 1. Therefore, when the rising edge of the reference signal CLK arrives, the value of the decoding signal dec2[6:0] becomes 15. Since the difference is 9, a problem will occur.

[0146] Based on the above examination, for example, within the temperature range that guarantees the operation of the time-to-digital converter 100, when the delay time of the multi-stage delay line 200 becomes maximum, such as Figure 17 as well as Figure 18 If the truth table holds true, then adjusting the delay time of the multi-stage delay line 200 will not cause any problems.

[0147] The time-to-digital converter 100 according to the second embodiment described above has the same effect as the time-to-digital converter 100 of the first embodiment.

[0148] Furthermore, according to the time-to-digital converter 100 of the second embodiment, in the transition state output device 1, since the number of internal states can be increased according to the number of delay elements included in the multi-level delay line 200, the resolution of the time digital value TD calculated by the arithmetic unit 50 can be improved.

[0149] Furthermore, in the time-to-digital converter 100 of the second embodiment, in the transition state output device 1, the multi-stage delay line 200 is not included in the oscillation ring of the ring oscillation circuit 10, and its state changes according to the state changes of the ring oscillation circuit 10. Therefore, if the delay time of the plurality of delay elements 201-1 to 201-q is set to be approximately constant, the duration of each state of the multi-stage delay line 200 is approximately constant. Therefore, according to the time-to-digital converter 100 of the second embodiment, in the transition state output device 1, the difference in the duration of each internal state obtained from the state information including the signal output from the ring oscillation circuit 10, the signal output from the state machine 20, and the signal output from the multi-stage delay line 200 can be reduced.

[0150] Furthermore, according to the time-to-digital converter 100 of the second embodiment, in the transition state output device 1, if the time from the state transition of the delay element 201-q of the last stage of the multi-stage delay line 200 to the transition of the ring oscillator circuit 10 to the next state is less than the average of the delay times of the multiple delay elements 201-1 to 201-q included in the multi-stage delay line 200, then since the duration of the internal state before the state of the ring oscillator circuit 10 is about to change will not be longer than the duration of other internal states, the difference in the duration of each internal state can be further reduced.

[0151] Furthermore, according to the time-to-digital converter 100 of the second embodiment, in the transition state output device 1, if the ring oscillator circuit 10 is transferred to the next state before the state transition of the delay element 201-q of the last stage of the multi-stage delay line 200, the internal state can be accurately calculated even if the period of the state change of the ring oscillator circuit 10 and the period of the state change of the multi-stage delay line 200 change due to temperature changes or the like.

[0152] 1-3. Third Implementation Method

[0153] Hereinafter, regarding the time-to-digital converter of the third embodiment, the same reference numerals are used to mark the same structural elements as in the first or second embodiment, and descriptions that are repeated in the first or second embodiment are omitted or simplified. The description mainly focuses on the differences from the first and second embodiments.

[0154] Due to the structural example of the time-to-digital converter 100 in the third embodiment and Figure 1The same applies, therefore its illustration is omitted. That is, in the time-to-digital converter 100 of the third embodiment, the structure of the transition state output device 1 is the same as that of the first embodiment. However, unlike the time-to-digital converter 100 of the first embodiment, in the time-to-digital converter 100 of the third embodiment, after the input trigger signal TRG, the ring oscillation circuit 10 does not stop, and when the number of transitions of the internal state of the transition state output device 1 exceeds the threshold TH, the number of transitions is used as the threshold TH to calculate the digital time value TD.

[0155] Figure 23 This is a diagram illustrating an example of the structure of the transfer state output device 1 included in the time-to-digital converter 100 of the third embodiment. Figure 23 In the example, the transition state output device 1 includes a logic AND circuit 11, a logic inversion circuit 12, a Gray code counter 21, a D flip-flop 31, a register 32, and a decoder 41.

[0156] The logic AND circuit 11 outputs a trigger signal TRG, which is then ANDed with the signal output from the logic inversion circuit 12. The signal output from the logic AND circuit 11 becomes low when the trigger signal TRG is low, and becomes the same logic level as the signal output from the logic inversion circuit 12 when the trigger signal TRG is high.

[0157] The logic inverting circuit 12 outputs a signal obtained by inverting the logic level of the signal output from the logic AND circuit 11. Therefore, when the trigger signal TRG is high, the logic level of the signal output from the logic AND circuit 11 alternates between low and high levels. That is, the logic AND circuit 11 and the logic inverting circuit 12 constitute a ring oscillation circuit 10, and the ring oscillation circuit 10 outputs the signal output from the logic AND circuit 11 as the oscillation signal D0.

[0158] Since the functions of Gray code counter 21, D flip-flop 31, register 32 and decoder 41 are the same as in the first embodiment, their descriptions are omitted.

[0159] Figure 24 This is a timing diagram illustrating an example of the operation of the transition state output device 1. Figure 24 In the example, when the trigger signal TRG changes from low to high, the enable signal EN changes from low to high, and the oscillation of the ring oscillator circuit 10 begins. Afterward, the ring oscillator circuit 10 continues to oscillate while the trigger signal TRG is high, and the oscillation stops when the trigger signal TRG changes from high to low.

[0160] The truth table of decoder 41 is as follows: Figure 3In this case, the output Case 1 state signal OUT[3:0] is given in the truth table of decoder 41. Figure 4 In this case, the status signal OUT[2:0] for Case2 is output. Figure 24 In the example, the period of the reference signal CLK is 2.5 times the period of the oscillation signal D0. Furthermore, in Figure 3 In the example, since the internal state transitions four times during one cycle of the oscillation signal D0, the internal state transitions ten times during one cycle of the reference signal CLK. Therefore, during the period when the enable signal EN is high, the value of the state signal OUT[3:0] of Case1 changes ten times at the rising edge of the reference signal CLK. Furthermore, in Figure 4 In the example, since the internal state transitions twice during one cycle of the oscillation signal D0, the internal state transitions five times during one cycle of the reference signal CLK. Therefore, during the period when the enable signal EN is high, the value of the state signal OUT[2:0] of Case2 changes five times at the rising edge of the reference signal CLK.

[0161] Figure 25 This diagram illustrates a structural example of the counting unit 60 included in the arithmetic unit 50 of the time-to-digital converter 100 in the third embodiment. The counting unit 60 includes a register 61, a subtractor 62, an accumulator 63, a multiplier 64, and a virtualization unit 65.

[0162] Since the functions of register 61, subtractor 62 and accumulator 63 are the same as in the first embodiment, their descriptions are omitted.

[0163] The signal C1 output from the subtractor 62 is input to the virtualization unit 65. As described above, the value of the signal C1 output from the subtractor 62 corresponds to the number of internal state transitions of the state output device 1 within the most recent cycle of the reference signal CLK. The virtualization unit 65 calculates the number of internal state transitions of the state output device 1 after the rising or falling edge of the trigger signal TRG by accumulating the value of the signal C1 synchronously with the reference signal CLK. Furthermore, if the calculated number of transitions does not exceed the threshold TH, the virtualization unit 65 directly virtualizes the state signal OUT into the signal OUT' and outputs the signal C2, which is the difference between the two signals OUT'. In this case, the values ​​of the signals C1 and C2 are equal.

[0164] If the calculated number of transitions exceeds the threshold TH, the virtualization unit 65 virtualizes the status signal OUT into a signal OUT' after replacing it with the threshold TH, and outputs a signal C2 that is equivalent to the difference between the signal OUT' and the signal C2.

[0165] Multiplier 64 multiplies the value of signal C2 output from virtualization unit 65 with the value of weighting coefficient signal WC output from accumulator 63 to calculate count value CNT. Count value CNT is output from counting unit 60.

[0166] exist Figure 25 The illustrations and explanations are omitted, but when the state transition of the state output device 1 stops, a reset signal to initialize the value to 0 can be input to the register 61 and the accumulator 63.

[0167] Figure 26 This is a graph showing the relationship between the phase difference PD of the time events of the reference signal CLK and the trigger signal TRG, and the digital value TD of the time. Figure 26 The values ​​of the status signal OUT, C1, OUT', C2, weighting coefficient signal WC, count value CNT, and count value DCNT are also shown. Furthermore, in Figure 26 In this example, the threshold TH is 64, and the constant value a is 1. Furthermore, T is the time of one cycle of the reference signal CLK.

[0168] like Figure 26 As shown, whenever a time event occurs with the reference signal CLK, signals OUT' and C2 are generated based on the state signal OUT and signal C1. Further, a count value CNT is generated based on signal C2 and the weighting coefficient signal WC. The count value DCNT, which holds the count value CNT, is accumulated, while the digital time value TD is incremented. When the time event of the reference signal CLK is taken as the 0th rising edge, with a phase difference PD of T×1.5, after the tenth rising edge, the value of the state signal OUT, which indicates the number of transitions in the internal state of the transition state output device 1 after the time event of the trigger signal TRG, exceeds the threshold TH, i.e., 64. Therefore, after the tenth rising edge of the reference signal CLK, signal OUT' is 64, and after the eleventh rising edge of the reference signal CLK, signal C2 is 0. Moreover, after the twelfth rising edge of the reference signal CLK, the digital time value TD becomes 377.

[0169] Furthermore, when the phase difference PD is T×1.7, after the tenth rising edge of the reference signal CLK, since the value of the status signal OUT exceeds the threshold TH (64), the signal OUT' is 64. After the eleventh rising edge of the reference signal CLK, the signal C2 is 0. Moreover, after the twelfth rising edge of the reference signal CLK, the digital time value TD becomes 391.

[0170] Furthermore, when the phase difference PD is T×2.7, after the eleventh rising edge of the reference signal CLK, since the value of the status signal OUT exceeds the threshold TH (64), the signal OUT' is 64. After the twelfth rising edge of the reference signal CLK, the signal C2 is 0. Moreover, after the thirteenth rising edge of the reference signal CLK, the digital time value TD becomes 455.

[0171] Furthermore, with a phase difference PD of T×3.7, after the twelfth rising edge of the reference signal CLK, since the value of the status signal OUT exceeds the threshold TH (64), the signal OUT' is 64. After the thirteenth rising edge of the reference signal CLK, the signal C2 is 0. Moreover, after the fourteenth rising edge of the reference signal CLK, the digital time value TD becomes 519.

[0172] Will Figure 26 and Figure 9 Comparing the phase differences PD, the digital time value TD remains the same regardless of whether it is T×1.5, T×1.7, T×2.7, or T×3.7. Therefore, even in the time-to-digital converter 100 of the third embodiment, as... Figure 10 As shown, the time digital value TD difference ΔTD is +14, +64, and +64 respectively. When the phase difference PD only increases the time T of one cycle of the reference signal CLK, the time digital value TD only increases the threshold TH, which is 64.

[0173] The time-to-digital converter 100 according to the third embodiment described above has the same effect as the time-to-digital converter 100 of the first embodiment.

[0174] Furthermore, according to the time-to-digital converter 100 of the third embodiment, since the number of transitions in the internal state of the transition state output device 1 exceeds the threshold TH, the arithmetic unit 50 calculates the time digital value TD using the number of transitions as the threshold TH, thus reducing the number of bits in the time digital value TD. In addition, since the transition state output device 1 does not require a circuit to stop the oscillation of the ring oscillation circuit 10, the size of the transition state output device 1 can be reduced.

[0175] 1-4. Fourth Implementation Method

[0176] Hereinafter, regarding the time-to-digital converter of the fourth embodiment, the same reference numerals are used to mark the same structural elements as in any of the first to third embodiments, and descriptions that are repeated in any of the first to third embodiments are omitted or simplified. The descriptions will mainly focus on the contents that are different from any of the first to third embodiments.

[0177] Due to the structural example of the time-to-digital converter 100 in the fourth embodiment and Figure 11 The same applies, therefore its illustration is omitted. However, in the time-to-digital converter 100 of the fourth embodiment, unlike the time-to-digital converter 100 of the second embodiment, the ring oscillation circuit 10 does not stop after the input trigger signal TRG. If the number of transitions of the internal state of the transition state output device 1 exceeds the threshold TH, the number of transitions is used as the threshold TH to calculate the time digital value TD.

[0178] That is, in the time-to-digital converter 100 of the fourth embodiment, the structure of the transfer state output device 1 is the same as that of the second embodiment, and the arithmetic unit 50 is the same as that of the third embodiment.

[0179] Figure 27 This is a diagram illustrating a structural example of the transfer state output device 1 included in the time-to-digital converter 100 according to the fourth embodiment. Figure 27 In the example, the transition state output device 1 includes a logic AND circuit 11, a logic inversion circuit 12, a Gray code counter 21, q+1 D flip-flops 31-0 to 31-q, a register 32, a decoder 41, a decoder 42, and q delay elements 201-1 to 201-q. q is an integer greater than 2.

[0180] The logic AND circuit 11 outputs a trigger signal TRG, which is then ANDed with the signal output from the logic inversion circuit 12. The signal output from the logic AND circuit 11 becomes low when the trigger signal TRG is low, and becomes the same logic level as the signal output from the logic inversion circuit 12 when the trigger signal TRG is high.

[0181] The logic inverting circuit 12 outputs a signal obtained by inverting the logic level of the signal output from the logic AND circuit 11. Therefore, when the trigger signal TRG is high, the logic level of the signal output from the logic AND circuit 11 alternates between low and high levels. That is, the logic AND circuit 11 and the logic inverting circuit 12 constitute a ring oscillation circuit 10, and the ring oscillation circuit 10 outputs the signal output from the logic AND circuit 11 as the oscillation signal D0.

[0182] Since the function of Gray code counter 21 is the same as in the first and second embodiments, its description is omitted. Since the functions of D flip-flops 31-0 to 31-q, register 32, decoder 41, decoder 42, and delay elements 201-1 to 201-q are the same as in the second embodiment, their descriptions are omitted. Furthermore, since the structure of arithmetic unit 50 is the same as in the third embodiment, its description is omitted.

[0183] Figure 28This is a timing diagram illustrating an example of the operation of the transition state output device 1. Figure 28 In the example, when the trigger signal TRG changes from low to high, the enable signal EN changes from low to high, and the oscillation of the ring oscillator circuit 10 begins. Afterward, the ring oscillator circuit 10 continues to oscillate while the trigger signal TRG is high, and the oscillation stops when the trigger signal TRG changes from high to low.

[0184] exist Figure 28 In the example, the period of the reference signal CLK is 2.5 times the period of the oscillation signal D0. Furthermore, since the internal state transitions sixteen times during one period of the oscillation signal D0, the internal state transitions forty times during one period of the reference signal CLK. Therefore, in Figure 28 In the example, during the period when the enable signal EN is high, the value of the status signal OUT[5:0] changes forty times during the rising edge of the reference signal CLK.

[0185] The time-to-digital converter 100 according to the fourth embodiment described above has the same effect as the time-to-digital converter 100 of the second embodiment.

[0186] Furthermore, according to the time-to-digital converter 100 of the fourth embodiment, since the number of transitions in the internal state of the transition state output device 1 exceeds the threshold TH, the arithmetic unit 50 calculates the time digital value TD using the number of transitions as the threshold TH, thus reducing the number of bits in the time digital value TD. In addition, since the transition state output device 1 does not require a circuit to stop the oscillation of the ring oscillation circuit 10, the size of the transition state output device 1 can be reduced.

[0187] 1-5. Fifth Implementation Method

[0188] Hereinafter, regarding the time-to-digital converter of the fifth embodiment, the same reference numerals are used to mark the same structural elements as in any of the first to fourth embodiments, and descriptions that are repeated in any of the first to fourth embodiments are omitted or simplified. The descriptions will mainly focus on the contents that are different from any of the first to fourth embodiments.

[0189] Figure 29 This is a functional block diagram of the time-to-digital converter 100 according to the fifth embodiment. Furthermore, Figure 30 This is another functional block diagram of the time-to-digital converter 100 according to the fifth embodiment. For example... Figure 29 as well as Figure 30 As shown, the time-to-digital converter 100 of the fifth embodiment includes a transfer state output device 1 and an arithmetic unit 50. Figure 29The transition state output device 1 in this embodiment is the same as the transition state output device 1 in the first or third embodiment. Furthermore, Figure 30 The transition state output device 1 in this embodiment is the same as the transition state output device 1 in the second or fourth embodiment.

[0190] Input N trigger signals TRG1 to TRG into the time-to-digital converter 100 N And the reference signal CLK. N is an integer greater than or equal to 2. Additionally, trigger signals TRG1 to TRG... N Each event in time arrives in its sequence at intervals of more than a specified time.

[0191] The transition status output device 1 is based on each trigger signal TRG1 to TRG N Initiate state transition and output state signals OUT[n:0] synchronously with the time event of the reference signal CLK. Input each state signal OUT[n:0] to the arithmetic unit 50.

[0192] The arithmetic unit 50 calculates the number of transitions of the internal state of the transition state output device 1 based on each state signal OUT[n:0], and calculates the number of transitions based on the number of transitions and the trigger signals TRG1 to TRG2. N The time event corresponds to N time numeric values ​​TD1~TD N Furthermore, the arithmetic unit 50 calculates the digital time values ​​TD1 to TD2 respectively. N The difference between any two values ​​in M ​​is the M time digital values ​​TDY1 to TDY2. M M is an integer greater than or equal to 1.

[0193] Figure 31 This is a diagram showing an example of the structure of the arithmetic unit 50. (Example) Figure 31 As shown, the arithmetic unit 50 includes a counting unit 60, a count value holding unit 70, an accumulation unit 80, and a time digital value generation unit 92.

[0194] For each integer i above 1 and below N, the trigger signal TRG i When the time event arrives, the counter 60 outputs a trigger signal TRG. i The corresponding count value is CNT. The counting unit 60 outputs the trigger signal TRG. i After the corresponding count value CNT is reached, the count value CNT held in the counting section 60 is initialized to 0. Following this, the trigger signal TRG is activated. i+1 When the time event arrives, the counter unit 60 outputs the trigger signal TRG. i+1 The corresponding count value is CNT.

[0195] The count value holding unit 70 reads the count values ​​CNT sequentially output from the counting unit 60 in sync with the reference signal CLK, and holds them as count values ​​DCNT.

[0196] The accumulator 80 accumulates each count value DCNT held sequentially in the count value holding unit 70 in sync with the reference signal CLK, thereby sequentially generating a time event and trigger signals TRG1 to TRG1 that are synchronized with the reference signal CLK. N The phase difference of each time event corresponds to N time digital values ​​TD1 to TD2. N In addition, the count value holding unit 70 and the accumulator unit 80 are initialized, for example, by being input with a reset signal (not shown).

[0197] The time digital value generation unit 92 synchronously generates the reference signal CLK based on the trigger signals TRG1 to TRG1. N The corresponding N time digital values ​​TD1~TD N Generate and trigger signals TRG1~TRG N The time interval corresponding to at least two time events, TDY1 to TDY M .

[0198] For example, M = N-1, the digital time value TDY i It can also be related to the trigger signal TRG i+1 The corresponding digital value of time TD i+1 and trigger signal TRG i The corresponding digital value of time TD i The difference.

[0199] Furthermore, the time digital value generation unit 92 can generate time digital values ​​TDY1 to TDY. M Perform the prescribed scaling and output, or convert the time digital values ​​TDY1 to TDY according to the prescribed conversion formula or table information. M Perform the conversion and output.

[0200] Additionally, trigger signals TRG1~TRG N Any of the trigger signals TRG j This is an example of the "first trigger signal", trigger signals TRG1~TRG N Any other trigger signal TRG k This is an example of a "second trigger signal". Furthermore, according to the trigger signal TRG... j The status signal OUT[n:0] output from the transition status output device 1 is an example of "first status information", based on the trigger signal TRG. kThe status signal OUT[n:0] output from the transition status output device 1 is an example of "second status information". Furthermore, according to the trigger signal TRG... j The digital time value TD output from the accumulator 80 j This is an example of a "first-time digital value," based on the trigger signal TRG. k The digital time value TD output from the accumulator 80 k This is an example of a "second time digital value".

[0201] In this embodiment, the timing event of the reference signal CLK and the trigger signals TRG1 to TRG N The timing events are set independently. That is, the timing event of the reference signal CLK is set independently of the timing events of the trigger signals TRG1 to TRG2. N The time events are not synchronized. Furthermore, the digital time values ​​TDY1 to TDY... M Each is connected to the trigger signals TRG1 to TRG N The phase difference between any two time events corresponds to each other. For example, the digital time values ​​TDY1 to TDY2. M Used as a trigger signal TRG1~TRG N It is used to determine the time interval between any two time events.

[0202] The time-to-digital converter 100 according to the fifth embodiment described above has the same effect as the time-to-digital converter 100 of the first to fourth embodiments.

[0203] Furthermore, according to the time-to-digital converter 100 of the fifth embodiment, it is possible to calculate the time-to-digital converter with respect to the trigger signals TRG1 to TRG2. N The time values ​​corresponding to at least two time intervals: TDY1 to TDY M Furthermore, due to the trigger signals TRG1~TRG N The counting unit 60, the count value holding unit 70, and the accumulator 80 are used to generate the digital time values ​​TDY1 to TDY. M Therefore, it is possible to miniaturize the arithmetic unit 50.

[0204] 2. A / D conversion circuit

[0205] 2-1. First Implementation Method

[0206] Figure 32 This is a diagram showing the structure of the A / D conversion circuit 300 according to the first embodiment. (As shown...) Figure 32As shown, the A / D conversion circuit 300 of the first embodiment includes a reference waveform signal generation circuit 102, a comparator 103, and a time-to-digital converter 100. Furthermore, the A / D conversion circuit 300 converts the input analog signal AIN into a digital signal DOUT and outputs it.

[0207] The reference waveform signal generation circuit 102 generates a reference waveform signal REF based on the reference signal CLK. The reference waveform signal REF is a signal in which the voltage changes with the same period as the reference signal CLK; for example, it can be a triangular wave signal, a ramp wave signal, a sine wave signal, a cosine wave signal, etc. Alternatively, the reference waveform signal generation circuit 102 can also generate the reference waveform signal REF based on a signal obtained by frequency division of the reference signal CLK. In this case, the reference waveform signal REF can also be a signal in which the voltage changes with a period obtained by frequency division of the reference signal CLK. By generating the reference waveform signal REF based on a signal obtained by frequency division of the reference signal CLK and suppressing timing fluctuations, the timing accuracy in the time-to-digital converter 100 is improved, resulting in improved A / D conversion accuracy and resolution.

[0208] Comparator 103 compares the voltage of analog signal AIN with the voltage of reference waveform signal REF generated by reference waveform signal generation circuit 102, and outputs trigger signal TRG.

[0209] As described above, the time-to-digital converter 100 calculates the phase difference between the time events of the reference signal CLK and the trigger signal TRG, that is, the digital time value TD corresponding to the time interval between the time events of the reference signal CLK and the trigger signal TRG.

[0210] Furthermore, the A / D conversion circuit 300 outputs a digital signal DOUT based on the time digital value TD. For example, the A / D conversion circuit 300 can output the time digital value TD as a digital signal DOUT, or it can convert the time digital value TD into a digital signal DOUT with a value that changes linearly with respect to the voltage of the analog signal AIN and output it.

[0211] Figure 33 This is a diagram illustrating an example of the waveforms of various signals in the A / D conversion circuit 300 of the first embodiment. Figure 33 In the example, the reference waveform signal REF is a triangular wave signal that becomes the minimum voltage on the rising edge of the reference signal CLK and the maximum voltage on the falling edge of the reference signal CLK. Furthermore, if the voltage of the analog signal AIN is higher than the voltage of the reference waveform signal REF, the trigger signal TRG goes high; if the voltage of the analog signal AIN is lower than the voltage of the reference waveform signal REF, it goes low.

[0212] In Figure 33 the example of, when the voltage values of the analog signal AIN are Va, Vb, and Vc, the time intervals between the rising edge of the reference signal CLK and the rising edge of the trigger signal TRG become ta, tb, and tc, respectively. Moreover, for Va < Vb < Vc, ta < tb < tc, the time interval between the rising edge of the reference signal CLK and the rising edge of the trigger signal TRG changes linearly with respect to the voltage of the analog signal AIN. Therefore, the A / D conversion circuit 300 can output a digital signal DOUT having time digital values TD corresponding to ta, tb, and tc.

[0213] According to the A / D conversion circuit 300 of the first embodiment, by using the time-to-digital converter 100, high precision, high resolution, high-speed processing, low power consumption, miniaturization, etc. can be achieved.

[0214] 2-2. Second Embodiment

[0215] Figure 34 is a diagram showing the structure of the A / D conversion circuit 300 of the second embodiment. As Figure 34 shown, the A / D conversion circuit 300 of the second embodiment includes a sample-and-hold circuit 101, a reference waveform signal generation circuit 102, a comparator 103, and a time-to-digital converter 100, and converts the input analog signal AIN into a digital signal DOUT and outputs it.

[0216] The sample-and-hold circuit 101 samples and holds the voltage of the analog signal AIN in synchronization with the reference signal CLK.

[0217] The reference waveform signal generation circuit 102 generates a reference waveform signal REF based on the reference signal CLK. The reference waveform signal REF is a signal whose voltage changes with the same period as the reference signal CLK. For example, it can also be a triangular wave signal, a ramp wave signal, a sine wave signal, a cosine wave signal, etc. In addition, the reference waveform signal generation circuit 102 can also generate the reference waveform signal REF based on a signal obtained by dividing the reference signal CLK. In this case, the reference waveform signal REF can also be a signal whose voltage changes with a period obtained by dividing the reference signal CLK. By generating the reference waveform signal REF based on a signal obtained by dividing the reference signal CLK and suppressing the fluctuation of the generation timing, the timing accuracy in the time-to-digital converter 100 is improved, and as a result, the accuracy and resolution of the A / D conversion are improved.

[0218] The comparator 103 compares the voltage VH held by the sample-and-hold circuit 101 with the voltage of the reference waveform signal REF generated by the reference waveform signal generation circuit 102, and outputs a trigger signal TRG.

[0219] As described above, the time-to-digital converter 100 calculates the phase difference between the time event of the reference signal CLK and the time event of the trigger signal TRG, that is, the time-to-digital value TD corresponding to the time interval between the time event of the reference signal CLK and the time event of the trigger signal TRG.

[0220] Furthermore, the A / D conversion circuit 300 outputs a digital signal DOUT based on the time-to-digital value TD. For example, the A / D conversion circuit 300 can output the time-to-digital value TD as the digital signal DOUT, or can convert the time-to-digital value TD into a digital signal DOUT having a value that linearly changes with respect to the voltage of the analog signal AIN and output it.

[0221] Figure 35 is a diagram showing an example of waveforms of various signals in the A / D conversion circuit 300 of the second embodiment. In Figure 35 this example, the voltage of the analog signal AIN is sampled and held at each rising edge of the reference signal CLK. In addition, the reference waveform signal REF is a triangular wave signal that becomes the minimum voltage at the rising edge of the reference signal CLK and becomes the maximum voltage at the falling edge of the reference signal CLK. Further, if the voltage VH is higher than the voltage of the reference waveform signal REF, the trigger signal TRG becomes high level, and if the voltage VH is lower than the voltage of the reference waveform signal REF, it becomes low level.

[0222] In Figure 35 this example, when the value of the voltage VH holding the voltage of the analog signal AIN is Va, Vb, Vc, the time intervals between the rising edges of the reference signal CLK and the trigger signal TRG become ta, tb, tc, respectively. And for Va < Vb < Vc, ta < tb < tc, the time interval between the rising edge of the reference signal CLK and the rising edge of the trigger signal TRG linearly changes with respect to the voltage of the analog signal AIN. Therefore, the A / D conversion circuit 300 can output a digital signal DOUT having time-to-digital values TD corresponding to ta, tb, tc.

[0223] According to the A / D conversion circuit 300 of the second embodiment, by using the time-to-digital converter 100, high precision, high resolution, high-speed processing, low power consumption, miniaturization, etc. can be achieved. In addition, according to the A / D conversion circuit 300 of the second embodiment, since the sampling timing is held constant by the sample-and-hold circuit 101, fluctuations in the A / D conversion timing can be reduced.

[0224] The present invention is not limited to this embodiment, and various modifications can be made within the scope of the gist of the present invention.

[0225] The above-described embodiments and modifications are examples and are not intended to limit the scope. For instance, appropriate combinations of the embodiments and modifications may be made.

[0226] This invention includes structures that are substantially the same as those described in the embodiments, for example, structures with the same function, method, and result, or structures with the same purpose and effect. Furthermore, this invention includes structures in which non-essential parts of the structures described in the embodiments have been replaced. Furthermore, this invention includes structures capable of achieving the same effect or purpose as those described in the embodiments. Furthermore, this invention includes structures in which known techniques have been added to the structures described in the embodiments.

[0227] The following content is derived from the above implementation methods and variations.

[0228] One embodiment of a transition state output device includes: a ring oscillation circuit that starts oscillating based on a trigger signal; a state machine that changes state according to state changes of the ring oscillation circuit; a transition state acquisition unit that acquires and maintains state information, including a signal output from the ring oscillation circuit and a signal output from the state machine, synchronously with a reference signal; and an internal state calculation unit that calculates an internal state corresponding to the number of state changes of the ring oscillation circuit based on the state information maintained by the transition state acquisition unit, wherein the time from the internal state transitioning from a first internal state to a second internal state until it transitions back to the first internal state is longer than the time interval for updating the state information maintained by the transition state acquisition unit.

[0229] In this transition state output device, since the ring oscillator circuit has an extremely simple structure, the period of state change is approximately constant. Furthermore, the state machine is not included in the oscillation ring of the ring oscillator circuit, and its state changes according to the state changes of the ring oscillator circuit; therefore, the period of state change of the state machine is also approximately constant. Thus, the duration of each state of the ring oscillator circuit and the state machine is approximately constant. Therefore, according to this transition state output device, the difference in the duration of each internal state obtained from state information including the signal output from the ring oscillator circuit and the signal output from the state machine can be reduced.

[0230] Furthermore, according to this transition state output device, since the time from the transition from the first internal state to the second internal state to the return to the first internal state is longer than the time interval for updating the state information held by the transition state acquisition unit, the transition state acquisition unit can acquire the state information before the state transition cycle is completed once.

[0231] In one embodiment of the transition state output device, the internal state may change synchronously with the timing of the change in the state of the ring oscillation circuit.

[0232] According to this transition state output device, since the timing of the state change of the ring oscillating circuit corresponds one-to-one with the timing of the internal state change, the period of the state change of the ring oscillating circuit is approximately constant, and therefore the duration of each internal state is approximately constant. Therefore, according to this transition state output device, the difference in the duration of each internal state can be further reduced.

[0233] In one embodiment of the transition state output device, the transition state output device may also include a multi-stage delay line, the multi-stage delay line being connected to a plurality of delay elements, and a signal output from the ring oscillation circuit being input to the multi-stage delay line, wherein the state information includes the signal output from the multi-stage delay line.

[0234] According to this transition state output device, the number of internal states can be increased based on the number of delay elements included in the multi-stage delay line.

[0235] Furthermore, in this transition state output device, the multi-stage delay lines are not included in the oscillation ring of the ring oscillator circuit, and their states change according to the state changes of the ring oscillator circuit. Therefore, if the delay times of the multiple delay elements are set to be approximately constant, the duration of each state of the multi-stage delay lines is approximately constant. Thus, according to this transition state output device, it is possible to reduce the differences in the duration of each internal state obtained from state information including the signal output from the ring oscillator circuit, the signal output from the state machine, and the signal output from the multi-stage delay lines.

[0236] In one embodiment of the transition state output device, the time from the state transition of the delay element at the last stage of the multi-stage delay line to the transition of the ring oscillation circuit to the next state can also be below the average delay time of the plurality of delay elements included in the multi-stage delay line.

[0237] According to this transition state output device, since the duration of the internal state before the state of the ring oscillation circuit is about to change is no longer than the duration of other internal states, the difference in the duration of each internal state can be further reduced.

[0238] In one embodiment of the transition state output device, the ring oscillation circuit may also transition to the next state before the state transition of the delay element in the last stage of the multi-stage delay line.

[0239] According to this transition state output device, by performing calculations on the internal state calculation unit, even if the period of state change of the ring oscillator circuit and the period of state change of the multi-stage delay line change due to temperature changes or other reasons, the internal state can be calculated accurately.

[0240] One method of a time-to-digital converter includes: a method of the transition state output device; and an arithmetic unit that calculates the number of transitions of the internal state and calculates a time digital value corresponding to the time event of the trigger signal based on the number of transitions.

[0241] According to this time-to-digital converter, since it has a transition state output device that can reduce the difference in the duration of each internal state, the arithmetic unit does not need to perform calculations to correct the number of transitions of the internal states, and can calculate a higher-precision digital time value. In addition, since the arithmetic unit does not need to perform correction calculations, the time from the input trigger signal to the calculation of the digital time value is shortened, and the effort required to generate correction information for correction calculations is not needed.

[0242] Furthermore, in this time-to-digital converter, since the transition state output device can acquire state information before the state transition cycle is completed, the arithmetic unit does not need to determine the number of times the internal state cycles during the period from acquiring state information from the transition state acquisition unit to acquiring the next state information. Therefore, the processing of the arithmetic unit can be simplified according to this time-to-digital converter.

[0243] In one embodiment of a time-to-digital converter, if the number of transitions in the internal state exceeds a threshold, the arithmetic unit may also use the number of transitions as a threshold to calculate the time digital value.

[0244] According to this time-to-digital converter, since the number of transitions in the internal state exceeds a threshold and the time digital value is calculated using that threshold, the number of bits in the time digital value can be reduced. Furthermore, since a circuit for stopping the oscillation of the ring oscillator circuit is not required, the size of the transition state output device can be reduced.

[0245] In one embodiment of the time-to-digital converter, the trigger signal can be used as the first trigger signal, the state information as the first state information, and the time digital value as the first time digital value. The ring oscillation circuit starts oscillating based on the second trigger signal. After the second trigger signal is input to the ring oscillation circuit, the transition state acquisition unit synchronously acquires and maintains second state information, including the signal output from the ring oscillation circuit and the signal output from the state machine, with the reference signal. The internal state calculation unit calculates the internal state corresponding to the number of state changes of the ring oscillation circuit based on the second state information maintained by the transition state acquisition unit. The arithmetic unit calculates the number of transitions of the internal state and calculates the second time digital value corresponding to the time event of the second trigger signal based on the number of transitions. The arithmetic unit calculates the difference between the first time digital value and the second time digital value.

[0246] Based on this time-to-digital converter, the digital time value corresponding to the time interval between the first trigger signal and the second trigger signal can be calculated.

[0247] An A / D conversion circuit converts an input analog signal into a digital signal and outputs it. The A / D conversion circuit includes: a time-to-digital converter; a reference waveform signal generation circuit that generates a reference waveform signal based on the reference signal; and a comparator that compares the voltage of the analog signal with the voltage of the reference waveform signal and outputs a trigger signal. The A / D conversion circuit outputs the digital signal, which is based on a digital time value calculated by the time-to-digital converter.

[0248] Based on this A / D conversion circuit, by using a time-to-digital converter, it is possible to achieve high precision, high resolution, high-speed processing, low power consumption, and miniaturization.

[0249] An A / D conversion circuit converts an input analog signal into a digital signal and outputs it. The A / D conversion circuit includes: a time-to-digital converter; a sample-and-hold circuit for sampling and holding the voltage of the analog signal; a reference waveform signal generation circuit for generating a reference waveform signal based on the reference signal; and a comparator for comparing the voltage held by the sample-and-hold circuit with the voltage of the reference waveform signal and outputting a trigger signal. The A / D conversion circuit outputs the digital signal, which is based on a digital time value calculated by the time-to-digital converter.

[0250] This A / D conversion circuit achieves high precision, high resolution, high-speed processing, low power consumption, and miniaturization by using a time-to-digital converter. Furthermore, since the sampling timing is kept constant through a sample-and-hold circuit, timing fluctuations in the A / D conversion are reduced.

Claims

1. A transfer status output device, characterized by, Possessing: a ring oscillator that oscillates based on a trigger signal; a multi-stage delay line that is not included in the ring oscillator, to which an oscillation signal output from the ring oscillator is input, the multi-stage delay line having a plurality of delay elements connected thereto; a state machine whose state changes in accordance with a change in state of the ring oscillator; a transition state acquisition section that acquires state information including the oscillation signal, a signal output from each of the plurality of delay elements, and a signal output from the state machine in synchronization with a reference signal; and an internal state calculation section that calculates an internal state corresponding to a number of changes in state of the ring oscillator based on the state information acquired by the transition state acquisition section, the state machine including: a Gray code counter that outputs a Gray code signal based on a change in state of the oscillation signal, the transition state acquisition section including: a D flip-flop that acquires the oscillation signal in synchronization with the reference signal and holds a first signal corresponding to a value of the oscillation signal; and a register that acquires the Gray code signal in synchronization with the reference signal and holds a second signal corresponding to a value of the Gray code signal, the internal state calculation section decoding a third signal including the first signal and the second signal and outputting a decoded signal, at least either of a rising edge or a falling edge is taken as a time event, the first signal is a signal indicating a state of the ring oscillator at timing of the time event, the second signal is a signal indicating a state of the state machine at timing of the time event, the decoded signal is a signal indicating the internal state at timing of the time event.

2. The transition state output apparatus according to claim 1, wherein a time from when the internal state transitions from a first internal state to a second internal state to when the internal state transitions again to the first internal state is longer than an interval of times at which the state information held by the transition state acquisition section is updated. Possessing:

3. A time-to-digital converter, characterized by the transition state output apparatus according to claim 1; and an operation section that operates a number of transitions of the internal state and calculates a time digital value corresponding to a phase difference between timing of a change in the reference signal and timing of a change in the trigger signal based on the number of transitions.

4. The time-to-digital converter according to claim 3, wherein in a case where the number of transitions of the internal state exceeds a threshold value, the operation section calculates the time digital value taking the number of transitions as the threshold value. Possessing:

5. An A / D conversion circuit characterized by comprising: the time-to-digital converter according to claim 4; a reference waveform signal generation circuit that generates a reference waveform signal based on the reference signal; and a comparator that compares a voltage of an input analog signal with a voltage of the reference waveform signal and outputs the trigger signal, a digital signal based on the time digital value is output. Possessing: the time-to-digital converter according to claim 4; 6. An A / D conversion circuit characterized by comprising: a sample-and-hold circuit that samples and holds a voltage of an input analog signal; ​ ​ a reference waveform signal generation circuit that generates a reference waveform signal based on the reference signal; and a comparator that compares the voltage held by the sample-and-hold circuit and the voltage of the reference waveform signal and outputs the trigger signal, a digital signal based on the time-to-digital value is output.

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