A successive approximation analog-to-digital converter and data acquisition system

Abstract

The present application discloses a successive approximation analog-to-digital converter and a data acquisition system, comprising: an asynchronous clock generation circuit, a detection unit, and a control unit; the detection unit is connected to both the clock source and the control unit, and is used to detect the delay state of the first delay unit of the asynchronous clock generation circuit, and send the delay state to the control unit, so as to determine the delay of the first delay unit due to process problems. The control unit is connected to the first delay unit, and is used to determine the delay caused by the process problem according to the delay state, calculate a preset delay time according to the delay, and control the delay of the first delay unit according to the preset delay time to ensure that the converter can complete the comparison work within the preset delay time. It can be seen that the successive approximation analog-to-digital converter provided by the present application can determine the working state of the comparator in the analog-to-digital converter according to the delay state of the analog-to-digital converter, and set a suitable delay, thereby improving the working efficiency of the conversion circuit and reducing the design cost.

Description

Technical Field

[0001] The present application relates to the field of electronic circuits, and in particular to a successive approximation analog-to-digital converter and a data acquisition system. Background Art

[0002] The Successive Approximation Analog-to-Digital Converter (SAR ADC) uses a successive approximation algorithm to convert the input voltage signal into a digital signal and output it. With the advantages of more digital modules and fewer analog modules, low power consumption and small size, it is widely used in communications, sensors, multimedia and other fields.

[0003] Figure 1 This is a structural diagram of a common asynchronous clock generation circuit, such as Figure 1 As shown, the SAR ADC includes a delay unit and a comparison unit. Each comparison cycle consists of a sampling phase and a comparison phase. During the comparison phase, the comparison unit compares the input signal with various standard signals and sends the comparison results to the control unit. The delay unit controls the duration of the comparison process. When the comparison is completed or the comparison time exceeds the preset delay time set by the delay unit, the next sampling cycle begins under the control of the clock signal CLKS.

[0004] However, SAR ADCs are significantly affected by process variations (such as process fluctuations, operating environment variations, and power supply voltage variations). This results in different SAR ADCs completing sampling and comparison operations at varying speeds. To ensure circuit reliability, sampling circuits typically require a significant margin for the preset delay time, which increases design costs and reduces conversion circuit efficiency.

[0005] It can be seen that how to provide a new analog-to-digital converter to reduce design costs and improve the efficiency of the conversion circuit is a problem that those skilled in the art need to solve urgently. Summary of the Invention

[0006] The purpose of this application is to provide a successive approximation analog-to-digital converter and a data acquisition system to reduce design costs and improve the working efficiency of the conversion circuit.

[0007] To solve the above technical problems, the present application provides a successive approximation analog-to-digital converter, comprising:

[0008] Asynchronous clock generation circuit 1, detection unit 2, control unit 3;

[0009] The asynchronous clock generating circuit 1 comprises a first delay unit 5;

[0010] The detection unit 2 and the control unit 3 are both connected to detect the delay state of the first delay unit 5 and send the delay state to the control unit 3;

[0011] The control unit 3 is connected to the first delay unit 5 and is configured to calculate a preset delay time according to the delay state and control the delay of the first delay unit 5 according to the preset delay time.

[0012] Preferably, the first delay unit 5 is specifically: a controllable delay unit having at least seven delay circuits and a decoder;

[0013] Each of the delay circuits includes: a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, and an inverter;

[0014] The second end of the first switch tube and the second end of the fourth switch tube of each delay circuit are both connected to a power supply;

[0015] The second end of the seventh switch tube and the second end of the eighth switch tube of each delay circuit are both grounded;

[0016] The control end of the first switch tube, the control end of the second switch tube, the control end of the third switch tube, the control end of the fifth switch tube, the control end of the sixth switch tube, and the control end of the seventh switch tube are all connected;

[0017] The first end of the first switching tube is connected to the second end of the second switching tube;

[0018] The first end of the second switch tube is connected to the second end of the third switch tube and the first end of the fourth switch tube;

[0019] The first end of the third switch tube is connected to the first end of the fifth switch tube, and the connection point between the two is connected to the control end of the first switch tube of the next delay circuit;

[0020] The second end of the fifth switch tube is connected to the first end of the sixth switch tube and the first end of the eighth switch tube;

[0021] The second end of the sixth switching tube is connected to the first end of the seventh switching tube;

[0022] The control end of the fourth switch tube is connected to the input ends of the decoder and the inverter;

[0023] The control end of the eighth switch tube is connected to the input end of the inverter.

[0024] Preferably, the detection unit 2 specifically includes:

[0025] A second delay unit 6 and a signal conversion unit, wherein the second delay unit 6 and the first delay unit 5 are located on the same chip and have the same process;

[0026] The first end of the second delay unit 6 is connected to the clock source 8, and is used to obtain the first clock signal and output the second clock signal;

[0027] The signal conversion unit outputs a detection signal according to the first clock signal and the second clock signal.

[0028] Preferably, the signal conversion unit includes: a charge pump 7 and a gate circuit;

[0029] The first clock signal and the second clock signal are input into the charge pump 7 via an AND gate circuit;

[0030] The charge pump 7 converts the first clock signal and the second clock signal into voltage signals.

[0031] Preferably, the control unit 3 is specifically an analog-to-digital converter;

[0032] The analog-to-digital converter is connected to the charge pump 7 and is used to obtain the detection signal and convert the detection signal into a binary signal to control the first delay unit 5 .

[0033] Preferably, each switch tube in the first delay unit 5 is a MOS tube.

[0034] Preferably, the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube are all PMOS tubes; the fifth switch tube, the sixth switch tube, the seventh switch tube, and the eighth switch tube are all NMOS tubes.

[0035] Preferably, the clock source 8 is a low-speed clock source.

[0036] Preferably, the asynchronous clock generation circuit 1 comprises: a dynamic comparator 4, a high-speed clock signal source;

[0037] The positive and negative output ends of the dynamic comparator 4 are connected to the input ends of the first delay unit 5 through a NAND gate. The output signal of the first delay unit 5 and the high-speed clock signal output by the high-speed clock signal source jointly control the working timing of the dynamic comparator 4.

[0038] In order to solve the above technical problems, the present application also provides a data acquisition system, including the successive approximation analog-to-digital converter.

[0039] The present application provides a successive approximation analog-to-digital converter, comprising: an asynchronous clock generation circuit, a detection unit, and a control unit; the detection unit is connected to both the clock source and the control unit, and is used to detect the delay state of the first delay unit of the asynchronous clock generation circuit, and send the delay state to the control unit, so as to determine the delay of the first delay unit due to process problems. The control unit is connected to the first delay unit, and is used to determine the delay caused by the process problem according to the delay state, calculate the preset delay time according to the delay, and control the delay of the first delay unit according to the preset delay time to ensure that the converter can complete the comparison work within the preset delay time. It can be seen that the successive approximation analog-to-digital converter provided by the present application can determine the working state of the comparator in the analog-to-digital converter according to the delay state of the analog-to-digital converter, and set a suitable delay for the comparator to prevent the preset delay time margin from being too large, thereby improving the working efficiency of the conversion circuit and reducing the design cost.

[0040] In addition, the present application also provides a data acquisition system, including the above-mentioned successive approximation analog-to-digital converter, with the same effect as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] Figure 1 This is a structural diagram of a common asynchronous clock generation circuit;

[0043] Figure 2 A structural diagram of a successive approximation analog-to-digital converter provided in an embodiment of the present application;

[0044] Figure 3 A structural diagram of a delay unit provided in an embodiment of the present application;

[0045] The reference numerals are as follows: 1 is an asynchronous clock generating circuit, 2 is a detection unit, 3 is a control unit, 4 is a dynamic comparator, 5 is a first delay unit, 6 is a second delay unit, 7 is a charge pump, and 8 is a clock source. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0047] The core of this application is to provide a successive approximation analog-to-digital converter and a data acquisition system.

[0048] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0049] In successive approximation analog-to-digital converter (SAR) applications, sufficient preset delay time is required to ensure the SAR ADC can complete data comparison. This preset delay time can typically be determined based on the SAR ADC's data sheet. However, SAR ADCs are significantly affected by PVT fluctuations (such as process fluctuations, operating environment changes, and power supply voltage variations), resulting in different SAR ADCs completing sampling and comparison tasks at varying speeds. When designing the SAR ADC sampling circuit, a large margin must be reserved for the preset delay time, which impacts the SAR ADC's operating efficiency.

[0050] To address the above technical issues, the present application provides a new successive approximation analog-to-digital converter (SAR ADC), comprising: an asynchronous clock generation circuit 1, a detection unit 2, and a control unit 3. In a specific implementation, the detection unit 2 detects the impact of PVT fluctuations on the delay unit of the asynchronous clock generation circuit 1, and the control unit 3 controls the delay time, enabling the SAR ADC to complete the comparison operation within the preset delay time selected during circuit design, thereby improving the operating efficiency of the sampling circuit.

[0051] Figure 2 This is a structural diagram of a successive approximation analog-to-digital converter provided in an embodiment of the present application, such as Figure 2 As shown, the analog-to-digital converter includes:

[0052] Asynchronous clock generation circuit 1, detection unit 2, control unit 3;

[0053] The detection unit 2 is connected to both the clock source 8 and the control unit 3, and is used to detect the delay state of the first delay unit 5 of the asynchronous clock generation circuit 1 and send the delay state to the control unit 3;

[0054] The control unit 3 is connected to the first delay unit 5 and is configured to calculate a preset delay time according to a delay state and control the delay of the first delay unit 5 according to the preset delay time.

[0055] like Figure 1As shown, the asynchronous clock generation circuit 1 includes a dynamic comparator 4, a first delay unit 5, and a high-speed clock signal source. The positive and negative output terminals of the dynamic comparator 4 are connected to the input terminals of the first delay unit 5 via a NAND gate. The output signal of the first delay unit 5 and the high-speed clock signal output by the high-speed clock signal source jointly control the operating timing of the dynamic comparator 4.

[0056] In a specific implementation, each working cycle of the asynchronous logic clock includes a sampling phase and a comparison phase. In the sampling phase, the clock source 8 signal CLKS output by the high-speed clock signal source is at a high level, the dynamic comparator 4 is in an inoperative state, its positive and negative output terminals are both at a high level, and the low-level signal is sent to the first delay unit 5 through the NAND gate; after the sampling phase, the conversion phase begins, the clock source 8 signal CLKS becomes a low level, and outputs a high-level signal CLKC through the NOR gate to control the comparator to perform the comparison operation. At this time, the output of the comparator is one high and one low, and the output Compout signal after the NAND gate is high. After the delay of the first delay unit 5, the CLKC signal is pulled low through the NAND gate, the dynamic comparator 4 is reset, the Compout signal is low, and after the delay of the first delay unit 5, the CLKC signal is pulled high. After all comparisons are completed, the rising edge of CLKS is controlled to arrive early to pull the CLKC signal low to enter the sampling phase of the next working cycle; or if all comparisons are not completed within the preset conversion time, when the rising edge of the clock source 8 signal CLKS arrives, CLKC will be forced to be pulled low to enter the sampling phase of the next working cycle.

[0057] It should be noted that the first delay unit 5 provided in the present application is a controllable delay unit, and its delay can be adjusted according to demand to ensure that the SAR ADC can complete the comparison work within the preset comparison time set when designing the circuit.

[0058] In a specific implementation, the first delay unit 5 can be a delay device with a control unit 3, such as a single-chip microcomputer clock; it can also be a delay device composed of electronic components such as switching tubes, which achieves the purpose of delay by utilizing the different conduction speeds between different electronic components.

[0059] Detection unit 2 is connected to both clock source 8 and control unit 3, and is used to detect the delay state of first delay unit 5 of asynchronous clock generation circuit 1 and send the delay state to control unit 3. In a specific implementation, a first clock signal obtained from clock source 8 is sent to the delay unit, and a second clock signal is obtained after passing through the delay unit. Due to process fluctuations during the manufacturing process and the influence of the operating environment, the actual delay of the delay unit may differ from the delay specified in the data sheet. Detection unit 2 can determine the actual delay of the delay unit by comparing the phase difference between the first clock signal and the second clock signal.

[0060] It should be noted that, in order to facilitate calculation and analysis of the phase difference between the first clock signal and the second clock signal, the signal source connected to the detection unit 2 is a low-speed clock source 8 .

[0061] After receiving the delay state, the control unit 3 calculates the preset delay time according to the delay state. It can be understood that the delay state can be the delay time calculated by the detection unit 2, or it can be the current signal generated according to the first clock signal and the second clock signal.

[0062] In a specific implementation, the detection unit 2 and the control unit 3 can be devices with a control system such as a single chip microcomputer, or can be devices composed of electronic components, which is not limited here.

[0063] It should be noted that the detection unit 2 can directly detect the delay state of the first delay unit 5, or it can detect the delay state of other delay units that are the same as the first delay unit 5 (with the same manufacturing process, located on the same chip, and the same working environment). The former is more reliable, but inputting the first clock signal into the first delay unit 5 may affect the normal operation of the first delay unit 5.

[0064] It is understandable that after the control unit obtains the delay state, it can determine the chip process level corresponding to the delay state by looking up the table, and then determine the delay time caused by the chip process problem based on the chip process level.

[0065] In the present embodiment, a successive approximation analog-to-digital converter is provided, which includes: an asynchronous clock generation circuit, a detection unit, and a control unit. The detection unit is connected to both the clock source and the control unit, and is used to detect the delay state of the first delay unit of the asynchronous clock generation circuit, and send the delay state to the control unit to facilitate determining the delay of the first delay unit due to process problems. The control unit is connected to the first delay unit, and is used to determine the delay caused by the process problem based on the delay state, calculate a preset delay time based on the delay, and control the delay of the first delay unit based on the preset delay time to ensure that the converter can complete the comparison work within the preset delay time. It can be seen that the successive approximation analog-to-digital converter provided in this embodiment can determine the working state of the comparator in the analog-to-digital converter based on the delay state of the analog-to-digital converter, and set an appropriate delay for the comparator to prevent the preset delay time margin from being too large, thereby improving the working efficiency of the conversion circuit and reducing the design cost.

[0066] Since the SAR ADC is a high-speed analog-to-digital converter, a high response speed is required for the first delay unit. However, devices such as a single-chip microcomputer need to be adjusted through a control system, which has a slow response speed and high cost. Therefore, in this embodiment, a controllable delay unit composed of electronic devices is selected as the first delay unit 5.

[0067] On the basis of the above embodiment, the first delay unit 5 is specifically: a controllable delay unit having at least seven delay circuits and a decoder;

[0068] Each delay circuit includes: a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, and an inverter;

[0069] The second end of the first switch tube and the second end of the fourth switch tube of each delay circuit are both connected to a power supply;

[0070] The second end of the seventh switch tube and the second end of the eighth switch tube of each delay circuit are both grounded;

[0071] The control end of the first switch tube, the control end of the second switch tube, the control end of the third switch tube, the control end of the fifth switch tube, the control end of the sixth switch tube, and the control end of the seventh switch tube are all connected;

[0072] The first end of the first switching tube is connected to the second end of the second switching tube;

[0073] The first end of the second switch tube is connected to the second end of the third switch tube and the first end of the fourth switch tube;

[0074] The first end of the third switch tube is connected to the first end of the fifth switch tube, and the connection point between the two is connected to the control end of the first switch tube of the next delay circuit;

[0075] The second end of the fifth switch tube is connected to the first end of the sixth switch tube and the first end of the eighth switch tube;

[0076] The second end of the sixth switch tube is connected to the first end of the seventh switch tube;

[0077] The control end of the fourth switch tube is connected to the input ends of the decoder and the inverter;

[0078] The control end of the eighth switch tube is connected to the input end of the inverter.

[0079] This embodiment takes a circuit with seven delay stages as an example to illustrate the delay unit. Figure 3 This is a structural diagram of a delay unit provided in an embodiment of the present application.

[0080] Table 1

[0081] Detection signal value Binary control signal Decoder output value 0 000 0000000 1 001 0000001 2 010 0000011 3 011 0000111 4 100 0001111 5 101 0011111 6 110 0111111 7 111 1111111

[0082] Table 1 is a truth table of a first delay unit 5 provided in an embodiment of the present application. As shown in Table 1, each bit of the decoder output value corresponds to the on and off of a first-level delay circuit. When a certain digit is 1, the delay circuit corresponding to the digit is turned on; when a certain digit is 0, the delay circuit corresponding to the digit is turned off.

[0083] In a specific implementation, the decoder converts the received binary control signal into a thermometer code to control the on and off of delay circuits of different delay levels to achieve different delay effects.

[0084] like Figure 3 As shown, the first delay unit 5 has seven delay circuits connected in series. Each delay circuit has two states: high delay and low delay. Taking delay circuit 301 as an example, when the number corresponding to delay circuit 301 in the decoder output is 1, the decoder outputs a high level to the fourth switch of delay circuit 301. At this time, the fourth and eighth switches are turned off. The signal flowing through the first delay unit 5 needs to pass through the first, second, third, fifth, sixth, and seventh switches, resulting in a slower signal speed and a larger signal delay. When the number corresponding to delay circuit 301 in the decoder output is 0, the decoder outputs a low level to the fourth switch of delay circuit 301. At this time, the fourth and eighth switches are turned on. The signal flowing through the first delay unit 5 needs to pass through the third, fourth, seventh, and eighth switches, resulting in a faster signal speed and a smaller signal delay. It should be noted that during design, the model of each switch can be adjusted according to actual needs to obtain the desired delay difference.

[0085] In this embodiment, a controllable delay unit composed of a switch tube is selected as the first delay unit, thereby improving the response speed of the delay unit and reducing the circuit cost.

[0086] In a specific implementation, the detection unit 2 can be a device with a control system such as a single-chip microcomputer, or a logic circuit. When detecting the delay state, the delay state of the first delay unit 5 can be directly detected, or the delay state of other delay units with the same condition as the first delay unit 5 can be detected.

[0087] Based on the above embodiment, the detection unit 2 specifically includes:

[0088] A second delay unit 6 and a signal conversion unit, wherein the second delay unit 6 and the first delay unit 5 are located on the same chip and have the same process;

[0089] A first end of the second delay unit 6 is connected to the clock source 8, for obtaining a first clock signal and outputting a second clock signal;

[0090] The signal conversion unit outputs a detection signal according to the first clock signal and the second clock signal.

[0091] Since inputting a detection clock signal into the first delay unit 5 may affect the normal operation of the first delay unit 5, in this embodiment, the delay state of the second delay unit 6 is selected for detection. The second delay unit 6 and the first delay unit 5 are located on the same chip, have the same working environment, and are manufactured using the same process. That is, the delay errors caused by PVT fluctuations are the same. Therefore, the delay state of the second delay unit 6 can be measured and the measurement result can be used as the delay state of the first delay unit 5.

[0092] It can be understood that in order to facilitate analysis of the error between the first clock signal and the second clock signal and reduce circuit cost, the clock source 8 used in this embodiment is a low-speed clock source 8 .

[0093] As a preferred embodiment, the signal conversion unit includes: a charge pump 7 and a gate circuit;

[0094] The first clock signal and the second clock signal are input into the charge pump 7 via the AND gate circuit;

[0095] The charge pump 7 converts the first clock signal and the second clock signal into voltage signals.

[0096] The detection circuit includes a second delay unit 6, a charge pump 7, and a gate circuit. In a specific implementation, a clock source 8 sends a first clock signal of a fixed frequency to the second delay unit 6. The first clock signal is converted into a second clock signal by the second delay unit 6. The delay of the second clock signal compared to the first clock signal is the delay caused by PVT fluctuations in the second delay unit 6. The second clock signal is ANDed with the first clock signal to generate a new clock signal, which is then input into the charge pump 7. The charge pump 7 charges and discharges according to the input signal. Clock signals with different duty cycles have different charge and discharge times, and the voltage signal output by the charge pump 7 is also different. Therefore, based on the value of the voltage signal output by the charge pump 7 and the corresponding relationship between the voltage signal and the delay of the delay unit, the delay caused by PVT fluctuations in the second delay unit 6 and the first delay unit 5 can be determined.

[0097] After obtaining the voltage signal output by the charge pump 7, it is necessary to adjust the delay of the first delay unit 5 according to the voltage signal. The delay of the first delay unit 5 can be adjusted by a device such as a single-chip microcomputer, or by an electronic device. The latter has lower costs.

[0098] As a preferred embodiment, the control unit 3 is specifically an analog-to-digital converter;

[0099] The analog-to-digital converter is connected to the charge pump 7 and is used to obtain the detection signal and convert the detection signal into a binary signal to control the first delay unit 5 .

[0100] In a specific implementation, the control unit 3 is a lightweight analog-to-digital converter, which is used to convert the value of the detection signal into a binary signal and send the binary signal to the decoder of the first delay unit 5 to adjust the delay of the first delay unit 5.

[0101] In this embodiment, a lightweight analog-to-digital converter, a charge pump, and a logic circuit are selected to form the detection unit and the control unit, thereby reducing the hardware cost of the circuit and improving the response speed of the circuit.

[0102] In a preferred embodiment, all switching transistors used in the first delay unit 5 are MOS transistors. Specifically, the first, second, third, and fourth switching transistors are PMOS transistors; the fifth, sixth, seventh, and eighth switching transistors are NMOS transistors. During circuit design, the delay of the first delay unit 5 can be changed by simply adjusting the type and model of each switching transistor.

[0103] In addition, the present application also provides a data acquisition system, including the above-mentioned successive approximation analog-to-digital converter, and also including a timing control unit, a sampling circuit, etc. The various parts of the successive approximation analog-to-digital converter have been described in detail in the above-mentioned embodiments and will not be repeated here.

[0104] In this embodiment, a data acquisition system is provided, including a successive approximation analog-to-digital converter, which includes: an asynchronous clock generation circuit, a detection unit, and a control unit. The detection unit is connected to both the clock source and the control unit, and is used to detect the delay state of the first delay unit of the asynchronous clock generation circuit, and send the delay state to the control unit to facilitate determining the delay of the first delay unit due to process problems. The control unit is connected to the first delay unit, and is used to determine the delay caused by the process problem based on the delay state, calculate a preset delay time based on the delay, and control the delay of the first delay unit based on the preset delay time to ensure that the converter can complete the comparison work within the preset delay time. It can be seen that the data acquisition system provided in this embodiment can determine the working state of the comparator in the analog-to-digital converter based on the delay state of the analog-to-digital converter, and set an appropriate delay for the comparator to prevent the preset delay time margin from being too large, thereby improving the working efficiency of the conversion circuit and reducing the design cost.

[0105] The above is a detailed introduction to a successive approximation analog-to-digital converter and a data acquisition system provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0106] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A successive approximation analog-to-digital converter, characterized in that include: Asynchronous clock generation circuit (1), detection unit (2), control unit (3); The asynchronous clock generation circuit (1) comprises a first delay unit (5); The detection unit (2) and the control unit (3) are both connected and used to detect the delay state of the first delay unit (5) and send the delay state to the control unit (3); The control unit (3) is connected to the first delay unit (5) and is used to calculate a preset delay time according to the delay state, and control the delay of the first delay unit (5) according to the preset delay time; Wherein, the detection unit (2) specifically includes: A second delay unit (6) and a signal conversion unit, wherein the second delay unit (6) and the first delay unit (5) are located on the same chip and have the same process; The first end of the second delay unit (6) is connected to the clock source (8) for obtaining a first clock signal and outputting a second clock signal; The signal conversion unit outputs a detection signal according to the first clock signal and the second clock signal; The signal conversion unit includes: a charge pump (7) and a gate circuit; The first clock signal and the second clock signal are input into the charge pump (7) via an AND gate circuit; The charge pump (7) converts the first clock signal and the second clock signal into voltage signals.

2. The successive approximation analog-to-digital converter according to claim 1, wherein The first delay unit (5) is specifically: a controllable delay unit having at least seven delay circuits and a decoder; Each of the delay circuits includes: a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, and an inverter; The second end of the first switch tube and the second end of the fourth switch tube of each delay circuit are both connected to a power supply; The second end of the seventh switch tube and the second end of the eighth switch tube of each delay circuit are both grounded; The control end of the first switch tube, the control end of the second switch tube, the control end of the third switch tube, the control end of the fifth switch tube, the control end of the sixth switch tube, and the control end of the seventh switch tube are all connected; The first end of the first switching tube is connected to the second end of the second switching tube; The first end of the second switch tube is connected to the second end of the third switch tube and the first end of the fourth switch tube; The first end of the third switch tube is connected to the first end of the fifth switch tube, and the connection point between the two is connected to the control end of the first switch tube of the next delay circuit; The second end of the fifth switch tube is connected to the first end of the sixth switch tube and the first end of the eighth switch tube; The second end of the sixth switching tube is connected to the first end of the seventh switching tube; The control end of the fourth switch tube is connected to the input ends of the decoder and the inverter; The control end of the eighth switch tube is connected to the output end of the inverter.

3. The successive approximation analog-to-digital converter according to claim 1, wherein: The control unit (3) is specifically an analog-to-digital converter; The analog-to-digital converter is connected to the charge pump (7) and is used to obtain the detection signal and convert the detection signal into a binary signal to control the first delay unit (5).

4. The successive approximation analog-to-digital converter according to claim 2, wherein: Each switch tube in the first delay unit (5) is a MOS tube.

5. The successive approximation analog-to-digital converter according to claim 2, wherein: The first switch tube, the second switch tube, the third switch tube, and the fourth switch tube are all PMOS tubes; the fifth switch tube, the sixth switch tube, the seventh switch tube, and the eighth switch tube are all NMOS tubes.

6. The successive approximation analog-to-digital converter according to claim 1, wherein: The clock source (8) is a low-speed clock source.

7. The successive approximation analog-to-digital converter according to claim 1, wherein: The asynchronous clock generation circuit (1) comprises: a dynamic comparator (4), a high-speed clock signal source; The positive and negative output terminals of the dynamic comparator (4) are connected to the input terminals of the first delay unit (5) via a NAND gate, and the output signal of the first delay unit (5) and the high-speed clock signal output by the high-speed clock signal source jointly control the working timing of the dynamic comparator (4).

8. A data acquisition system, characterized in that: A successive approximation analog-to-digital converter comprising the method according to any one of claims 1 to 7.

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