A radiation-resistant reinforced payload master control device supporting SPACE VPX architecture

Abstract

The present invention discloses a radiation-resistant reinforced payload main controller based on a 6U VPX architecture, which relates to the field of aerospace circuits. The main controller includes: a processor module and an FPGA module. The board is standardized in design, with a unified structure, a unified size, and a standardized interface. It has strong portability and can greatly save the development cost and development cycle of payload products. The present invention uses the "COTS+aerospace grade+anti-amplitude noise reinforcement" concept for design. As the control unit of the payload, the present invention uses a high-reliability FPGA dedicated refresh circuit and core processor in the hardware circuit design of the payload main controller. In the software design, a triple-module redundant design and an EDAC design are used to enhance the reliability of the payload system.

Description

Technical Field

[0001] The present invention relates to an aerospace product, a communication payload master control device for satellite internet, and specifically to the device's core processor chip S698PM, an interface expansion FPGA and its refresh circuit, and an interconnection interface supporting SPACE VPX. Background Art

[0002] The satellite networking communication payload system is one of the key subsystems of the communication satellite constellation. The satellite networking communication payload master control device is the core processing unit that controls the various components of the satellite networking communication payload. With the rapid development of the satellite Internet era, the flexibility and functional requirements of the on-board networking communication payload and the master control unit are becoming more and more powerful. The payload master control device is the hub for the control of the networking communication payload and the transmission of remote control and telemetry data. It is an indispensable part of satellite networking and one of the important development directions of the on-board components of today's satellite Internet. The satellite Internet networking communication payload currently mainly transmits satellite-to-ground information through microwave antennas, transmits inter-satellite information through laser links, and realizes information routing through routing units. Satellite Internet requires low-latency information transmission, so it not only requires low latency for each transmission terminal, but also requires low latency for some of the payload master control devices, and quickly runs the control algorithms of terminals such as microwave antennas and lasers. The cost of using aerospace-grade devices in traditional aerospace is too high. Satellite Internet is composed of a large number of satellite networks. Traditional aerospace manufacturing is not suitable for the development of satellite Internet. Therefore, commercial aerospace has begun to use aerospace-grade processing industrial-grade devices, and has carried out reliability design through space radiation-resistant reinforcement technology to reduce the development cost by technical means. Therefore, the main control equipment of networking communication payloads will inevitably tend to develop in the direction of high processing and low cost, and tend to shift from relying on device reliability to strengthening technical reliability.

[0003] The communication payload master control equipment of satellite Internet needs to deal with multi-terminal control, high-processing algorithms, low-latency transmission and other processing, so it needs a powerful CPU processing and a large number of communication peripheral interfaces. Traditional aerospace needs to pay huge component costs while ensuring reliability. Therefore, it is necessary to reduce the use of aerospace-grade devices, especially CPU, FPGA and other high-cost devices through circuit reinforcement technology and software reinforcement technology. At present, the main on-board circuit reinforcement technologies include anti-fuse FPGA, circuit redundancy, etc., and the main software reinforcement technologies include ECC design, program refresh, and triple-mode redundant reading, which can save the development cost of on-board products to a certain extent. At present, the processors used in the communication payload master control equipment are basically domestic low-calculation or foreign high-cost processors. Foreign components also have security issues and out-of-stock risks. In view of the current status of domestic on-board components, domestic component manufacturers such as Zhuhai Orbit and Shanghai Fudan Micro have achieved relatively obvious results. S698PM is a 4-core domestic processor with two-level cache, 1652DMIPS@500MHz, DDR2 memory, on-chip storage with EDAC radiation hardening technology, supports XX operating system, and can adapt to the high-speed processing of satellite network communication payload master control equipment. JFMRS01RH is a domestic refresh chip specially used for refreshing FPGA SRAM, which can support the configuration data refresh of many Xilinx and Fudan Micro FPGAs, and can be used to expand the FPGA radiation hardening of peripheral interfaces.

[0004] At present, the payload master control devices of various units mostly have customized sizes and interfaces for the payload master control boards based on the in-satellite layout, and do not adopt standardized designs. The SpaceVPX architecture evolved from the Open vpx architecture. The entire system is more standardized and has a wider applicability. Each slot adopts a standardized design with unified structure, size, and interface. Summary of the invention

[0005] The technical problem solved by the present invention is: to provide a device that supports the SPACE VPX architecture, standardizes the interface and size design of the payload main control circuit, utilizes the "COTS+aerospace grade+anti-amplitude noise reinforcement" design concept, combines the existing domestic chip achievements, and, under the premise of ensuring on-board reliability, aims at the satellite Internet communication payload main control requirements such as high-calculation grain, multi-process processing, and low cost, to provide a satellite networking communication payload main control device that supports the SPACE VPX architecture, is based on the S698PM processor, and has a refresh chip JFMRS01RH, which is high-performance, anti-radiation reinforced, and can be reconfigured on-orbit.

[0006] The technical solution of the present invention is: a radiation-resistant reinforced load main controller supporting SPACE VPX architecture, the main control device includes: a processor module and an interface expansion FPGA module, the processor module includes: a processor chip S698PM, an interface circuit, FLASH1, FLASH2 and DDR2; the processor chip is connected to the interface circuit, FLASH1, FLASH2, DDR2, the interface circuit includes: RS422, CAN interface, 1553B interface, Ethernet interface, PMC interface; the FLASH1 is a PROM, used to store the Boot Loader of the processor chip, the FLASH2 is used to store four NOR FLASH application programs of the same program, and the DDR2 is used to store the data of the processor;

[0007] The interface expansion FPGA module comprises: FPGA, refresh circuit, interface converter, connector, NOR FLASH, JTAG interface and power management module; the interface expansion FPGA module peripheral local Bus interface is connected to FPGA at one end and connected to S698PM chip of processor module at the other end; the refresh circuit is connected to NOR FLASH through FLASH interface and connected to interface expansion FPGA through SelectMAP interface; one end of interface converter is connected to FPGA and the other end is connected to connector; the FPGA is also connected to JTAG interface and connector; the power management module completes power supply configuration on the board and supplies power to each chip; the interface expansion FPGA program is loaded from NOR FLASH through refresh circuit and refreshes the interface expansion FPGA program regularly during operation; the loader and application program in NORFLASH adopts regional multi-backup storage; S698PM processing executes terminal control algorithm, remote control command parsing, telemetry and routing data packaging, status monitoring of load master through Linlix operating system, and manages memory allocation, resource scheduling, process switching, interrupt priority and exception handling of the system.

[0008] Furthermore, a pre-installation test interface is additionally provided, and the test interface is connected to the connector; the power management module includes a current limiting protection circuit and a timing control circuit; the number of PMC interfaces is 4, and the number of connector interfaces is 6.

[0009] High-performance processing. The present invention uses an interface expansion FPGA as the hub of the peripheral interface, which can simultaneously meet the integrated processing of broadband regenerative communication payloads and the information interaction of routing units, user-side baseband processing, feed-side baseband processing, laser terminals, expansion modules, and satellite platforms. The interface compatibility is strong, and the processor S698PM used has 4-core CPU processing, 1652DMIPS@500MHz, DDR2 memory, supports multiple operating systems, supports multi-process processing, and can quickly run multiple application software such as protocol conversion, terminal control algorithms, data packaging, instruction parsing, and status monitoring at the same time.

[0010] Cost saving. The interface expansion FPGA used in the present invention is an industrial-grade FPGA of the K7 series of Xilinx, or the FPGA of the same series of Xilinx produced by Shanghai Fudan Microelectronics. Compared with the traditional aerospace industry, which uses all aerospace-grade devices, the present invention can save costs to a great extent and better adapt to the mass production of satellite Internet.

[0011] Standardized design. The existing load controller structure and interface design are mostly custom designs without standardized design, which is not conducive to mass production and testing. The present invention supports SPACE VPX specifications, meets VITA design specifications, adopts standardized design, unified structure, unified size, and standardized interface. It can shorten the production cycle in mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 To invent a radiation-resistant reinforced payload main controller layout and interface diagram based on 6U VPX architecture.

[0013] In the figure, 1. Processor chip, 2. K7 series FPGA, 3. Single particle refresh circuit, 4. 6U VPX connector, 5NORFLASH, 6. Pre-installation test interface, 7. Power management module, 8. 10M / 100M Ethernet driver, 9. FLASH1, 10. FLASH2, 11. DDR2. DETAILED DESCRIPTION

[0014] The following will provide a clear and complete description of the technical solutions in the implementation of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0015] A radiation-resistant reinforced payload master control device supporting spaceVPX architecture, wherein the structural dimensions of the FPGA baseboard of the payload master control are 233.35 mm×160 mm×25 mm.

[0016] The payload main control module consists of two parts: an FPGA baseboard with a standard 6U VPX architecture and a CPU daughter card. The FPGA baseboard mainly completes interface expansion, which is implemented by FPGA (K7) and refreshes the functional FPGA configuration by refreshing the chip to achieve anti-radiation reinforcement. The payload main control implements tasks such as terminal control algorithm, remote control command analysis, telemetry and routing data packaging, status monitoring, and manages system-level operations such as system memory allocation, resource scheduling, process switching, interrupt priority, and exception handling.

[0017] The processor is S698PM of Zhuhai Orbit Aerospace Technology Co., Ltd., which is the core chip of the CPU daughter card. It is composed of on-board data storage devices DDR2 and FLASH, PROM, interface drive circuit (including 1553B, SpaceWire, Ethernet, RS422, CAN, GPIO, etc.), secondary power supply circuit and expansion interface. The secondary power supply part on the board completes the distribution of the daughter card working voltage. The CPU daughter card integrates a variety of communication interfaces, including 1 CAN bus interface, 1 local Bus interface, 1 JTAG interface, 1 10M / 100M Ethernet bus interface, 1 1553B interface, 1 RS422 interface, 1 RS232 interface and 1 IIC interface. The controllers of these communication interfaces are all integrated in the S698PM chip. It is only necessary to design the interface drive circuit in the periphery. The CPU daughter card is connected to the FPGA baseboard through four PMC interfaces of P11, P12, P13 and P14.

[0018] The core device S698PM chip is taped out using a wide temperature physical process. The triple-mode redundancy (TMR) technology is used to reinforce the redundancy of all internal sequential logic units, and the error detection and correction (EDAC) technology is used to reinforce the internal memory and external memory interface. The chip has excellent reliability design, with a total dose (TID) better than 300Krad (Si), a single event upset (SEU) better than 1E-5 errors / device / day, and a single event latch (SEL) better than 99.8MeV.cm2 / mg.

[0019] The invention states that the CPU supports on-track reconstruction, which can be achieved through program injection and instruction injection functions, and supports local reconstruction according to injection instructions or controlling the lower-level FPGA for reconstruction. Local reconstruction supports two options: reconstruction using injected program data and reconstruction using firmware program data in the local PROM of the CPU daughter card.

[0020] The board supports the Linux operating system, as well as system operations such as threads, process management, and memory resource allocation of the Linux operating system, and also supports the operation of application software; the RAM, ROM and other storage spaces required by the software are all designed with margin to ensure that the data storage range meets the requirements; it supports 4 backup storage of applications, and each reset operation automatically jumps to the next backup storage area to read data; it supports caching of user business data, and the storage FLASH is not less than 64MB; the application is designed with redundancy, and the 4 backups are distinguished in the order of A\B\C\D marks, and the isolation area of ​​each storage area is not less than 32Kb. Each reset jumps to different memories through BootLoader to read data; the error checking and correction design, the software has EDAC error checking and correction functions for internal / external memories to ensure the validity and rationality of the software; the application includes multiple functions such as payload remote control and telemetry processing, orbit six-number calculation, multiple exception processing (circuit, voltage, temperature), antenna control algorithm, data channel switching, lower-level FPGA control, laser terminal control, routing information transmission, routing table transmission, dynamic loading (analyzing lower-level unit reconstruction data and transmission).

[0021] The FPGA baseboard is composed of FPGA and peripheral devices, power conversion processing, refresh circuit and flash, interface expansion circuit (including RS422, CAN, PPS, etc.), OC instruction processing circuit and VPX interface, etc. At the same time, the CPU subboard is fixed on the FPGA baseboard and communicates with the FPGA baseboard through 4 PMC interfaces.

[0022] The FPGA uses the K7 series FPGA of Xilinx Company, which has rich logic resources and sufficient IO ports.

[0023] The refresh circuit uses Shanghai Fudan Micro's JFMRS01RH, which uses SMIC 0.18um CMOS technology and DICE design reinforcement method, with single event upset (SEU) ≥ 75MeV cm2 / mg, single event lock (SEL) ≥ 37MeV cm2 / mg, and has high resistance to single event effects. The device supports refresh and reconstruction of FPGAs of Xilinx and Fudan Micro's VIRTEX4, VIRTEX5, VIRTEX6, and KINTEX7 series.

[0024] The NOR FLASH stores the configuration data of the FPGA. Two 265M domestic devices are selected for NOR FLASH. Each flash is divided into two areas to place two bit streams, one for the main and one for the backup. The refresh circuit reads the data in the NOR FLASH and configures the FPGA through the select Map interface.

[0025] The VPX connector of the base plate uses a hybrid analog-digital connector from Guizhou Aerospace Corporation and is connected to the chassis backplane.

[0026] The power management module includes a current limiting protection circuit and a timing control circuit

[0027] The FPGA baseboard can exchange data with the CPU daughter card through the local bus; the local bus must meet the addressing requirements of no less than 16 bits; the FPGA baseboard provides 5V working voltage for the CPU daughter card to complete the distribution of working voltage within the board; when resetting, the control FPGA board and the load main control CPU board will be reset together according to the remote control command requirements, or a separate reset signal can be used to reset the FPGA or CPU separately; the baseboard comes with NOR FLASH that can store four copies of the same program, and the isolation between the two storage areas is ≥1M byte, and the total storage space is not less than 64M byte, each reset jumps to a different storage area to read the code program, and the jump order is 1-2-3-4-1-2-3-4; the baseboard has a data reconstruction function, which can realize reconstructed data transmission through a dedicated RS422 channel; the baseboard has a data recovery function, which can be enabled and disabled through the CPU board transmission instruction. When a copy of data in the storage area is found to be double-wrong through ECC detection, the data in the double-wrong area is restored by calling another correct storage data; the user interface required by the CPU is expanded through the rich IO ports of the FPGA itself, and the expansion interfaces include RS422, CAN, PPS, OC, etc.; the FPGA baseboard provides wiring for the RS422, 1553B, CAN and other communication buses led out by the CPU to the VPX connector and the J30J connector.

[0028] The board is designed as VPX architecture: it complies with the topology defined by the space VPX interface, and the payload master controller adopts the 6UVPX standard board design. Domestic CPU + radiation-resistant reinforcement technology: The CPU core device uses a new domestic SPARC V8 architecture multi-core SOC chip, which is compatible with the most advanced LEON4 core in the world. The device is a radiation-resistant device, and uses triple-mode redundancy (TMR) technology to redundantly reinforce all internal sequential logic units, and uses error detection and correction (EDAC) technology to reinforce the internal memory and external memory interface. FPGA + dedicated single-particle refresh circuit: The interface expansion is completed through the rich logic resources and IO resources of the FPGA, and the high-reliability JFMRS01RH device is used to regularly refresh the configuration registers of the SRAM-type FPGA device through hardware circuit design and program design. The space adaptability design for the space radiation environment includes: the core device of the high-level management unit adopts radiation-resistant chip; three-module redundant design; dual redundant design for data channel; the payload main control module is composed of two parts: FPGA baseboard and CPU daughter card of standard 6U VPX architecture. The FPGA baseboard mainly completes the interface expansion, including rich RS422 interface, OC command control interface, etc., and communicates with other modules in the payload through the backplane topology. The interface uses dual redundant design. It is specifically implemented by FPGA, and the functional FPGA is refreshed and reinforced by refreshing the chip. The CPU device interface types are rich, including RS422 interface, CAN interface, LVDS interface, 10M / 100M network port, 1553B interface, which can match the interface of various external satellite platforms and communicate with them to complete the main functions of remote control command parsing, telemetry data framing, orbit six number calculation, etc. of the payload main control module.

Claims

1. A radiation-hardened payload controller supporting the SPACE VPX architecture, the controller comprising: Processor module and interface expansion FPGA module, the processor module includes: processor chip S698PM, interface circuit, FLASH1, FLASH2 and DDR2; the processor chip is connected to the interface circuit, FLASH1, FLASH2, DDR2, the interface circuit includes: RS422, CAN interface, 1553B interface, Ethernet interface, PMC interface; the FLASH1 is a PROM, used to store the BootLoader of the processor chip, the FLASH2 is used to store four NOR FLASH application programs of the same program, and the DDR2 is used to store the data of the processor; Adopting domestically produced CPU + radiation-resistant reinforcement technology: The CPU core device uses domestically produced SPARC V8 architecture multi-core SOC chips, which are compatible with the world's most advanced LEON4 core. The device is radiation-resistant, and uses triple-mode redundancy technology to reinforce all internal sequential logic units, and uses error detection and correction technology to reinforce the internal memory and external memory interface with radiation-resistant reinforcement design; The interface expansion FPGA module comprises: FPGA, refresh circuit, interface converter, connector, NOR FLASH, JTAG interface and power management module; the interface expansion FPGA module peripheral local Bus interface is connected to FPGA at one end and connected to S698PM chip of processor module at the other end; the refresh circuit is connected to NOR FLASH through FLASH interface and connected to interface expansion FPGA through Select MAP interface; one end of interface converter is connected to FPGA and the other end is connected to connector; the FPGA is also connected to JTAG interface and connector; the power management module completes power supply configuration on the board and supplies power to each chip; the interface expansion FPGA program is loaded from NOR FLASH through refresh circuit and refreshes the interface expansion FPGA program regularly during operation; the loading program and application program in NOR FLASH adopts multi-backup storage in different regions; S698PM processing executes terminal control algorithm, remote control command parsing, telemetry and routing data packaging, status monitoring of load master through Linlix operating system, and manages memory allocation, resource scheduling, process switching, interrupt priority and exception handling of the system.

2. The radiation-resistant reinforced payload master controller supporting the SPACE VPX architecture according to claim 1, characterized in that: A pre-installation test interface is additionally provided, and the test interface is connected to the connector; the power management module includes a current limiting protection circuit and a timing control circuit; the number of PMC interfaces is 4, and the number of connector interfaces is 6.

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