Method for manufacturing a semiconductor device and shielded gate trench device

Abstract

The application relates to a preparation method of a semiconductor device and a shield gate trench device, and the method comprises the following steps: obtaining a substrate provided with a trench, a first dielectric layer is formed on the inner wall of the trench, a space in the trench without the first dielectric layer is provided with a polysilicon structure, and the top of the polysilicon structure is lower than the surface of the substrate; wet etching is used to remove the part of the first dielectric layer which is higher than the polysilicon structure; the top of the polysilicon structure is bombarded by plasma so that the top of the polysilicon structure is partially removed; a first oxide layer is thermally grown on the inner wall of the trench and the surface of the polysilicon structure; and a second dielectric layer is filled into the trench, and the second dielectric layer fills the trench. The edge of the polysilicon structure is bombarded by plasma, the width of the top of the polysilicon structure is reduced, the purpose of avoiding the formation of small holes on the two sides of the top of the polysilicon structure is achieved, and the purpose of eliminating the gate-source short circuit caused by filling abnormality is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a preparation method of a semiconductor device and a shield gate trench device. BACKGROUND

[0002] The shield gate trench (SGT) product is prone to form small holes on both sides of the shield gate polysilicon. When the polysilicon gate is formed in the deep trench, the polysilicon gate is prone to enter the small holes, causing the gate-source short circuit. In addition, the protruding structure on the top of the shield gate is prone to form a sharp tip charge concentration, which may cause the shield gate and the gate to be broken down and leak during operation. SUMMARY

[0003] Therefore, it is necessary to provide a preparation method of a semiconductor device and a shield gate trench device.

[0004] To achieve the above-mentioned purpose, in one aspect, the present application provides a preparation method of a semiconductor device, comprising:

[0005] obtaining a substrate with a trench, a first dielectric layer is formed on the inner wall of the trench, and a polysilicon structure is formed in the space of the trench without the first dielectric layer, and the top of the polysilicon structure is lower than the surface of the substrate;

[0006] wet etching to remove the part of the first dielectric layer higher than the polysilicon structure;

[0007] plasma bombardment on the top of the polysilicon structure to partially remove the top of the polysilicon structure;

[0008] thermally growing a first oxide layer on the inner wall of the trench and the surface of the polysilicon structure;

[0009] filling a second dielectric layer in the trench, and the second dielectric layer fills the trench.

[0010] In one of the embodiments, the first dielectric layer is an insulating oxide layer, and the step of obtaining a substrate with a trench, a first dielectric layer is formed on the inner wall of the trench, and a polysilicon structure is formed in the space of the trench without the first dielectric layer, and the top of the polysilicon structure is lower than the surface of the substrate comprises:

[0011] etching the substrate with a mask layer to form a trench in the position of the substrate without the mask layer;

[0012] thermally growing the insulating oxide layer on the inner wall of the trench;

[0013] The step of plasma bombardment on the edge of the polysilicon structure comprises:

[0014] The edge of the mask layer on the top of the trench is bombarded so that the edge of the mask layer is partially removed.

[0015] In one embodiment, the mask layer is a silicon nitride layer.

[0016] In one embodiment, the step of filling the trench with a second dielectric layer includes forming the second dielectric layer by a high-density plasma chemical vapor deposition process.

[0017] In one embodiment, the step of bombarding the edge of the polysilicon structure with plasma includes forming the plasma by a high-density plasma chemical vapor deposition machine.

[0018] In one embodiment, the process gas of the high-density plasma chemical vapor deposition machine includes helium and oxygen.

[0019] In one embodiment, the volume flow ratio of helium to oxygen in the process gas is not less than 1.

[0020] In one embodiment, the step of bombarding the edge of the polysilicon structure with plasma so that the edge of the polysilicon structure is partially removed causes the two sides of the top of the polysilicon structure to form a polysilicon descending slope structure extending to the top of the first dielectric layer after removal, the slope structure having an obtuse angle with the top of the first dielectric layer.

[0021] In one embodiment, the step of bombarding the edge of the mask layer on the top of the trench so that the edge of the mask layer is partially removed includes removing the part of the mask layer protruding from the top of the inner wall of the trench so that the mask layer no longer protrudes from the top of the inner wall of the trench after removal.

[0022] In one embodiment, the semiconductor device is a shield gate trench device, and the polysilicon structure is used to form a shield gate structure.

[0023] The present application also provides a shield gate trench device, comprising:

[0024] a substrate having a trench;

[0025] a shield gate dielectric layer on the bottom and inner wall of the trench;

[0026] a shield gate polysilicon layer in the trench, the two sides of the top of the shield gate polysilicon layer being a descending slope structure.

[0027] In one embodiment, the slope structure has an obtuse angle with the top of the shield gate dielectric layer.

[0028] The preparation method of the semiconductor device can improve the sharp corners of the top edge of the polysilicon structure exposed due to the isotropic wet etching. Specifically, in order to remove the first dielectric layer on the inner wall of the trench higher than the top of the polysilicon structure, the wet etching step of the preparation method removes the first dielectric layer on both sides of the top of the polysilicon structure, so that the edge of the top of the polysilicon structure is exposed. When the first oxide layer is thermally grown on the exposed polysilicon structure, the first oxide layer grows faster on the edge of the top of the polysilicon structure due to the difference in crystal direction between the top of the polysilicon structure and other positions of the polysilicon structure, so that the first oxide layer on the top of the polysilicon structure and the edge of the top of the polysilicon structure is thicker, forming a structure protruding outward on both sides of the top. The protruding structure makes it difficult to fill the space below the second dielectric layer when the second dielectric layer is filled into the trench, thereby forming a small hole. The plasma bombardment can remove part of the polysilicon on the edge, so that the width of the top of the polysilicon structure is smaller, so that the first oxide layer thermally grown does not form the protruding structure, thereby avoiding affecting the filling capacity when the second dielectric layer is filled, achieving the purpose of avoiding the formation of a small hole on both sides of the top of the polysilicon structure, and further achieving the purpose of eliminating the gate-source short circuit caused by the filling abnormality. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0030] Figure 1 The scanning electron microscope photos of the cracks under the silicon nitride mask layer after filling silicon dioxide in the trench of the exemplary shield gate trench device and the small holes on both sides of the top of the polysilicon of the shield gate;

[0031] Figure 2 The flowchart of the preparation method of the semiconductor device in an embodiment;

[0032] Figure 3 The flowchart of step S102 in an embodiment;

[0033] Figure 4 The cross-sectional structure schematic diagram of the substrate provided with a mask layer in the preparation method of the semiconductor device provided in an embodiment;

[0034] Figure 5 For Figure 4 The corresponding cross-sectional structure schematic diagram of the semiconductor device after forming the trench;

[0035] Figure 6 The flowchart of the preparation method of the semiconductor device in an embodiment;Figure 5 A corresponding cross-sectional view of the semiconductor device after forming the polysilicon structure;

[0036] Figure 7 To Figure 6 A corresponding cross-sectional view of the semiconductor device after removing the portion of the first dielectric layer above the polysilicon structure;

[0037] Figure 8 To Figure 7 A corresponding cross-sectional view of the semiconductor device after performing the plasma bombardment;

[0038] Figure 9 A corresponding cross-sectional view of the semiconductor device after forming the second dielectric layer in an embodiment, and a corresponding cross-sectional view of the shield gate trench device;

[0039] Figure 10 A corresponding cross-sectional view of the semiconductor device after forming the second dielectric layer in an embodiment, and a corresponding cross-sectional view of the shield gate trench device;

[0040] Figure 11 A corresponding cross-sectional view of the semiconductor device after forming the second dielectric layer in an embodiment, and a corresponding cross-sectional view of the shield gate trench device; DETAILED DESCRIPTION

[0041] In order to facilitate the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The drawings show embodiments of the present application. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein in the specification merely describe specific embodiments of the present application for the purpose of illustration, and are not intended to limit the present application.

[0043] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0044] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0045] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0046] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic and their shapes do not necessarily illustrate the actual shape of a region of a device and are merely meant to be an illustration rather than a limitation.

[0047] With reference to Figure 10 In the preparation process of an exemplary shield gate trench (SGT) product, a shield gate oxide layer is formed on the inner wall of a deep trench, a shield gate polysilicon structure is formed in the deep trench, the top of the shield gate polysilicon structure is lower than the surface of the substrate, i.e. the top of the shield gate oxide layer, and then the part of the shield gate oxide layer higher than the shield gate polysilicon structure is removed by a wet etching process. Due to the isotropic characteristics of the wet etching, in the process of completely removing the part of the shield gate oxide layer formed on the inner wall of the deep trench and higher than the shield gate polysilicon structure by the etching process, the shield gate oxide layer on both sides of the top of the shield gate polysilicon structure will be etched away, so that the edges of the top of the shield gate polysilicon structure are exposed, two small trenches are formed inside the deep trench between the sidewalls of the shield gate polysilicon structure and the sidewalls of the deep trench, and the depth of the small trenches increases with the increase of the thickness of the shield gate oxide layer.

[0048] When a thin sacrificial oxide layer is grown in the deep trench by a subsequent thermal oxidation process, due to the different crystal orientations of the shield gate polysilicon structure and the polysilicon structure at other positions, the oxidation rate of the polysilicon to form the sacrificial oxide layer is different, and after the growth of the Sacrificial Oxide is completed, the small trenches on both sides of the top of the shield gate polysilicon structure will become a concave structure with a narrow top and a wide bottom (i.e. an exocentric structure is formed on both sides of the top of the shield gate polysilicon structure), and when a polysilicon gate oxide layer is filled into the deep trench by a high-density plasma chemical vapor deposition process, it is difficult to fill the position of the concave structure in the small trenches on both sides of the top of the shield gate polysilicon structure, so that small holes (as shown in Figure 1 ) are formed in the small trenches, and the quality of the polysilicon gate oxide layer filled in the small trenches is poor, which is easy to cause gate-source leakage, and when a polysilicon gate is formed in the deep trench, the polysilicon gate is easy to enter the small holes, causing gate-source short circuit.

[0049] Secondly, after the trench is formed, the surface of the substrate is covered with a silicon nitride mask layer used for forming the trench. When a shielding gate oxide layer is grown in the trench by dry oxygen, the silicon nitride mask layer below the sidewall of the trench will be consumed. After the part of the shielding gate oxide layer higher than the shielding gate polysilicon structure is removed by a subsequent wet etching process, the silicon nitride mask layer will protrude relative to the trench, that is, the part of the silicon nitride mask layer close to the trench will be suspended above the trench. When a polysilicon gate oxide layer is formed to fill the trench by plasma chemical vapor deposition, a small crack (as shown in Figure 1 ) will be formed below the protruding position of the silicon nitride mask layer due to the inclined direction of the plasma at the edge of the wafer, so that the etching rate in the trench is different when the polysilicon gate oxide layer is etched by a subsequent wet etching process, resulting in a difference in the thickness of the polysilicon gate oxide layer between the gate and the source, and the problem of breakdown leakage is likely to occur.

[0050] To solve the above problems, the application provides a new preparation method of a semiconductor device and a new shielding gate trench device.

[0051] Referring to Figure 2 , a flowchart of the preparation method of the semiconductor device in an embodiment is shown.

[0052] As Figure 2 shown, in one of the embodiments, a preparation method of a semiconductor device is provided, which comprises the following steps:

[0053] S102, a substrate with a trench is obtained.

[0054] The substrate with the trench is obtained, a first dielectric layer is formed on the inner wall of the trench, a polysilicon structure is formed in the space of the trench without the first dielectric layer, and the top of the polysilicon structure is lower than the surface of the substrate.

[0055] The substrate can be a silicon substrate, a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, etc. The trench can be formed in a single-crystal silicon epitaxial layer on the surface of the substrate, and the substrate is described as a silicon substrate below.

[0056] S104, a part of the first dielectric layer higher than the polysilicon structure is removed by wet etching.

[0057] By the wet etching process, the part of the first dielectric layer higher than the polysilicon structure in the trench is removed, and a shielding gate dielectric layer composed of the remaining first dielectric layer is obtained.

[0058] S106, the top of the polysilicon structure is partially removed by plasma bombardment.

[0059] The polycrystalline silicon structure top is partially removed by removing both sides of the polycrystalline silicon structure top in the trench through plasma bombardment, the top width of the polycrystalline silicon structure is narrowed, and the sharp corner top of the polycrystalline silicon structure is smoothed. The step S108 can avoid the first oxide layer (i.e. the sacrificial oxide layer) growing faster at the edge of the polycrystalline silicon structure top due to the different crystal direction of the polycrystalline silicon structure top and other positions when the first oxide layer is thermally grown in the trench, and the first oxide layer at the polycrystalline silicon structure top and its edge is thicker, which results in the structure protruding outward on both sides of the top.

[0060] S108, thermally growing a first oxide layer on the inner wall of the trench and the surface of the polycrystalline silicon structure.

[0061] In one of the embodiments, a thin sacrificial oxide layer is formed in the furnace tube.

[0062] S110, filling a second dielectric layer in the trench, and the second dielectric layer fills the trench.

[0063] In one of the embodiments, the first dielectric layer is an insulating oxide layer, and the step S102 includes:

[0064] Firstly, etching the substrate with the mask layer to form a trench in the position of the substrate not covered by the mask layer. Secondly, forming a first dielectric layer on the inner wall of the trench through chemical vapor deposition process. Thirdly, forming a polycrystalline silicon structure in the space of the trench not covered by the first dielectric layer, and the top of the polycrystalline silicon structure is lower than the surface of the substrate. The third step can be performed by using conventional process for forming a structure with the top lower than the surface of the substrate, which is not described here. Figure 3 The flow chart of the step S102 in one of the embodiments is shown in the figure. In this embodiment, the first dielectric layer is an insulating oxide layer, and the step S102 includes:

[0065] S202, etching the substrate with the mask layer to form a trench in the position of the substrate not covered by the mask layer.

[0066] Figures 4 to 9 The preparation method of the semiconductor device of the present application is introduced by taking the preparation of the shield gate trench device as an example. Referring to Figure 4 In one of the embodiments, a silicon oxide film 103 is formed on the substrate 102, and the mask layer is located on the silicon oxide film 103.

[0067] Referring to Figure 5Step S202 may specifically include: First, forming a mask layer 104 on the substrate 102, the mask layer 104 exposing a portion of the silicon oxide thin film 103 (and a portion of the substrate 102). Second, performing an etching process to remove the portion of the silicon oxide thin film 103 not covered by the mask layer 104 and the portion of the substrate 102 below it, forming trenches 106 in the substrate 102, and obtaining an oxide layer 202 composed of the remaining silicon oxide thin film 103.

[0068] In one embodiment, the mask layer 104 includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbide layer, a silicon carbonitride layer, and a silicon carbonitride layer. The following description uses a silicon nitride layer as an example to illustrate that the mask layer 104 is a silicon nitride layer.

[0069] S204, the insulating oxide layer is formed by thermal growth on the inner wall of the trench.

[0070] like Figure 6 The silicon on the inner wall of the trench 106 is oxidized by a thermal oxidation process to form an insulating oxide layer 108 on the inner wall of the trench 106. For example, the substrate 102 is placed in a furnace tube and oxygen is introduced to perform dry oxygen oxidation to form the insulating oxide layer 108; or the substrate 102 is placed in a furnace tube and oxygen and water vapor are introduced to perform wet oxygen oxidation to form the insulating oxide layer 108; or the substrate 102 is placed in a furnace tube and oxygen and hydrogen are introduced to perform hydrogen-oxygen synthesis oxidation to form the insulating oxide layer 108; or the substrate 102 is placed in a furnace tube and oxygen and chlorine-containing gas are introduced to perform chlorine-doped oxidation to form the insulating oxide layer 108, etc.

[0071] After forming an insulating oxide layer 108 on the inner wall of the trench 106, a polysilicon structure 110 is formed in the trench 106, with the top of the polysilicon structure 110 being lower than the surface of the substrate 102. In practical applications, the polysilicon structure 110 can be formed using conventional processes for forming structures with the top lower than the surface of the substrate, such as polysilicon deposition followed by etch-back, which will not be elaborated here.

[0072] like Figure 7As shown, after forming the polysilicon structure 110, wet etching removes the portion of the insulating oxide layer 108 above the polysilicon structure 110, resulting in a shielding gate dielectric layer 204 composed of the remaining insulating oxide layer 108. Specifically, a wet etching process is performed to remove the insulating oxide layer 108 located between the top of the trench 106 opening and the top of the polysilicon structure 110. Simultaneously, the portion of the oxide layer 202 above the insulating oxide layer 108 is removed, resulting in a shielding gate dielectric layer 204 composed of the remaining insulating oxide layer 108. Because wet etching is isotropic, and the ratio of the depth to the width of the insulating oxide layer 108 to be removed on the sidewall of the trench 106 is greater than 1, after the wet etching process, the insulating oxide layers 108 on both sides of the top of the polysilicon structure 110 are removed, making the top of the polysilicon structure 110 higher than the top of the shielding gate dielectric layer 204.

[0073] After obtaining the shielding gate dielectric layer 204, plasma bombardment is performed to partially remove the top of the polysilicon structure 110. This narrows the top of the polysilicon structure 110 and smooths out the sharp corners. This avoids the situation where, during the thermal growth of the first oxide layer (i.e., sacrificial oxide layer) in the trench, the first oxide layer at the top edge of the polysilicon structure 110 grows faster and thicker due to the different crystal orientation of the polysilicon at the top and other locations, resulting in a convex structure on both sides of the top.

[0074] like Figure 8 As shown, plasma bombards the edges of the polysilicon structure 110, causing the top two sides of the polysilicon structure 110 to be removed, forming a ramp structure 208 extending towards the top 206 of the shielding gate dielectric layer 204. The angle between the ramp structure 208 and the top of the shielding gate dielectric layer 204 is an obtuse angle, resulting in a shielding gate polysilicon layer 210 composed of the remaining polysilicon structure 110. In this way, when filling the second dielectric layer in the subsequent step (S110), both sides of the polysilicon structure 110 can be filled, avoiding the formation of small holes. This prevents the polysilicon gate from entering the small holes and causing a gate-source short circuit when forming the polysilicon gate in the trench 106.

[0075] See Figure 6 and Figure 7The dry oxidation of the insulating oxide layer 108 in the trench 106 consumes the silicon on the sidewall of the trench 106 under the mask layer 104. Therefore, after removing the portion of the insulating oxide layer 108 above the polysilicon structure 110, the mask layer 104 protrudes relative to the trench 106. In one embodiment, the plasma in step S106 also bombards the edge of the mask layer 104 on the top of the trench 106, so that the edge of the mask layer 104 is partially removed. At this time, the width of the top of the mask layer 104 is narrowed, so as to avoid the formation of a crack under the protruding portion of the mask layer 104 during the subsequent formation of the polysilicon gate oxide layer filling the trench 106 by plasma chemical vapor deposition, due to the directionality of the plasma at the edge of the wafer. The crack will cause different etching rates in the trench 106 during the subsequent wet etching of the polysilicon gate oxide layer, so that the thickness of the polysilicon gate oxide layer between the gate and the source has a difference, which is prone to cause the problem of breakdown leakage. In actual production process, the edge of the mask layer 104 can be removed by plasma bombardment without damaging the oxide layer 202 under the mask layer 104.

[0076] In one embodiment, the step of bombarding the edge of the mask layer 104 on the top of the trench 106 to partially remove the edge of the mask layer 104 includes removing the portion of the mask layer 104 protruding above the top of the inner wall of the trench 106, so that the bottom edge of the mask layer 104 is aligned with the top of the trench 106. That is, the portion of the mask layer 104 hanging above the trench 106 is removed.

[0077] In one embodiment, the step of bombarding the edge of the polysilicon structure 110 includes forming plasma by using a high-density plasma chemical vapor deposition (HDPCVD) machine and bombarding the edge of the polysilicon structure 110.

[0078] In one embodiment, the process gas of the HDPCVD includes helium and oxygen.

[0079] In one embodiment, the volume flow ratio of helium and oxygen in the HDPCVD process gas is not less than 1. Further, the flow of helium is greater than or equal to 90sccm and less than or equal to 110sccm, and the flow of oxygen is greater than or equal to 90sccm and less than or equal to 110sccm. The top radio frequency power (RF-TOP) is between 4700W and 5000W, for example 4850W; the bottom radio frequency power (RF-BIAS) is between 2600W and 3100W, for example 2850W; the side radio frequency power (RF-SIDE) is between 800W and 1000W, for example 900W; and the reaction pressure is between 3mTorr and 5mTorr, for example 3mTorr, all of which include both endpoints. In actual applications, the parameters of the high-density plasma etching process are adjusted according to the thickness of the first dielectric layer and the feature size of the deep trench. Within a certain range, the greater the thickness of the first dielectric layer and the greater the feature size of the deep trench, the greater the rate and the longer the time of the high-density plasma etching process.

[0080] Referring to Figure 9 In one embodiment, the step S110 includes forming the second dielectric layer by a high-density plasma chemical vapor deposition process.

[0081] Specifically, the second dielectric layer 112 filling the trench 106 is formed by a high-density plasma chemical vapor deposition process. Typically, the high-density plasma chemical vapor deposition process is followed by a step of performing chemical mechanical polishing.

[0082] In one embodiment, the second dielectric layer 112 includes a silicon oxide layer.

[0083] In one embodiment, the method for manufacturing the semiconductor device further includes a step of etching the second dielectric layer 112 to obtain the gate oxide layer above the shielding gate polysilicon layer 210.

[0084] The preparation method of the semiconductor device can improve the sharp corners of the top edge of the polysilicon structure exposed due to the isotropic wet etching. Specifically, the wet etching step of the method is to remove the first dielectric layer on the inner wall of the trench higher than the top of the polysilicon structure, which causes the first dielectric layer on both sides of the top of the polysilicon structure to be removed, so that the edge of the top of the polysilicon structure is exposed. When the first oxide layer is thermally grown on the exposed polysilicon structure, the growth rate of the first oxide layer on the edge of the top of the polysilicon structure is faster than that of the polysilicon structure at other positions due to the difference in crystal direction, so the first oxide layer on the top of the polysilicon structure and the edge of the top of the polysilicon structure is thicker, forming a structure protruding outward on both sides of the top. The protruding structure makes it difficult to fill the space below the second dielectric layer when filling the second dielectric layer into the trench, thereby forming a small hole. The plasma bombardment can remove part of the polysilicon on the edge, so that the width of the top of the polysilicon structure is smaller, so that the first oxide layer thermally grown does not form the protruding structure, thereby avoiding affecting the filling capacity when the second dielectric layer is filled, achieving the purpose of avoiding the formation of a small hole on both sides of the top of the polysilicon structure, and further achieving the purpose of eliminating the gate-source short circuit caused by the filling abnormality.

[0085] It should be understood that although Figure 1 , Figure 3 The steps in the flowchart of the method are displayed in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, Figure 1 , Figure 3 At least part of the steps in the method can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps in other steps.

[0086] As shown in Figure 9 , the present application also provides a shield gate trench device, comprising:

[0087] A substrate 102 having a trench 106;

[0088] A shield gate dielectric layer 204 is located at the bottom and inner wall of the trench 106;

[0089] A shield gate polysilicon layer 210 is provided in the trench 106, and the top of the shield gate polysilicon layer 210 has two downwardly extending slope structures 208, and the included angle between the slope structure 208 and the top 206 of the shield gate dielectric layer 204 is an obtuse angle.

[0090] In one embodiment, the shielded gate trench device further comprises a gate oxide layer above the shielded gate polysilicon layer 210.

[0091] As Figure 11 shown, it is a topographic comparison chart of scanning electron microscope photos of cross-sectional structures of semiconductor devices respectively made by the method for making semiconductor devices of the present application and by a conventional method for making semiconductor devices, from which Figure 11 It can be seen that the semiconductor device made by the method for making semiconductor devices of the present application has a relatively flat top corner of the shielded gate polysilicon layer (the portion circled by the dashed line in the trench in the figure), no voids on both sides, no abnormal filling, and no cracks at the opening of the trench (the portion circled by the dashed line at the opening of the trench in the figure).

[0092] The shielded gate trench device has a shielded gate polysilicon layer in the trench, which is made of polysilicon material, and the top of the shielded gate polysilicon layer has downwardly extending slope structures on both sides, and the included angle between the slope structures and the top of the shielded gate dielectric layer is obtuse. The width of the top of the polysilicon structure becomes smaller, so the first oxide layer grown by heat will not form the above-mentioned convex structure, thus avoiding affecting the filling capacity when filling the second dielectric layer, achieving the purpose of avoiding the formation of small holes on both sides of the top of the polysilicon structure. The included angle between the slope and the top of the shielded gate dielectric layer is obtuse. The width of the top of the polysilicon structure is small, and no convex structure grown by heat is formed at the top of the polysilicon structure, which can avoid affecting the filling capacity when filling the polysilicon gate, achieving the purpose of avoiding the formation of small holes on both sides of the top of the polysilicon structure, and further achieving the purpose of eliminating the gate-source short circuit caused by filling abnormalities.

[0093] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above-mentioned terms does not necessarily refer to the same embodiment or example.

[0094] The technical features of the above-mentioned embodiments can be combined in any way. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present specification.

[0095] The above embodiments only express several implementation ways of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation to the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: a substrate with a trench is obtained, a first dielectric layer is formed on the inner wall of the trench, and a polysilicon structure is formed in the space of the trench without the first dielectric layer, the top of the polysilicon structure being lower than the surface of the substrate; wet etching is performed to remove the part of the first dielectric layer higher than the polysilicon structure, so as to obtain a shielding gate dielectric layer composed of the remaining first dielectric layer; after the wet etching, the first dielectric layer on both sides of the top of the polysilicon structure is removed, so that the top of the polysilicon structure is higher than the top of the shielding gate dielectric layer; the edge of the polysilicon structure is bombarded by plasma, so that the edge of the polysilicon structure is partially removed, and a shielding gate polysilicon layer composed of the remaining polysilicon structure is obtained; a first oxide layer is thermally grown on the inner wall of the trench and the surface of the polysilicon structure; a second dielectric layer is filled into the trench, and the second dielectric layer fills the trench; the method for manufacturing a semiconductor device further comprises the following steps: the second dielectric layer is etched, so as to obtain a gate oxide layer above the shielding gate polysilicon layer; the gate oxide layer comprises the first oxide layer and the remaining second dielectric layer.

2. The production method according to claim 1, characterized by, The first dielectric layer is an insulating oxide layer, and the step of obtaining the substrate with the trench and forming the first dielectric layer on the inner wall of the trench comprises the following steps: the substrate with the mask layer is etched to form a trench in the position of the substrate without the mask layer; the insulating oxide layer is thermally grown in the inner wall of the trench; the step of bombarding the edge of the polysilicon structure by plasma comprises the following step: the edge of the mask layer on the top of the trench is bombarded, so that the edge of the mask layer is partially removed.

3. The preparation method according to claim 2, characterized in that, The mask layer is a silicon nitride layer.

4. The method of claim 1, wherein, The step of filling the second dielectric layer into the trench comprises the following step: the second dielectric layer is formed by a high-density plasma chemical vapor deposition process.

5. The preparation method according to claim 1, characterized in that, The step of bombarding the edge of the polysilicon structure by plasma adopts a high-density plasma chemical vapor deposition machine to form plasma.

6. The preparation method according to claim 5, characterized in that, The process gas for forming plasma by the high-density plasma chemical vapor deposition machine comprises helium and oxygen.

7. The preparation method according to claim 6, characterized in that, The volume flow ratio of helium to oxygen in the process gas is not less than 1.

8. The preparation method according to claim 1, characterized in that, The step of bombarding the edge of the polysilicon structure by plasma so that the edge of the polysilicon structure is partially removed makes both sides of the top of the polysilicon structure form a polysilicon descending slope structure extending to the top of the first dielectric layer after the removal, and the angle between the slope structure and the top of the first dielectric layer is an obtuse angle.

9. The preparation method according to claim 2, characterized in that, The step of bombarding the edge of the mask layer on the top of the trench so that the edge of the mask layer is partially removed comprises the following step: the part of the mask layer protruding outward from the top of the inner wall of the trench is removed, so that the mask layer no longer protrudes outward from the top of the inner wall of the trench after the removal.

10. A shielded gate trench device, characterized by, The method comprises the following steps: a substrate with a trench is obtained; a shielding gate dielectric layer is located at the bottom and inner wall of the trench. A shielding gate polysilicon layer is arranged in the trench, and two sides of the top of the shielding gate polysilicon layer are downwardly extending slope structures; the top of the shielding gate polysilicon layer is higher than the top of the shielding gate dielectric layer. A gate oxide layer is arranged above the shielding gate polysilicon layer and in contact with the shielding gate polysilicon layer, and the gate oxide layer comprises a first oxide layer and a second dielectric layer; the first oxide layer is formed by thermal growth on the inner wall of the trench and the surface of the polysilicon structure after plasma bombardment; and the second dielectric layer is arranged in the trench.

11. The shielded gate trench device of claim 10, wherein, The included angle between the slope structure and the top of the shielding gate dielectric layer is an obtuse angle.

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